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However, high performance chip multiprocessors use a shared memory model, which generates large numbers of short messages, creating high arbitration latency overhead for photonic switching networks. In this paper, we explore techniques that intelligently use information from the memory hierarchy to predict communication in order to setup photonic circuits with reduced or eliminated arbitration latency. Firstly, we present a switch scheduling algorithm, which arbitrates on a per memory transaction basis and holds open photonic circuits to exploit temporal locality. We show that this can reduce the average arbitration latency overhead by 60% and eliminate arbitration latency altogether for up to 70% of memory transactions. We then demonstrate that this switch scheduling algorithm operating with a central photonic crossbar or Clos switch has significant energy efficiency benefits over arbitration\u2010free photonic networks such as single writer multiple reader networks. Finally, we demonstrate that cache miss prediction can be used to predict 86% of more complex memory transactions involving multiple nodes or main memory. Copyright \u00a9 2014 John Wiley &amp; Sons, Ltd.<\/jats:p>","DOI":"10.1002\/cpe.3334","type":"journal-article","created":{"date-parts":[[2014,8,14]],"date-time":"2014-08-14T23:29:19Z","timestamp":1408058959000},"page":"2551-2566","source":"Crossref","is-referenced-by-count":4,"title":["Towards zero latency photonic switching in shared memory networks"],"prefix":"10.1002","volume":"26","author":[{"given":"Muhammad Ridwan","family":"Madarbux","sequence":"first","affiliation":[{"name":"Department of Electronic and Electrical Engineering University College London London UK"}]},{"given":"Anouk","family":"Van\u2009Laer","sequence":"additional","affiliation":[{"name":"Department of Electronic and Electrical Engineering University College London London UK"}]},{"given":"Philip M.","family":"Watts","sequence":"additional","affiliation":[{"name":"Department of Electronic and Electrical Engineering University College London London UK"}]},{"given":"Timothy M.","family":"Jones","sequence":"additional","affiliation":[{"name":"Computer Laboratory University of Cambridge Cambridge UK"}]}],"member":"311","published-online":{"date-parts":[[2014,8,14]]},"reference":[{"key":"e_1_2_10_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.64"},{"key":"e_1_2_10_3_1","first-page":"153","volume-title":"ACM SIGARCH Computer Architecture News","author":"Vantrease D","year":"2008"},{"key":"e_1_2_10_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2020712"},{"key":"e_1_2_10_5_1","first-page":"429","volume-title":"ACM SIGARCH Computer Architecture News","author":"Pan Y","year":"2009"},{"key":"e_1_2_10_6_1","doi-asserted-by":"crossref","unstructured":"HendryG KamilS BibermanA ChanJ LeeBG MohiyuddinM JainA et al.Analysis of photonic networks for a chip multiprocessor using scientific applications.3rd ACM\/IEEE International Symposium on Networks\u2010on\u2010Chip 2009. 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