{"id":"https://openalex.org/W2580911598","doi":"https://doi.org/10.1109/patmos.2016.7833687","title":"Novel memristive logic architectures","display_name":"Novel memristive logic architectures","publication_year":2016,"publication_date":"2016-09-01","ids":{"openalex":"https://openalex.org/W2580911598","doi":"https://doi.org/10.1109/patmos.2016.7833687","mag":"2580911598"},"language":"en","primary_location":{"id":"doi:10.1109/patmos.2016.7833687","is_oa":false,"landing_page_url":"https://doi.org/10.1109/patmos.2016.7833687","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100635998","display_name":"Xiaohan Yang","orcid":"https://orcid.org/0000-0003-4425-4531"},"institutions":[{"id":"https://openalex.org/I124261462","display_name":"Oxford Brookes University","ror":"https://ror.org/04v2twj65","country_code":"GB","type":"education","lineage":["https://openalex.org/I124261462"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Xiaohan Yang","raw_affiliation_strings":["Department of Computing & Communication Technologies, Oxford Brookes University, Oxford, UK"],"affiliations":[{"raw_affiliation_string":"Department of Computing & Communication Technologies, Oxford Brookes University, Oxford, UK","institution_ids":["https://openalex.org/I124261462"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029448207","display_name":"Adedotun Adeyemo","orcid":"https://orcid.org/0000-0003-2003-3937"},"institutions":[{"id":"https://openalex.org/I124261462","display_name":"Oxford Brookes University","ror":"https://ror.org/04v2twj65","country_code":"GB","type":"education","lineage":["https://openalex.org/I124261462"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Adedotun Adeyemo","raw_affiliation_strings":["Department of Computing & Communication Technologies, Oxford Brookes University, Oxford, UK"],"affiliations":[{"raw_affiliation_string":"Department of Computing & Communication Technologies, Oxford Brookes University, Oxford, UK","institution_ids":["https://openalex.org/I124261462"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101613535","display_name":"Anu Bala","orcid":"https://orcid.org/0000-0002-5510-0549"},"institutions":[{"id":"https://openalex.org/I124261462","display_name":"Oxford Brookes University","ror":"https://ror.org/04v2twj65","country_code":"GB","type":"education","lineage":["https://openalex.org/I124261462"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Anu Bala","raw_affiliation_strings":["Department of Computing & Communication Technologies, Oxford Brookes University, Oxford, UK"],"affiliations":[{"raw_affiliation_string":"Department of Computing & Communication Technologies, Oxford Brookes University, Oxford, UK","institution_ids":["https://openalex.org/I124261462"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076588539","display_name":"Abusaleh Jabir","orcid":null},"institutions":[{"id":"https://openalex.org/I124261462","display_name":"Oxford Brookes University","ror":"https://ror.org/04v2twj65","country_code":"GB","type":"education","lineage":["https://openalex.org/I124261462"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Abusaleh Jabir","raw_affiliation_strings":["Department of Computing & Communication Technologies, Oxford Brookes University, Oxford, UK"],"affiliations":[{"raw_affiliation_string":"Department of Computing & Communication Technologies, Oxford Brookes University, Oxford, UK","institution_ids":["https://openalex.org/I124261462"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100635998"],"corresponding_institution_ids":["https://openalex.org/I124261462"],"apc_list":null,"apc_paid":null,"fwci":0.3718,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.6847987,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"196","last_page":"199"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.794320821762085},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6578673124313354},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6130171418190002},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6038581728935242},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5805578231811523},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5780688524246216},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5120363831520081},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.494078665971756},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.471027672290802},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.40927934646606445},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.39021939039230347},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23025569319725037},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19130036234855652},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.18865525722503662},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1704355776309967}],"concepts":[{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.794320821762085},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6578673124313354},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6130171418190002},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6038581728935242},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5805578231811523},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5780688524246216},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5120363831520081},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.494078665971756},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.471027672290802},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.40927934646606445},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.39021939039230347},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23025569319725037},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19130036234855652},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.18865525722503662},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1704355776309967}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/patmos.2016.7833687","is_oa":false,"landing_page_url":"https://doi.org/10.1109/patmos.2016.7833687","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","raw_type":"proceedings-article"},{"id":"pmh:oai:ray.yorksj.ac.uk:13544","is_oa":false,"landing_page_url":"https://orcid.org/0009-0000-6242-5248","pdf_url":null,"source":{"id":"https://openalex.org/S4306400356","display_name":"Research at York St John (York St John University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I124246371","host_organization_name":"York St John University","host_organization_lineage":["https://openalex.org/I124246371"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":null,"raw_type":"PeerReviewed"},{"id":"pmh:tle:34fc9be0-f9a3-4d20-bc21-f898e743cbed:b4ef9587-4603-18f8-a471-bb20511f0ad9:1","is_oa":false,"landing_page_url":"https://radar.brookes.ac.uk/radar/items/34fc9be0-f9a3-4d20-bc21-f898e743cbed/1","pdf_url":null,"source":{"id":"https://openalex.org/S4306400541","display_name":"Radar (Oxford Brookes University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I124261462","host_organization_name":"Oxford Brookes University","host_organization_lineage":["https://openalex.org/I124261462"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","raw_type":"Conference Paper/Proceeding/Abstract"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W12618665","https://openalex.org/W845285418","https://openalex.org/W1569612250","https://openalex.org/W1578783943","https://openalex.org/W1985857102","https://openalex.org/W2004782555","https://openalex.org/W2021383442","https://openalex.org/W2066280488","https://openalex.org/W2081729575","https://openalex.org/W2106343578","https://openalex.org/W2112181056","https://openalex.org/W2139580250","https://openalex.org/W2140133741","https://openalex.org/W2162651880","https://openalex.org/W2195265150","https://openalex.org/W2332935940","https://openalex.org/W6600515825","https://openalex.org/W6623449936","https://openalex.org/W6687642761"],"related_works":["https://openalex.org/W2017528947","https://openalex.org/W2789662562","https://openalex.org/W2098419840","https://openalex.org/W2526300902","https://openalex.org/W2170504327","https://openalex.org/W2121963733","https://openalex.org/W2542337934","https://openalex.org/W1977171228","https://openalex.org/W2766377030","https://openalex.org/W1985308002"],"abstract_inverted_index":{"We":[0,37],"present":[1,39,48,75],"techniques":[2],"for":[3,27,42,55,66,78],"realising":[4,43,79],"reliable":[5,110],"logic":[6,32,45],"functions":[7],"and":[8,47],"more":[9],"complex":[10],"systems":[11],"based":[12,92],"on":[13,93],"the":[14,34,117],"switching":[15],"characteristics":[16],"of":[17],"memristors.":[18],"First":[19],"we":[20,74],"show":[21,99],"that":[22,100],"memristors":[23],"have":[24,63],"inherent":[25],"properties":[26],"representing":[28],"multiple":[29],"valued":[30],"MIN-MAX":[31],"over":[33],"post":[35],"algebra.":[36],"also":[38],"efficient":[40,81],"architectures":[41],"multifunction":[44],"gates,":[46],"a":[49],"technique":[50],"with":[51,58],"hybrid":[52],"1T-4M":[53,95],"architecture":[54],"seamless":[56],"integration":[57],"existing":[59],"CMOS":[60,118],"logic.":[61],"Memristors":[62],"tremendous":[64],"potential":[65],"security":[67],"aware":[68],"hardware":[69],"synthesis.":[70],"To":[71],"this":[72],"end,":[73],"design":[76,103],"methods":[77],"highly":[80],"Galois":[82],"Field":[83],"circuits,":[84],"which":[85],"are":[86],"widely":[87],"used":[88],"in":[89],"crypto":[90],"hardware,":[91],"our":[94,101],"architectures.":[96],"Experimental":[97],"results":[98],"proposed":[102],"requires":[104],"significantly":[105],"lower":[106],"power":[107],"while":[108],"maintaining":[109],"operations":[111],"at":[112],"high":[113],"frequencies":[114],"compared":[115],"to":[116],"counterparts.":[119]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}