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ORCID35th FPL 2025: Leiden, The Netherlands
- 35th International Conference on Field-Programmable Logic and Applications, FPL 2025, Leiden, The Netherlands, September 1-5, 2025. IEEE 2025, ISBN 979-8-3315-9153-3
- Kyuseung Han, Hyeonguk Jang, Sukho Lee, Sung-Eun Kim, Kyudong Hwang, Jae-Jin Lee:
NPX: Automating Neuromorphic Processor Design from Spike-Based Learning to FPGA Prototyping. 1 - Xiaoke Wang, Dirk Stroobandt:
Interconnection-Aware Resynthesis for Improving FPGA Physical Design. 1-2 - Andrew David Gunter, Steven J. E. Wilton:
Open-Source FPGA Routing Runtime Prediction for Improved Productivity Via Smart Route Termination. 1-9 - Davide Nicolini, Corrado De Sio, Eleonora Vacca, Luca Sterpone:
Routino: Accelerating FPGA Routing Through Efficient Memory Representation. 1-9 - Andrew David Gunter, Steven J. E. Wilton:
Versatile Place and Route with Continuous Routing Runtime Prediction and Smart Route Termination. 1 - Bea Healy, Brandon Freiberger, Jonas Kuenstler, King Lok Chung, Emil Cozac, Meinhard Kissich, Gennadiy Knis, Ron Sass, Dirk Koch, Jan Gray, Guy Lemieux:
Virtualization and Dynamic Reconfiguration of Custom Instruction Accelerators (CIA) in RISC-V Embedded Systems. 1-9 - Piotr Wzorek, Kamil Jeziorek, Marcin Kowalczyk, Krzysztof Blachut, Tomasz Kryjak, Marek Gorgon:
Live Demonstration: Continuous Processing of Event-Data with Graph Convolutional Neural Networks Implemented for SoC FPGA. 1 - Andrew David Gunter, Steven J. E. Wilton:
Using Data to Reduce Uncertainty in FPGA Routing. 1-2 - Dirk Koch, Myrtle Shah, King Lok Chung, Jonas Kuenstler, Marcel Jung, Jakob Ternes, Asma Mohsin, Gennadiy Knis:
FPGAs with FABulous - Framework and Chips. 1 - Pedro Henrique Di Francia Rosso, Guido Araujo:
Multi-FPGA Programming Using OpenMP. 1 - Yuanqi Wang, Yunfei Dai, Jiangnan Li, Kaixiang Zhu, Huizhen Kuang, Hao Zhou, Eric Ren, Xifan Tang, Weijun Qin, Tao Li, Lingli Wang:
GEF: A GNN-Based Evaluation Framework for FPGA Routing Architecture. 1-9 - Hazem M. Sharf, Mohamed Hassan:
FPGA-Based MPSoCs for High-Performance Sensor Fusion: Accelerating Covariance Intersection. 1-10 - Giuseppe Sorrentino, Davide Conficconi:
Towards Accelerated Healthcare Federated System Through Heterogeneous Accelerators. 1-2 - Markus Rein, Dirk Stroobandt:
Reducing FPGA Placement Runtime by Clustering of Netlist Blocks. 1-2 - Atreyee Saha, Sandesh Goyal, Aashish Tripathi:
Programmable Congestion Generator for Evaluating FPGA Interconnect Robustness. 1-9 - Andrea Guerrieri, Isaac John Wetenkamp, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne:
Compile in Seconds and Run on an FPGA with DynaRapid. 1 - Zhigang Wei, Aman Arora, Emily Shriver, Lizy K. John:
ATAPP: Architecture and Technology Aware Power Predictor for Unseen FPGAS. 1-10 - Qaisar Farooq, Idilio Drago:
Energy-Efficient DNNs on FPGAs for Edge-Cloud Computer Vision. 1-2 - Je Yang, Gabriele Tombesi, Joseph Zuckerman, Luca P. Carloni:
ReconFormer: A Multi-Level Run-Time Reconfigurable System-on-Chip for Accelerating Transformers. 10-17 - Xianfeng Cao, Huizhen Kuang, Yuanqi Wang, Lingli Wang:
FLAIC: A Novel FPGA Logic Architecture via Fine-Grained Cut Topology Analysis. 18-26 - Junius Pun, Xilai Dai, Grace Zgheib, Mahesh A. Iyer, Andrew Boutros, Vaughn Betz, Mohamed S. Abdelfattah:
Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage. 27-36 - Qilong Zhu, Yunfei Dai, Shiyan Bi, Huizhen Kuang, Dylan Wang, Wenbo Yin, Lingli Wang:
DEFA: Design Space Exploration for FPGA Overlay Accelerators Through Frequency Prediction and Bayesian Optimization. 37-45 - Shashwat Khandelwal, Jakoba Petri-Koenig, Thomas B. Preußer, Michaela Blott, Shanker Shreejith:
FINN-GL: Generalized Mixed-Precision Extensions for FPGA-Accelerated LSTMS. 46-54 - Nicolai Fiege, Martin Hardieck, Peter Zipf:
Multiplexer Optimizations for Virtex FPGAs. 55-59 - Binbin Wang, Xinmu Wang, Xinyu Zhang, Shibo Tang, Huisi Zhou, Wei Hu:
Identifying Sat Resilient Blocks Through LUT Switching Analysis for Breaking Compound Logic Locking Schemes. 60-67 - Martim Rosado, Pedro Tomás, Nuno Roma, André David:
URAM-Based Asynchronous FIFO Design for Improved Throughput and FPGA RAM Usage. 68-72 - Mohamed A. Elgammal, Vaughn Betz:
From Errors to Solutions: LLM-Powered Command Scripting for FPGA Cad Tools. 73-82 - Qin Luo, Xinshi Zang, Evangeline F. Y. Young, Martin D. F. Wong:
TRPlaceFPGA-MP: A Two-Stage Reinforcement Learning Framework for Fast FPGA Macro Placer. 83-90 - Zhihan Xu, Rajgopal Kannan, Viktor K. Prasanna:
FAME: FPGA Acceleration of Secure Matrix Multiplication with Homomorphic Encryption. 100-109 - Muhammad Shakeel Akram, Bogaraju Sharatchandra Varma, Vincent Meyers, Mehdi B. Tahoori, Dewar Finlay:
F2Opt: Novel Fine-Tuning and Folding Algorithms for FPGA-Based DNN Accelerators. 110-119 - Tong Wu, Niall Emmart, Oliver Diessel:
AffiNiTy: A Multi-Scalar Multiplication Accelerator with a Novel Batched Inversion Architecture. 130-138 - Zexuan Deng, Han Jiao, Wenjin Huang, Yihua Huang:
EViL: An Efficient Vision-LSTM Accelerator Based on FPGA. 139-143 - Manno Versluis, Yizhuo Wu, Chang Gao:
SparseDPD: A Sparse Neural Network-Based Digital Predistortion FPGA Accelerator for RF Power Amplifier Linearization. 154-158 - Sadegh Yazdanshenas, Jeffrey Chromczak:
Routing Struggle: A Metric to Quantify Routability. 186-194 - Haoran Wu, Ce Guo, Wayne Luk, Robert Mullins:
Aspo: Constraint-Aware Bayesian Optimization for Fpga-Based Soft Processors. 195-203 - Nicolai Fiege, Peter Zipf:
Improving Boolean Satisfiability-Based Modulo Scheduling. 204-212 - Martin Langhammer, Bogdan Pasca:
Maximum FPGA: A 32K-Point 32-Parallel Floating Point FFT. 213-221 - Gavin Lusby, Nachiket Kapre:
Cocotb-Pynq: Co-Simulating Python+RTL Applications Targeting Pynq Platforms with Cocotb. 222-226 - Jiacheng Cao, Jiaqi Guo, Wei Xiong, Huanlin Luo, Jian Wang, Jinmei Lai:
EQViTA: an End-To-End Quantized Vision Transformer Accelerator Implemented on Resource-Constrained FPGAs. 227-235 - Miyuru Thathsara, Damith Anhettigama, Siew-Kei Lam:
FPGA Stereo Visual Slam with Efficient Stereo Feature Matching and Key-Frame Generation. 236-244 - Wei Xiong, Jianfan Zhang, Xingzhe Zhu, Jiacheng Cao, Jian Wang, Jinmei Lai:
A High-Performance and Resource-Efficient FPGA-Based Multi-Object Tracking System Using Event Cameras. 245-253 - Satwant Singh, Michael Schneider, Ziad Aboud, Jonathan Peterson, Senani Gunaratna, Ting Yew, Cindy Lee, Rick Crotty:
Four-Input Lookup Table (LUT4) and Architectural Enhancements Enable Power Efficient Mid-Range FPGAs. 254-262 - Can Xiao, Jianyi Cheng, Yiren Zhao:
Refining Datapath for Microscaling ViTs. 263-272 - Ahmad Othman, Darmen Ilyas, Ahmed Kamaleldin, Diana Göhringer:
Towards Instruction-Controlled In-Pipeline GEMM Acceleration in a Dual-Issue RISC-V Core for Edge Applications. 273-281 - Riadh Ben Abdelhamid, Vladislav Válek, Kevin Klein, Dirk Koch:
Design Space Exploration of Fast RISC-V Processors for Scalable Kilo-Core FPGA Systems. 282-290 - Vladislav Válek, Martin Spinler, Jakub Cabal, Tomás Martínek:
DMA Calypte: Open-Source Ultra-Low Latency DMA Engine for FPGAs. 291-295 - Mugdha P. Jadhao, Alan T. L. Bacellar, Shashank Nag, Igor D. S. Miranda, Felipe M. G. França, Lizy K. John:
Hybrid Weightless Neural Networks for Efficient Edge Inference. 296-304 - Jude Haris, José Cano:
Accelerating Transposed Convolutions on FPGA-Based Edge Devices. 305-313 - Carol Jingyi Li, Ruilin Wu, Philip H. W. Leong:
AMD Versal Implementations of FAM and SSCA Estimators. 314-322 - Kaustubh Manohar Mhatre, Endri Taka, Aman Arora:
GAMA: High-Performance GEMM Acceleration on AMD Versal ML-Optimized AI Engines. 323-331 - Hyeonguk Jang, Sukho Lee, Jae-Jin Lee, Kyuseung Han:
NeuGEMM: A Reordering-Free Unified GEMM-Conv2D Accelerator for Lightweight Neuromorphic Processors. 332-336 - Eleonora Cabai, Giuseppe Sorrentino, Marco Domenico Santambrogio, Davide Conficconi:
Accelerating K-Means: A Vectorized Approach for AI Engines & Neural Processing Units. 337-341 - Pedro Henrique Di Francia Rosso, Guido Araujo:
Maximizing Resource Utilization for Stencil Computing. 348-349 - Taku Nishikawa, Koichi Marumo, Shinichi Yamagiwa:
Performance Impact on Reducing Energy Consumption Applying Adaptive Stream-Based Entropy Coding on FPGA. 355 - Lukas Stasytis, Felix Jentzsch, Zsolt István:
Analytical Buffer Sizing for Neural Network Inference Applications on FPGAs. 356 - David Vodák, Oliver Gurka, Jirí Matousek, Daniel Kondys:
Connection Tracking at 400 Gbps. 361
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