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ORCID10. IDT 2015: Dead Sea, Amman, Jordan
- 10th International Design & Test Symposium, IDT 2015, Dead Sea, Amman, Jordan, December 14-16, 2015. IEEE 2015, ISBN 978-1-4673-9994-4
- Hanna Windele:
Keynote 1: "Merger mania". 1 - Said Hamdioui:
Keynote 2: "Computing for big-data: Beyond CMOS and beyond Von-Neumann". 1 - Yervant Zorian:
Keynote 3: "Ensuring robustness in today's IoT era". 1
Invited
Special Session 1: HW Security and Reliability
- Muhammad Yasin
, Ozgur Sinanoglu:
Transforming between logic locking and IC camouflaging. 1-4 - Nektarios Georgios Tsoutsos, Michail Maniatakos:
Obfuscated arbitrary computation using cryptographic primitives. 5-8 - Hussam Amrouch, Jörg Henkel:
Reliability degradation in the scope of aging - From physical to system level. 9-12
Special Session 2: Validation and Verification
- Ra'ed Al-Omari, Shahil Rais:
Revolutionizing validation: The Intel approach for TTM. 13 - Mohamed Abdelsalam, Ashraf Salem:
SoC verification platforms using HW emulation and co-modeling Testbench technologies. 14-19
Regular papers
Session 1: Multi-Core Architectures
- Mwaffaq Otoom, JoAnn M. Paul:
Chip-level programming of heterogeneous multiprocessors. 20-25 - Mariem Makni, Mouna Baklouti, Smaïl Niar, Morteza Biglari-Abhari, Mohamed Abid:
Heterogeneous multi-core architecture for a 4G communication in high-speed railway. 26-31 - Imran Ashraf, Mottaqiallah Taouil, Koen Bertels:
Memory profiling for intra-application data-communication quantification: A survey. 32-37
Session 2: Analog Design
- Khaled A. El-Gammal, Ahmed N. Hassan, Sameh A. Ibrahim:
A 10 Gbps ADC-based equalizer for serial I/O receiver. 38-43 - Mahitab F. Eladwy, Sameh A. Ibrahim, Mohamed Dessouky:
A low-temperature-coefficient curvature-compensated bandgap reference with mismatch attenuation. 44-48
Session 3: Simulation and Verification
- Hanan Tawfik, Mona Safar, Mohamed Abdel Salam, M. Watheq El-Kharashi, Ashraf Salem:
Toward the interfacing of systemC-AMS models with hardware-emulated platforms. 54-59 - Eman El Mandouh, Amr G. Wassal:
Guiding intelligent testbench automation using data mining and formal methods. 60-65
Session 4: Hardware Testing
- Raimund Ubar, Stephen Adeboye Oyeniran, Mario Schölzel, Heinrich Theodor Vierhaus:
Multiple fault testing in systems-on-chip with high-level decision diagrams. 66-71 - Silviu Folea, Szilárd Enyedi, Liviu Miclea, Horia Hedesiu:
Reconfigurable test platform for modular embedded systems in manufacturing processes. 72-77 - Hussam M. N. Al Hamadi, Amjad Gawanmeh, Mahmoud Al-Qutayri:
An automatic ECG generator for testing and evaluating ECG sensor algorithms. 78-83
Session 5: Data Management and Design Space Exploration
- Cheng Qian, Libo Huang, Peng Xie, Nong Xiao, Zhiying Wang:
Efficient data management on 3D stacked memory for big data applications. 84-89 - Braham Lotfi Mediouni, Smaïl Niar, Rachid Benmansour, Karima Benatchba, Mouloud Koudil:
A bi-objective heuristic for heterogeneous MPSoC design space exploration. 90-95 - Samir Ben Abid, Nejib Mediouni, Oussama Kallel, Salem Hasnaoui:
NRTBox: A Matlab Simulink toolbox for NoC switch performance evaluation and early architectural exploration using discrete event simulation. 96-99
Session 6: Reliability and Test
- Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor:
BTI analysis of SRAM write driver. 100-105 - Hao Luo, Mehrdad Nourani:
Aging and leakage tradeoff in VLSI circuits. 106-111 - Tanusree Kaibartta, Debesh K. Das:
Testing of 3D IC with minimum power using genetic algorithm. 112-117
Session 7: Built-in Self-Test
- Kosuke Sawaki, Satoshi Ohtake:
A method of LFSR seed generation for hierarchical BIST. 118-123 - Abdallatif S. Abu-Issa, Iyad K. Tumar, Wasel T. Ghanem:
SR-TPG: A low transition test pattern generator for test-per-clock and test-per-scan BIST. 124-128
Session 8: Hardware Security
- Arash Nejat, David Hély, Vincent Beroulle:
Facilitating side channel analysis by obfuscation for Hardware Trojan detection. 129-134 - Ahmed Bellemou, Mohamed Anane, Nadjia Benblidia, Mohamed Issad:
FPGA implementation of scalar multiplication over Fp for elliptic curve cryptosystem. 135-140
Posters Session
- Khaled Salah:
A novel wavelet-based method for TSV modeling. 141-142 - Nejib Mediouni, Samir Ben Abid, Oussama Kallel, Salem Hasnaoui:
High level NoC modeling using discrete event simulation. 143-144 - Khaled Fathy, Khaled Salah, Rafik Guindi:
A proposed methodology to improve UVM-based test generation and coverage closure. 147-148 - Nahla Mohamed, Mona Safar, Ayman M. Wahba, Ashraf Salem:
Automatic test pattern generation for virtual hardware model using constrained symbolic execution. 149-150 - Nejib Mediouni, Samir Ben Abid, Oussama Kallel, Salem Hasnaoui:
SimEvents based high level early design space exploration and modeling of a 3D Network on Chip. 157-158 - Venkata Narasimha Inukollu, Taeghyun Kang, Nina Sakhnini:
Design constraints and challenges behind fault tolerance systems in a mobile application framework. 159-160
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