Shunli Ma

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Fan Ye 0001

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Publications

2021
[j7]
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Manxin Li, Yuting Yao, Biao Hu, Jipeng Wei, Yong Chen, Shunli Ma, Fan Ye, Junyan Ren:
A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS. IEEE Access 9: 77545-77554 (2021)
2019
[c15]
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  - conf/asicon/YaoWLMYR19
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Yuting Yao, Jipeng Wei, Manxin Li, Shunli Ma, Fan Ye, Junyan Ren:
A 256MHz Analog Baseband Chain with tunable Bandwidth and Gain for UWB Receivers. ASICON 2019: 1-4
[c13]
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  - conf/iscas/WeiYLM0R19
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Jipeng Wei, Yuting Yao, Longheng Luo, Shunli Ma, Fan Ye, Junyan Ren:
A Novel Nauta Transconductor for Ultra-Wideband gm-C Filter with Temperature Calibration. ISCAS 2019: 1-4
2015
[c10]
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  - conf/asicon/AnMCZ0R15
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Fazhi An, Shunli Ma, Qian Chen, Guangyao Zhou, Fan Ye, Junyan Ren:
A wide-division-ratio 100MHz-to-5GHz multi-modulus divider chain for wide-band PLL. ASICON 2015: 1-4
[c9]
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  - conf/asicon/ChenAZM0R15
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Qian Chen, Fazhi An, Guangyao Zhou, Shunli Ma, Fan Ye, Junyan Ren:
A 39 GHz-80 GHz millimeter-wave frequency doubler with low power consumption in 65nm CMOS tehnology. ASICON 2015: 1-4
[c8]
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  - conf/asicon/ZhouMAL0R15
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Guangyao Zhou, Shunli Ma, Fazhi An, Ning Li, Fan Ye, Junyan Ren:
A 30-GHz to 39-GHz mm-Wave low-power injection-locked frequency divider in 65nm CMOS. ASICON 2015: 1-4
[c7]
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  - conf/esscirc/MaZJCCYR15
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Shunli Ma, Guangyao Zhou, Jianbing Jiang, Chixiao Chen, Yongzhen Chen, Fan Ye, Junyan Ren:
A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system. ESSCIRC 2015: 136-139
2014
[c5]
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  - conf/iscas/DaiCMYR14
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Guoxian Dai, Chixiao Chen, Shunli Ma, Fan Ye, Junyan Ren:
A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators. ISCAS 2014: 2365-2368

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