Synchronous latency-insensitive design for multiple clock domain.

Anders Edman Anders Edman Christer Svensson Behzad Mesgarzadeh Synchronous latency-insensitive design for multiple clock domain. 83-86 2005 SoCC https://doi.org/10.1109/SOCC.2005.1554462 conf/socc/2005 db/conf/socc/socc2005.html#EdmanSM05 Anders Edman Christer Svensson Timing closure through a globally synchronous, timing partitioned design methodology. 71-74 2004 conf/dac/2004 DAC https://doi.org/10.1145/996566.996586 db/conf/dac/dac2004.html#EdmanS04 Mikael Olausson Anders Edman Dake Liu Bit Memory Instructions for a General CPU. 215-218 2004 conf/iwsoc/2004 IWSOC https://doi.org/10.1109/IWSOC.2004.1319881 https://doi.ieeecomputersociety.org/10.1109/IWSOC.2004.1319881 db/conf/iwsoc/iwsoc2004.html#OlaussonEL04

Anders Edman Jacob Christensen 0002 Anders Emrich Christer Svensson A low-power 416-lag 1.5-b 0.5-TMAC correlator in 0.6-μm CMOS. 258-265 2001 36 IEEE J. Solid State Circuits 2 https://doi.org/10.1109/4.902766 db/journals/jssc/jssc36.html#EdmanCES01

Daniel Eckerbert Henrik Eriksson Per Larsson-Edefors Anders Edman An interconnect-driven design of a DFT processor. 569-572 2000 ISCAS https://doi.org/10.1109/ISCAS.2000.857498 conf/iscas/2000 db/conf/iscas/iscas2000.html#EckerbertELE00 Anders Åström Michael Hall Anders Edman A comparison of bit-serial and multi-bit processor elements in a real-time signal processing SIMD architecture. 245-250 1996 HiPC https://doi.org/10.1109/HIPC.1996.565830 https://doi.ieeecomputersociety.org/10.1109/HIPC.1996.565830 conf/hipc/1996 db/conf/hipc/hipc1996.html#AstromHE96 Anders Åström Jacob Christensen 0002 Daniel Eckerbert Anders Emrich Henrik Eriksson Michael Hall Per Larsson-Edefors Dake Liu Behzad Mesgarzadeh Mikael Olausson Christer Svensson