Sound event detection based on auxiliary decoder and maximum probability aggregation for DCASE Challenge 2024 Task 4.

Sang Won Son

Sang Won Son Jongyeon Park Hong Kook Kim Sulaiman Vesal Jeong Eun Lim Sound event detection based on auxiliary decoder and maximum probability aggregation for DCASE Challenge 2024 Task 4. 2024 abs/2406.12721 CoRR https://doi.org/10.48550/arXiv.2406.12721 db/journals/corr/corr2406.html#abs-2406-12721 streams/journals/corr

Ji Won Kim Sang Won Son Yoonah Song Hong Kook Kim Il Hoon Song Jeong Eun Lim Semi-supervsied Learning-based Sound Event Detection using Freuqency Dynamic Convolution with Large Kernel Attention for DCASE Challenge 2023 Task 4. 2023 abs/2306.06461 CoRR https://doi.org/10.48550/arXiv.2306.06461 db/journals/corr/corr2306.html#abs-2306-06461

Venumadhav Bhagavatula Fan Zhang Che-Chun Kuo Anirban Sarkar 0002 Ashutosh Verma Tienyu Chang Xiaohua Yu Daeyoung Yoon Ivan Siu-Chuang Lu Sang Won Son Thomas Byunghak Cho A 5G FR2 Power-Amplifier With an Integrated Power-Detector for Closed-Loop EIRP Control. 1257-1266 2022 57 IEEE J. Solid State Circuits 5 https://doi.org/10.1109/JSSC.2022.3146872 db/journals/jssc/jssc57.html#BhagavatulaZKSV22

Ashutosh Verma Venumadhav Bhagavatula Amitoj Singh Wanghua Wu Hariharan Nagarajan Pak-Kim Lau Xiaohua Yu Omar Elsayed Ajaypat Jain Anirban Sarkar 0002 Fan Zhang Che-Chun Kuo Patrick McElwee Pei-Yuan Chiang Chengkai Guo Zhanjun Bai Tienyu Chang Abishek Mann Andreas Rydin Xingliang Zhao Jeiyoung Lee Daeyoung Yoon Chih-Wei Yao Siuchuang-Ivan Lu Sang Won Son Thomas Byunghak Cho A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW. 1-3 2022 ISSCC https://doi.org/10.1109/ISSCC42614.2022.9731664 conf/isscc/2022 db/conf/isscc/isscc2022.html#VermaBSWNLYEJSZ22

Wanghua Wu Chih-Wei Yao Chengkai Guo Pei-Yuan Chiang Lei Chen Pak-Kim Lau Zhanjun Bai Sang Won Son Thomas Byunghak Cho A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO. 3756-3767 2021 56 IEEE J. Solid State Circuits 12 https://doi.org/10.1109/JSSC.2021.3111134 db/journals/jssc/jssc56.html#WuYGCCLBSC21

Wanghua Wu Chih-Wei Yao Chengkai Guo Pei-Yuan Chiang Pak-Kim Lau Lei Chen Sang Won Son Thomas Byunghak Cho 32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels. 444-446 2021 ISSCC https://doi.org/10.1109/ISSCC42613.2021.9365850 conf/isscc/2021 db/conf/isscc/isscc2021.html#WuYGCLCSC21

Wanghua Wu Chih-Wei Yao Kunal Godbole Ronghua Ni Pei-Yuan Chiang Yongping Han Yongrong Zuo Ashutosh Verma Ivan Siu-Chuang Lu Sang Won Son Thomas Byunghak Cho A 28-nm 75-fs<sub>rms</sub> Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction. 1254-1265 2019 54 IEEE J. Solid State Circuits 5 https://doi.org/10.1109/JSSC.2019.2899726 db/journals/jssc/jssc54.html#WuYGNCHZVLSC19

Chih-Wei Yao Ronghua Ni Chung Lau Wanghua Wu Kunal Godbole Yongrong Zuo Sangsoo Ko Nam-Seog Kim 0001 Sangwook Han Ikkyun Jo Joonhee Lee Juyoung Han Daehyeon Kwon Chulho Kim Shinwoong Kim Sang Won Son Thomas Byunghak Cho A 14-nm 0.14-ps<sub>rms</sub> Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration. 3446-3457 2017 52 IEEE J. Solid State Circuits 12 https://doi.org/10.1109/JSSC.2017.2742518 db/journals/jssc/jssc52.html#YaoNLWGZKKHJLHK17

Venumadhav Bhagavatula Dae Hyun Kwon Jaehun Lee Quang-Diep Bui Jeong-Hyun Choi Siuchuang-Ivan Lu Sang Won Son 13.3 A SAW-less reconfigurable multimode transmitter with a voltage-mode harmonic-reject mixer in 14nm FinFET CMOS. 220-221 2017 ISSCC https://doi.org/10.1109/ISSCC.2017.7870340 conf/isscc/2017 db/conf/isscc/isscc2017.html#BhagavatulaKLBC17 Chih-Wei Yao Wing Fai Loke Ronghua Ni Yongping Han Haoyang Li Kunal Godbole Yongrong Zuo Sangsoo Ko Nam-Seog Kim 0001 Sangwook Han Ikkyun Jo Joonhee Lee Juyoung Han Daehyeon Kwon Chulho Kim Shinwoong Kim Sang Won Son Thomas Byunghak Cho 24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and -78dBc fractional spur for cellular RFICs. 422-423 2017 ISSCC https://doi.org/10.1109/ISSCC.2017.7870441 conf/isscc/2017 db/conf/isscc/isscc2017.html#YaoLNHLGZKKHJLH17

Siddharth Seth Dae Hyun Kwon Sriramkumar Venugopalan Sang Won Son Yongrong Zuo Venumadhav Bhagavatula Jaehyun Lim Dongjin Oh Thomas Byunghak Cho A Dynamically Biased Multiband 2G/3G/4G Cellular Transmitter in 28 nm CMOS. 1096-1108 2016 51 IEEE J. Solid State Circuits 5 https://doi.org/10.1109/JSSC.2015.2510023 db/journals/jssc/jssc51.html#SethKVSZBLOC16

Zhanjun Bai Venumadhav Bhagavatula Quang-Diep Bui Tienyu Chang Lei Chen Pei-Yuan Chiang Thomas Byunghak Cho Jeong-Hyun Choi Omar Elsayed Kunal Godbole Chengkai Guo Juyoung Han Sangwook Han Yongping Han Ajaypat Jain Ikkyun Jo Chulho Kim Hong Kook Kim Ji Won Kim Nam-Seog Kim 0001 Shinwoong Kim Sangsoo Ko Che-Chun Kuo Dae Hyun Kwon Daehyeon Kwon Chung Lau Pak-Kim Lau Jaehun Lee Jeiyoung Lee Joonhee Lee Haoyang Li Jaehyun Lim Jeong Eun Lim Wing Fai Loke Ivan Siu-Chuang LuSiuchuang-Ivan Lu Abishek Mann Patrick McElwee Hariharan Nagarajan Ronghua Ni Dongjin Oh Jongyeon Park Andreas Rydin Anirban Sarkar 0002 Siddharth Seth Amitoj Singh Il Hoon Song Yoonah Song Sriramkumar Venugopalan Ashutosh Verma Sulaiman Vesal Wanghua Wu Chih-Wei Yao Daeyoung Yoon Xiaohua Yu Fan Zhang Xingliang Zhao Yongrong Zuo