<?xml version="1.0"?>
<dblpperson name="Chin-I Su" pid="232/6757" n="9">
<person key="homepages/232/6757" mdate="2019-01-07">
<author pid="232/6757">Chin-I Su</author>
</person>
<r><article key="journals/jssc/HungWHHCSKLLHTC23" mdate="2025-11-15">
<author pid="263/0656">Je-Min Hung</author>
<author pid="316/3699">Tai-Hao Wen</author>
<author pid="235/2373">Yen-Hsiang Huang</author>
<author pid="263/0535">Sheng-Po Huang</author>
<author pid="68/1232">Fu-Chun Chang</author>
<author pid="232/6757">Chin-I Su</author>
<author pid="176/6156">Win-San Khwa</author>
<author orcid="0000-0001-7737-7250" pid="148/4759">Chung-Chuan Lo</author>
<author pid="124/2061">Ren-Shuo Liu</author>
<author orcid="0000-0003-4070-5059" pid="30/9427">Chih-Cheng Hsieh</author>
<author orcid="0000-0002-9689-1236" pid="14/9801">Kea-Tiong Tang</author>
<author pid="79/10249">Yu-Der Chih</author>
<author pid="196/1851">Tsung-Yung Jonathan Chang</author>
<author orcid="0000-0001-6905-6350" pid="89/6934">Meng-Fan Chang</author>
<title>8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices.</title>
<pages>303-315</pages>
<year>2023</year>
<volume>58</volume>
<journal>IEEE J. Solid State Circuits</journal>
<number>1</number>
<ee>https://doi.org/10.1109/JSSC.2022.3200515</ee>
<url>db/journals/jssc/jssc58.html#HungWHHCSKLLHTC23</url>
</article>
</r>
<r><inproceedings key="conf/vlsit/WenHHWCLCSKWLLH23" mdate="2024-02-20">
<author pid="316/3699">Tai-Hao Wen</author>
<author pid="263/0656">Je-Min Hung</author>
<author pid="352/8151">Hung-Hsi Hsu</author>
<author pid="41/5176-9">Yuan Wu 0009</author>
<author pid="68/1232">Fu-Chun Chang</author>
<author pid="316/3362">Chung-Yuan Li</author>
<author pid="341/5208">Chih-Han Chien</author>
<author pid="232/6757">Chin-I Su</author>
<author pid="176/6156">Win-San Khwa</author>
<author pid="15/10711">Jui-Jen Wu</author>
<author pid="148/4759">Chung-Chuan Lo</author>
<author pid="124/2061">Ren-Shuo Liu</author>
<author pid="30/9427">Chih-Cheng Hsieh</author>
<author pid="14/9801">Kea-Tiong Tang</author>
<author pid="158/9037">Mon-Shu Ho</author>
<author pid="79/10249">Yu-Der Chih</author>
<author pid="196/1851">Tsung-Yung Jonathan Chang</author>
<author pid="89/6934">Meng-Fan Chang</author>
<title>A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices.</title>
<pages>1-2</pages>
<year>2023</year>
<booktitle>VLSI Technology and Circuits</booktitle>
<ee>https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185326</ee>
<crossref>conf/vlsit/2023</crossref>
<url>db/conf/vlsit/vlsit2023.html#WenHHWCLCSKWLLH23</url>
</inproceedings>
</r>
<r><inproceedings key="conf/isscc/HungHHCWSKLLHTC22" mdate="2025-11-15">
<author pid="263/0656">Je-Min Hung</author>
<author pid="235/2373">Yen-Hsiang Huang</author>
<author pid="263/0535">Sheng-Po Huang</author>
<author pid="68/1232">Fu-Chun Chang</author>
<author pid="316/3699">Tai-Hao Wen</author>
<author pid="232/6757">Chin-I Su</author>
<author pid="176/6156">Win-San Khwa</author>
<author orcid="0000-0001-7737-7250" pid="148/4759">Chung-Chuan Lo</author>
<author pid="124/2061">Ren-Shuo Liu</author>
<author pid="30/9427">Chih-Cheng Hsieh</author>
<author pid="14/9801">Kea-Tiong Tang</author>
<author pid="79/10249">Yu-Der Chih</author>
<author pid="196/1851">Tsung-Yung Jonathan Chang</author>
<author pid="89/6934">Meng-Fan Chang</author>
<title>An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices.</title>
<pages>1-3</pages>
<year>2022</year>
<booktitle>ISSCC</booktitle>
<ee>https://doi.org/10.1109/ISSCC42614.2022.9731715</ee>
<crossref>conf/isscc/2022</crossref>
<url>db/conf/isscc/isscc2022.html#HungHHCWSKLLHTC22</url>
</inproceedings>
</r>
<r><article key="journals/jssc/LiW00LSCTCCSKB21" mdate="2026-01-29">
<author orcid="0000-0001-6070-6310" pid="164/4195-1">Ziyun Li 0001</author>
<author orcid="0000-0001-5112-639X" pid="216/3667">Zhehong Wang</author>
<author orcid="0000-0001-5968-5751" pid="85/2168-6">Li Xu 0006</author>
<author orcid="0000-0002-1380-269X" pid="98/783-1">Qing Dong 0001</author>
<author orcid="0000-0002-4194-8119" pid="41/1201-1">Bowen Liu 0001</author>
<author pid="232/6757">Chin-I Su</author>
<author pid="115/7013">Wen-Ting Chu</author>
<author pid="273/0370">George Tsou</author>
<author pid="79/10249">Yu-Der Chih</author>
<author pid="196/1851">Tsung-Yung Jonathan Chang</author>
<author orcid="0000-0003-2598-0458" pid="83/6040">Dennis Sylvester</author>
<author orcid="0000-0002-6658-5502" pid="77/6653">Hun-Seok Kim</author>
<author orcid="0000-0001-6744-7075" pid="b/DBlaauw">David T. Blaauw</author>
<title>RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator.</title>
<pages>1105-1115</pages>
<year>2021</year>
<volume>56</volume>
<journal>IEEE J. Solid State Circuits</journal>
<number>4</number>
<ee>https://doi.org/10.1109/JSSC.2020.3045369</ee>
<url>db/journals/jssc/jssc56.html#LiW00LSCTCCSKB21</url>
</article>
</r>
<r><inproceedings key="conf/isscc/XueHKHHCCLJSKLL21" mdate="2025-11-15">
<author pid="216/3418">Cheng-Xin Xue</author>
<author pid="263/0656">Je-Min Hung</author>
<author pid="237/0958">Hui-Yao Kao</author>
<author pid="235/2373">Yen-Hsiang Huang</author>
<author pid="263/0535">Sheng-Po Huang</author>
<author pid="68/1232">Fu-Chun Chang</author>
<author pid="27/7017">Peng Chen</author>
<author pid="205/0213">Ta-Wei Liu</author>
<author pid="287/1810">Chuan-Jia Jhang</author>
<author pid="232/6757">Chin-I Su</author>
<author pid="176/6156">Win-San Khwa</author>
<author orcid="0000-0001-7737-7250" pid="148/4759">Chung-Chuan Lo</author>
<author pid="124/2061">Ren-Shuo Liu</author>
<author pid="30/9427">Chih-Cheng Hsieh</author>
<author pid="14/9801">Kea-Tiong Tang</author>
<author pid="79/10249">Yu-Der Chih</author>
<author pid="196/1851">Tsung-Yung Jonathan Chang</author>
<author pid="89/6934">Meng-Fan Chang</author>
<title>A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices.</title>
<pages>245-247</pages>
<year>2021</year>
<booktitle>ISSCC</booktitle>
<ee>https://doi.org/10.1109/ISSCC42613.2021.9365769</ee>
<crossref>conf/isscc/2021</crossref>
<url>db/conf/isscc/isscc2021.html#XueHKHHCCLJSKLL21</url>
</inproceedings>
</r>
<r><inproceedings key="conf/vlsic/ChouLLSTCTCOCCC20" mdate="2020-08-24">
<author pid="216/3542">Chung-Cheng Chou</author>
<author pid="216/3890">Zheng-Jun Lin</author>
<author pid="19/9675">Chien-An Lai</author>
<author pid="232/6757">Chin-I Su</author>
<author pid="156/4962">Pei-Ling Tseng</author>
<author pid="21/11438">Wei-Chi Chen</author>
<author pid="167/5232">Wu-Chin Tsai</author>
<author pid="115/7013">Wen-Ting Chu</author>
<author pid="01/5170">Tong-Chern Ong</author>
<author pid="228/7054">Harry Chuang</author>
<author pid="79/10249">Yu-Der Chih</author>
<author pid="196/1851">Tsung-Yung Jonathan Chang</author>
<title>A 22nm 96KX144 RRAM Macro with a Self-Tracking Reference and a Low Ripple Charge Pump to Achieve a Configurable Read Window and a Wide Operating Voltage Range.</title>
<pages>1-2</pages>
<year>2020</year>
<booktitle>VLSI Circuits</booktitle>
<ee>https://doi.org/10.1109/VLSICircuits18222.2020.9163014</ee>
<crossref>conf/vlsic/2020</crossref>
<url>db/conf/vlsic/vlsic2020.html#ChouLLSTCTCOCCC20</url>
</inproceedings>
</r>
<r><inproceedings key="conf/vlsic/WangLX0SCTCCSKB20" mdate="2026-01-30">
<author pid="216/3667">Zhehong Wang</author>
<author pid="164/4195-1">Ziyun Li 0001</author>
<author orcid="0000-0001-5968-5751" pid="85/2168-6">Li Xu 0006</author>
<author pid="98/783-1">Qing Dong 0001</author>
<author pid="232/6757">Chin-I Su</author>
<author pid="115/7013">Wen-Ting Chu</author>
<author pid="273/0370">George Tsou</author>
<author pid="79/10249">Yu-Der Chih</author>
<author pid="196/1851">Tsung-Yung Jonathan Chang</author>
<author pid="83/6040">Dennis Sylvester</author>
<author pid="77/6653">Hun-Seok Kim</author>
<author pid="b/DBlaauw">David T. Blaauw</author>
<title>An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24&#215;1 Mb eRRAM.</title>
<pages>1-2</pages>
<year>2020</year>
<booktitle>VLSI Circuits</booktitle>
<ee>https://doi.org/10.1109/VLSICircuits18222.2020.9162811</ee>
<crossref>conf/vlsic/2020</crossref>
<url>db/conf/vlsic/vlsic2020.html#WangLX0SCTCCSKB20</url>
</inproceedings>
</r>
<r><inproceedings key="conf/asscc/LaiCWLTWWSCLOCC18" mdate="2019-01-07">
<author pid="19/9675">Chien-An Lai</author>
<author pid="216/3542">Chung-Cheng Chou</author>
<author pid="232/6695">Chi-Hsiang Weng</author>
<author pid="216/3890">Zheng-Jun Lin</author>
<author pid="156/4962">Pei-Ling Tseng</author>
<author pid="232/6760">Chien-Fan Wang</author>
<author pid="232/6696">Chih-Chen Wang</author>
<author pid="232/6757">Chin-I Su</author>
<author pid="21/11438">Wei-Chi Chen</author>
<author pid="93/6225">Yu-Cheng Lin</author>
<author pid="01/5170">Tong-Chern Ong</author>
<author pid="17/289">Chi Chang</author>
<author pid="79/10249">Yu-Der Chih</author>
<author pid="196/1851">Tsung-Yung Jonathan Chang</author>
<title>Logic Process Compatible 40nm 256K&#215;144 Embedded RRAM with Low Voltage Current Limiter and Ambient Compensation Scheme to Improve the Read Window.</title>
<pages>13-16</pages>
<year>2018</year>
<booktitle>A-SSCC</booktitle>
<ee>https://doi.org/10.1109/ASSCC.2018.8579345</ee>
<crossref>conf/asscc/2018</crossref>
<url>db/conf/asscc/asscc2018.html#LaiCWLTWWSCLOCC18</url>
</inproceedings>
</r>
<r><inproceedings key="conf/ieeesensors/TranCSZ16" mdate="2023-12-13">
<author pid="336/1362">Trong-Hieu Tran</author>
<author pid="21/10668-1">Paul C.-P. Chao 0001</author>
<author pid="232/6757">Chin-I Su</author>
<author pid="143/3981">Hsiao-Wen Zan</author>
<title>A fast readout circuit for an organic vertical nano-junction sensor.</title>
<pages>1-3</pages>
<year>2016</year>
<booktitle>IEEE SENSORS</booktitle>
<ee>https://doi.org/10.1109/ICSENS.2016.7808665</ee>
<crossref>conf/ieeesensors/2016</crossref>
<url>db/conf/ieeesensors/ieeesensors2016.html#TranCSZ16</url>
</inproceedings>
</r>
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<co c="0"><na f="c/Chang:Chi" pid="17/289">Chi Chang</na></co>
<co c="0"><na f="c/Chang:Fu=Chun" pid="68/1232">Fu-Chun Chang</na></co>
<co c="0"><na f="c/Chang:Meng=Fan" pid="89/6934">Meng-Fan Chang</na></co>
<co c="0"><na f="c/Chang:Tsung=Yung_Jonathan" pid="196/1851">Tsung-Yung Jonathan Chang</na></co>
<co c="1"><na f="c/Chao_0001:Paul_C==P=" pid="21/10668-1">Paul C.-P. Chao 0001</na></co>
<co c="0"><na f="c/Chen:Peng" pid="27/7017">Peng Chen</na></co>
<co c="0"><na f="c/Chen:Wei=Chi" pid="21/11438">Wei-Chi Chen</na></co>
<co c="0"><na f="c/Chien:Chih=Han" pid="341/5208">Chih-Han Chien</na></co>
<co c="0"><na f="c/Chih:Yu=Der" pid="79/10249">Yu-Der Chih</na></co>
<co c="0"><na f="c/Chou:Chung=Cheng" pid="216/3542">Chung-Cheng Chou</na></co>
<co c="0"><na f="c/Chu:Wen=Ting" pid="115/7013">Wen-Ting Chu</na></co>
<co c="0"><na f="c/Chuang:Harry" pid="228/7054">Harry Chuang</na></co>
<co c="0"><na f="d/Dong_0001:Qing" pid="98/783-1">Qing Dong 0001</na></co>
<co c="0"><na f="h/Ho:Mon=Shu" pid="158/9037">Mon-Shu Ho</na></co>
<co c="0"><na f="h/Hsieh:Chih=Cheng" pid="30/9427">Chih-Cheng Hsieh</na></co>
<co c="0"><na f="h/Hsu:Hung=Hsi" pid="352/8151">Hung-Hsi Hsu</na></co>
<co c="0"><na f="h/Huang:Sheng=Po" pid="263/0535">Sheng-Po Huang</na></co>
<co c="0"><na f="h/Huang:Yen=Hsiang" pid="235/2373">Yen-Hsiang Huang</na></co>
<co c="0"><na f="h/Hung:Je=Min" pid="263/0656">Je-Min Hung</na></co>
<co c="0"><na f="j/Jhang:Chuan=Jia" pid="287/1810">Chuan-Jia Jhang</na></co>
<co c="0"><na f="k/Kao:Hui=Yao" pid="237/0958">Hui-Yao Kao</na></co>
<co c="0"><na f="k/Khwa:Win=San" pid="176/6156">Win-San Khwa</na></co>
<co c="0"><na f="k/Kim:Hun=Seok" pid="77/6653">Hun-Seok Kim</na></co>
<co c="0"><na f="l/Lai:Chien=An" pid="19/9675">Chien-An Lai</na></co>
<co c="0"><na f="l/Li:Chung=Yuan" pid="316/3362">Chung-Yuan Li</na></co>
<co c="0"><na f="l/Li_0001:Ziyun" pid="164/4195-1">Ziyun Li 0001</na></co>
<co c="0"><na f="l/Lin:Yu=Cheng" pid="93/6225">Yu-Cheng Lin</na></co>
<co c="0"><na f="l/Lin:Zheng=Jun" pid="216/3890">Zheng-Jun Lin</na></co>
<co c="0"><na f="l/Liu_0001:Bowen" pid="41/1201-1">Bowen Liu 0001</na></co>
<co c="0"><na f="l/Liu:Ren=Shuo" pid="124/2061">Ren-Shuo Liu</na></co>
<co c="0"><na f="l/Liu:Ta=Wei" pid="205/0213">Ta-Wei Liu</na></co>
<co c="0"><na f="l/Lo:Chung=Chuan" pid="148/4759">Chung-Chuan Lo</na></co>
<co c="0"><na f="o/Ong:Tong=Chern" pid="01/5170">Tong-Chern Ong</na></co>
<co c="0"><na f="s/Sylvester:Dennis" pid="83/6040">Dennis Sylvester</na></co>
<co c="0"><na f="t/Tang:Kea=Tiong" pid="14/9801">Kea-Tiong Tang</na></co>
<co c="1"><na f="t/Tran:Trong=Hieu" pid="336/1362">Trong-Hieu Tran</na></co>
<co c="0"><na f="t/Tsai:Wu=Chin" pid="167/5232">Wu-Chin Tsai</na></co>
<co c="0"><na f="t/Tseng:Pei=Ling" pid="156/4962">Pei-Ling Tseng</na></co>
<co c="0"><na f="t/Tsou:George" pid="273/0370">George Tsou</na></co>
<co c="0"><na f="w/Wang:Chien=Fan" pid="232/6760">Chien-Fan Wang</na></co>
<co c="0"><na f="w/Wang:Chih=Chen" pid="232/6696">Chih-Chen Wang</na></co>
<co c="0"><na f="w/Wang:Zhehong" pid="216/3667">Zhehong Wang</na></co>
<co c="0"><na f="w/Wen:Tai=Hao" pid="316/3699">Tai-Hao Wen</na></co>
<co c="0"><na f="w/Weng:Chi=Hsiang" pid="232/6695">Chi-Hsiang Weng</na></co>
<co c="0"><na f="w/Wu:Jui=Jen" pid="15/10711">Jui-Jen Wu</na></co>
<co c="0"><na f="w/Wu_0009:Yuan" pid="41/5176-9">Yuan Wu 0009</na></co>
<co c="0"><na f="x/Xu_0006:Li" pid="85/2168-6">Li Xu 0006</na></co>
<co c="0"><na f="x/Xue:Cheng=Xin" pid="216/3418">Cheng-Xin Xue</na></co>
<co c="1"><na f="z/Zan:Hsiao=Wen" pid="143/3981">Hsiao-Wen Zan</na></co>
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