A 3nm FinFET 2.2Gsearch/s 0.305fJ/b TCAM with Dynamically Gated Search Lines for Data-Center ASICs.

Chetan Deshpande Sushil Kumar Gajanan Jedhe Chetan Deshpande Agastya Gouoi Phoebe Su Kim Soon Jway TzeYing Seoh A 3nm FinFET 2.2Gsearch/s 0.305fJ/b TCAM with Dynamically Gated Search Lines for Data-Center ASICs. 496-498 2025 ISSCC https://doi.org/10.1109/ISSCC49661.2025.10904633 conf/isscc/2025 db/conf/isscc/isscc2025.html#KumarJDGSJS25 En-Jui Chang Cheng-Xin Xue Chetan Deshpande Gajanan Jedhe Jenwei Liang Chih-Chung Cheng Hung-Wei Lin Chia-Da Lee Sushil Kumar Kim Soon Jway Zijie Guo Ritesh Garg Allen-Cl Lu Chien-Hung Lin Meng-Han Hsieh Tsung-Yao Lin Chih-Cheng Chen A 12-nm 0.62-1.61 mW Ultra-Low Power Digital CIM-based Deep-Learning System for End-to-End Always-on Vision. 1-2 2023 VLSI Technology and Circuits https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185296 conf/vlsit/2023 db/conf/vlsit/vlsit2023.html#ChangXDJLCLLKJG23 Gajanan Jedhe Chetan Deshpande Sushil Kumar Cheng-Xin Xue Zijie Guo Ritesh Garg Kim Soon Jway En-Jui Chang Jenwei Liang Zhe Wan Zhenhao Pan A 12nm 137 TOPS/W Digital Compute-In-Memory using Foundry 8T SRAM Bitcell supporting 16 Kernel Weight Sets for AI Edge Applications. 1-2 2023 VLSI Technology and Circuits https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185253 conf/vlsit/2023 db/conf/vlsit/vlsit2023.html#JedheDKXGGJCLWP23 Chetan Deshpande Ritesh Garg Gajanan Jedhe Gaurang Narvekar Sushil Kumar A 5nm Fin-FET 2G-search/s 512-entry x 220-bit TCAM with Single Cycle Entry Update Capability for Data Center ASICs. 1-2 2021 VLSI Circuits https://doi.org/10.23919/VLSICircuits52068.2021.9492464 conf/vlsic/2021 db/conf/vlsic/vlsic2021.html#DeshpandeGJNK21 En-Jui Chang Chih-Cheng Chen Chih-Chung Cheng Ritesh Garg Agastya Gouoi Zijie Guo Meng-Han Hsieh Gajanan Jedhe Kim Soon Jway Sushil Kumar Chia-Da Lee Jenwei Liang Chien-Hung Lin Hung-Wei Lin Tsung-Yao Lin Allen-Cl Lu Gaurang Narvekar Zhenhao Pan TzeYing Seoh Phoebe Su Zhe Wan Cheng-Xin Xue