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Sehyeon Chung

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2020 – today

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2026
[c12]
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  - conf/aspdac/SeoCCCK26
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Hyunbae Seo, Handong Cho, Sehyeon Chung, Kyu-Myung Choi, Taewhan Kim:
ML-driven Design Technology Co-Optimization Framework for Advanced Technology Nodes. ASP-DAC 2026: 29-34
[c11]
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Hyunbae Seo, Sehyeon Chung, Taewhan Kim:
Enhancing Pin Accessibility Through Pin Pattern Migration and Optimization Across Cell Boundaries. ASP-DAC 2026: 1280-1286
2025
[c10]
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Sehyeon Chung, Hyun-chul Hwang, Byung Su Kim, Jaeha Lee, Kunhyuk Kang, Taewhan Kim:
Late Breaking Results: Utilization of Hybrid Threshold-Voltage Flip-flops for Power Recovery. DAC 2025: 1-2
[c9]
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Jaehoon Ahn, Sehyeon Chung, Taewhan Kim:
Adaptive Pin Pattern Modification on Standard Cells Towards ECO Routing. ICCAD 2025: 1-9
[c8]
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Sehyeon Chung, Hyunbae Seo, Taewhan Kim:
Synthesis of Standard Cells of Minimum Delay. ICCAD 2025: 1-8
[c7]
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Yeongyeong Shin, Sehyeon Chung, Taewhan Kim:
Timing-Driven Multi-Bit Flip-Flop Allocation Utilizing Design-Technology Co-Optimization Techniques. ICCD 2025: 416-423
2024
[c6]
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Handong Cho, Hyunbae Seo, Sehyeon Chung, Kyu-Myung Choi, Taewhan Kim:
Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes. DATE 2024: 1-6
[c5]
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  - conf/iccad/ChungSCC024
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Sehyeon Chung, Hyunbae Seo, Handong Cho, Kyumyung Choi, Taewhan Kim:
Optimal Layout Synthesis of Multi-Row Standard Cells for Advanced Technology Nodes. ICCAD 2024: 38:1-38:8
2023
[c4]
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Jooyeon Jeong, Sehyeon Chung, Kyeongrok Jo, Taewhan Kim:
Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility. DATE 2023: 1-6
2022
[j1]
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Sehyeon Chung, Taewhan Kim:
ECO routing based on network flow method. Integr. 86: 1-8 (2022)
[c3]
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Sehyeon Chung, Jooyeon Jeong, Taewhan Kim:
Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis. ISLPED 2022: 17:1-17:6
[c2]
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Suwan Kim, Sehyeon Chung, Taewhan Kim, Heechun Park:
Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs. ISLPED 2022: 26:1-26:6
2021
[c1]
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Jaejoon Yoon, Sehyeon Chung, Taewhan Kim:
Analyses of Power Staple Inserting Methodologies for Mitigating IR-Drops. ISOCC 2021: 169-170

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