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ORCIDRavi S. Siddanath
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2020 – today
- 2026
[j3]Ravi S. Siddanath, Sukhen Mondal
, Manish Goswami, Kavindra Kandpal:
A Comprehensive Survey of Custom Layout Techniques for 6T, 8T, and 10T SRAM Bitcells Across Planar CMOS and FinFET Technology Nodes. IEEE Access 14: 24923-24941 (2026)- [j2]Mohit Gupta, Ravi S. Siddanath, Layak Singh Yadav, Mudit Gupta, Manish Goswami, Kavindra Kandpal:
Design of Hybrid, High-Speed, Nonvolatile Ternary Content Addressable Memory Using CMOS and RRAM. J. Circuits Syst. Comput. 35(2) (2026) - 2025
- [c2]Mohit Gupta, Ravi S. Siddanath, Mudit Gupta, Surya Prakash, Manish Goswami, Kavindra Kandpal:
Energy-Efficient, Nonvolatile 8T-2MTJ Ternary CAM Cell for Low Search Delay. AICAS 2025: 1-5 - [c1]Ravi S. Siddanath, Mohit Gupta, R. Dhirendra Rao, Souvik Kumar Das, Raghavendra Manjunath Hegde, Prasanna Kumar Misra, Manish Goswami, Kavindra Kandpal:
High-Precision BGR Design with Advanced Curvature Compensation & Optimized Layout in 28 nm CMOS Technology. ISVLSI 2025: 1-6 - 2024
- [j1]Ravi S. Siddanath, Mohit Gupta, Chaitanya Joshi, Manish Goswami, Kavindra Kandpal:
A 10T SRAM architecture with 40 % enhanced throughput for IMC applications benchmarked with CIFAR-10 dataset. Integr. 98: 102225 (2024)
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