SoC test integration platform.

Kun-Cheng Wu Augusli Kifli Kun-Cheng Wu SoC test integration platform. 1-2 2015 VLSI-DAT https://doi.org/10.1109/VLSI-DAT.2015.7114546 conf/vlsi-dat/2015 db/conf/vlsi-dat/vlsi-dat2015.html#KifliW15 Bing-Chuan Bai Augusli Kifli Chien-Mo James Li Kun-Cheng Wu Fault modeling and testing of retention flip-flops in low power designs. 684-689 2009 ASP-DAC https://doi.org/10.1109/ASPDAC.2009.4796559 http://dl.acm.org/citation.cfm?id=1509788 conf/aspdac/2009 db/conf/aspdac/aspdac2009.html#BaiKLW09 Augusli Kifli Y. W. Chen Yu-Wen Tsai Kun-Cheng Wu A Practical DFT Approach for Complex Low Power Designs. 90-91 2009 Asian Test Symposium https://doi.org/10.1109/ATS.2009.61 https://doi.ieeecomputersociety.org/10.1109/ATS.2009.61 conf/ats/2009 db/conf/ats/ats2009.html#KifliCTW09 Bing-Chuan Bai Chien-Mo James Li Augusli Kifli Even Tsai Kun-Cheng Wu Power scan: DFT for power switches in VLSI designs. 1 2009 ITC https://doi.org/10.1109/TEST.2009.5355631 https://doi.ieeecomputersociety.org/10.1109/TEST.2009.5355631 conf/itc/2009 db/conf/itc/itc2009.html#BaiLKTW09 Kun-Cheng Wu Yu-Wen Tsai Structured ASIC, evolution or revolution? 103-106 2004 conf/ispd/2004 ISPD https://doi.org/10.1145/981066.981088 db/conf/ispd/ispd2004.html#WuT04 Bing-Chuan Bai Y. W. Chen Augusli Kifli Chien-Mo James Li Even Tsai Yu-Wen Tsai