A 1V fractional-N PLL with nonlinearity-insensitive modulator.

Ping-Ying Wang Yi-Chieh Huang Che-Fu Liang Ping-Ying Wang A 1V fractional-N PLL with nonlinearity-insensitive modulator. 1-4 2015 A-SSCC https://doi.org/10.1109/ASSCC.2015.7387447 conf/asscc/2015 db/conf/asscc/asscc2015.html#HuangLW15 Che-Fu Liang Ping-Ying Wang 10.8 A wideband fractional-N ring PLL using a near-ground pre-distorted switched-capacitor loop filter. 1-3 2015 ISSCC https://doi.org/10.1109/ISSCC.2015.7062990 conf/isscc/2015 db/conf/isscc/isscc2015.html#LiangW15 Yi-Chieh Huang Che-Fu Liang Hsien-Sheng Huang Ping-Ying Wang 15.3 A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO. 270-271 2014 ISSCC https://doi.org/10.1109/ISSCC.2014.6757430 conf/isscc/2014 db/conf/isscc/isscc2014.html#HuangLHW14

Yi-Chieh Huang Ping-Ying Wang Shen-Iuan Liu An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits. 148-152 2012 59-II IEEE Trans. Circuits Syst. II Express Briefs 3 https://doi.org/10.1109/TCSII.2012.2184378 db/journals/tcas/tcasII59.html#HuangWL12

Ping-Ying Wang Hsiu-Ming Chang 0001 Kwang-Ting Cheng An all-digital built-in self-test technique for transfer function characterization of RF PLLs. 359-364 2011 DATE https://doi.org/10.1109/DATE.2011.5763063 https://doi.ieeecomputersociety.org/10.1109/DATE.2011.5763063 conf/date/2011 db/conf/date/date2011.html#WangCC11 Ping-Ying Wang Chia-Huang Fu All digital modulation bandwidth extension technique for narrow bandwidth analog fractional-N PLL. 270-273 2010 ESSCIRC https://doi.org/10.1109/ESSCIRC.2010.5619877 conf/esscirc/2010 db/conf/esscirc/esscirc2010.html#WangF10

Ping-Ying Wang Jing-Hong Conan Zhan Hsiang-Hui Chang Hsiu-Ming (Sherman) Chang A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes. 2182-2192 2009 44 IEEE J. Solid State Circuits 8 https://doi.org/10.1109/JSSC.2009.2022304 db/journals/jssc/jssc44.html#WangZCC09

Ping-Ying Wang Jing-Hong Conan Zhan Hsiang-Hui Chang Bing-Yu Hsieh An analog enhanced all digtial RF fractional-N PLL with self-calibrated capability. 749-752 2008 CICC https://doi.org/10.1109/CICC.2008.4672195 conf/cicc/2008 db/conf/cicc/cicc2008.html#WangZCH08 Ping-Ying Wang Hsiang-Hui Chang Jing-Hong Conan Zhan A fractional spur reduction technique for RF TDC-based all digital PLLs. 422-425 2008 ESSCIRC https://doi.org/10.1109/ESSCIRC.2008.4681882 conf/esscirc/2008 db/conf/esscirc/esscirc2008.html#WangCZ08 Ping-Ying Wang Hsiu-Ming Chang 0001 A charge pump-based direct frequency modulator. 1962-1965 2008 ISCAS https://doi.org/10.1109/ISCAS.2008.4541829 conf/iscas/2008 db/conf/iscas/iscas2008.html#WangC08 Hsiang-Hui Chang Ping-Ying Wang Jing-Hong Conan Zhan Bing-Yu Hsieh A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE. 200-201 2008 ISSCC https://doi.org/10.1109/ISSCC.2008.4523126 conf/isscc/2008 db/conf/isscc/isscc2008.html#ChangWZH08 Ping-Ying Wang Meng-Ta Yang Shang-Ping Chen Meng-Hsueh Lin Jing-Bing Yang RTL-based Clock Recovery Architecture with All-Digital Duty-Cycle Correction. 254-600 2007 ISSCC https://doi.org/10.1109/ISSCC.2007.373390 conf/isscc/2007 db/conf/isscc/isscc2007.html#WangYCLY07 Ping-Ying Wang C.-H. Chou Hsueh-Wu Kao Chaos in delay locked loop. 2006 conf/iscas/2006 ISCAS https://doi.org/10.1109/ISCAS.2006.1692564 db/conf/iscas/iscas2006.html#WangCK06 Ping-Ying Wang Hsiang Ji Hsieh Yung-Yu Lin Meng-Ta Yang Hsueh-Wu Kao A phase locked loop with a mixed mode loop filter for clock/data recovery in optical disc drives. 5007-5010 2005 conf/iscas/2005 ISCAS (5) https://doi.org/10.1109/ISCAS.2005.1465758 db/conf/iscas/iscas2005-5.html#WangHLYK05 Hsiang-Hui Chang Hsiu-Ming Chang 0001Hsiu-Ming (Sherman) Chang Shang-Ping Chen Kwang-Ting Cheng C.-H. Chou Chia-Huang Fu Bing-Yu Hsieh Hsiang Ji Hsieh Hsien-Sheng Huang Yi-Chieh Huang Hsueh-Wu Kao Che-Fu Liang Meng-Hsueh Lin Yung-Yu Lin Shen-Iuan Liu Jing-Bing Yang Meng-Ta Yang Jing-Hong Conan Zhan