Processor subsystem interconnect architecture for a large symmetric multiprocessing system.

George C. Wellwood

Pak-kin Mak Gary E. Strait Michael A. Blake Kevin W. Kark Vesselina K. Papazova A. E. (Rick) Seigler Gary A. Van Huben Liyong Wang George C. Wellwood Processor subsystem interconnect architecture for a large symmetric multiprocessing system. 323-338 2004 48 IBM J. Res. Dev. 3-4 https://doi.org/10.1147/rd.483.0323 db/journals/ibmrd/ibmrd48.html#MakSBKPSVWW04

Luiz C. Alves Myron L. Fair Patrick J. Meaney C. L. Chen William J. Clarke George C. Wellwood Norman E. Weber Indravadan N. Modi Brian K. Tolan Fritz Freier RAS design for the IBM eServer z900. 503-522 2002 46 IBM J. Res. Dev. 4-5 https://doi.org/10.1147/rd.464.0503 db/journals/ibmrd/ibmrd46.html#AlvesFMCCWWMTF02

Luiz C. Alves Michael A. Blake C. L. Chen William J. Clarke Myron L. Fair Fritz Freier Gary A. Van Huben Kevin W. Kark Pak-kin Mak Patrick J. Meaney Indravadan N. Modi Vesselina K. Papazova A. E. (Rick) Seigler Gary E. Strait Brian K. Tolan Liyong Wang Norman E. Weber