Design Method of Vertical Lattice Loop Structure for Parasitic Inductance Reduction in a GaN HEMTs-Based Converter.

Si-Seok Yang Sung-Soo Min Chan-Hyeok Eom Rae-Young Kim Gi-Young Lee Design Method of Vertical Lattice Loop Structure for Parasitic Inductance Reduction in a GaN HEMTs-Based Converter. 117215-117224 2022 10 IEEE Access https://doi.org/10.1109/ACCESS.2022.3220325 db/journals/access/access10.html#YangMEKL22