Fully integrated, high performance triple SD PLL (2.2Ghz to 4.4Ghz) with minimized interaction.

Tue, 01 Jan 2008 00:00:00 +0100

Stefano Cipriani, Eric Duvivier, Gianni Puccio, Lorenzo Carpineto, Biagio Bisanti, Francesco Coppola, Martin Alderton, Jeremy Goldblatt:
Fully integrated, high performance triple SD PLL (2.2Ghz to 4.4Ghz) with minimized interaction. ESSCIRC 2008: 366-369