Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization.

Nick Kanopoulos Nikos Kanopoulos Nick Kanopoulos Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization. 2 https://doi.org/10.1007/978-3-540-30205-6_2 2004 conf/patmos/2004 PATMOS db/conf/patmos/patmos2004.html#Kanopoulos04 Kostas Adaos George Alexiou Nick Kanopoulos Development of reusable serial FIR filters with reprogrammable coefficients designed for serial dataflow architectures. 567-570 2000 ICECS https://doi.org/10.1109/ICECS.2000.911603 conf/icecsys/2000 db/conf/icecsys/icecsys2000.html#AdaosAK00 Kostas Adaos G. Ph. Alexiou Nikos Kanopoulos Efficient implementation of a serial/parallel multiplier for IP based development and rapid prototyping in VLSI digital signal processing. 33-36 1999 ICECS https://doi.org/10.1109/ICECS.1999.812217 conf/icecsys/1999 db/conf/icecsys/icecsys1999.html#AdaosAK99 Nick Kanopoulos Testability Concepts and DFT. 1999 The VLSI Handbook https://doi.org/10.1201/9781420049671.sec9 reference/vlsi/1999 db/reference/vlsi/vlsi1999.html#Kanopoulos99

Theodore Karoubalis George Alexiou Nick Kanopoulos A dual rail circuits synthesis environment for the implementation of multiple output boolean functions. 329-342 1998 26 Int. J. Circuit Theory Appl. 4 https://doi.org/10.1002/(SICI)1097-007X(199807/08)26:4<329::AID-CTA17>3.0.CO;2-G db/journals/ijcta/ijcta26.html#KaroubalisAK98

Kostas Adaos George Alexiou Nick Kanopoulos An Extensible, Low Cost Rapid Prototyping Environment Based on a Reconfigurable Set of FPGAs. 78-83 1998 conf/rsp/1998 International Workshop on Rapid System Prototyping https://doi.org/10.1109/IWRSP.1998.676672 https://doi.ieeecomputersociety.org/10.1109/IWRSP.1998.676672 db/conf/rsp/rsp1998.html#AdaosAK98 Tassos Markas E. Edwards S. Wang J. Medero Nick Kanopoulos Automatic synthesis of an 8-bit CPU with 100% on-line error detection capability. 968-971 1996 ICECS https://doi.org/10.1109/ICECS.1996.584547 conf/icecsys/1996 db/conf/icecsys/icecsys1996.html#MarkasEWMK96 W. Weber Michael G. McNamer Nick Kanopoulos TESPAD: a testability specifications advisor for a structured test methodology. 1068-1071 1996 ICECS https://doi.org/10.1109/ICECS.1996.584605 conf/icecsys/1996 db/conf/icecsys/icecsys1996.html#WeberMK96 Theodoros Antonakopoulos 0001 C. Powers Nick Kanopoulos A versatile wireless system for real-time telemetry applications. 1194-1197 1996 ICECS https://doi.org/10.1109/ICECS.1996.584639 conf/icecsys/1996 db/conf/icecsys/icecsys1996.html#AntonakopoulosP96

Apostolos Dollas Nick Kanopoulos Reducing the Time to Market Through Rapid Prototyping - Guest Editors' Introduction. 14-15 1995 28 Computer 2 db/journals/computer/computer28.html#DollasK95 http://doi.ieeecomputersociety.org/10.1109/MC.1995.10018

Theodore Karoubalis Kostas Adaos George Alexiou Nick Kanopoulos A new efficient dcvs circuit synthesis technique used for an improved implementation of a serial/parallel multiplier. 587-598 1995 23 Int. J. Circuit Theory Appl. 6 https://doi.org/10.1002/cta.4490230604 db/journals/ijcta/ijcta23.html#KaroubalisAAK95

Jason P. Hurst Nick Kanopoulos Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits. 346-352 1995 conf/ats/1995 Asian Test Symposium https://doi.org/10.1109/ATS.1995.485359 https://doi.ieeecomputersociety.org/10.1109/ATS.1995.485359 db/conf/ats/ats1995.html#HurstK95 Theodore Karoubalis George Alexiou Nick Kanopoulos Optimal synthesis of differential cascode voltage switch (DCVS) logic circuits using ordered binary decision diagrams (OBDDs). 282-287 1995 EURO-DAC https://doi.org/10.1109/EURDAC.1995.527418 https://doi.ieeecomputersociety.org/10.1109/EURDAC.1995.527418 http://dl.acm.org/citation.cfm?id=224332 conf/eurodac/1995 db/conf/eurodac/euro-dac1995.html#KaroubalisAK95

George Alexiou Dimitrios Stiliadis Nick Kanopoulos On the design of a high-performance, expandable, sorting engine. 121-135 1994 18 Integr. 1 https://doi.org/10.1016/0167-9260(94)90014-0 db/journals/integration/integration18.html#AlexiouSK94

Theodoros Antonakopoulos 0001 Nick Kanopoulos Multiple boundary scan-paths for minimizing circuit-board test-application time. 377-386 1994 40 Microprocess. Microprogramming 6 https://doi.org/10.1016/0165-6074(94)90104-X db/journals/jsa/jsa40.html#AntonakopoulosK94

Tassos Markas Mark Royals Nick Kanopoulos Design and DCVS implementation of a self-checking bus-monitor unit for highly reliable fault-tolerant system configurations. 149-156 1994 2 IEEE Trans. Very Large Scale Integr. Syst. 2 https://doi.org/10.1109/92.285742 db/journals/tvlsi/tvlsi2.html#MarkasRK94

George Alexiou Dimitrios Stiliadis Nick Kanopoulos Design and Implementation of a High-Performance, Modular, Sorting Engine. 2-8 1994 conf/eurodac/1994edac EDAC-ETC-EUROASIC db/conf/eurodac/eurodac1994.html#AlexiouSK94 https://doi.org/10.1109/EDTC.1994.326907

Nazar S. Haider Nick Kanopoulos Efficient board interconnect testing using the split boundary scan register. 181-189 1993 4 J. Electron. Test. 2 https://doi.org/10.1007/BF00971646 db/journals/et/et4.html#HaiderK93

Mark Royals Tassos Markas Nick Kanopoulos John H. Reif James A. Storer On the design and implementation of a lossless data compression and decompression chip. 948-953 1993 September 28 IEEE J. Solid State Circuits 9 https://doi.org/10.1109/4.236174 db/journals/jssc/jssc28.html#RoyalsMKRS93 streams/journals/jssc

George Alexiou Nick Kanopoulos A new serial/parallel two's complement multiplier for vlsi digital signal processing. 209-214 1992 20 Int. J. Circuit Theory Appl. 2 https://doi.org/10.1002/cta.4490200207 https://www.wikidata.org/entity/Q126239574 db/journals/ijcta/ijcta20.html#AlexiouK92

Nick Kanopoulos Joseph H. Carabetta Design and implementation of a totally self-checking 16 × 16 bit array multiplier. 215-228 1992 14 Integr. 2 https://doi.org/10.1016/0167-9260(92)90027-V db/journals/integration/integration14.html#KanopoulosC92

Mark Royals Tassos Markas Nick Kanopoulos A user programmable macrocell generator for the IEEE 1149.1 boundary scan standard interface port. 493-500 1992 35 Microprocess. Microprogramming 1-5 https://doi.org/10.1016/0165-6074(92)90359-F db/journals/jsa/jsa35.html#RoyalsMK92

Nick Kanopoulos Dimitris Pantzartzis Frederick R. Bartram Design of Self-Checking Circuits Using DCVS Logic: A Case Study. 891-896 1992 41 IEEE Trans. Computers 7 db/journals/tc/tc41.html#KanopoulosPB92 https://doi.org/10.1109/12.256445 http://doi.ieeecomputersociety.org/10.1109/12.256445

Nazar S. Haider Nick Kanopoulos The split boundary scan register technique for testing board interconnects. 43-48 1992 VTS https://doi.org/10.1109/VTEST.1992.232722 https://doi.ieeecomputersociety.org/10.1109/VTEST.1992.232722 conf/vts/1992 db/conf/vts/vts1992.html#HaiderK92

Tassos Markas Mark Royals Nick Kanopoulos On Distributed Fault Simulation. 40-52 1990 23 Computer 1 db/journals/computer/computer23.html#MarkasRK90 https://doi.org/10.1109/2.48798 http://doi.ieeecomputersociety.org/10.1109/2.48798

Tassos Markas Nick Kanopoulos A bus-monitor unit for fault-tolerant system configurations. 521-527 1990 30 Microprocessing and Microprogramming 1-5 https://doi.org/10.1016/0165-6074(90)90293-I db/journals/jsa/jsa30.html#MarkasK90

Nick Kanopoulos Nagesh Vasanthavada Testing of differential cascade voltage switch (DCVS) circuits. 806-813 1990 June 25 IEEE J. Solid State Circuits 3 https://doi.org/10.1109/4.102679 db/journals/jssc/jssc25.html#KanopoulosV90 streams/journals/jssc

Mark Royals Tassos Markas Tianmaw Yang Nick Kanopoulos Creating the IC palette [ASIC design]. 76-86 1990 RSP https://doi.org/10.1109/IWRSP.1990.144037 https://doi.ieeecomputersociety.org/10.1109/IWRSP.1990.144037 conf/rsp/1990 db/conf/rsp/rsp1990.html#RoyalsMYK90

Jill J. Hallenbeck James R. Cybrynski Nick Kanopoulos Tassos Markas Nagesh Vasanthavada The Test Engineer's Assistant: A Support Environment for Hardware Design for Testability. 59-68 1989 22 Computer 4 db/journals/computer/computer22.html#HallenbeckCKMV89 https://doi.org/10.1109/2.25383 http://doi.ieeecomputersociety.org/10.1109/2.25383

Nagesh Vasanthavada Nick Kanopoulos A built-in test module for fault isolation. 58-65 1989 6 IEEE Des. Test 3 https://doi.org/10.1109/54.32413 db/journals/dt/dt6.html#VasanthavadaK89

J. Dodrill Nick Kanopoulos On the design of a real-time digital median filter. 245-249 1989 27 Microprocessing and Microprogramming 1-5 https://doi.org/10.1016/0165-6074(89)90054-9 db/journals/jsa/jsa27.html#DodrillK89

Nick Kanopoulos Peter N. Marinos Design of a bus-monitor for real-time applications. 717-721 1988 24 Microprocess. Microprogramming 1-5 https://doi.org/10.1016/0165-6074(88)90136-6 db/journals/jsa/jsa24.html#KanopoulosM88

Nick Kanopoulos Nagesh Vasanthavada Robert L. Baker 0003 Design of an image edge detection filter using the Sobel operator. 358-367 1988 April 23 IEEE J. Solid State Circuits 2 https://doi.org/10.1109/4.996 db/journals/jssc/jssc23.html#KanopoulosVB88 streams/journals/jssc

Jill J. Hallenbeck Nick Kanopoulos Nagesh Vasanthavada James W. Watterson CAD Tools for Supporting System Design for Testability. 993 1988 conf/itc/1988 ITC db/conf/itc/itc1988.html#HallenbeckkKVW88 https://doi.org/10.1109/TEST.1988.207889

Nick Kanopoulos Nagesh Vasanthavada A monolithic scan-line bit producer for real-time image rasterization. 57-63 1987 21 Microprocess. Microprogramming 1-5 https://doi.org/10.1016/0165-6074(87)90018-4 db/journals/jsa/jsa21.html#KanopoulosV87

Nick Kanopoulos Peter N. Marinos A High-Performance Single-Chip VLSI Signal Processor Architecture. 166-179 1986 conf/awoc/1986 Aegean Workshop on Computing db/conf/awoc/awoc86.html#KanopoulosM86 https://doi.org/10.1007/3-540-16766-8_15

Nick Kanopoulos Vassilios Makios A single-chip adaptive delta modulator with optimum performance. 319-328 1985 3 Integr. 4 https://doi.org/10.1016/0167-9260(85)90016-1 db/journals/integration/integration3.html#KanopoulosM85

Nikos Kanopoulos G. Thomas Mitchell Design for Testability and Self-Testing Approaches for Bit-Serial signal Processors. 52-59 1984 1 IEEE Des. Test 2 https://doi.org/10.1109/MDT.1984.5005609 db/journals/dt/dt1.html#KanopoulosM84

Nick Kanopoulos G. Thomas Mitchell Testing of Bit-Serial Signal Processors. 719-727 1983 conf/itc/1983 ITC db/conf/itc/itc1983.html#KanopoulosM83 Kostas Adaos George AlexiouG. Ph. Alexiou Theodore Antonakopoulos 0001Theodoros Antonakopoulos 0001 Robert L. Baker 0003 Frederick R. Bartram Joseph H. Carabetta James R. Cybrynski J. Dodrill Apostolos Dollas E. Edwards Nazar S. Haider Jill J. Hallenbeck Jason P. Hurst Theodore Karoubalis Vassilios Makios Peter N. Marinos Tassos Markas Michael G. McNamer J. Medero G. Thomas Mitchell Dimitris Pantzartzis C. Powers John H. Reif Mark Royals Dimitrios Stiliadis James A. Storer Nagesh Vasanthavada S. Wang James W. Watterson W. Weber Tianmaw Yang