"AutoClock: Automated Clock Management for Power-Efficient HLS Designs on ..."

Jiawei Liang et al. (2025)

> Home

Details and statistics

DOI: 10.1109/DAC63849.2025.11133279

access: closed

type: Conference or Workshop Paper

metadata version: 2026-02-25

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/dac/LiangDZLXZ25
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/dac/LiangDZLXZ25
Jiawei Liang, Linfeng Du, Xiaofeng Zhou, Zhe Lin, Jiang Xu, Wei Zhang:
AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAs. DAC 2025: 1-7

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.