Introduction to

Memory
Reviewed 2026

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1
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3
Table of Contents

1 Goal, Objectives and Target Audience

2 Introduction to Semiconductor Memory

3 Semiconductor Devices Overview

4 Introduction to DRAM

5 Introduction to Flash

6 Key Terminology/Glossary

7 Document Updates

4
Introduction to Memory - Goal and Objectives
Participants will be able to understand basic concepts of semiconductor memory technologies.

Objectives:
1. Explain what is Semiconductor Memory
2. Describe some of the fundamental semiconductor devices used in memory (resistor, diode,
capacitor, transistor)
3. Describe the basic structure and operation of a MOSFET transistor
4. Describe the basic structure and operation of DRAM memory
5. Describe the basic structure and operation of Flash memories

5
Target Audience
• This Introduction to Memory module covers the basic structure and
operation of DRAM and Flash memory
Pro tip
• Interns, NCGs (New College Grads), and new employees in technical Everyone interviewing at Micron
roles need to understand these concepts can use this presentation to
• Examples of critical target audience roles at Micron that utilize these prepare for the interview by
concepts: learning foundational information
– Process Technicians – Test Engineer about memory. Check out the
– Design Engineer – Probe Engineer candidate guides for Engineering,
– Product Engineer – Characterization Engineer Technician and Business roles.
– Verification Engineer – Reliability Engineer • Micron engineering candidate guide
– Process Engineer – Signal Integrity Engineer • Micron technician candidate guide
– Process Integration Engineer – Quality Engineer
• Micron business candidate guide

6
2. Introduction to
Semiconductor
Memory

7
 Types of Semiconductor Devices
LOGIC DEVICES MEMORY DEVICES SPECIALTY DEVICES
CPU (Central Processing Unit)
GPU (Graphics Processing Unit)
DRAM
CPU
(under fan)

DRAM
CMOS Image Sensors
Memory
Cards
Flash
NAND
GPU
(under fan)

NOR
LEDs
NAND SSD MICRON Products
CPUs can have GPU cores integrated on same chip 8
Logic vs Memory

LOGIC MEMORY
• A logic chip performs a function on given data • A memory chip allows you to store & retrieve data

• A processor or controller chip • A chip that holds programs and data (temporarily or
• Logic implies "processing" permanently)
• a fixed operation is performed • DRAMs are for temporary workspace
• a set of instructions is executed that may vary • Flash memory is used like a disk drive (permanent
until erased)

9
Basic Memory Operations

WRITE OR READ ERASE

PROGRAM

WRITE or PROGRAM or READ information from the ERASE or delete information

store information (1s and 0s) memory from the memory
in the memory

Example: Snap a picture Example: You look at a Example: You don’t like the
with a phone. The picture picture you took yesterday. picture, so you “erase” it
is “written/programmed” in You are “reading” it from from the memory!
memory. the memory.

10
How Memory Works – Binary language
• Electronic systems store information using digital technology
• Digital technology uses BITs and BYTEs to encode information (1 BYTE = 8 BITs)
• Each BIT is a single piece of information that can have one of two values: 0 or 1
• Groups of BITs are used to represent whole pieces of information, such as a letter, a number, or a color
• 1 BYTE of information is required to represent a letter
• The name Micron is represented by six BYTEs as follows

M i c r o n

01001101 01101001 01100011 01110010 01101111 01101110

11
Memory Storage
• Memory (data) storage is not a modern invention.
• Over the years many different approaches have been used to store information…

1725 1930 1940 1950 1960 1970 1980 1990 2000 2010 2020 Future

Punched tape 1725 – 1990

Punched cards 1890 – 2000 Magnetic Tape
Magnetic
1928 – Present
Hard Drive Storage
1956 – Present Floppy Disk
1969 – Present Compact Disc 1979 – Present Optical
DVD 1995 – Present
Blu-ray 2005 – Present Storage

DRAM Charge
4Jun68 – Present Storage
Flash (NOR & NAND)
1988 – Present
Resistance
Storage
Storage Class Memory
2012 – 3DXP ended 2021
Maybe another chance in the future?

12
Memory Storage Methods

Magnetic Optical Charge Resistance

Hard Disk Drive

1 0 1 1 0 1 0 1
Read head senses changes in direction of domains
within the thin magnetic film: change = 1, no
change = 0

(binary code for “µ”)

13
Memory Storage Methods

Magnetic Optical Charge Resistance

CD ROM, DVD, Blu-Ray

Digital Video Blu-Ray

Compact
Disc
CD ROM Disc Disc
780nm Red
Laser
DVDLaserRed
650nm 405nm Blue
Laser
Blu-Ray

Track pitch Track pitch Track pitch

1.6µm 0.74µm 0.30µm

CD DVD Blu-Ray

Storing Binary 1’s and 0’s with

indentations in a metallic film
Storage Capacity:
750MB x 6 = 4.5GB x 5.6 = 25GB
Optical microscope photos

14
Memory Storage Methods

Magnetic Optical Charge Resistance

DRAM NAND Flash

+
Storing Binary 1’s and 0’s based on +
how much charge is kept in the
+
+
storage node

+
+
Storage Node +
+

Storage Node

15
Memory Storage Methods

Magnetic Optical Charge Resistance

Cross-Point

Storage Node

Electrical Current
Storing Binary 1’s and 0’s based on how much
resistance there is to current flowing through the storage
node

16
Major Types of Memory

• Memory can be classified as Volatile or Non-Volatile

• Volatile (example: DRAM)
• Memory that will lose stored information when power is removed from the part

• Non-Volatile (example: NOR Flash & NAND Flash)

• Memory that will retain stored information even when power is removed from the part

Quiz: What type of memory (volatile or non-volatile) do you want for the memory
that stores the pictures you take in a smart phone?

17
Summary of Silicon-Based Memory Technologies
Short
Full Name Description Type Speed Density Primary Applications
Name
SRAM Static Random Data is stored as the state of a Volatile Very Fast Read Low Cache between CPU and
Access Memory digital flip-flop. Does not require and Write other memory types.
refresh.

DRAM Dynamic Random Data is stored as charge on a Volatile Fast Read and High “Scratch Pad” for a CPU.
Access Memory capacitor. Charge is quickly lost Write Computers, servers,
and must be constantly “refreshed”. laptops, tablets, PDA’s, cell
phones, AI applications,
etc.
NAND NAND Flash Data is stored by “trapping” charge Non- Slow Read, Very High Long term storage: digital
Memory in a film. Volatile Very Slow Write cameras, cell phones,
Data can be stored for up to 10 MP3s, memory sticks,
years without need for refresh. SSDs, etc.

NOR NOR Flash Similar to NAND Flash, but the Non- Faster access Medium Applications that require
Memory array is configured for faster Volatile time than NAND fast access time like code
read/write. execution. Example: OS
(Operative System)

NAND/NOR are not acronyms:

NAND refers to the series arrangement of memory cells similar to NAND (Not AND) digital logic
NOR memory cells are arranged in parallel like NOR (Not OR) digital logic 18
 Comparison of Memory Types
Power Consumption Write Speed Read Speed Cost per Bit

Magnetic SRAM SRAM $ SRAM

Power Consumption

Hard drive

Read Speed
Write Speed
DRAM DRAM NOR

Cost per Bit

SRAM NAND NOR DRAM
DRAM
NOR NAND NAND
NOR
Magnetic Magnetic Magnetic
NAND Hard drive Hard drive Hard drive

Lower is better Higher is better Higher is better Lower is better

to extend battery charge for faster operation for faster operation for higher density
in mobile devices and reduce at similar price point
operating costs in data centers

19
 DRAM = Dynamic Random Access Memory
DDR = Double Data Rate
LPDDR = Low Power Double Data Rate

DRAM (DDR, LPDDR, GDDR & HBM) GDDR = Graphics Double Data Rate
HBM = High Bandwidth Memory

Automotive Personal
Smartphone Data Center PC Gaming Game Console
ADAS Computing

Content • High-performance volatile memory AR/VR

Creation Applications
• Modules & components
• Low power consumption
Smart factory & • High-bandwidth Work from
Robotics Anywhere
• System level solutions

Industrial IoT Aerospace and Database/ Medical

Telco & Edge Generative AI
Applications Defense Hypervisor Equipment

20
 ADAS = Advanced Driver Assistance Systems
AI = Artificial Intelligence

Flash Memory (NAND and NOR)

AR = Augmented Reality
IoT = Internet of Things
VR = Virtual Reality

Automotive Personal Portable

Smartphone Data Center Game Console
ADAS Computing Storage

Video • Long-term memory storage AR/VR

Surveillance Applications
• Security Protection
• Low Power Consumption

Smart factory & • Reprogrammable Point of Sales /

Robotics Wearable
• Booting Software

Industrial IoT Aerospace and Drones and Medical

Networking Energy
Applications Defense Transport Equipment

21
3. Semiconductor
Devices Overview
Fundamentals | Capacitors | Transistors

23
Conductors, Insulators & Semiconductor Materials
Conductors
• Allow electrical current to flow easily
• Conductors used in integrated circuits are mostly metals: Aluminum, Tungsten and Copper

Insulators
• Very resistive to electrical current flow
• Used to electrically isolate one part of the circuit from another
• Some insulators used in integrated circuits: Silicon dioxide and Silicon nitride

Semiconductors
• Between conductors and insulators on the resistivity scale
• The semiconductor used in Micron is Silicon
• Silicon resistivity can be changed via “doping” (see upcoming slide)

24
Resistivity Scale
• Electrical resistivity is a measure of how strongly a material opposes the flow of electric current.

• Low resistivity indicates a material that readily allows the movement of electrical charge.

Resistivity () .cm

10-20 10-15 10-10 10-5 100 105 1010 1015 1020

{
{

{
Conductors Insulators

Super-Conductors
Semiconductors

25
Semiconductor Doping Intrinsic Si

Intrinsic (pure) Silicon

– Very resistive to electrical current flow
– Intrinsic silicon has very few applications in memory chips
– Silicon has 4 valence electrons (in outer shell)

Doped Silicon N-Type Si

– A small percentage of impurities (“dopants”) are added to the silicon
– Dopants reduce the resistance of the silicon
– Dopants can be “N-type” or P-type”

N-Type Silicon
– Most common N-Type Dopants are Arsenic (As) or Phosphorous (P)
– Current is carried by electrons that have a negative charge (N-Type) P-Type Si
– Phosphorous and Arsenic have 5 valence electrons (in outer shell)

P-Type Silicon
– Most common P-Type Dopants is Boron (B)
– Current is carried by “holes” that have a positive charge (P-Type)
– Boron has 3 valence electrons (in outer shell)
26
Important Semiconductor Components
• Resistors • Diodes
• Reduces or limits current flow • Allows current to flow in one
direction

p n • Can be used to electrically

isolate adjacent devices from
each other

• Capacitors • Transistors

• Stores an electrical charge • Controls current flow

• Has two conductive plates • Can function like a switch or
separated by an insulator valve

27
Resistors
Definition: A device that reduces or limits current flow

• A resistor is created by using a material less conductive (more resistive) anywhere along the path of current flow

• Resistors can have a fixed or variable resistance value

Voltage Divider Circuit

R1

R2 Vout = Vin (R2 / R1+R2)

Vin

28
Capacitors
Definition: An electronic device used to store electric charge

• A capacitor consists of:

• Two conductive “plates” – we arbitrarily call them “top” and “bottom” plates
• An insulating layer known as a “dielectric” that electrically separates the two plates

• Opposite charges on the plates are held in place by their mutual attraction, but they cannot cross the dielectric layer

Positive charge

top conductive plate

+ + + +
dielectric
bottom conductive plate
– – – –
Circuit symbol for a Negative charge
capacitor

Capacitor
29
Capacitors
• If a capacitor is hooked up to a power source, such as a battery, the capacitor will “charge up” until it can hold no more
charge

• Analogy: This is like filling a bucket with water until it can hold no more water

+ – 3/4

+ –
+ –
+ –

charge
capacitor

+ time
electrons

_
battery
30
Capacitors
• When the battery is disconnected, the capacitor will gradually begin to lose the charge. This is known as “discharging”.

• Analogy: This is like water slowly leaking out of small holes in a bucket

+ – 3/4

+ –
+ –
+ –

charge
capacitor

+ time

_
battery
31
 Q = Capacitance x Applied Voltage
Capacitors Q=CxV
How much charge (Q) can a capacitor hold? C ≈ k x plate area / spacing
• As the surface area of the conductive plates is increased, the capacitor can hold
more charge. – + + –
• Note: The plates do not have to be flat! – + + –
– + + –
• The charge (Q) stored in a capacitor, under a given voltage (V), is called the – + + –
“capacitance.”
– + + –
– + + –
– + + –
– + + –

+
+
+
+
+

+
+
+
+
+
+
+
– – – – – – – – – – – –

Small flat plates → Large flat plates → Large cylindrical plates →

less charge can be more charge can be stored but even more charge can be
stored require more X x Y area on stored with less area on the
wafer surface wafer!
32
Into the Z Dimension!
If we make the capacitor X x Y larger
we cannot achieve higher die
density on wafer

Current cylindrical
“containers” have a
So maintain same height ~40x their
X x Y on wafer but diameter “footprint”
go vertical on wafer!

33
Capacitors
How much charge can a capacitor hold? C ≈ k x plate area / spacing
• As the spacing between the plates decreases, the capacitor can hold more charge. This spacing can also be thought as
the dielectric thickness.

• The choice of dielectric material can also increase the amount of charge that can be stored.
• “High k” dielectric materials can store more charge.

“low k” “low k” “high k”

dielectric dielectric dielectric

+ + ++ Dielectric
++++++ ++++++++
Constant k
– – – – –––––– –––––––– SiO2 3.9
Si3N4 7.5
Ta2O5 22
Wide space between Narrow space Narrow space, with HfO2 25
plates → between plates → special dielectric → ZrO2 25
less charge can be stored more charge can be even more charge
TiO2 80
stored can be stored
34
Diodes
Definition: An electronic device that allows current to flow in one direction only

• Formed by connecting a P-type material with an N-type material

Metal contact Metal contact

Schematic symbol for a diode Anode p n Cathode

Simplified physical
structure of a diode

Forward biased:
+ - Current flows
P side N side
Diodes

Reverse biased: - +
Negligible current flows
P side N side

35
Diodes
• Diodes can be used to electrically isolate adjacent devices from each other
• In the example below, the P-Well and N-Well form a diode where they meet
• By applying a negative voltage to the P-Well and a positive voltage to the N-Well, the diode is reverse-biased, and
current cannot flow between devices A and B

Contact

Contact
Device A Device B
Negative (–) Voltage Positive (+) Voltage

Key:
STI: shallow trench isolation

36
Transistors
Definition: An electronic device that can control the current running though it – like an On/Off switch

• The most common type is the Field Effect Transistor (FET)

• Used in digital applications
• Low-power device
• Still being scaled below 10 nm

Substrate
Circuit symbol of a Structure of a MOSFET Transistor
MOSFET Transistor

MOSFET: Metal Oxide Semiconductor Field Effect Transistor

37
MOSFET Overview
Structure of a MOSFET
• Doped semiconductor (silicon) substrate
• Doped source and drain regions (oppositely doped from substrate)
• Insulating gate oxide
• Metal control gate on top of oxide is used to apply voltages that turn the
transistor ON or OFF
• The “channel” is the region beneath the gate where electrons will flow
from source to drain under the right conditions

Doped N-type in Doped P-type in this example

this example (also called the Pwell)
MOSFET: Metal Oxide Semiconductor Field Effect Transistor

38
MOSFET Overview
OFF STATE Control Gate Voltage = -3V

• Drain voltage is higher than source voltage, creating a

voltage drop. Current could flow through the device under Drain Voltage = +3V
these conditions if the gate allows. Source Voltage = 0V

• Negative voltage applied to the control gate attracts

positive charges (“holes”) into the channel region

• The holes in the channel act as a barrier so current cannot

flow between the Source and Drain

• The transistor is OFF

Holes accumulate
in the channel
No current flow

39
MOSFET Overview
ON STATE Control Gate Voltage = +3V

• Drain voltage is higher than source voltage, creating a

voltage drop. Current could flow through the device under Drain Voltage = +3V
these conditions if the gate allows. Source Voltage = 0V

• Positive voltage applied to the control gate attracts

negative charges (electrons) into the channel region

• Electrons in the channel create an electrical connection

between the Source and Drain, allowing current to flow

• The transistor is ON

Electrons accumulate
in the channel
Current can flow

40
MOSFET States: OFF and ON Summary

Control Gate Voltage = -3V Control Gate Voltage = +3V

Drain Drain
Source Voltage Source Voltage
Voltage +3V Voltage +3V
0V 0V

OFF STATE ON STATE

41
MOSFET Transistor Dimensions
Three Important Dimensions (but many others!):
• Gate Length (LG): As the gate length (channel) gets
shorter, the device can switch faster. The tradeoff is
an increase of leakage current in the off-state.

• Gate Width (WG): As the gate gets wider, more

current can flow from drain to source in the on-state
which improves circuit speed. The tradeoff is that
more silicon area is needed.
tOX
• Gate Oxide Thickness (tOX): As the gate oxide gets WG
thinner, the device can switch faster. The tradeoff is
an increase of leakage current through the gate.

LG

42
4. Introduction to
DRAM

43
Basic DRAM Memory Cell
• Shown on this slide is all that is needed to store a single “bit” (1 or
0) of digital information on a DRAM

• Each cell consists of one transistor and one capacitor.

• A DRAM chip has billions of these “cells”

top plate
dielectric
bottom plate Capacitor (“container”):
• Used to store charge
Word Line: • Shape is a cylinder
• Turns transistor • This is the DRAM
ON or OFF storage node
contact to
digit line
Digit Line (“Bit Line”): control contact to capacitor
• Path for charge in/out gate
of memory cell
Transistor (“access device”):
source drain
• Controls the flow of charge
in/out of the capacitor
gate
oxide
P well

44
DRAM Operation – Write
1. Bit Line delivers positive voltage to the source of the transistor.

bottom plate

top plate
dielectric
Capacitor

Word Line:

Bit Line: Gate

source drain
Transistor

P well

45
DRAM Operation – Write
1. Bit Line delivers positive voltage to the source of the transistor.
2. Word Line delivers positive voltage to the gate, which
creates the channel and turns it ON.
bottom plate

top plate
dielectric
Capacitor

Word Line:

Bit Line: Gate

source drain
Transistor

channel
P well

46
DRAM Operation – Write
1. Bit Line delivers positive voltage to the source of the transistor.
2. Word Line delivers positive voltage to the gate, which
creates the channel and turns it ON.
bottom plate
3. Bit Line voltage passes through the source and drain to the

top plate
dielectric
capacitor.
Capacitor

Word Line:

Bit Line: Gate

source drain
Transistor

channel
P well

47
DRAM Operation – Write
1. Bit Line delivers positive voltage to the source of the transistor.
2. Word Line delivers positive voltage to the gate, which
creates the channel and turns it ON. + – – +
+ – – + bottom plate
3. Bit Line voltage passes through the source and drain to the + – – +
+ – – +

top plate
dielectric
capacitor. + – – + Capacitor
4. The bottom plate charges positive, this writes a “1”. + – – +
+ – – +
• If bottom plate charges negative, a “0” is stored. + – – +
Word Line: + – – + Charge is trapped,
+ + storing a “1”.

Bit Line: Gate

source drain
Transistor

channel
P well

48
DRAM Operation – Write
1. Bit Line delivers positive voltage to the source of the transistor.
2. Word Line delivers positive voltage to the gate, which
creates the channel and turns it ON. + – – +
+ – – + bottom plate
3. Bit Line voltage passes through the source and drain to the + – – +
+ – – +

top plate
dielectric
capacitor. + – – + Capacitor
4. The bottom plate charges positive, this writes a “1”. + – – +
+ – – +
• If bottom plate charges negative, a “0” is stored. + – – +
Word Line: + – – +
5. Word Line turns off transistor, Charge is trapped,
+ + storing a “1”.
“trapping” the charge on the
capacitor. Bit Line: Gate

source drain
Transistor

P well

49
DRAM Operation – Read
1. Word Line delivers positive voltage to the gate, which
creates the channel and turns it ON.
+ – – +
+ – – + bottom plate
+ – – +
+ – – +

top plate
dielectric
+ – – + Capacitor
+ – – +
+ – – +
+ – – +
Word Line: + – – +
+ +

Bit Line: Gate

source drain
Transistor

channel
P well

50
DRAM Operation – Read
1. Word Line delivers positive voltage to the gate, which
creates the channel and turns it ON.
2. Charge on capacitor passes from drain to source and onto + – – +
the Bit Line. + – – + bottom plate
+ – – +
+ – – +

top plate
dielectric
+ – – + Capacitor
+ – – +
+ – – +
+ – – +
Word Line: + – – +
+ +

Bit Line: Gate

source drain
Transistor

channel
P well

51
DRAM Operation – Read
1. Word Line delivers positive voltage to the gate, which
creates the channel and turns it ON.
2. Charge on capacitor passes from drain to source and onto
the Bit Line. bottom plate

top plate
dielectric
3. Charge on capacitor is (temporarily) lost.
Capacitor

Word Line:

Bit Line: Gate

source drain
Transistor

channel
P well

52
DRAM Operation – Read
1. Word Line delivers positive voltage to the gate, which
creates the channel and turns it ON.
2. Charge on capacitor passes from drain to source and onto
the Bit Line. bottom plate

top plate
dielectric
3. Charge on capacitor is (temporarily) lost.
Capacitor
4. Sensing circuits on the Bit Line interpret the charge
(positive = “1”, negative = “0”) and send to the CPU.
Word Line:

Bit Line: Gate

“1” sent to CPU!
source drain
Transistor

channel
P well

53
DRAM Operation – Read
1. Word Line delivers positive voltage to the gate, which
creates the channel and turns it ON.
2. Charge on capacitor passes from drain to source and onto + – – +
the Bit Line. + – – + bottom plate
+ – – +
+ – – +

top plate
dielectric
3. Charge on capacitor is (temporarily) lost.
+ – – + Capacitor
4. Sensing circuits on the bit line interpret the charge + – – +
(positive = “1”, negative = “0”) and send to the CPU. + – – +
+ – – +
Word Line: + – – +
5. Lost charge on the capacitor
+ +
must be “refreshed”
(same as write operation). Bit Line: Gate

source drain
Transistor

channel
P well

54
Read (& Refresh)

Word Line
Bit Line

Word Line turns ON

WL ON
Vccp

Vccr “1” Sense Amp Reads a “1”

Ready to Read Charge from Capacitor Ready for next Read

Vccr/2

“0”
Ground
Sense Amp Reads a “0”

Container depth ~1um

human hair ~70um
3D Model of a DRAM Array
55
 Evolution of DRAM

2025
2022 1
1

2020
1 1
2014 Micron’s Next
World’s Most
8Gb DRAM
2002 Advanced
DRAM Process
1992 1Gb DRAM Technology

1987 16Mb DRAM

1981 1Mb DRAM
64K DRAM 44 years
>2,000,000x density increase
56
56
DRAM Scaling Trend
With each generation, by reducing the feature sizes of our memory cells on each die we can increase
density, achieve higher bits per wafer, and lower cost per bit.

Bits/wafer

DRAM Minimum
Feature size

57
58
DRAM DRAM
technology
leadership

Innovation and
execution for sustained 1β 1γ
First to market with First to ship 6th
leadership next-generation generation process
process node node-based
memory

• Leverages EUV lithography and next-generation

HKMG* CMOS technology. Results in greater than
30% more bits-per-wafer output over 1β node
• 1γ-based DDR5 for data center and client,
delivering up to a 15% speed increase and over
1γ 20% power reduction**
• The world's first 1γ-based LPDDR5X for mobile,
offering a 10.7 Gbps speed grade and up to 20%
power savings**
• Deployed on computing platforms, from the cloud
to edge AI devices
*High-K metal gate
** Compared to the previous generation
59
1γ: The world’s
most advanced
DRAM
First in the industry to ship samples
of 1γ (1-gamma), sixth-generation
DRAM node-based DDR5 and
LPDDR5X memory
• Builds on Micron’s previous 1α (1-alpha)
and 1β (1-beta) DRAM node leadership

• Leverages EUV lithography and next-

generation HKMG and CMOS
technology

• Deployed on computing platforms from

the cloud to edge AI devices like AI PCs,
smartphones and automobiles

• Features advanced power, performance

and bit density

*High-K metal gate

** Compared to the previous generation
60
This 24GB HBM3 Gen2 contains 8 of the leading-edge 1Beta 24Gbit DRAM die! Those HBM3-
specific die are interconnected vertically by Thru-Silicon Vias (TSVs) that are formed in the
wafer during in-fab processing
From Micron News Release 26Jul23 LINK 61
5. Introduction to
Flash

62
Structure of a Basic Flash Cell

Dielectric – insulator

Control Gate – where a controlling

voltage is applied Floating Gate – conducting or semi-
conducting layer that is surrounded by a
dielectric used to store charge and alter the
threshold voltage of the device. This is the
“storage node” of the NAND cell.

Gate (Tunnel) oxide layer – insulator

Symbol of the dual

gate transistor

Source Drain

63
NAND Function
• High voltage on the Control Gate causes electrons to tunnel through the gate oxide and get trapped within the Floating Gate

++++++++++++

- -- -- ---- - -----
- -- -- ---- - -----
- -- -----
- - - - - - - - - - -- -- -- -- --
- - - - - - - - - -

Source Drain
e-

64
Programming / Writing a NAND Cell
• Ground the substrate

• Apply ~+20V to the control gate

• Electrons in the substrate tunnel through the gate oxide and

relocate in the floating gate

• When voltage is released, electrons are trapped in the

floating gate making NAND Flash a non-volatile memory

• For some of our parts, data is guaranteed for 10 years

Source Drain

Note: cell design and voltage values have evolved from technology node to technology node. Design and values shown here for
educational purpose.

65
Erasing a NAND Cell
• Ground the control gate

• Apply ~+20V to the substrate

• Electrons trapped within the floating gate tunnel back

through the gate oxide into the substrate

Source Drain

20V

Note: cell design and voltage values have evolved from technology node to technology node. Design and values shown here for
educational purpose.

66
 VREAD = 3.0 V
Reading a NAND Cell
Reading a Programmed Cell:
• 0.5V on drain, 0V on source create a voltage drop
• VREAD = 3.0V on the control gate attempts to create a channel to 0V +++++++++++++ 0.5 V
turn transistor ON - -- -- ----
• Electrons trapped in the floating gate prevent the channel from - -- -- ----
forming so transistor remains OFF (VREAD not sufficient to form No channel?
Source Drain
channel) No current!
• No current flows between source and drain so a logic “0” is read
VREAD = 3.0 V

Reading an Erased Cell:

• 0.5V on drain, 0V on source create a voltage drop
• VREAD = 3.0V on the gate attempts to create a channel to turn
transistor ON 0V +++++++++++++ 0.5 V
• With no electrons trapped in the floating gate, the channel is
formed, and transistor turns ON
• Current flows between source and drain so a logic “1” is read -------------
Source Channel! Drain
Current!
Note: cell design and voltage values have evolved from technology node to
technology node. Design and values shown here for educational purpose. 67
Flash Function: Logic States

# of e- Trapped in Cell Threshold

State of the Cell Current in Channel Logic State
Floating Gate Voltage

Low Low Not Programmed Yes 1

High High Programmed No 0

68
NAND Flash vs. NOR Flash Bit Line (BL)
NAND SGS WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 SGD
▪ Higher Density
but Slower

Shared Select Gate Source (SGS) and Bit Line connections for a string of NAND Flash Memory Cells
BL
Source
SGS WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 SGD
N-Gnd N N N N N N N N N N-BL

Bit Line (BL)

NOR WL0 WL1 WL2 WL3 WL4 WL5
▪ Lower Density
but Faster
Key
Individual Bit Line connections for each NOR Flash Memory Cell BL: Bit Line
BL SGS: Select Gate Source Transistor
Source SGD: Select Gate Drain Transistor
WL0 WL1 WL2 WL3 WL4 WL5
N - BL N - Gnd N - BL N - Gnd N - BL N - Gnd N - BL
WL: Word Line
P
69
Multi Level Cell (MLC) Technology
• So far we have seen a NAND cell that can store 1 bit per cell where the cell is in one of two possible states:
• Programmed (Logic 0) or cup is full
• Erased (Logic 1) or cup is empty

• Continuous innovations in NAND technology now allow us to store more than 1 bit per cell.

• Micron has NAND parts that can store 2, 3, or 4 bits in each cell.
• SLC: 1 bit per cell (Single level Cell)

Erased Programmed
Logic 1 Logic 0

70
Multi Level Cell (MLC) Technology
• So far we have seen a NAND cell that can store 1 bit per cell where the cell is in one of two possible states:
• Programmed (Logic 0) or cup is full
• Erased (Logic 1) or cup is empty

• Continuous innovations in NAND technology now allow us to store more than 1 bit per cell.

• Micron has NAND parts that can store 2, 3, or 4 bits in each cell.
• SLC: 1 bit per cell (Single level Cell)
• MLC: 2 bits per cell (Multi Level Cell)
• TLC: 3 bits per cell (Triple Level Cell)
• QLC: 4 bits per cell (Quad Level Cell)

• These new cells are allowed to have have many

“partially full” states

• Consider this MLC example ➔ Erased Programmed Programmed Programmed

Level 0 Level 1 Level 2 Level 3

71
MLC = Multi Level Cell (2 bits per cell)
QLC = Quad Level Cell (4 bits per cell)
SLC = Single Level Cell (1 bit per cell)
SSD = Solid State Drive
Tb = Terabit (one trillion bits or 1,000 gigabits)
TLC = Triple Level Cell (3 bits per cell)

Micron 2018 Analyst & Investor Event 72

Charge States in NAND SLC/MLC/TLC/QLC Memory
QLC - Quad Level Cell
16 Charge States:
1 Erased + 15 Programmed
4 Bits per cell L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 VTH

TLC - Triple Level Cell

8 Charge States: 1.3x capacity increase
1 Erased + 7 Programmed
3 Bits per cell L0 L1 L2 L3 L4 L5 L6 L7 VTH

MLC - Multi-Level Cell E P1 P2 P3

4 Charge States: 1.5x capacity increase
1 Erased + 3 Programmed
2 Bits per cell L0 L1 L2 L3 VTH

SLC - Single Level Cell E P

2 Charge States: 2x capacity increase
1 Erased + 1 Programmed
1 Bit per cell L0 L1 VTH

Graphic is in arbitrary x/y scale

73
2D NAND of Years Past
• Early NAND generations arranged the cells horizontally

Source Memory Cell Memory Cell Memory Cell Drain Select

Memory Cell
Select Gate Gate
Source Drain

Programed Erased Programmed Programmed Programmed

NAND String

74
 Into the Z Dimension!

The 2D string of NAND

memory cells requires
more X x Y area if we
expand for higher
density (more cells per
string)

We can increase density

by going to 3D to
leverage the vertical
direction through the
implementation of many
“tiers” of memory cells

75
3D NAND Drain

• By standing the string cells on end

and enabling completely new and
innovative designs, processes, and
methods we can achieve increasing
memory densities within a given X x Y
area on the wafer. Only ~38
tiers shown
in this SEM

3D Model of a 3D NAND Array Stacked tiers ~10um

human hair ~70um

Source SEM = Scanning Electro Microscope

76
 232 layer NAND: the World’s
most advanced NAND.
NAND Scaling Trend Up to 1 terabyte (TB)

2D NAND X, Y “Footprint”
Scaling needed to gain
higher density for each
new generation
3D NAND X, Y “Footprint”
Scaling could be relaxed
due to gain in density by
adding vertical tiers

BL = Bit Line
Gb = Gigabits
WL = Word Line
77
 *CuA – CMOS Under Array - another Micron innovation – by locating all support circuitry
underneath the memory cell tiers, the die size can be further minimized, thereby gaining even
higher bit density (like all supporting utilities and parking garage installed beneath a skyscraper!)
CuA = CMOS Under Array
CY = Calendar Year
SSD = Solid State Drive
Tb = Terabit
TLC = Triple Level Cell (3 bits per cell)

From 12 May 2022 Micron Investor Day 2022 79

From 30 Jul 2024 Micron Press Release LINK 80
NAND NAND
technology
leadership

Innovation and
execution for sustained
leadership G8 G9
First to market with First to market with
industry’s most advanced industry’s fastest NAND
NAND in volume production in volume production

• Best-in-class performance and density compared to competitors

• The industry's highest transfer speed of 3.6 GB/s
• High performance for devices from PC to edge and into AI-enabled cloud
• First to ship G9 TLC NAND in an SSD — Micron 2600 SSD
G9 • Enables award-winning PCIe Gen5 performance — Micron 4600 SSD
• First PCIe Gen6 SSD for high-performance AI workloads — Micron 9650 SSD
• Lowest latency PCIe Gen5 mainstream performance SSD — Micron 7600 SSD
• Industry-leading storage density — Micron 6600 ION SSD

81
Summary – DRAM vs. NAND

• DRAM (Dynamic Random Access Memory) and NAND are two common memory or storage options with different designs
and working principles.
• DRAM is a volatile memory, meaning data stored in it is lost when there is a power failure or when you shut down your
system. It is a type of semiconductor memory used to temporarily store the program code or data required by the
computer’s processor. DRAM is typically used in personal computers, servers, workstations, processors, graphics cards,
video gaming consoles, and other gaming devices.
• NAND, is a non-volatile storage technology that does not need any power to hold the data stored in it. It is a common type
of flash memory that is usually used in different types of storage devices such as Solid State Drives (SSDs), Secure Digital
(SD) cards, and Universal Serial Bus (USB) flash drives.
• In terms of memory cell construction, a DRAM is made up of a transistor and a capacitor, while NAND uses a dual-gate
transistor.
• DRAM has fast read/write speed and high performance, making it widely used in computer memory. NAND, however, has
a larger storage capacity and better data persistence, making it widely used in storage media.

82
6. Key
Terminology/
Glossary

83
Terminology: wafer, die, array, periphery, scribe
• Memory is fabricated on a 300 mm diameter silicon wafer. We try to maximize our die per wafer.

• A die is the memory chip which has a memory array and a periphery
• The array (DRAM cells or NAND cells) stores information
• The periphery has many circuits that operate with the array (pumps, regulators, IO (Input/Output), ESD, etc.)

• The scribe or frame is the region between die. It contains hundreds of alignment and metrology structures and electrical
test circuits to enable in-line measurements and electrical testing. Die gets cut apart through the die singulation process for
packaging.

Array Array
die die die
Array Array
scribe

Array Array
die die
Array Array

Example of a die floorplan. Array is the Wafer Example of scribe circuits around die
dark red. Periphery shown in other colors. (not to scale) 84
Glossary
Term or acronym Definition/description

Array The die has a memory array and a periphery. The memory array is where the data (1s and 0s) is stored.
Capacitor An electronic device used to store electric charge. A capacitor consists of two conductive “plates” and an insulating layer known as a “dielectric” that
electrically separates the two plates.
Conductor A material that allows electrical current to flow easily. Examples of conductors used in integrated circuits are metals like aluminum, tungsten and
copper.
CuA CMOS Under Array - a Micron innovation. An architecture that consists on locating all support circuitry (periphery) underneath the memory cell array.
CuA allows the die size to be further minimized, thereby gaining higher bit density (like all supporting utilities and parking garage installed beneath a
skyscraper!)
Die A memory die is a semiconductor memory chip in its state before it is packaged. At Micron, memory die are fabricated on a silicon substrate. Hundreds
of memory die are built on the wafer, and after fabrication is completed, each memory die gets cut apart through the die singulation process. Individual
memory die are very delicate, so they next go through the Packaging process.
Diode An electronic device that allows current to flow in one direction only. Formed by connecting a P-type material with an N-type material. Diodes can be
used to electrically isolate adjacent devices from each other
DRAM Dynamic Random Access Memory. This is one of the types of semiconductor memory that Micron designs and fabricates. In DRAM memory data is
stored as electrical charge on a capacitor. Charge is quickly lost though, so data must be constantly “refreshed”. DRAM is one of the fastest memories
and provides both fast read and write operations. DRAM can be found in applications like computers, servers, laptops, tablets, cell phones, AI
applications, etc.
Frame The frame or scribe is the region of the wafer that separates one die from another die. The frame contains hundreds of alignment and metrology
structures to enable in-line measurements, and electrical test circuits to enable electrical testing. These structures are sacrificial as they are cut apart
through the die singulation process as each die needs to be cut apart before packaging.
Insulator A material that is very resistive to electrical current flow. Examples of insulators used in integrated circuits are silicon dioxide (SiO2) and silicon nitride
(Si3N4).
MLC Multi Level Cell. it refers to a NAND architecture that allows to program 2 bits per memory cell.

85
Glossary
Term or acronym Definition/description

MOSFET Metal Oxide Semiconductor Field Effect Transistor. A low-power electronic transistor device used in digital applications.
NAND This is one of the types of semiconductor Flash memory that Micron designs and fabricates. In NAND memory data is stored by “trapping”
charge in a film. Data can be stored for up to 10 years without need for refresh. While NAND has a slower read and write than other memory
types like DRAM, this memory is a good fit for many non-volatile high-density applications that require large amounts of storage like cellphones,
SSDs, etc. NAND is not an acronym; NAND refers to the series arrangement of memory cells similar to the NAND (Not AND) digital logic.
Non-volatile Refers to the type of semiconductor memory that will retain stored information even when power is removed from the part. Examples of non-
volatile memory are NAND Flash and NOR Flash.
NOR This is one of the types of semiconductor Flash memory that Micron designs and fabricates. Similar to NAND, in NOR the memory data is
stored by “trapping” charge in a film. But unlike NAND, the NOR architecture is designed for faster read/write operations. While NOR is slower
than DRAM memory, this memory is a good fit for many non-volatile applications and it is used for applications that require fast access time like
code execution, for example for storing and booting the Operative System (OS). NOR is not an acronym; NOR refers to memory cells arranged
in parallel like a NOR (Not OR) digital logic.
Periphery A memory die is a memory chip in its state before it is packaged. The die has a memory array and a periphery. The periphery is the region of
the die that has the many circuits that allow to operate on the memory array. Some of the periphery circuits are pumps, regulators, IO
(Input/Output), ESD (electrostatic discharge circuits), etc.
QLC Quad Level Cell. it refers to a NAND architecture that allows to program 4 bits per memory cell.
Resistivity Electrical resistivity is a measure of how strongly a material opposes the flow of electrical current. Resistivity is represented by the Greek letter
. Low resistivity indicated a material that readily allows movement of electrical charge.
Resistor A device that reduces or limits current flow. A resistor is created by using a material less conductive (more resistive) anywhere along the path of
current flow.
Scribe See Frame
Semiconductor A material that is between conductors and insulators on the resistivity scale. The semiconductor material used at Micron is silicon.

86
Glossary
Term or acronym Definition/description

SLC Single Level Cell. In NAND Flash, it refers to a NAND architecture that allows to program only 1 bit per memory cell.
Silicon, doped A small percentage of controlled impurities or dopants are added to the silicon to reduce its resistance.
Silicon, intrinsic Intrinsic Silicon is pure silicon. This material has 4 valance electrons and is very resistive. Intrinsic silicon has very few applications in memory
chip manufacturing.
Silicon, n-type An n-type dopant is an element that is added to the silicon that has more valence electrons than the silicon. The most common n-type dopants
used at Micron are arsenic (As) and phosphorous (P), both with 5 valence electrons. In the regions of the die where the silicon has been doped
n-type there is an excess of electrons so current is carried by electrons.
Silicon, p-type An p-type dopant is an element that is added to the silicon that has less valence electrons than the silicon. The most common p-type dopant
used at Micron is boron (B) with 3 valence electrons. In the regions of the die where the silicon has been doped p-type there is an excess of
“holes” so current is thought as carried by “holes” that have a positive charge.
TLC Triple Level Cell. In NAND Flash, it refers to a NAND architecture that allows to program 3 bits per memory cell.
Transistor An electronic device that can control the current running though it – like an On/Off switch.
Volatile Refers to the type of semiconductor memory that will lose stored information when power is removed from the part. Examples of volatile
memory are DRAM and SRAM.

87
7. Document
Updates

88
Document Updates
Date Description
January 2025 • Added goals, objectives and target audience
• Added several new images
• Added acronym legends
• Added glossary section
April 2025 • Slide 57: Added DRAM 1 technology – Micron’s newest DRAM technology
• Slide 58: New slide comparing DRAM 1α, 1, and 1γ technologies
• Slide 79: Added summary slide DRAM vs. NAND
January 2026 • Slides 7, 8, 20, 21, 62: replaced images with newer Micron products
• Slide 59: new slide
• Slide 60: new slide
• Slide 81: new slide

89
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on an “AS IS” basis without warranties of any kind. Statements regarding products, including statements regarding product features, availability, functionality,
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