Franco Maloberti
Layout of Analog
CMOS
Integrated Circuit
Part 3
Passive components: Resistors, Capacitors
F. Maloberti - Layout of Analog CMOS IC
Outline
Introduction
Process and Overview Topics
Transistors and Basic Cells Layout
Passive components: Resistors, Capacitors
System level Mixed-signal Layout
F. Maloberti - Layout of Analog CMOS IC
Integrated Capacitors
Capacitors in IC are parallel plate capacitors
No fringing effect
C=
0 r
WL
t ox
Material
SiO2 Dry Oxide
SiO2 Plasma
Si3N4 LPCVD
Si3N4 Plasma
F. Maloberti - Layout of Analog CMOS IC
Rel. Permittivity
3.9
4.9
6-7
6-9
Diel. Strength
11 V/nm
3-6 V/nm
10 V/nm
5 V/nm
Types of Integrated Capacitors
Poly-poly
Sandwich
Lateral plates
(flux capacitor)
Poly- diffusion
Poly-channel
F. Maloberti - Layout of Analog CMOS IC
Features of Integrated Capacitors
Extra mask
Electrodes : metal; polysilicon; diffusion
Insulator : silicon oxide; polysilicon oxide; CVD oxide
0 r
C=
WL
t ox
2
C r t ox
+
=
C r t ox
F. Maloberti - Layout of Analog CMOS IC
L 2 W 2
+
+
L W
Factor affecting accuracy
Oxide damage
Impurities
t ox
t ox
Grow rate
Poly grain size
Bias condition
Bias history (for CVD)
Stress
Temperature
F. Maloberti - Layout of Analog CMOS IC
L W
L W
Etching
Alignment
Layout of Capacitors
poly 1
metal
contact
poly 2
poly 2
on thick
oxide
area without
poly 1
(thick oxide)
poly 1
contact
To achieve good matching :
Use of unity capacitors connected in parallel
Use W = L fairly large
F. Maloberti - Layout of Analog CMOS IC
Flux Capacitor Layout
Use of the same metal layer
Exploit the lateral flux
The parasitic capacitance
plate -substrate is low
because the metal sits on
thick oxide
Use thick metal layers
Maximize the perimeter (use
of fractals)
Very good matching!
F. Maloberti - Layout of Analog CMOS IC
Common Centroid Structures
C1
TC1
C2
TC2
C3
TC3
C 2 = C1
C3 = 2C1
C4 = 4C1
C5 = 8C1
F. Maloberti - Layout of Analog CMOS IC
C4
TC4
C5
TC5
Matching of Capacitors
Matching accuracy is better than matched resistors, because :
<<
W
W
<
W cap W res
t ox
t ox
(because the capacitors are square)
x j
<
x j
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Undercut Effect
W = W - 2x
L = L - 2x
Effective area :
A = WL = WL - 2(L + W)x
A= A - Px
The undercut effect gives the
same proportional reduction if
the perimeter-area ratio is kept
constant
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Matched Capacitors: Exercise
Layout the following three capacitors
C1= 0.95 pF
C2=1.24 pF
C3= 1.37 pF
The absolute accuracy is not important. What matter is the
capacitance ratios.
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Fringing Effect
Equation
C=
0 r
WL
t ox
is an approximation
tox
tox
Fringing
field
0 r
C=
(W tox )( L tox ) + C fring
tox
Fringing depends on the boundary conditions
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MOS Capacitors Features
Type
tox
nm
Voltage
Accuracy Temperature
Coefficient Coefficient
ppm/V
ppm/oC
%
7 - 14
20 - 50
60 - 300
poly - diff.
15 - 20
poly I - poly II
15 -25
6 - 12
20 - 50
40 - 200
metal - poly
500 - 700
6 - 12
50 - 100
40 - 200
metal - diff.
1200 - 1400
6 - 12
50 - 100
60 - 300
metal I - metal II 800 - 1200
6 - 12
50 - 100
40 200
F. Maloberti - Layout of Analog CMOS IC
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Parasitic Capacitances
diffusion
poly-poly or poly-metal
Cp,b
0.05C
0.02 C
Cp,t
0.01C
0.005 C
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High impedance
node connected
to the top plate
Rules for Capacitor Matching
Use identical geometries
Use large unity capacitance (minimize fringing)
Use common centroid arrangement
Use dummy capacitors
Use shielding
Account for the connections contribution
Dont run connections over capacitor
Place capacitor in low stress areas
Place capacitors far from power devices
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Integrated Capacitors
Issues to remember
Use unit capacitors
Make bigger capacitors integer multiples of the
unit capacitor
Use common centroid layout to match capacitors
Use multiple contacts to lower series resistance
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Integrated Resistor Cross-section
A resistor is made of a strip of resistive layer.
L
R = 2R cont + R
W
The endings resistance can be significant!
F. Maloberti - Layout of Analog CMOS IC
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Diffused Resistances
a,b) diffusion
c) n-well (or p-well)
d) Pinched well
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Polysilicon Resistances
Conductive layers
can be used to shield
the conductor-oxideconductor structure
F. Maloberti - Layout of Analog CMOS IC
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Well or Pinched-well Resistors
Well layers have a large
specific resistance
but
They have a large voltage
and temperature coefficient
They are weakly insulated
from the surrounding
Layers close to the surface
contribute to the conductivity
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Large Value Resistors
In order to have large value resistors :
Use of long strips (large L/W)
Use of layers with high sheet resistance (bad performances)
Layout : rectangular snake
(!!)
Resistance at the corners
Current flows in different directions
DONT USE IT IN PRECISE
APPLICATIONS!
F. Maloberti - Layout of Analog CMOS IC
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Prevent Current Leakage!
N-Well
Substrate bias
n+ diffusion
p+ diffusion
Prevents
lateral leakage
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Features of Resistors
Type
of layer
n + diff
Sheet
Voltage
Accuracy Temperature
Resistance
Coefficient Coefficient
ppm/V
ppm/oC
/0
%
30 - 50
20 - 40
200 - 1K
50 - 300
p + diff
50 -150
20 - 40
200 - 1K
50 - 300
n - well
2K - 4K
15 - 30
5K
10K
p - well
3K - 6K
15 - 30
5K
10K
pinched n - well
6K - 10K
25 - 40
10K
20
pinched p - well
9K - 13K
25 - 40
10K
20
first poly
20 - 40
25 - 40
500 - 1500
20 - 200
second poly
15 - 40
25 - 40
500 - 1500
20 - 200
F. Maloberti - Layout of Analog CMOS IC
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Resistors Accuracy
R=
L
L
R =
W
W xj
If the parameter are statistically independent the standard deviation of the
resistance is :
2
R L W x j
+
=
+
+
R L W x j
Since in general L >> W
L
W
<<
L
W
F. Maloberti - Layout of Analog CMOS IC
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Resistors Accuracy (cont.)
for polysilicon resistors is larger than for diffused resistors.
(Polysilicon is composed of a conglomerate of independently oriented grain
of crystalline silicon)
Accuracy :
Absolute accuracy is poor because of the large parameter drift
Ratio (or matching) accuracy is better because it depends on the local
variation of parameters.
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Factor Affecting Accuracy
Polysilicon grain size
Doping dose
Crystal defects
Stress
Temperature
L W
L W Etching
Boundary
Side diffusivity
F. Maloberti - Layout of Analog CMOS IC
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x j
xj
Implant dose
Side diffusivity
Deposition rate
Other Elements
Plastic packages cause a large pressure on the die (= 800 Atm.). It determines
a variation of the resistivity.
For <100> material the variation is unisotropic, so the minimum is get if the
resistance have a 45o orientation.
compensated
Temperature :
Temperature gradient on the
chip may produce thermal
induced mismatch.
uncompensated
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Effect of Etching
Wet etching : isotropic (undercut effect)
HF for SiO2 ; H3PO4 for Al
x for polysilicon may be 0.35 - 0.5 with
standard deviation 0.02 .
Reactive ion etching (R.I.E.)(plasma etching
associated to bombardment) : unisotropic.
x for polysilicon is 0.2 with standard deviation 0.015
Boundary :
The etching depends on the
boundary conditions
Use of dummy strips
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Side Diffusion
Contribution of Endings
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Interdigitized and Common Centroid
R1
R2
R2
R1
121212212121
Exercise: draw a 121212121212 connection and compare the two solutions
Exercise: draw a common centroid structure (12 elements per resistor)
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Resistor Guidelines
For matching :
Use of equal structures
Not too narrow (W = 10 mm)
Interdigitize
Thermal effect compensation
45o orientation (if stressed)
For good TC :
Use of n+ or p+ layers
Use of poly layers
For absolute value :
Use of diffused layers
Suitable endings
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Simple Model
Field oxide
T1
Poly
T2
Deposited
oxide (ILO)
Substrate
R1
T1
C1
C2
SUBS
(A)
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R2
C1
C2
SUBS
R1
T1
T2
(B)
T2
C3
Metal Resisitors
The sheet resistance of Al metallization is around 100 m/
Current
lead
Ld
Sense
lead
Wd
Sense lead
Current lead
(MTL-1)
Wd
Ld
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(B)
Adjusting Resistor Values
Range of slide
Sliding contact:
requires to change the
contact mask only
(A)
Trimpad
Metal fuse
and
Poly-fuse
Trimpad
Metal
Nitride
opening
Nitride
opening
(A)
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Low-sheet
poly
(B)
Use of Fuses To Adjust Resistors
Rx
F1
4Rlsb
F1
F2
F3
2Rlsb
Rmsb
F3
F2
Rmsb/2
Rmsb/4
Rlsb
(B)
(A)
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Rx
Rules for Resistor Matching
Use the same material
Identical geometry, same orientation
Close proximity
Interdigitate arrayed resistors
Use dummy elements
Place resistors in low stress area
Place resistors away from power devices
Use electrostatic shielding
Use proper endings
F. Maloberti - Layout of Analog CMOS IC
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Integrated Resistors
Issue to remember
Integrated resistors and features
Resistor endings
Make bigger resistors integer multiples of the unit resistor
Finger two or more resistors for matching
Do not snake a resistor; use metal to make turns
Well under the resistor to shield from interference
Substrate bias around the resistor
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