(A constituent college of Sri Siddhartha University)

2012-13
Department of Electronics & Communication
LOGIC DESIGN LAB MANUAL
III SEM BE
Name :
Sem : . Sec:

Logic Design Lab Manual

Contents

Exp No

Title

Page No.

1.

Simplification, Realization of Boolean Expression Using Logic

Gates/Universal Gates

1-2

2.

Half/Full Adder and Half/Full Subtractors.

3-7

3.

Parallel Adder/Subtractor.

9-11

4.

BCD To Excess-3 And Excess-3 To BCD code converter

13-15

5.

Binary-to-Gray And Gray-to-Binary code converter

17-19

6.

Multiplexer Using IC 74153

21-24

7.

De-multiplexer Using IC 74139

25-28

8.

Comparators

29-31

9.

Encoder & Decoder

33-35

10.

Flip-Flops

37-39

11.

Asynchronous counters

41-44

12.

Synchronous counters

45-46

13.

Decade and binary counters

47-53

14.

Shift Registers

55-58

15.

Johnson Counter/ Ring Counter

59-60

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Logic Design Lab manual

GIVEN EXPRESSION:
Y=(A,B,C,D)= (5,7,9,11,13,15)

Implementation:
Using Basic Gates:

Using Universal Gates:

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Logic Design Lab manual

EXPERIMENT NO. 1:

DATE: / /

SIMPLIFICATION, REALIZATION OF BOOLEAN EXPRESSION USING LOGIC

GATES/UNIVERSAL GATES

AIM: To Simplify and Realize Boolean Expressions Using Logic Gates/Universal Gates.
APPARATUS REQUIRED:- IC Trainer Kit, patch chords, IC7408, IC7432 , IC7400,
IC7402, IC 7404,IC 7486.
Procedure:
1. Place the IC in the socket of the trainer kit.
2. Make the connections as shown in the circuit diagram.
3. Apply the different combinations of input according to truth table and verify the
output.
Simplification of expression:Y=(A,B,C,D)= (5,7,9,11,13,15)
Write the expression using K-map
Y=ABCD+ABCD+ABCD+ABCD+ABCD+ABCD
Y =ABD (C+C)+ABD(C+C)+ABD(C+C)
Y =ABD+ABD+ABD
Y =BD(A+A)+ABD
Y=BD+ABD
Y=D(B+AB)
Y=D(A+B)
Y =AD+BD
Exercise: Simplify and realize the following POS expn. and implement using nand
gates only: Y(A,B,C,D)=(5,7,9,11,13,15)

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Logic Design Lab manual

Half Adder
Logic Diagram

Truth Table
A
0
0
1
1

B Sum (S) Carry (C)

0
0
0
1
1
0
0
1
0
1
0
1

Circuit Diagram
USING BASIC AND XOR GATES

USING NAND GATES ONLY

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Logic Design Lab manual

EXPERIMENT NO. 2:

DATE: / /

HALF/FULL ADDER AND HALF/FULL SUBTRACTORS.

Aim: - To realize half/full adder and half/full subtractor.

i.

Using X-OR and basic gates

ii.

Using only nand gates.

Apparatus Required: IC Trainer Kit, patch chords , IC 7486, IC 7432, IC 7408, IC 7400, etc.
Procedure: 1. Verify the gates.
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to the truth
table.
4. Note down the output readings for half/full adder and half/full subtractor
sum/difference and the carry/borrow bit for different combinations of
inputs.

Exercise: Implement half/full adder and half/full adder circuits using NOR gates
only. Which is better, NAND or NOR? Why?

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Full Adder
Logic Diagram
Ci
0
0
0
0
1
1
1
1

A
0
0
1
1
0
0
1
1

B
0
1
0
1
0
1
0
1

Truth Table
Sum (S) Carry (Co)
0
0
1
0
1
0
0
1
1
0
0
1
0
1
1
1

Circuit Diagram
USING BASIC AND XOR GATES

USING NAND GATES ONLY

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Half subtractor
Logic Diagram

Truth Table
A B
0
0
1
1

0
1
0
1

Diff
(D)
0
1
1
0

Borrow
(B0)
0
1
0
0

Circuit Diagram
USING BASIC AND XOR GATES

USING NAND GATES ONLY

DIFF

BORROW

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Full subtractor

Logic Diagram:

Truth Table

Circuit Diagram
(USING BASIC AND XOR GATES)

(USING NAND GATES ONLY)

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Pin Detail: -

7483

Adder: -

Truth Table: A3 A2 A1 A0 B3 B2 B1 B0 C4 (V) S3(V) S2(V) S1(V) S0(V)

0

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EXPERIMENT NO. 3:

DATE: / /

PARALLEL ADDER/SUBTRACTOR

AIM: - To realize IC 7483 as parallel adder / Subtractor.

Apparatus Required: IC Trainer Kit, patch chords, IC 7483, IC 7404, etc.
Procedure: 1. Apply the inputs to A0 to A3 and B0 to B3.
2. Connect C0 to the Ground.
3. Check the output sum on the S0 to S3 and also C4.
4. For subtraction connect C0 to Vcc, Apply the B input through NOT gate, which
gives the complement of B.
5. The truth table of adder and Subtractor are noted down.

Exercise:
Implement parallel adder/subtractor using IC 7483 and xor gates.

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Subtractor:-

Truth Table for Subtractor

A3 A2 A1 A0 B3 B2 B1 B0 C4(V) S3(V) S2(V) S1(V) S0(V)

0

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BCD To Excess-3:
Truth Table For Code Conversion: Inputs

Outputs

B3 B2 B1 B0

E3
(v)

E2
(v)

E1
(v)

E0
(v)

1
0
0
1
Circuit diagram using NAND gates

only:

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EXPERIMENT NO. 4:

DATE: / /

BCD TO EXCESS-3 AND EXCESS-3 TO BCD CODE CONVERTER

AIM: - To study and verify BCD to excess 3 code and excess-3 to BCD code conversion
using NAND gates.

APPARATUS REQUIRED: IC Trainer Kit, patch chords, IC 7400, IC 7404, etc.

Procedure: - (BCD Excess 3 and Vice Versa)

1. Make the connections as shown in the fig.
2. Pin [14] of all ICS are connected to +5V and pin [7] to the ground.
3. The inputs are applied at E3, E2, E1, and E0 and the corresponding outputs at B3,
B2, B1, and B0 are taken for excess 3 to BCD.
4. The inputs are applied at B3, B2, B1, and B0 and the corresponding outputs are
E3, E2, E1 and E0 for BCD to excess 3.
5. Truth tables are verified.

Exercise:
Implement BCD to excess-3 and excess-3 to BCD code converter using parallel
adder IC 7483.

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Excess-3 To BCD :Truth Table For Code Conversion: Inputs

Outputs

E3 E2 E1 E0 B3 (v) B2 (v) B1 (v) B0(v)

0

1 1 0 0 1
Circuit diagram using NAND gates only:

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Binary to Gray:

Circuit diagram using EX-OR Gates:

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EXPERIMENT NO. 5:

DATE: / /

BINARY-TO-GRAY AND GRAY-TO-BINARY CODE CONVERTER

AIM: - To convert given binary numbers to gray codes.

APPARATUS REQUIRED: IC Trainer Kit, patch chords, IC 7486, etc
PROCEDURE: 1. The circuit connections are made as shown in fig.
2. Pin (14) is connected to +Vcc and Pin (7) to ground.
3. In the case of binary to gray conversion, the inputs B0, B1, B2 and B3 are given at
respective pins and outputs G0, G1, G2, G3 are taken for all the 16 combinations
of the input.
4. In the case of gray to binary conversion, the inputs G0, G1, G2 and G3 are given at
respective pins and outputs B0, B1, B2, and B3 are taken for all the 16
combinations of inputs.
5. The values of the outputs are tabulated.

Exercise:
Implement binary to gray and gray to binary code converter using nand gates
only.

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Gray to binary:
Truth-table:
G3

G2

G1

G0

B3

B2

B1

B0

Circuit Diagram using EX-OR Gates

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Pin Details: -

Truth Table: CHANNEL A

CHANNEL B

SELECT

INPUTS

INPUTS

O/P

SELECT O/P

LINES

LINES

Ioa

I1a

I2a

I3a

S1

S2

Za(v)

Iob

I1b

I2b

I3b

S1

S2

Za(v)

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EXPERIMENT NO. 6:

DATE: / /
MULTIPLEXER USING IC 74153

Aim: - To verify the truth table of multiplexer using 74153

To study the arithmetic circuits half-adder and half Subtractor, full adder and full
Subtractor using multiplexer.
Apparatus Required: IC Trainer Kit, patch chords, IC 74153, IC 74139, IC 7404, etc.
Procedure: 1. The Pin [16] is connected to + Vcc.
2. Pin [8] is connected to ground.
3. The inputs are applied either to A input or B input.
4. If MUX A has to be initialized, Ea is made low and if MUX B has to be initialized,
Eb is made low.
5. Based on the selection lines one of the inputs will be selected at the output and
thus the truth table is verified.
6. In case of half adder using MUX, sum and carry is obtained by applying a
constant inputs at I0a, I1a, I 2a, I 3a and I 0b, I 1b, I 2b and I3b and the corresponding
values of select lines are changed as per table and the output is taken at Z0a as
sum and Z0b as carry.
7. In this case, the channels A and B are kept at constant inputs according to the
table and the inputs A and B are varied. Making Ea and Eb zero and the output is
taken at Za, and Zb.
8. In full adder using MUX, the input is applied at Cn-1, An and Bn. According to the
table corresponding outputs are taken at Cn and Dn.

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Half Adder Using 74153

Half Subtractor Using 74153:

Full Adder Using 74153: -

Full Subtractor Using 74153: -

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Truth Tables: Full Adder
An Bn Cn-1 Sn (V) Cn (V)
Half adder

A B Sn (V) Cn (V)

0 0

0 1

1 0

1 1

Full subtractror
An Bn Cn-1 Dn (V) Bn (V)
Half subtractor

A B Dn (V) Bn (V)

0 0

0 1

1 0

1 1

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Pin details:

Truth Table For Demux: CHANNEL A

Inputs

CHANNEL B

Outputs

Inputs

Outputs

a S1a S0a Y0a Y1a Y2a Y3a

b S1b S0b Y0b Y1b Y2b Y3b

Half subtractor:-

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EXPERIMENT NO. 7:

DATE: / /
DE-MULTIPLEXER USING IC 74139

Aim: - To verify the truth table of de-multiplexer using 74139.

To study the arithmetic circuits half-adder and half Subtractor, full adder and full
Subtractor using de- multiplexer.
Apparatus Required: IC Trainer Kit, patch chords, IC 74153, IC 74139, IC 7404, etc
Procedure: 1. The inputs are applied to either a input or b input
2. The demux is activated by making Ea low and Eb low.
3. The truth table is verified.

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Full subtractor using IC 74139:-

Truth Table
Half Subtractor
A B Dn (V) Bn (V)
0 0

0 1

1 0

1 1

Full Subtractor
Bn

Cn1

Dn
(V)

Bn
(V)

An

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One Bit Comparator: -

Truth-table
Y0
A

Y1

Y2

B
(A<B) (A>B) (A=B)

Two Bit Comparator: -

A1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

A0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

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B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Y2(A=B)
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1

Y1(A>B)
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
0

Y0(A<B)
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
1

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Logic Design Lab manual

Date: __/__/____

Experiment No:8

COMPARATORS

Aim: - To verify the truth table of one bit and two bit comparators using logic
gates and four bit and eight bit comparators using IC 7485.

Apparatus Required: IC 7485, IC 7404, IC 7408, etc.

Procedure: 1. Verify the gates.

2. Make the connections as per the circuit diagram.
3. Switch on Vcc.
4. Applying i/p and Check for the outputs.
5. The voltameter readings of outputs are taken and tabulated in tabular
column.
6. The o/p are verified.
Exercise:

Implement one bit, two bit comparator circuit using nand gates only.

Write the function table for 8 bit comparator .

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4-bit Comparator
LOGIC DIAGRAM:

FUNCTION TABLE :
Comparing
Cascading
I/Ps
I/Ps

Outputs

A>B A=B A<B A>B A=B A<B

A>B

A=B

A<B

X
1
X
0
0
1
X

X
0
1
0
0
0
X

X
0
X
1
0
1
X

1
1
0
0
1
0
0

0
0
1
0
0
0
0

0
0
0
1
0
0
1

8-Bit Comparator: LSB

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MSB

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PIN DETAILS:-

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FUNCTION TABLE:

EI
H
L
L
L
L
L
L
L
L
L

0
X
H
X
X
X
X
X
X
X
L

1
X
H
X
X
X
X
X
X
L
H

INPUTS
2
3
4
X
X
X
H
H
H
X
X
X
X
X
X
X
X
X
X
X
L
X
L
H
L
H
H
H
H
H
H
H
H

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5
X
H
X
X
L
H
H
H
H
H

6
X
H
X
L
H
H
H
H
H
H

7
X
H
L
H
H
H
H
H
H
H

A2
H
H
L
L
L
L
H
H
H
H

OUTPUTS
A1 A0 GS
H
H
H
H
H
H
L
L
L
L
H
L
H
L
L
H
H
L
L
L
L
L
H
L
H
L
L
H
H
L

E0
H
L
H
H
H
H
H
H
H
H

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Experiment No: 9

DATE: __/__/____
ENCODER & DECODER

AIM:-To convert a given octal input to the binary output and to study the LED
display using 7447 7-segment decoder/ driver.

APPARATUS REQUIRED: IC 74148, IC 7447, 7-segment display, etc.

PROCEDURE: - ( Priority Encoder)

1. Connections are made as per circuit diagram.
2. The octal inputs are given at the corresponding pins.
3. The outputs are verified at the corresponding output pins.

PROCEDURE: - (Decoder)
1. Connections are made as per the circuit diagram.
2. Connect the pins of IC 7447 to the respective pins of the LED display board.
3. Give different combinations of the inputs and observe the decimal numbers
displayed on the board.

Exercise: Implement the following expression using decoder and logic gates.

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BCD TO SEVEN SEGMENT DECODER CIRCUIT DIAGRAM WITH LED DISPLAY

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TRUTH-TABLE:
INPUTS

DECIMAL
DIGIT

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

15

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LED
DISPLAY
VALUE
0
1
2
3
4
5
6
7
8
9

SEVEN SEGMENTS LEVEL

a

1
0
1
1
0
1
0
1
1
1

1
1
1
1
1
0
0
1
1
1

1
1
0
1
1
1
1
1
1
1

1
0
1
1
0
1
1
0
1
0

1
0
1
0
0
0
1
0
1
0

1
0
0
0
1
1
1
0
1
1

0
0
1
1
1
1
1
0
1
1

No seg.
glows

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Circuit Diagram: - (Master Slave JK Flip-Flop)

Truth Table:- (Master Slave JK Flip-Flop)

Preset Clear

K Clock Qn+1

Qn + 1

X X

Set

X X

0 0

Qn

Qn

0 1

Reset
No
Change
Reset

1 0

Set

1 1

Qn

Qn

Toggle

D Flip-Flop:-

7410

Truth Table:Preset Clear D Clock Qn+1

Qn + 1

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Date: __/__/____

Experiment No: 10
FLIP-FLOPS

Aim: Verification of truth-tables of the following types of flip-flops using NAND

gates and using IC 7476:
i. JK Master Slave FF
ii. D-FF
iii. T-FF
iv. SR-FF

Apparatus Required: IC 7410, IC 7400, IC 7476, etc.

Procedure: 1. Connections are made as per circuit diagram.

2. The truth table is verified for various combinations of inputs.

Exercise:

Write the timing diagrams for all the above Flip-Flops

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T Flip-Flop:-

Truth Table:-

Preset Clear T Clock Qn+1

Qn + 1

Qn

Qn

Qn

Qn

SR Flip-flop:

Truth-table:

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Circuit Diagram: - 3-Bit Asynchronous Up Counter

Truth-table:
3-bit Asynchronous up counter
Clock
QC
QB
QA
0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
8
0
0
0
9
0
0
1
Circuit Diagram: - 3-Bit Asynchronous Down Counter

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Experiment No: 11

Date: __/__/____
ASYNCHRONOUS COUNTERS

Aim: Realization of 3-bit asynchronous up/down counters and design of Mod-N

counter design.
Apparatus Required: IC 7408, IC 7476, IC 7400, IC 7432 etc.

Procedure: 1. Connections are made as per circuit diagram.

2. Clock pulses are applied one by one at the clock I/P and the O/P is
observed at QA, QB & QC for IC 7476.
3. Truth table is verified.

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Truth-table:
3-bit Asynchronous down counter
Clock
QC
QB
QA
0
1
1
1
1
1
1
0
2
1
0
1
3
1
0
0
4
0
1
1
5
0
1
0
6
0
0
1
7
0
0
0
8
1
1
1
9
1
1
0
Mod 5 Asynchronous up Counter:-

Truth-table:
Mod 5 Asynchronous counter
Clock
QC
QB
QA
0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
0
0
0

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Mod 3 Asynchronous up Counter:-

Truth-table:
Clock QB QA
0
0
0
1
0
1
2
1
0
3
0
0
Mod 4 Asynchronous down Counter:QA

QB

7432

Vcc
Pre

clk

clk

Pre

Q
7476

J
clk

Q
7476

K
Clr

Clr

Vcc

Truth-table:
Clock QB QA
0
1
1
1
1
0
2
0
1
3
0
0

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State Diagram

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Experiment No: 12

Date: __/__/____

SYNCHRONOUS COUNTERS

Aim: Design and Realization of 3-bit synchronous counters.

Apparatus Required: IC 7408, IC 7476, IC 7400, IC 7432, etc.
Design steps :
1. Write the truth-table or state diagram.
2. From truth-table/state-diagram, derive the state transition table.
3. Decide the no. and type of flip-flops to be used.
4. Using the corresponding excitation tables, derive the input and output
equations and simplify using K-maps.
5. Using the derived simplified input and output expressions with flipflops, draw the circuit diagram.
Procedure: 1. Connections are made as per circuit diagram.
2. Clock pulses are applied simultaneously at the clock I/Ps of all 7476 ICs
used in the circuit and the O/P is observed at the outputs of ICs 7476.
3. Truth table is verified.

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Internal Diagram of IC 7490

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Experiment No: 13

Date: __/__/____
DECADE AND BINARY COUNTERS

Aim: Realization of decade and binary counters.

Apparatus Required: IC 7408, IC 7476, IC 7400, IC 7432, IC 7490, IC 74192, IC 74193 etc.
Procedure (IC 74192, IC 74193):1. Connections are made as per the circuit diagram except the connection
from output of NAND gate to the load input.
2. The data (0011) = 3 is made available at the data i/ps A, B, C & D
respectively.
3. The load pin made low so that the data 0011 appears at QD, QC, QB & QA
respectively.
4. Now connect the output of the NAND gate to the load input.
5. Clock pulses are applied to count up pin and the truth table is verified.
6. Now apply (1100) = 12 for 12 to 5 counter and remaining is same as for 3 to
8 counter.

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Circuit Diagram for Decade

Counter

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Circuit diagram for Preset value=8, N=6 (To count from 8 to 3)

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Circuit Diagram: - Shift Left
Clock Serial i/p QA QB QC QD
1

SIPO (Right Shift):-

Clock Serial i/p QA QB QC QD

1

Clock

Serial
i/p

do=0

d1=1

d2=1

d3=1

0=do

1=d1

1=d2

1=d3

SISO:-

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QA QB QC

QD

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Experiment No: 14

Date: __/__/____
SHIFT REGISTERS

Aim:-

Realization of 3-bit counters as a sequential circuit and Mod-N counter

design (7476, 7490, 74192, 74193).

Apparatus Required: IC 7495, etc.

Procedure: Serial In Parallel Out:5. Connections are made as per circuit diagram.
6. Apply the data at serial i/p
7. Apply one clock pulse at clock 1 (Right Shift) observe this data at QA.
8. Apply the next data at serial i/p.
9. Apply one clock pulse at clock 2, observe that the data on QA will shift to QB
and the new data applied will appear at QA.
10. Repeat steps 2 and 3 till all the 4 bits data are entered one by one into the
shift register.

Serial In Serial Out:1. Connections are made as per circuit diagram.

2. Load the shift register with 4 bits of data one by one serially.
3. At the end of 4th clock pulse the first data d0 appears at QD.
4. Apply another clock pulse; the second data d1 appears at QD.
5. Apply another clock pulse; the third data appears at QD.
6. Application of next clock pulse will enable the 4th data d3 to appear at QD.
Thus the data applied serially at the input comes out serially at QD

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PISO:-

Mode Clock Parallel i/p

Parallel o/p

A B C D QA QB QC QD
1

1 0 1 1

X X X X

X X X X

X X X X

PIPO:-

Clock Parallel i/p

Parallel o/p

A B C D QA QB QC QD
1

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1 0 1 1

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Parallel In Parallel Out:1.
2.
3.
4.

Connections are made as per circuit diagram.

Apply the 4 bit data at A, B, C and D.
Apply one clock pulse at Clock 2 (Note: Mode control M=1).
The 4 bit data at A, B, C and D appears at QA, QB, QC and QD respectively.

Parallel In Serial Out:1. Connections are made as per circuit diagram.

2. Apply the desired 4 bit data at A, B, C and D.
3. Keeping the mode control M=1 apply one clock pulse. The data applied at A,
B, C and D will appear at QA, QB, QC and QD respectively.
4. Now mode control M=0. Apply clock pulses one by one and observe the data
coming out serially at QD.
Left Shift:1. Connections are made as per circuit diagram.
2. Apply the first data at D and apply one clock pulse. This data appears at QD.
3. Now the second data is made available at D and one clock pulse applied.
The data appears at QD to QC and the new data appears at QD.
4. Step 3 is repeated until all the 4 bits are entered one by one.
5. At the end 4th clock pulse the 4 bits are available at QA, QB, QC and QD.

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Circuit Diagram: - Ring Counter

Mode Clock QA QB QC QD
1

repeats

Johnson Counter:-

Mode Clock QA QB QC QD

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10

repeats

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Experiment No: 15

Date: __/__/____
JOHNSON COUNTERS / RING COUNTER

Aim:-

Design and testing of Ring counter/ Johnson counter.

Apparatus Required: IC 7495, IC 7404, etc.

Procedure: 1. Connections are made as per the circuit diagram.

2. Apply the data 1000 at A, B, C and D respectively.
3. Keeping the mode M = 1, apply one clock pulse.
4. Now the mode M is made 0 and clock pulses are applied one by one and the
truth table is verified.
5. Above procedure is repeated for Johnson counter also.

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Useful IC Pin details

7400(NAND)

7404(NOT)

7432(OR)

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7402(NOR)

7408(AND)

7486(XOR)

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7410(3-i/p NAND)

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7420(4-i/p NAND)

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