A
PROJECT
REPORT
ON CASCODE
CURRENT
MIRROR
(BIMOS LAB)
SUMITTED BY:
Reshbha Munjal
2k6/ECE/689
Rohit Garg 2k6/ECE/690
[Link] 2k6/ECE/691
Sahil Jindal 2k6/ECE/692
CERTIFICATE
This is to certify that the hardware project entitled Cascode Current Mirror done
by:
1. Reshbha Munjal 2k6/ECE/689
2. Rohit Garg 2k6/ECE/690
3. [Link] 2k6/ECE/691
4. Sahil Jindal 2k6/ECE/692
is an authentic work carried out by them at DCE under my guidance. The matter
embodied in this report has been true and sincere to the best of my knowledge.
Ms Neeta Pandey
(DCE)
ACKNOWLEDGEMEN
T
We would like to take this opportunity in thanking all our mentors in DCE
for their guidance and support. Without them we would not have been able
to make this project report. We would like to mention a special thanks to
Mrs. Neeta Pandey without whose help this project could not be possible.
They assisted us throughout the execution of the project with their in depth
knowledge of the subject. We are highly indebted to everyone who made
this project possible.
Reshbha Munjal 2k6/ECE/689
Rohit Garg 2k6/ECE/690
[Link] 2k6/ECE/691
Sahil Jindal 2k6/ECE/692
INDEX
ACKNOWLEDGEMENT
CERTIFICATE
AIM
APPARATUS
THEORY
PROCEDURE
ORCAD SIMULATION
AIM
To construct and
study the
characteristics of
a Cascode
Current Mirror.
APPARATUS
10 V DC SOURCES
CATHODE RAY OSCILLOSCOPE
FOUR 1R530 NMOS
TWO 1KΩ RESISTANCES
CONECTING WIRES
SOLDERING MACHINE
BREAD BOARD
THEORY
CURRENT MIRROR
A current mirror is a circuit designed to copy a current through one active device
by controlling the current in another active device of a circuit, keeping the output
current constant regardless of loading. The current being 'copied' can be, and
sometimes is, a varying signal current. Conceptually, an ideal current mirror is
simply an ideal current amplifier. The current mirror is used to provide bias
currents and active loads to circuits.
There are three main specifications that characterize a current mirror. The first is
the current level it produces. The second is its AC output resistance, which
determines how much the output current varies with the voltage applied to the
mirror. The third specification is the minimum voltage drop across the mirror
necessary to make it work properly. This minimum voltage is dictated by the
need to keep the output transistor of the mirror in active mode. The range of
voltages where the mirror works is called the compliance range and the voltage
marking the boundary between good and bad behavior is called the compliance
voltage. There are also a number of secondary performance issues with mirrors,
for example, temperature stability.
The main property/feature of a current source/sink is that the current though the
device is independent of the voltage across it. The figure below shows the most
basic of current sink. The current Lout is set by the voltage applied across the
gate-source of the device, the greater the voltage the larger the current flow
through the device. However as you can see from figure as the current
increases then the slope in the saturation increases – for an ideal current
sink/source we want this region to be flat i.e. very high resistance. These
saturation slopes extrapolate to a point on the –x axis known as the Channel
length modulation parameter λ, which is equal 1/-x, typical values are 0.01-0.05.
The smaller this value then the smaller the slope in saturation and the better the
current source/sink will be.
The output resistance rout is given by:
As the slope in saturation region is determined by the output resistance rout then
increasing this will greatly improve the performance of the current source/sink. In
addition we would like to reduce Vsat to allow larger voltage swings across the
device.
BASIC CURRENT MIRROR
The basic current mirror can also be implemented using MOSFET transistors, as
shown in figure. Transistor M1 is operating in the saturation or active mode, and
so is M2. In this setup, the output current IOUT is directly related to IREF.
The drain current of a MOSFET ID is a function of both the gate-source voltage
and the drain-to-gate voltage of the MOSFET given by ID = f (VGS, VDG), a
relationship derived from the functionality of the MOSFET device. In the case of
transistor M1 of the mirror, ID = IREF. Reference current IREF is a known current, and
can be provided by a resistor as shown, or by a "threshold-referenced" or "self-
biased" current source to ensure that it is constant, independent of voltage
supply variations.
Using VDG=0 for transistor M1, the drain current in M1 is ID = f (VGS, VDG=0), so we
find: f (VGS, 0) = IREF, implicitly determining the value of VGS. Thus IREF sets the
value of VGS. The circuit in the diagram forces the same VGS to apply to transistor
M2. If M2 also is biased with zero VDG and provided transistors M1 and M2 have
good matching of their properties, such as channel length, width, threshold
voltage etc., the relationship IOUT = f (VGS, VDG=0 ) applies, thus setting IOUT = IREF;
that is, the output current is the same as the reference current when VDG=0 for
the output transistor, and both transistors are matched.
The drain-to-source voltage can be expressed as VDS=VDG +VGS. With this
substitution, the Shichman-Hodges model provides an approximate form for
function f (VGS, VDG):
where, Kp is a technology related constant associated with the transistor, W/L is
the width to length ratio of the transistor, VGS is the gate-source voltage, Vth is the
threshold voltage, λ is the channel length modulation constant, and VDS is the
drain source voltage.
Output resistance
Because of channel-length modulation, the mirror has a finite output (or Norton)
resistance given by the rO of the output transistor, namely
where λ = channel-length modulation parameter and VDS = drain-to-source bias.
Compliance voltage
To keep the output transistor resistance high, VDG ≥ 0 V .That means the lowest
output voltage that results in correct mirror behavior, the compliance voltage, is
VOUT = VCV = VGS for the output transistor at the output current level with VDG = 0
V, or using the inverse of the f-function.
For Shichman-Hodges model, f -1 is approximately a square-root function.
CASCODE CURRENT MIRROR
The cascode is a two-stage amplifier composed of a transconductance amplifier
followed by a current buffer. Compared to a single amplifier stage, this
combination may have one or more of the following advantages: higher input-
output isolation, higher input impedance, higher output impedance, higher gain or
higher bandwidth. In modern circuits, the cascode is often constructed from two
transistors, with one operating as a common emitter or common source and the
other as a common base or common gate. The cascode improves input-output
isolation (or reverse transmission) as there is no direct coupling from the output
to input. This eliminates the Miller effect and thus contributes to a higher
bandwidth.
This term originally appeared in a January 1939 paper in the Review
Of Scientific Instruments by Hickman and Hunt entitled “On Electronic Voltage
Stabilizers.” They explained this term as a contraction of the phrase cascade to
cathode, which is the terminal of a triode vacuum tube that is functionally
analogous to the source of an MOS transistor. We will also consider the behavior
of an improved current mirror made from a pair of MOS cascodes.
The figure below shows an example of cascode amplifier with a common source
amplifier as input stage driven by signal source Vin. This input stage drives a
common gate amplifier as output stage, with output signal Vout.
The major advantage of this circuit arrangement stems from the placement of the
upper FET as the load of the input (lower) FET's output terminal (drain). Because
at operating frequencies the upper FET's gate is effectively grounded, the upper
FET's source voltage (and therefore the input transistor's drain) is held at nearly
constant voltage during operation. In other words, the upper FET exhibits a low
input resistance to the lower FET, making the voltage gain of the lower FET very
small, which dramatically reduces the Miller feedback capacitance from the lower
FET's drain to gate. This loss of voltage gain is recovered by the upper FET.
Thus, the upper transistor permits the lower FET to operate with minimum
negative (Miller) feedback, improving its bandwidth.
The upper FET gate is electrically grounded, so charge and discharge of stray
capacitance Cdg between drain and gate is simply through RD and the output load
(say Rout), and the frequency response is affected only for frequencies above the
associated RC time constant: τ = Cdg RD//Rout, namely f = 1/(2πτ), a rather high
frequency because Cdg is small. That is, the upper FET gate does not suffer from
Miller amplification of Cdg.
If the upper FET stage were operated alone using its source as input node, it
would have good voltage gain and wide bandwidth. However, its low input
impedance would limit its usefulness to very low impedance voltage drivers.
Adding the lower FET results in a high input impedance, allowing the cascode
stage to be driven by a high impedance source.
On the other hand, if the upper FET was replaced by a typical inductive/resistive
load, and only the input transistor used with the output taken from the input
transistor's drain, the cascode configuration offers the same input impedance,
potentially greater gain and much greater bandwidth.
Stability
The cascode arrangement is also very stable. Its output is effectively isolated
from the input both electrically and physically. The lower transistor has nearly
constant voltage at both drain and source and thus there is essentially "nothing"
to feed back into its gate. The upper transistor has nearly constant voltage at its
gate and source. Thus, the only nodes with significant voltage on them are the
input and output, and these are separated by the central connection of nearly
constant voltage and by the physical distance of two transistors. Thus in practice
there is little feedback from the output to the input. Metal shielding is both
effective and easy to provide between the two transistors for even greater
isolation when required. This would be difficult in one-transistor amplifier circuits,
which at high frequencies would require neutralization.
Biasing
As shown, the cascode circuit using two "stacked" FET's imposes some
restrictions on the two FET's -- namely, the upper FET must be biased so its
source voltage is high enough (the lower FET drain voltage may swing too low,
causing it to leave saturation). Insurance of this condition for FET's requires
careful selection for the pair, or special biasing of the upper FET gate, increasing
cost.
The cascode circuit can also be built using bipolar transistors, or MOSFETs, or
even one FET (or MOSFET) and one BJT. In the latter case, the BJT must be the
upper transistor; otherwise, the (lower) BJT will always saturate (unless
extraordinary steps are taken to bias it).
Advantages
The cascode arrangement offers high gain, high slew rate, high stability, and high
input impedance. The parts count is very low for a two-transistor circuit.
Disadvantages
The cascode circuit requires two transistors and requires a relatively high supply
voltage. For the two-FET cascode, both transistors must be biased with ample
VDS in operation, imposing a lower limit on the supply voltage.
CHARACTERISTICS OF CASCODE
The cascode configuration can be represented as a simple voltage amplifier (or
more accurately as a g-parameter two-port network) by using its input
impedance, output impedance, and voltage gain. These parameters are related
to the corresponding g-parameters below. Other useful properties not considered
here are circuit bandwidth and dynamic range.
The idealized small-signal equivalent circuit can be constructed for the circuit in
the figure below by replacing the current sources with open-circuits and the
capacitors with short circuits, assuming they are large enough to act as short-
circuits at the frequencies of interest. Small-signal parameters can be derived for
the MOSFET version, replacing the MOSFET by its hybrid-pi model equivalent.
This derivation can be simplified by noting that the MOSFET gate current is zero,
so the small-signal model for the BJT becomes that of the MOSFET in the limit of
zero base current:
where VT is the thermal voltage.
The combination of factors gmrO occurs often in the above formulas, inviting
further examination. For the bipolar transistor this product is
In a typical discrete bipolar device the Early voltage VA ≈ 100 V and the thermal
voltage near room temperature is VT ≈ 25 mV, making gmrO ≈ 4000, and a rather
large number. We find for the MOSFET in the active mode:
At the 65 nanometer technology node, ID ≈ 1.2 mA/μ of width, supply voltage is
VDD = 1.1 V; Vth ≈ 165 mV, and Vov = VGS-Vth ≈ 5%VDD ≈ 55 mV. Taking a typical
length as twice the minimum, L = 2 Lmin = 0.130 μm and a typical value of λ ≈ 1/(4
V/μm L), we find 1/λ ≈ 2 V, and gmrO ≈ 110, still a large value. The point is that
because gmrO is large almost regardless of the technology, the tabulated gain and
the output resistance for both the MOSFET and the bipolar cascode are very
large.
PROCEDURE
1. Arrange the various components on the Circuit Board.
2. Solder the various components to make the circuit.
3. Supply DC voltages to the circuit.
4. Study the characteristics of the Cascode.
5. Perform the software simulation of the circuit using ORCAD to verify the
result.
SIMULATION
RESULTS
PROGRAM
.model nmos NMOS(Level=3 U0=460.5 TOX=1.0E-8 TPG=1 VTO=0.62
JS=1.08E-6
+XJ=0.15U
+RS=417 RSH=1.81 LD=0.04U VMAX=130E3 NSUB=1.71E17 PB=0.761
ETA=0.00 THETA=0.129 PHI=0.905
+GAMMA=0.69 KAPPA=.10 CJ=76.4E-5 MJ=0.357 CJSW=5.68E-10
MJSW=0.302 CGSO=1.38E-10 CGDO=1.38E-10
+ CGBO=3.45E-10 KF=3.07E-28 AF=1 WD=+0.11U DELTA=0.42 NFS=1.2E11)
M1 1 1 0 0 nmos w = 1u, l = 1u
M2 2 1 0 0 nmos w = 1u, l = 1u
M3 4 3 2 0 nmos w = 1u, l = 1u
M4 3 1 0 nmos w = 1u, l = 1u
V1 3 0 3V
V2 4 0 5V
.dc V2 0 5 0.1
.probe
.end
