CANDIDATE DECLARATION

I hereby certify that the work which is being presented in the thesis titled “32-Bit
Multiplier Using Vedic techniques” by Mr. Kulwinder Singh in partial fulfilment of
requirements for the award of degree of [Link]. (ECE) submitted in the Department of
(ECE) at Yadavindra College of Engineering under Punjabi University, Patiala is an
authentic record of my own work carried out during a period from September to
February 2018 under the supervision of Parminder Singh Jassal (Assistant Professor,
ECE) & Ashwani Kumar (Assistant Professor, ECE). The matter presented in this
thesis not been submitted by me in any other University for the award of [Link] Degree.
Place: Kulwinder Singh
Date: Class Roll No. 21492107

This is to certify that the above statement made by the candidate is correct to the best
of my knowledge and belief.

(Signature of Examiner)

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 ACKNOWLEDGEMENT
I express my sincere gratitude to many people who have helped me and supported
during the thesis work. Without them I could not have completed the thesis on time.
I am thankful to m y guides, Er. Parminder Singh Jassal ( Assistant
Professor, ECE) & Ashwani Kumar (Assistant Professor, ECE) for his
encouragement, patience and valuable guidance throughout entire thesis.
I am falling short of words for expressing my feelings of gratitude towards my
teachers for extending their valuable guidance and timely support.
I also want to thank my colleagues and friends for their encouragement while
completing this thesis work, I want to thank my parents, without their emotional and
moral support nothing was possible. Their love and support always encouraged me,
and last but not least I am very thankful to God, who provided me good health and
good people around me.

Kulwinder Singh

[Link] (ECE)

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 ABSTRACT
This thesis work is devoted for the design of high speed 32 bit vedic multiplier. For
arithmetic multiplication various Vedic multiplication techniques like Urdhva
tiryakbhyam, Nikhilam and Anurupye has been thoroughly discussed. Multiplication
unit is the main part of any arithmetic logic unit for DSP and other digital applications
It has been found that Urdhva tiryakbhyam Sutra is efficient Sutra (Algorithm), giving
minimum delay for multiplication of all types of numbers, either small or large. The
32 bit vedic Multiplier is design with ripple carry adder which reduce the delay and
reduce the complexity of the design. The design is implemented in VHDL and
synthesis and simulation is done with the help of Xylinx ISE tool. In this thesis the
multiplier is design with lower bit to higher bit. Firstly the 2 bit vedic multiplier
should be design. In ordered to design 4 bit vedic multiplier, four 2 bit vedic
multiplier should be needed. The 8 bit vedic multiplier is implemented with the help
of 4 bit vedic multipliers. Similarly the 32 bit vedic multiplier is designed with the
help of 16 bit vedic multipliers. The desired results is achieved with the design
proposed multipler. The 32 bit vedic multiplier using multiplexer adder reduce the
delay 4.7% from conventional multiplier.

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 TABLE OF CONTENTS

Plagiarism certificate i
Candidate's declaration ii
Acknowledgement iii
Abstract iv
Table of Contents v
List of Figures viii
List of Table x
List of abbreviations xi
1. Introduction
1.1 Brief overview..............…………………………………………………………1

1.2 Multipliers...........................……………………………………………………..2

1.2.1 Array Multiplier………….......……………………………………………..2

1.2.1 Booth Multiplier…………...………………………………………………..3

1.2.3 Wallace-Tree Multiplier……………..……………………………………..3

1.2.4 Dadda Multiplier……………….…………………………………………..3

1.2.5 Vedic Multiplier………….………………………………………………...4

1.3 Advantages of Vedic Multiplier…………..…………………………………..…4

1.4 Objective of Thesis……………………………………………………………….5

1.5 Organization of Thesis……………………………………………………….5-6

2. Vedic Multiplier Techniques

2.2 Algorithm……………………………………………………………………….8

2.2.1 Urdhva Tiryakbhyam Sutra……………………………………………….8

2.2.2 Nikhliam Sutra…………………………………………………………...11

3. Literature Review
3.1 Span of Research Work……………………………………………………12-16

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4. Research Methodology
4.1 Methodology………………………………………………………………..…17

4.2 Steps for Designing and simulation………………………………………..18-21

5. Designing of Vedic Multiplier

5.1. 2*2 Vedic Multiplier…………………………….………………………..…24

5.2. 4*4 Vedic Multiplier……………………………………………………...….25

5.3. 8*8 Vedic Multiplier………………………………………………………….26

5.4. 16*16 Vedic Multiplier………………………………………………….……27

5.5. 32*32 Vedic Urdhva Multiplier………………………………………………29

5.6. 32*32 Nikhliam Vedic Multiplier………………….…………………………..31

6. Simulation and Result

6.2. 32 bit Nikhliam Vedic Multiplier……………………………………………34

6.3. 16 bit Vedic Multiplier……………………………………………………….35

6.4. 8 bit Vedic Multiplier…………….……………………………………….….36

6.5. 4 bit Vedic Multiplier……………….……………………………………..…37

7. Conclusion and Future Scope

7.2 Future Scope…………………………………………………………………..40

Reference........................................................................................41-43

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 LIST OF FIGURE
Fig.1.1. The vedic Multiplication……………………………………………………..4

Fig.2.1. Line diagram of two 3-bit numbers multiplication…..………………………9

Fig.2.2. vedic multiplication of three bit no………………………………………....10

Fig.2.3. Multiplication using N.............................................................……………..11

Fig.5.1. Architecture of 2 bit vedic multiplier………..........................................…...23

Fig.5.2. Architecture of 4 bit vedic multiplier…………………………………..…...24

Fig.5.3. Architecture of 8 bit vedic multiplier………………………………..……...25

Fig.5.4. Architecture of 16 bit vedic multiplier…………………………………..….26

Fig.5.5. Block diagram of 16 bit vedic mutiplier…………………………………....27

Fig.5.6. RTL Shematic of 16 bit vedic multiplier……………………………….…..27

Fig.5.7. Architecture of 32 bit Urdhva vedic multiplier………………………..… 28

Fig.5.8. RTL Shematic of 32 bit Urdhva vedic multiplier…………………..………29

Fig.5.9. Architecture of 32 bit Nikhilam vedic multiplier……………………..…….30

Fig.6.1. Simulation of 32 urdhva vedic multiplier…………………………….….….32

Fig.6.2. Simulation of 32 Nikhilam vedic multiplier…………………………..….…33

Fig.6.3. Simulation of 16 vedic multiplier……………………………………...……34

Fig.6.4. Simulation of 8 vedic multiplier…………………………………….......…..35

Fig.6.5. Simulation of 4 vedic multiplier……….……………………………….......36

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 LIST OF TABLE
Table No. Caption Page No.
6.1 Delay of vedic multipliers 37
7.1 comparison of Delay in vedic multipliers 38

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 LIST OF ABBREVIATIONS

IC Integrated circuits

VLSI Very Large Scale Integrated circuits

CPU Central Processing Unit

RAM Random access memory

DSP Digital Processing Unit

FFT Fast Fourier Transformation

ALU Arithmetic Logic Unit

VHDL VHSIC Hardware Description Language

FPGA Field Programmable Gate Arrays

RTL Register-transfer level

MUX Multiplexer

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