Lecture 4
Interfacing and Some
Common Building Blocks
CoE 111: Advanced Digital Design
Synchronous Data Transfer
• In synchronous systems, clock is used to coordinate data transfer.
• By design, the clock period is sufficiently long to accommodate wire delay and time
to get the data into the receiver.
• Assumes sender is ready to send data and receiver ready to receive data on each
cycle (How about for cases where the assumption does not hold?)
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Data Transfer with Control
• Overhead control signals are used to ensure that both ends are ready.
• Rx broadcasts ready signal (checked by Tx).
• Tx sends data and asserts valid (checked by Rx).
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Communicating Across Clock Boundaries
• Many synchronous systems need to interface to asynchronous input signals (ex.
interrupts from I/O, data transfers from devices with their own clocks).
• Problem: no known timing relationship between source and destination
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Synchronizer Circuit
• Use a flip-flop to bring asynchronous signal into timing domain of system clock.
• Produces synchronous input at each cycle that meets setup/hold time requirements of
the next stage
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Metastability
• When setup and/or hold times of a flip-flop are not met, flip-flop could be put into
metastable state.
• Noise will be amplified and push flip-flop to a stable state. However, in theory, the
time to transition to a stable state is unbounded.
• If the system uses a synchronizer output and the output is still in metastable state,
then it will lead to synchronizer failure.
• To avoid synchronizer failure, wait long enough before using a synchronizer’s
output.
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Reliable Synchronizer Design
• The probability that a flip-flop stays in metastable state decreases exponentially
with time.
• Solution: Any scheme that delays using the signal can be used to decrease the
probability of failure.
• If the clock period is greater than the metastability resolution time plus FF2 setup
time, FF2 gets synchronized version of ASYNCIN.
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FIFO Memory
• Used to implement queues
• Decouples producer and consumer
• Producer can perform many writes without consumer performing any reads (or vice
versa). However, because of finite buffer size, FIFO memories, on average, need
equal number of reads and writes.
• Typical uses:
• Interfacing I/O devices, such as network interface: Data bursts from network, then
processor bursts to memory buffer (operations not synchronized)
• Audio output: The processor produces output samples in bursts. Audio DAC clocks it out
at constant sample rate.
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FIFO Memory
• Allows sender and receiver to transfer data independently
• Need to consider buffer size (production, consumption rate)
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Memory Inference
// implementation of 64x1 RAM with asynchronous read
module ram64x1(clk, we, d, addr, q);
input clk, we, d;
input [5:0] addr;
output q;
reg [63:0] temp; // infers memory array
always@(posedge clk)
if (we)
temp[addr] <= d;
assign q = temp[addr]; // asynchronous read
endmodule
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Memory Inference
// implementation of 64x1 RAM with synchronous read
module ram64x1(clk, we, d, addr, q);
input clk, we, d;
input [5:0] addr;
output reg q;
reg [63:0] temp; // infers memory array
always@(posedge clk) begin
if (we)
temp[addr] <= d;
q <= temp[addr]; // synchronous read
end
endmodule
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Memory Inference
// implementation of a dual-read port 64x16 RAM
reg [15:0] ram [63:0];
always@(posedge clk)
if (we)
ram[wr_addr] <= din;
assign dout = ram[rd_addr1];
assign dout = ram[rd_addr2];
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[Link]
$readmemh ABCD
1234
• Used to initialize RAM B00B
FACE
• Useful for simulations 0101
• May not be synthesized (depends on tool)
reg [15:0] ram [63:0];
always@(posedge clk)
if (we)
ram[wr_addr] <= din;
assign dout = ram[rd_addr1];
assign dout = ram[rd_addr2];
initial begin
$readmemh(“[Link]”, ram);
end
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FIFO Memory
module fifo(clk, nrst, WE, RE, DIN, DOUT, full, empty);
input clk, nrst, WE, RE;
input [7:0] DIN;
output [7:0] DOUT;
output full, empty;
reg [7:0] memory [0:3];
reg [1:0] head, tail;
...
endmodule
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FIFO Memory
module fifo(clk, nrst, WE, RE, DIN, DOUT, full, empty);
...
always@(posedge clk)
if (!nrst)
tail <= 0;
else
if (WE)
tail <= tail + 1;
always@(posedge clk)
if (WE)
memory[tail] <= DIN;
...
endmodule
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FIFO Memory
module fifo(clk, nrst, WE, RE, DIN, DOUT, full, empty);
...
reg [7:0] DOUT;
always@(posedge clk)
if (!nrst)
DOUT <= 0;
else
if (RE)
DOUT <= memory[head];
always@(posedge clk)
if (!nrst)
head <= 0;
else
if (RE)
head <= head + 1;
...
endmodule
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FIFO Memory
module fifo(clk, nrst, WE, RE, DIN, DOUT, full, empty);
...
reg [2:0] count;
always@(posedge clk)
if (!nrst)
count <= 0;
else
case ({WE, RE})
2'b10: count <= count + 1;
2'b01: count <= count - 1;
endcase
assign empty = (count == 0)? 1’b1 : 0;
assign full = (count == 3'd4)? 1’b1 : 0;
...
endmodule
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FIFO Memory
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Purely Asynchronous Circuits
• Many researchers (and a few industrial designers) have proposed a variety of
circuit design methodologies that eliminate the need for a globally distributed clock.
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Self-timed Transfer
• Request/acknowledge “handshake” is used to coordinate data transfer.
• Note, transfer is insensitive to any delay in sending and receiving.
• Example below shows 4-cycle (“return-to-zero”) signaling. Communications are
represented by a wire transition followed by a reset; a transition sequence from 0
to 1 and back to 0 counts as single communication.
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Self-timed Transfer
• Example below shows 2-cycle (“non-return-to-zero”) signaling. It requires only 2
transitions. Communications are represented by any wire transition; transitions
from 0 to 1 and from 1 to 0 both count as communications.
• May lead to higher performance
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Counters
• Special FSMs that repeatedly sequence to a set of outputs
• Often used in hardware design since most computations include iteration (ex.
sequential multiplication, bit serial communication circuits)
• Other uses: clock divider
• Counters simplify controller design.
• Provides specific number of cycles of action
• Sometimes used with a decoder to generate a sequence of timed control signals
• Consider using a counter when FSM has little branching
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Example
Counters
reg [3:0] count;
wire done;
always@(posedge clk)
if (!nrst)
count <= 0;
else
if ((count == 0) && (en))
count <= count + 1;
else
if (count < 4’d13)
count <= count + 1;
assign done = (count == 4’d13)? 1’b1 : 1’b0;
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Shift Registers
• Useful for serial-to-parallel data conversion
reg [15:0] shiftreg;
always@(posedge clk)
if (!nrst)
shiftreg <= 0;
else
if (en)
shiftreg <= {din, shiftreg[15:1]};
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Example
Serial Adder
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Example
Serial Adder
// shift registers
reg [7:0] opA_sr, opB_sr, sum_sr;
assign sum = sum_sr;
// 1-bit adder
wire sum_1b, cout;
reg cin, init_cin;
assign {cout, sum_1b} = {1’b0, opA[0]} + {1’b0, opB[0]} + cin;
always@(posedge clk)
if (!nrst) cin <= 0;
else
if (init_cin) cin <= 0;
else cin <= cout;
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Example
Serial Adder
// controller
reg [1:0] state;
reg [2:0] count;
always@(posedge clk)
if (!nrst) begin
state <= 0;
end
else
case (state)
2’d0: if (en) state <= 2’d1;
else state <= 2’d0;
2’d1: state <= 2’d2;
2’d2: if (count == 3’d7) state <= 2’d3;
else state <= 2’d2;
default: state <= 2’d0;
endcase
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Example
Serial Adder
// controller: counter
always@(posedge clk)
if (!nrst)
count <= 0;
else
case (state)
2’d0: if (en) count <= 0;
2’d1, 2’d2: count <= count + 1;
endcase
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Example
Serial Adder
// controller: init_cin
always@(*)
if ((state == 2’d0) && en) init_cin <= 1’b1;
else init_cin <= 0;
// controller: done
always@(*)
if (state == 2’d3)
done <= 1’b1;
else
done <= 0;
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Example
Serial Adder
// controller: operand SRs
always@(posedge clk)
if (!nrst) begin
opA_sr <= 0;
opB_sr <= 0;
end
else
case (state)
2’d0: if (en) begin
opA_sr <= a; opB_sr <= b;
end
2’d1, 2’d2: begin
opA_sr <= {1’b0, opA_sr[7:1];
opB_sr <= {1’b0, opB_sr[7:1];
end
endcase
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Example
Serial Adder
// controller: sum SR
always@(posedge clk)
if (!nrst)
sum_sr <= 0;
else
if ((state == 2’d1) || (state == 2’d2))
sum_sr <= {sum_1b, sum_sr[7:1]};
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Automated Testing
• High-level constructs such as for and while loops can be employed to aid testing.
• Example: Serial-adder test
• Read test inputs from “memory”.
• Automatically set inputs of unit under test.
• Check if answer is correct (display result).
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Example
Serial Adder Test
reg [15:0] tests [0:64];
reg [15:0] current_test;
integer no_tests, i;
// clock generator
always
#5 clk = ~clk;
// memory for test inputs
initial begin
$readmemh(“[Link]”, tests);
end
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Example
Serial Adder Test
// UUT inputs / outputs
reg [7:0] a, b;
reg clk, nrst, en;
wire [7:0] sum;
// instantiation
serial_adder UUT(clk, nrst, en, a, b, sum);
initial begin
no_tests = 10;
nrst = 0;
en = 0;
clk = 0;
#8
nrst = 1’b1;
...
end
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Example
Serial Adder Test
initial begin
...
for (i=0; i<no_tests; i=i+1) begin
#10
current_test = test[i];
a = current_test[15:8];
b = current_test[7:0];
en = 1’b1;
#10
en = 0;
while(!done) begin #10; end
if (sum == (a + b))
$display(“%d+%d=%d correct”, a, b, sum);
else
$display(“%d+%d=%d wrong”, a, b, sum);
end
end
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