ISSN (Online) : 2455 - 3662

SJIF Impact Factor :5.148

EPRA International Journal of

Multidisciplinary
Research
Monthly Peer Reviewed & Indexed
International Online Journal

Volume: 5 Issue: 3 March 2019

Published By :EPRA Publishing

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Volume: 5 | Issue: 3 | March 2019 || SJIF Impact Factor: 5.148 ISSN (Online): 2455-3662

EPRA International Journal of

Multidisciplinary Research (IJMR) Peer Reviewed Journal

DESIGN OF CMOS BANDGAP VOLTAGE REFERENCE

CIRCUIT

Gayathri SK1 Pradeep B2

Department of Electrical and Electronics Department of Electrical and Electronics
Engineering, Engineering,
[Link] College of Engineering and [Link] College of Engineering and
Technology, Technology,
Pollachi, T.N, Pollachi, T.N,
India India

Krishnaveni N3
Department of Electrical and Electronics Engineering,
[Link] College of Engineering and Technology,
Pollachi, T.N,
India

ABSTRACT
This project implements the design of Bandgap reference circuit using the conventional method and the gm/ID method in
CMOS 180nm technology. The circuit is designed, simulated and output voltage reference is found to be 1.2V at room
temperature with the temperature range of -45°C to +125°C under a supply voltage of 1.8V. The BGR circuit is designed
using two methodologies they are the traditional method and gm/ID method. The circuit was designed using Cadence
Virtuoso schematic editor window and simulated using Spectre ADE. The bandgap reference circuit is used to provide a DC
reference voltage that has little dependence on temperature variations. The important building block of many analog circuits
is Temperature-independent references. They are commonly used in A/D and D/A converters, flash memories ,DRAMs as
well as in variable gain amplifiers. In addition to the voltage stabilization over wide temperature ranges, there are errors
introduced by process variations and power supply noise. The most widely used method for overcoming these challenges is
bandgap reference circuit.
KEYWORDS— Bandgap voltage reference (BGR), PTAT-Proportional to absolute temperature, CTAT-Complimentary
to absolute temperature, Temperature coefficient(TC).


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 EPRA International Journal of Multidisciplinary Research (IJMR) | ISSN (Online): 2455 -3662 | SJIF Impact Factor: 5.148

I. INTRODUCTION
In low-noise and low-jitter integrated circuits reference
voltages, with high robustness against supply noise or
temperature variations, are broadly demanded. Voltage
references are important for ADC, DAC or memories and they
are the essential part of every chip as the proper working
conditions of the circuit needs some biasing. The voltage
reference are required to be accurate and constant i.e.
independent on temperature and supply voltage, preferably
independent of the process and mismatch, low voltage and low
power. It is hardly possible to design a circuit with ideal
parameters and in most cases, temperature and supply voltage
independence are preferred. These circuits can be useful for
some applications due to their simplicity, despite poor voltage
reference accuracy. Bandgap reference circuit is designed to
produce a stable and precise output reference voltage which is Figure 1: PTAT voltage realization
independent of variations in Process, Voltage, and
Temperature (PVT). The PTAT circuit is shown in Fig[1] is simulated and the
Based on the slope of variations through a wide temperature behaviour is shown in Fig[2]
temperature range, the temperature coefficient (TC) is either
positive or negative. If both the positive and negative TC
quantities participate in summation with proper proportion we
can able to achieve a zero TC. For example, the base-emitter
voltage of BJT transistor, VBE and the thermal voltage (VT),
are known as negative and positive TC voltage terms
respectively. Then, a zero TC voltage, VRef can be constructed
by summing them.

II. PTAT CIRCUIT

The topology that provides PTAT TC is shown in Fig[1].
Assume that there are two identical NPN bipolar transistors Figure 2: Graph of the PTAT circuit
Q1 and Q2, each one has a diff erent DC bias current. Their
base and collector are connected and thus they behave like a III. CTAT CIRCUIT
diode. The simplified Shockley's equation is given by Eq.[3] A simple diode is used in order to generate CTAT circuit.
it describes current through the diode and from the Eq.[3] Vbe NPN transistor shown in Fig.[5] has a base and collector
is expressed by Eq.[4]. connected which in turn act as diode that has two terminals. In
Ic = Is ·exp(Vbe/VT) (3) this configuration, the base-emitter junction is exploited to
Vbe = kT /q ·ln(Ic/Is) (4) obtain a diode. If a positive voltage is applied to pn junction, a
Eq.[5,6] show voltage across these two BJTs forward biased region is entered. The relationship between I-V
Vbe1 = VT ·ln(Ic1/Is) (5) is approximated by Eq.[9] called Shockley’s equation.
Vbe2 = VT ·ln(Ic2/Is) (6) I = Is ·exp( V /VT ) (9)
∆Vbe = Vbe2 −Vbe1 = VT ·ln(Ic2/Ic1) (7) VT = thermal voltage, given by Eq.[10]
VT is thermal voltage. Compare Equation 4,7 and it is Is = saturation current
evident that the expression is directly proportional to
temperature i.e VT = kT/q. Therefore ∆Vbe is rising with
temperature so it is known as PTAT circuit. The term
ln(Ic2/Ic1) is a design choice of diff erent currents. The same
circuit can be built with the same currents Ic1 = Ic2 and use
diff erent area of PN junction. Or both principles together can
be used, i.e. diff erent current and area.

Figure 3: CTAT voltage realization

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consequence, controlled temperature dependent voltage close

VT = kT/q ≈ 26mV/K T = 300K (10) to the material bandgap of silicon(~1.22V) results. Voltage
where k = Boltzmann’s constant = 1.38e-23 J/K references obtained according to this approach are called
T = the absolute temperature in Kelvin bandgap reference(BGR) circuits.
q = the magnitude of elementary electron charge = 1.60e-19 C
It can be derived, As mentioned before, to compensate temperature
∂V be/∂T ∼ = −2mV/K (11) dependence the BGR circuit is designed by exploiting CTAT
The temperature behavior of diode connected bipolar and PTAT. The thermal voltage VT = kT/q has a positive
transistor was simulated. The ∂V be/∂T of NPN (180nm PDK) temperature coefficient (PTAT) and it rises by +85uV/K.
is −2.27mV/K at room temperature, the reference simulation Voltage base-emitter Vbe has a negative temperature
result is shown in Fig.[4]. coefficient (CTAT) and its drop is about -2mV/K. Ideally, a
M zero TC is achieved by adding these two voltages, the
simulation result of BGR is shown in Fig.[6]. It is evident that
PTAT and CTAT are diff erent scales, therefore PTAT is
multiplied by constant K to ensure their mutual compensation.
Then the basic relation for BGR is
VREF = m*VPTAT(T)+n*VCTAT(T). (12)
Ideal means that output voltage Vref has zero TC.

Figure 4: Graph of the CTAT circuit

IV. BANDGAP REFERENCE VOLTAGE

Bandgap reference (BGR) is used in both analog and digital
circuits. It is an analog reference integrated circuit. In today’s
market, the ICs are being built to achieve higher integration
and higher performance. Due to this trend the ICs have Figure 6: Zero TC due to PTAT and CTAT
become complex and dependent on parameters such as
temperature, supply voltage and process corners (TVP). The
block diagram of BGR is shown in Fig[5]
V. DESIGN
The BGR design is given below
(16)
(17)

Slope of Vref =0 which implies

(18)

By solving the equation with values

and α2=1, we get α1=18.82

(19)
Figure 5: Block diagram of the Bandgap reference voltage
Where Io=5µA, VT=26mV, N=2
circuit
Thus R1=3.6kΏ

A conventional bandgap reference is a circuit that (20)

performs summation of the forward-biased diode voltage
having a negative temperature coefficient and a voltage Substituting the values we get R2=97.74kΏ
proportional to absolute temperature (PTAT). As a

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The basic circuit diagram with designed resistance values is

shown in Fig [7].

Figure 8: Simulation Diagram of PTAT

The simulated result of the PTAT circuit is shown in Fig [9],

the output voltage is varying proportionally with respect to
temperature.

Figure 7: Circuit Diagram of BGR

VI. RESULTS
The circuits are designed using Cadence –Virtuoso Schematic
Editor in 180nm CMOS technology. The circuits are simulated
using Cadence Spectre and the results of the simulations are
analyzed
The PTAT circuit with a current mirror for constant current
supply is simulated it is shown in Fig [8].

Figure 9: Simulation Results of PTAT

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The CTAT circuit with a constant current source is simulated

it is shown in Fig [10].
The simulated result of the CTAT circuit is shown in Fig [11],
the output voltage is inversely proportional to absolute
temperature.

Figure 12: Simulation Diagram of BGR

Figure 10: Simulation Diagram of CTAT

Figure 13: Simulation Results of BGR

The MOSFET is characterized using the gm/ID, optimized for

Figure 11: Simulation Results of CTAT a specific width and the BGR circuit is designed. The designed
BGR is simulated in the cadence virtuoso environment it is
shown in Fig [14]. The designed BGR circuit is simulated by
This BGR is built in the cadence environment and it is ADXL window for a range of temperature from -45oc to
+125oc and the output waveform is shown in Fig [15].
simulated for the temperature sweep it is shown in Fig[12].
The simulated result of BGR is shown in Fig[13], it is plotted
for PTAT, CTAT and BGR voltages with respect to
temperature

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 EPRA International Journal of Multidisciplinary Research (IJMR) | ISSN (Online): 2455 -3662 | SJIF Impact Factor: 5.148

Figure 15: Simulation Results of BGR using gm/ID

Parameter Traditional method gm/ID method
VII. CONCLUSION
Supply Voltage 1.8v 1.8v
A bandgap reference circuit that produces 1.22 V was
Output Voltage 1.53v-1.57v 1.23v-1.26v presented. All the design specifications were met at
Range nominal operating conditions and displayed over the design
temperature range of -45oc to 125oc. The circuit is designed
Output Variations 40mv 30mv for operation with a 1.8V supply. Simulations also showed
the circuit meets the design at most of the corners but could
Temperature Range -45 to 125oc -45 to 125oc
be improved in future work. The BGR is designed using
the traditional method. The circuit was designed in the
virtuoso schematic editor and simulated using ADXL window.
The parameter analysis of the BGR circuit is achieved. The
parameter analysis and comparison of traditional method and
gm/ID method is tabulated in the Table
Table: Parameter Analysis
. REFERENCES
1. B. Razavi, “Design of Analog CMOS Integrated Circuits,”
Tata McGraw Hill Edition,2002
2. [Link], [Link], and [Link], “CMOS Circuit Design,
Layout, and Simulation,” IEEE Press Series on Microelectronic
Systems, 2002.
3. [Link], and [Link], “CMOS Digital Integrated Circuits:
Analysis and Design,” McGraw-Hill Publication, 3rd Edition,
2003.
4. Lianxi Liu, Junchao Mu, and Zhangming Zhu, “A 0.55V,28-
ppm/oc,83-nw CMOS sub-BGR with UltraLow Power Curvature
Compensation”, IEEE Transactions on Circuits and Systems-
I,[Link].1,January 2018
5. Jonathan [Link], Jorge Guilherme and Nuno Horfa, “Design of
a BGR Suitable for the Space Industry with Performance of 1.2V
with 0.758ppm/oc TC from 55oc to 125oc”, NGCAS2017-New
Generation of circuits and systems
6. R.E. Best, “CMOS Design of analog circuits and Applications,”
Figure 14: Simulation of gm/ID BGR McGraw-Hill Publication, 5th Edition, 2003
7. [Link], and [Link], “CMOS Digital Integrated Circuits:
Analysis and Design,” McGraw-Hill Publication, 3rd Edition,
2003.

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