Name :- Bharat Arora
Section :- A RollNo:- 18
University Rollno :- 191500212
OBJECTIVES :
The following will detail the necessary requirements to implement a display into a circuit. This
application note will also provide the basic functionality of a seven-segment display. In terms
of hardware, the implementation of the display into a counter using a CD74HC4511E driver will be
discussed. Schematics are included in order to explicitly show the correct implementation of the
display into a simple binary counter.
MATERIALS/EQUIPMENT
NEEDED DC Voltage Source (capable of 10 Vdc)
(1) four-bit dip switch
(1) 7447 (BCD to seven-segment decoder driver)
(7) 470 Ω - current limiting resistors
(4) 1kΩ – resistors
(1) Common anode seven segment display
INTRODUCTION
A seven-segment decoder is a logic circuit often used for the visual display of digital information.
The seven outputs of the decoder will drive the seven segments on a corresponding display. BCD is
the acronym for Binary Coded Decimal. The BCD system is used to represent the decimal numbers
from 0 to 9 in a binary format suitable for digital devices. A four-bit code is required with the decimal
characters 0 through 9 represented by the binary numbers 0000 through 1001. The combinations
1010 through 1111 are not used. A BCD to seven-segment decoder will allow the display of a binary
coded decimal on a seven-segment display. The input to the decoder is a number from 0 through 9
in BCD and the output provides the seven inputs required to drive the seven-segment display.
In the early years of digital design such a logic circuit would have been implemented using SSI
technology; however, for many years popular circuits such as the BCD to seven-segment decoder
have been available in MSI packages. Although our design will include the development of logic
circuits for the BCD to seven-segment decoder, to simplify our laboratory circuit, the 7447 (BCD to
seven-segment decoder driver) will be used. Simple dipswitches will provide the BCD input to the
7447 and the output of which will drive the seven-segment display. The display controller for a BCD
to seven-segment decoder/driver will be developed
PRELAB 1.
Create the truth table describing the function of a BCD to seven-segment decoder. The lower case
letters, a-g, represent the segments on the display while the upper case letters A-D represent the
BCD input. Observe that A is the lest-significant bit of the BCD input.
Procedure
Bring flash drives to store your data.
Ask the TA questions regarding any procedures about which you are uncertain
. Implement the complete design (synthesize, map, and Place & Route) of your two designs using the
Xilinx ISE tools. Program the FPGA using the bit-stream file which is generated in the process.
Te four 4-bit inputs to the four 7-segment displays on the Nexsys board should be the following:
1. Te first 4 of the 8 switches on the Nexsys board
2. Te last 4 of the 8 switches on the Nexsys board
3. A + B (the 4-bit sum of the two values above; ignore the effects of overflow)
4. A – B (the 4-bit difference of the two values above; ignore sign & underflow)
For checkoff, you will show the TA the following:
1. Show the two designs working on the board.
2. Demonstrate the input patterns you have used in the test bench. Show that your simulation
results above match the observed waveforms on the DLA.
3. Demonstrate your 4-digit display to your TA with the clock at 1 KHz.
Result:
Seven Segment Display is been implemented and verified.
