Lecture 5: Memory Addressing
KT6144 / KT6213
! The common memory-addressing techniques are as follows:
◦ Immediate addressing
◦ Absolute addressing
◦ Indexed addressing
◦ Indirect addressing
◦ Indexed-indirect addressing
◦ Base-displacement addressing
◦ PC-relative addressing
◦ Stack-register addressing
◦ Auto increment and auto decrement addressing
◦ Segment-register addressing
KT6144 / KT6213
KT6144 / KT6213
! Operand is part of instruction
! Operand = address field
! e.g. ADD #5
◦ Add 5 to contents of accumulator
◦ 5 is operand
! No memory reference to fetch data
! Fast
! Limited range
Instruction
Opcode Operand
KT6144 / KT6213
! Address field contains address of operand
! Effective address (EA) = address field (A)
! e.g. ADD A
◦ Add contents of cell A to accumulator
◦ Look in memory at address A for operand
◦ Other example
SUB $100
ADD $1001
! Single memory reference to access data
! No additional calculations to work out effective address
! Limited address space
KT6144 / KT6213
Instruction
Opcode Address A
Memory
Operand
KT6144 / KT6213
! Operand is held in register named in address filed
! EA = (R)
! Limited number of registers
! Very small address field needed
◦ Shorter instructions
◦ Faster instruction fetch
! No memory access
! Very fast execution
! Very limited address space
! Multiple registers helps performance
◦ Requires good assembly programming or compiler writing
◦ i.e. C programming
" register int a;
! Compare With: Direct addressing
KT6144 / KT6213
Instruction
Opcode Register Address R
Registers
Operand
KT6144 / KT6213
! Using index registers
! One field of the instruction holds index-register
designator
! Effective address is calculated, based on the value at the
designated index-register and the address field in the
instruction
IR = base (Index register)
D = displacement
EA = IR + D
Good for accessing arrays
EA = IR + D
IR++
KT6144 / KT6213
Instruction
OP 0 IR Displacement D
Memory
Index Registers
0
1
2 Operand
3
4 +
5
6
7
KT6144 / KT6213
! Indicated index register is automatically incremented or
decremented
! post-, pre-incremented
++R, R++
! post-, pre-decremented
--R, R--
KT6144 / KT6213
! Memory cell pointed to by address field contains the address of
(pointer to) the operand
! EA = (A)
◦ Look in A, find address (A) and look there for operand
! e.g. ADD (A)
◦ Add contents of cell pointed to by contents of A to
accumulator
! Large address space
! 2n where n = word length
! May be nested, multilevel, cascaded
◦ e.g. EA = (((A)))
" Draw the diagram yourself
! Multiple memory accesses to find operand
! Hence slower
KT6144 / KT6213
Instruction
Opcode 1 Address A
Memory
Indirection bit Pointer to operand
Operand
KT6144 / KT6213
! Indirect addressing is denoted by an indirection bit
◦ 0 - direct addressing
◦ 1 - indirect addressing
! Example
◦ When use in branch instruction
" target address will cover larger address space
depending on the width of the main memory
KT6144 / KT6213
Indirect branch Instruction Main Memory
Opcode 123
Branch address
123 Target address
Target address Target instruction
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! Compare with: indirect addressing
! EA = (R)
! Operand is in memory cell pointed to by contents of
register R
! Large address space (2n)
! One fewer memory access than indirect addressing
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Instruction
Opcode Register Address R
Memory
Registers
Pointer to Operand Operand
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Instruction
OP 1 IR Displacement D
Memory
Index Registers
0
1
2
3
Operand address
4 Pointer to Operand +
5
6
7 Operand
KT6144 / KT6213
Instruction
OP B D
Main Memory
Base Registers
0
1
2 Efective address
Operand
3
4 Pointer to Operand +
5
6
7
KT6144 / KT6213
Instruction
OP I B D
Main Memory
Base Registers
0
1
2 Efective address Operand
3
4 Pointer to Operand +
5
6
7
Index Registers
0
1
2
3
4 Pointer to Operand
5
6
KT6144 / KT6213
7
! PC - Relative Addressing
◦ A version of base-displacement addressing
◦ B = Program counter, PC
EA = D + (PC)
! Stack-register Addressing
◦ Operand is (implicitly) on top of stack
◦ e.g.
ADD pop top two items from stack
and add
KT6144 / KT6213
• Ease of Implementation (Job of Architect/Designer)
– Does the ISA lead itself to efficient implementations?
• Ease of Programming (Job of Programmer/Compiler)
– Can the compiler use the ISA effectively?
• Future Compatibility
– ISAs may last 30+yrs
– Special Features, Address range, etc. need to be thought
out
KT6144 / KT6213
• 32-bit ISA, instructions could be huge (up to 321), 16 GPRs
• Operated on data types from 8 to 128-bits,
decimals, strings
• Orthogonal, memory-to-memory, all operand
modes supported
• Hundreds of special instructions
• Simple compiler, hand-coding was common
• CPI was over 10!
KT6144 / KT6213
• Variable length ISA (1-16 bytes)
• FP Operand Stack
• 2 operand instructions (extended accumulator)
– Register-register and register-memory support
• Scaled addressing modes
• Has been extended many times (as AMD has recently done
with x86-64)
• Intel, initially went to IA64, now backtracking
KT6144 / KT6213
! Complex instruction set computer
many addressing modes;
many operations.
! Reduced instruction set computer
load/store;
pipelined instructions.
KT6144 / KT6213
CISC RISC Superscalar
IBM DEC VAX Intel Motorola MIPS IBM Intel
370/168 11/780 486 88000 R4000 RS/6000 80960
1973 1978 1989 1988 1991 1990 1989
No. of instruction
208 303 235 51 94 184 62
Instruction size (octets)
2-6 2-57 1-11 4 32 4 4 or 8
Addressing modes
4 22 11 3 1 2 11
GP Registers
16 16 8 32 32 32 23-256
Control memory (k bytes) (microprogramming)
420 480 246 0 0 0 0
KT6144 / KT6213
! In the early 1980s, several architects started investigating computers
with simple ISAs, similar to that of CDC 6600. Computer scientists
employed the term RISC, for reduced-instruction-set computers, to
describe these machines. Although no definition is universally
accepted, a RISC computer has most of the following properties:
[Link] are conceptually simple.
[Link] are of a uniform length.
[Link] use one (or very few) instruction formats.
[Link] instruction set is orthogonal (that is, there is little overlapping of
instruction functionality).
[Link] use one (or very few) addressing modes.
[Link] architecture is a load-and-store architecture (only load and store
instructions reference memory; all operate instructions are register-to-
register instructions).
[Link] ISA supports two (or a few more) datatypes (typically integer and
floating point).
KT6144 / KT6213
! There are two schools of thought on instruction-set design: one
favors complex instruction sets, the other favors reduced
instruction sets. Proponents of CISC architectures give many
arguments in their favor, including the following:
◦ Richer (more complex) instruction sets improve the merit of
the architecture, since operations implemented in microcode
execute faster than operations implemented in software.
◦ Richer instruction sets do not increase the cost of
implementation (in dollars) over that of simpler instruction
sets.
◦ The need for upward compatibility within a family results in an
increase in the instruction-set size, and upward compatibility is
easier to implement in microcode.
◦ Richer instruction sets simplify compiler design.
◦ Complex instructions sets make cloning of a computer more
difficult, thus protecting proprietary designs.
KT6144 / KT6213
! Some of the reasons proponents give in favor of RISC
architectures are:
◦ The basic hardware is simpler, so it can be cheaper and
faster, more than compensating for the increased
number of instructions required to perform some
operations.
◦ Instruction caches easily compensate for the large
number of bits in the instructions required by a RISC.
◦ It is easier to compile for a RISC than for a CISC
architecture.
◦ Design effort, and hence development cost, for a RISC is
less than for a CISC.
◦ It is easier to introduce parallelism into the control unit
of a RISC than a CISC.
KT6144 / KT6213
! From the standpoint of designing a computer family, a
designer must consider the following factors when deciding
between a RISC or a CISC architecture.
◦ If the ISA is successful and too simple, it invites plug-
compatible competition (cloning).
◦ If the ISA is too complex, supercomputer and pipelined
implementations may be impossible.
◦ If the instruction encoding is too inefficient, large
programs will use excessive memory and memory
bandwidth. The memory system and its connection to the
CPU is an expensive component of computers. The
increased memory bandwidth of a RISC may well make it
more expensive, negating a major RISC advantage.
KT6144 / KT6213
! Quantitative
◦ compare program sizes and execution speeds
! Qualitative
◦ examine issues of high level language support and use of
VLSI real estate
! Problems
◦ No pair of RISC and CISC that are directly comparable
◦ No definitive set of test programs
◦ Difficult to separate hardware effects from compiler
effects
◦ Most commercial devices are a mixture
KT6144 / KT6213
! storage order of words
◦ little-endian - store the little end of the word first
! processor organisation
◦ registers
◦ where it stores information
◦ what it does in executing instructions
◦ MIPS:
" all registers are 32-bit
" PC (program counter) holds address of next instruction
" 32 general purpose registers (can use name or number)
" instruction set: load & store, operations, jump & branch,
others
KT6144 / KT6213
• Simplicity favors regularity
– fixed size instructions – 32-bits
– only three instruction formats
• Good design demands good compromises
– three instruction formats
• Smaller is faster
– limited instruction set
– limited number of registers in register file
– limited number of addressing modes
• Make the common case fast
– arithmetic operands from the register file (load-store
machine)
– allow instructions to contain immediate operands
KT6144 / KT6213
! All
MIPS instructions are 32 bits long. The three instruction
formats are:
31 26 21 16 11 6 0
R-type op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
I-type 31 26 21 16 0
op rs rt immediate
6 bits 5 bits 5 bits 16 bits
J-type 31 26 0
op target address
6 bits 26 bits
! The different fields are:
◦ op: operation of the instruction
◦ rs, rt, rd: the source and destination register specifiers
◦ shamt: shift amount
◦ funct: selects the variant of the operation in the “op” field
◦ address / immediate: address offset or immediate value
◦ target address: target address of the jump instruction
KT6144 / KT6213
Instruction formats and addressing modes
Instruction formats
• register
• immediate
• jump
Addressing modes
• immediate - value built in to the instruction
• register - register used for data
Memory referencing - used with load and store instructions
• label - fixed address built in to the instruction
• indirect - register contains the address
• Base addressing - field of a record
• Indexed addressing - element of an array
KT6144 / KT6213
Instruction formats
! all instructions fit in 32-bit words
! decoding starts with the leftmost 6-bits, the op code
Register
! For operations using only registers as operands, the operation code is
000000
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
000000 src reg target reg Dest shift amt function
000000 01010 00111 00101 00000 100010
! the last line of the table gives as an example a subtract instruction, sub
$5, $10, $7
! 3 5-bit fields identify the 3 regs: src, target/src, dest (diff from assembly)
KT6144 / KT6213
Instruction formats (Register)
! flow between registers and ALU
! add $t3, $t1, $t2
◦ $t1 = $9, $t2 = $10, $t3 = $11
KT6144 / KT6213
Immediate
! 16-bit immediate (constant), 6-bit op, 2 regs
! addi $t1, $t2, 0xfffe (actually adds 0xfffffffe, -2)
! shorter numbers are sign extended
6 bits 5 bits 5 bits 16 bits
op code src reg target reg immediate value
001000 01010 01001 1111 1111 1111 1110
KT6144 / KT6213
Jump
! use all 26-bits following the op code for jump address
! last 2 bits are always 0 (word alignment)
! upon execution, the 26-bit jump target is shifted left 2 bits
and stored in the PC, causing the jump
6 bits 26 bits - jump target (words)
j 0x0040000c
000010 0x0100003
! can only target the first 256Mb of memory
! workarounds: reserve “low” memory, use jump-reg instructions
KT6144 / KT6213
! First, let’s think about how different instructions get
executed
KT6144 / KT6213
KT6144 / KT6213
Step 2: Components of the Datapath
CarryIn
! Adder
A
32
Adder
Sum
32
B Carry
! MUX 32
Select
A
32
MUX
! ALU Y
32
B
32
OP
3
A
32
ALU
Result
32 Combinational Logic:
B
32 Does not use a clock
KT6144 / KT6213
• Fetching instructions involves
– reading the instruction from the
Instruction Memory
– updating the PC to hold the
address of the next instruction
– PC is updated every cycle, so it
does not need an explicit write
control signal
– Instruction Memory is read every
cycle, so it doesn’t need an explicit
read control signal
KT6144 / KT6213
• Decoding instructions involves
– sending the fetched instruction’s opcode and function
field bits to the control unit
– reading two values from the Register File
• Register File addresses are contained in the instruction
KT6144 / KT6213
• R format operations (add, sub, slt, and, or)
– perform the indicated (by op and funct) operation on values in rs and
rt
– store the result back into the Register File (into location rd)
– Note that Register File is not written every cycle (e.g. sw), so we need
an explicit write control signal for the Register File
KT6144 / KT6213
• Load and store operations
– compute a memory address by adding the base register
(in rs) to the 16-bit signed offset field in the instruction
• base register was read from the Register File during
decode
• offset value in the low order 16 bits of the instruction
must be sign extended to create a 32-bit signed value
– store value, read from the Register File during
decode,must be written to the Data Memory
– load value, read from the Data Memory, must be stored
in the Register File
KT6144 / KT6213
KT6144 / KT6213
• Branch operations have to
– compare the operands read from the Register File during
decode (rs and rt values) for equality (zero ALU output)
– compute the branch target address by adding the updated
PC to the sign extended16-bit signed offset field in the
instruction
• “base register” is the updated PC
• offset value in the low order 16 bits of the instruction must
be sign extended to create a 32-bit signed value and then
shifted left 2 bits to turn it into a word address
KT6144 / KT6213
KT6144 / KT6213
• Jump operations have to
– replace the lower 28 bits of the PC with the lower 26
bits of the fetched instruction shifted left by 2 bits
KT6144 / KT6213
• Assemble the datapath segments, add control lines as
needed, and design the control path
• Fetch, decode and execute each instructions in one
clockcycle – single cycle design
– no datapath resource can be used more than once per
instruction, so some must be duplicated (e.g., why we
have a separate Instruction Memory and Data Memory)
– to share datapath elements between two different
instruction classes will need multiplexors at the input of
the shared elements with control lines to do the
selection
• Cycle time is determined by length of the longest path
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• Selecting the operations to perform (ALU, Register File and Memory read/
write)
• Controlling the flow of data (multiplexor inputs)
• Information comes from the 32 bits of the instruction
• Observations
– op field always in bits 31-26
– addr of two registers to be read are always specified by the rs and rt
fields (bits 25-21 and 20-16)
– addr. of register to be written is in one of two places – in rt (bits 20-
16) for lw; in rd (bits 15-11) for R-type instructions
– base register for lw and sw always in rs (bits 25-21)
– offset for beq, lw, and sw always in bits 15-0
KT6144 / KT6213
Almost – ALU control is yet to be expanded
KT6144 / KT6213
