Exercise 2 - Summer Semester 2019

April 24, 2019

This document is part of the laboratory for the exam ”Fundamentals of

IC Deign”. It is for students attending the same-named lecture organized by
the Institute for Integrated Circuits of the TUHH. All information is supplied
without liability.

During this laboratory the simulation software LTSpice by Analog Devices

will be used.

Exercise 2 helps students understand how biasing circuits are designed (in spe-
cific ß-multiplier circuit). Once the students have gained basic understanding
on ß-multiplier circuits, they should be able to design it on LTSpice for the
specifications provided in this documents. Upon successful implementation of
the design, students have to submit a report in the form of electronic letter.
Institute for Integrated Circuits
Prof. Dr.-Ing. Matthias Kuhl

Task 2 Introduction to biasing circuits

Task 2.1 The elementary biasing circuit

A basic NMOS current mirror shown in the Figure 1, copies the current Iref in the output
branch. The mirroring equation is given by
W2
Io L2 1 + λ(Vo − VDS1,sat )
= W1
(1)
Iref L1
1 + λ(VDS1 − VDS1,sat )

For now, if the channel length modulation λ is neglected, then the mirroring ratio is only
dependent on the W L
ratio of transistors M1 and M2 .

Figure 1: Schematic of the basic current mirror.

The current Iref can simply be generated using a resistor between the supply VDD and
VGS1 as shown in Figure 2 and the current equation is then given by
VDD − VGS1 KPn W1
Iref = = (VGS1 − Vthn )2 (2)
R 2 L1

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Figure 2: Elementary biasing circuit.

Ths output current Io of the biasing circuit presented in Figure 2 is dependent on the
supply VDD and it’s sensitivity w.r.t VDD is given by
W2  
VDD ∆Io VDD L2 gm1
SenIVoDD = = W1
(3)
Io ∆VDD Io L1
1 + gm1 R

Note that the equation 3 does not take channel length modulation into consideration.

In 350 nm CMOS technology, VDD = 3.3 V , KPn = 180 µA/V 2 , VGS = 500 mV and
if VDsat = 200 mV is chosen, then as shown in Figure 2, a resistor R = 260 kOhms is
required the generate an output current Io of 10 µA. The transconductance gm1 is calcu-
lated to be 108 µS and hence the sensitivity SenIVoDD = 1.22 using equation 3. Simulating
the same in LTSpice, the sensitivity was found out to be SenIVoDD = 1.21 as shown in
the graph 3. It is inferred from the graph and the sensitivity equation that the output
current Io is highly sensitive to supply VDD variations and hence the circuit has low line
regulation.

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Figure 3: Output current vaiation w.r.t supply variations for the schematic shown in Figure 2.

Note: One can simulate and verify the design on LTSpice.

Task 2.2 ß-multiplier circuit

Task 2.2.1 Understanding the background

As discussed in the previous section, the circuit shown in Figure 2 is not supply indepen-
dent which is a major drawback. In order to attain supply independency, consider placing
the resistor R on the source of the nMOS rather than on the drain as shown in Figure
4. Suppose a current Iref is flowing in both the branches of Figure 4 and the transistors
M 1 and M 2 have a ratio ß2 = Kß1 , where β = KPn W L
, then the reference current can be
written as

VGS1 − VGS2
Iref = (4)
R

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Figure 4: Resistor connected to the drain of nMOS.

which is only valid when VGS1 > VGS2 and is accomplished by using larger value for ß2
and hence the name ß-multiplier. Now that the current reference Iref is generated from
equation 4, a PMOS current mirror is required to force same current to flow in the nMOS
transistors M 1 and M 2 and is shown in Figure 5.

Figure 5: Schematic of ß-multiplier circuit.

The saturation current of a MOS is given by

ß
ID = (VGS − Vth )2 (5)
2

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From this, the gate-source voltage VGS can be represented as

r
2ID
VGS = + Vth (6)
ß
Substituting equation 6 in equation 4, the reference current can be written as
 2  
2 1 2 1
Iref = 2 1− √ or VGSeff = 1− √ (7)
R · KPn · WL1
1
K R · KPn · W
L1
1
K

If the value of K is chosen to be 4, then the transconductance is expressed as

r
W 1
gm = 2KPn · · Iref = (8)
L R
and is often termed as constant-gm biasing circuit and is independent of MOSFET process
variations.
As can be seen in equation 7, the reference current Iref has no term which is dependent on
supply and thus making the ß-multiplier circuit supply independent (VDD invariant). The-
oretically, sensitivity of reference current on supply should be zero SenIVref
DD
= VIDD ∆Iref
ref ∆VDD
=0
as per equation 7. But, if channel length modulation is taken into consideration, a non
zero value for sensitivity SenIVref
DD
= 0.22 is obtained as shown in the graph 6, orders of
magnitude smaller than the sensitivity of previously discussed biasing circuit.

L=4*350nm
KPn=180u
W=3.889u

Figure 6: Output current vaiation w.r.t supply variations of a ß-multiplier.

The reference current Iref has certain temperature behaviour and can be obtained by
taking the derivative of the equation 7.
 2  2
∂Iref −4 1 ∂R 2 1 ∂KPn
= 3 W1
1− √ · − 2 W1
1− √ · (9)
∂T R · KPn · L1 K ∂T R · KPn · L1 K ∂T

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Dividing both sides by Iref , we get the temperature coefficient of it.

 
1 ∂Iref 1 ∂R 1 ∂KPn
T CIref = · = −2 − (10)
∂Iref ∂T ∂R ∂T ∂KPn ∂T

At this point KPn = µCox and the 2nd part in the RHS of equation 10 becomes
1 ∂KPn 1 ∂µ
= (11)
∂KPn ∂T ∂µ ∂T

The mobility term can be further represented as µ = µ0 T −1.5 and it’s temperature depen-
dency is
1 ∂µ −1.5
= (12)
∂µ ∂T T
.
Assuming that the resistor R in equation 10 has negligible temperature dependency, it
can be smplified to
 
1 ∂Iref 1 ∂R 1.5 1.5
T CIref = · = −2 + ≈ (13)
∂Iref ∂T ∂R ∂T T T

At 300 ◦ k, equation 13 is equal to T CIref = 5000 ppm/◦ C and is represented in the graph
Figure 7 when simulated on LTSpice.

Figure 7: Iref and T CIref vaiation w.r.t temperature of a ß-multiplier.

Task 2.2.2 ß-Multiplier design in LTSpice

Now that some basic understanding on biasing circuits is gained, design a ß-multiplier
circuit that satisfies the following specifications
• Supply voltage range: VDD = 3.0 to 3.6 V

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• Temperature range: −45◦ C to 85◦ C

• Reference current: Iref = 10 ± 1% µA
∆Iref
• Supply dependency: ∆VDD
= 800 nS
∆Iref
• Temperature dependency: ∆T
= 40 nA/◦ C
Hints
• Use VGSeff = 200 mV for both nMOS and pMOS transistors
• ”.op” spice directive is used to find the operating regions of the transistors
• Sweep the supply VDD to determine the supply dependency of Iref
• To find the temperature dependency, use the spice directives ”.step temp −45 85 5”
and ”.op”

Task 2.2.3 Startup circuitry of a ß-multiplier

The ß-multiplier circuit discussed in previous section has two operating points and is
presented in Figure 8. OP1 occurs when the system is in the off state when the gates of
nMOS (M1, M2) and pMOS (M3, M4) transistors are at 0 V and VDD respectively, and
when the supply VDD is turned on the ß-multiplier is in it’s normal operating state OP2.
Unfortunately, at power up, the ß-multiplier does not go to OP2 but rather is stuck at
OP1. This is due to the reason that the nMOS and pMOS transistors are still at 0 V
and VDD respectively. In order to ß-multiplier to OP2 state, the gates of M3, M4 has to
be discharged and the M1, M2 have to be charged to a certain potential. This is done by
the Start-up circuitry and is shown in Figure 9 and a sample startup graph is presented
in Figure 10.

Figure 8: Operating points of a ß-multiplier.

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Figure 9: Schematic of ß-multiplier circuit with start-up circuitry.

Figure 10: Startup response of a ß-multiplier

There are a few design consideration that have to be taken care of

• Once ß-multiplier is at OP2, the start-up circuitry should not affect it’s normal
operating condition
• The start-up circuit should consume as low power as possible, as this power is wasted

Task 2.2.4 Start-up circuitry for a ß-Multiplier design in LTSpice

A startup circuit has to be addded to the previous designed ß-multiplier circuit in LTSpice.
The design should fulfill the following criterian.

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• Once ß-multiplier is at OP2, the start-up circuitry should not affect it’s normal
operating condition
• The start-up circuit should consume no more than 1 µA of current
• The start-up time should be less than 1 µs
• Total power consumption of the ß-multiplier should be no more than 100 µW
Hints
• Set the gates M1,2,3,4 to their initial condition using the spice directive ”.ic V (V biasp) =
3.3 V (V biasn) = 0”
• Use transient analysis to find out the start-up current/power and time

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