LTC2992

Dual Wide Range

Power Monitor

FEATURES DESCRIPTION
n Rail-to-Rail Input Range: 0V to 100V The LTC®2992 is a rail-to-rail system monitor that mea-
n Wide Input Supply Range: 2.7V to 100V sures current, voltage, and power of two supplies. It
n Measures Current, Voltage, and Power features an operating range of 2.7V to 100V and includes
n Shunt Regulator for Supplies >100V a shunt regulator for supplies above 100V. The voltage
n 8-/12-Bit ADCs with Less Than ±0.3% Total Unad- measurement range of 0V to 100V is independent of the
justed Error input supply. Two ADCs simultaneously measure each
n Four General Purpose Inputs/Outputs Configurable supply’s current. A third ADC monitors the input voltages
as ADC Inputs and four auxiliary external voltages. Each supply’s current
n Continuous Scan and Snapshot Modes and power is added for total system consumption. Mini-
n Stores Minimum and Maximum Measurements mum and maximum values are stored and an overrange
n Alerts When Alarm Thresholds Exceeded alert with programmable thresholds minimizes the need
n Shutdown Mode with IQ < 50μA for software polling. Data is reported via a standard I2C
n Split SDA Pin Eases Opto-Isolation interface. Shutdown mode reduces current consumption
n Available in 16-Lead 4mm × 3mm DFN and MSOP to 25μA typically.
Packages
The LTC2992 I2C interface includes separate data input
and output pins for use with standard or opto-isolated I2C
APPLICATIONS connections. The LTC2992-1 has an inverted data output
n Telecom Infrastructure for use with inverting opto-isolator configurations.
n Industrial Equipment All registered trademarks and trademarks are the property of their respective owners.
n Automotive
n Computer Systems and Servers

TYPICAL APPLICATION
Dual Wide Range Power Monitor
ADC Error (GPIO)
VIN2 0.01Ω 0.50
VOUT2 12-BIT MODE
0V TO 100V

VIN1 0.01Ω
VOUT1 0.25
3V TO 100V
MAX ERROR
ADC ERROR (%)

SENSE1+ SENSE1– SENSE2+ SENSE2–

0
MEASURED TYPICAL
VDD GPIO1
VOLTAGE 1
SDAI MEASURED
LTC2992 GPIO2
I2C VOLTAGE 2 –0.25
SDAO
INTERFACE DATAREADY
GPIO3
SCL
GPIO4 ALERT
INTVCC GND ADR0 ADR1 –0.50
2992 TA01a 0 1024 2048 3072 4096
CODE
2992 TA01b

0.1μF

Rev A

Document Feedback For more information [Link] 1

LTC2992
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltages Average Pin Currents
VDD ...................................................... –0.3V to 100V INTVCC .............................................. –10mA to 35mA
INTVCC (Note 3) ..... –0.3V to Lesser of 5.8V, VDD + 0.3V SCL, SDAI ............................................................5mA
Analog Input Voltages SDAO, SDAO, GPIO1-4 .......................................20mA
SENSEn+, SENSEn– .................................–1V to 100V Operating Junction Temperature Range
SENSEn+ to SENSEn– ..................................–1V to 1V LTC2992C ................................................ 0°C to 70°C
ADR0, ADR1 ............................................ –0.3V to 7V LTC2992I .............................................–40°C to 85°C
GPIO1-4 ................................................... –0.3V to 7V LTC2992H .......................................... –40°C to 125°C
Digital Input/Output Voltages Storage Temperature Range .................. –65°C to 150°C
SCL, SDAI (Note 4) ............................... –0.3V to 5.9V Lead Temperature (Soldering, 10sec)
SDAO, SDAO, GPIO1-4 ............................. –0.3V to 7V MS Package Only .............................................. 300°C

PIN CONFIGURATION
LTC2992 LTC2992

TOP VIEW
SENSE1– 1 16 SENSE2–
TOP VIEW
SENSE1+ 2 15 SENSE2+
SENSE1– 1 16 SENSE2–
GPIO1 3 14 GPIO2 SENSE1+ 2 15 SENSE2+
GPIO3 4 13 GPIO4 GPIO1 3 14 GPIO2
17 GPIO3 4 13 GPIO4
ADR1 5 12 GND ADR1 5 12 GND
ADR0 6 11 SDAO ADR0 6 11 SDAO
INTVCC 7 10 SDAI
INTVCC 7 10 SDAI VDD 8 9 SCL
VDD 8 9 SCL
MS PACKAGE
DE PACKAGE 16-LEAD PLASTIC MSOP
16-LEAD (4mm × 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 120°C/W, θJC = 21°C/W
TJMAX = 150°C, θJA = 43°C/W, θJC = 5.5°C/W
EXPOSED PAD (PIN 17) PCB GND CONNECTION IS OPTIONAL

LTC2992-1 LTC2992-1

TOP VIEW
–
SENSE1 1 16 SENSE2– TOP VIEW
SENSE1+ 2 15 SENSE2+ SENSE2–
SENSE1– 1 16
GPIO1 3 14 GPIO2 SENSE1+ 2 15 SENSE2+
GPIO3 4 13 GPIO4 GPIO1 3 14 GPIO2
17 GPIO3 4 13 GPIO4
ADR1 5 12 GND ADR1 5 12 GND
ADR0 6 11 SDAO ADR0 6 11 SDAO
INTVCC 7 10 SDAI
INTVCC 7 10 SDAI VDD 8 9 SCL
VDD 8 9 SCL
MS PACKAGE
16-LEAD PLASTIC MSOP
DE PACKAGE
16-LEAD (4mm × 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 120°C/W, θJC = 21°C/W
TJMAX = 150°C, θJA = 43°C/W, θJC = 5.5°C/W
EXPOSED PAD (PIN 17) PCB GND CONNECTION IS OPTIONAL

Rev A

2 For more information [Link]

 LTC2992
ORDER INFORMATION [Link]

TUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2992CDE#PBF LTC2992CDE#TRPBF 2992 16-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C
LTC2992IDE#PBF LTC2992IDE#TRPBF 2992 16-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C
LTC2992HDE#PBF LTC2992HDE#TRPBF 2992 16-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LTC2992CDE-1#PBF LTC2992CDE-1#TRPBF 29921 16-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C
LTC2992IDE-1#PBF LTC2992IDE-1#TRPBF 29921 16-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C
LTC2992HDE-1#PBF LTC2992HDE-1#TRPBF 29921 16-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LTC2992CMS#PBF LTC2992CMS#TRPBF 2992 16-Lead Plastic MSOP 0°C to 70°C
LTC2992IMS#PBF LTC2992IMS#TRPBF 2992 16-Lead Plastic MSOP –40°C to 85°C
LTC2992HMS#PBF LTC2992HMS#TRPBF 2992 16-Lead Plastic MSOP –40°C to 125°C
LTC2992CMS-1#PBF LTC2992CMS-1#TRPBF 29921 16-Lead Plastic MSOP 0°C to 70°C
LTC2992IMS-1#PBF LTC2992IMS-1#TRPBF 29921 16-Lead Plastic MSOP –40°C to 85°C
LTC2992HMS-1#PBF LTC2992HMS-1#TRPBF 29921 16-Lead Plastic MSOP –40°C to 125°C
Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: [Link]
For more information on tape and reel specifications, go to: [Link] Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VDD is from 3V to 100V unless otherwise noted. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supplies
VDD VDD Input Supply Voltage l 3 100 V
VCC INTVCC Input Supply Voltage l 2.7 5.8 V
IDD VDD Supply Current VDD = 48V, INTVCC Open l 1.2 1.6 mA
Shutdown l 25 50 µA
ICC INTVCC Supply Current INTVCC = VDD = 5V l 1.0 1.4 mA
Shutdown l 25 50 µA
VCC(LDO) INTVCC Linear Regulator Voltage 8V < VDD < 100V l 4.6 5 5.4 V
ILOAD = 0mA
∆VCC(LDO) INTVCC Linear Regulator Load Regulation 8V < VDD < 100V l 100 250 mV
ILOAD = 0mA to 10mA
VCCZ Shunt Regulator Voltage at INTVCC VDD = 48V, ICC = 1.5mA l 5.8 6.2 6.7 V
∆VCCZ Shunt Regulator Load Regulation VDD = 48V, ICC = 1.5mA to 35mA l 250 mV
VCC(UVL) INTVCC Supply Undervoltage Lockout INTVCC Rising, VDD = INTVCC l 2.2 2.5 2.69 V
VDD(UVL) VDD Supply Undervoltage Lockout VDD Rising, INTVCC Open l 2.4 2.7 3 V
VCCI2C(RST) INTVCC I2C Logic Reset INTVCC Falling, VDD = INTVCC l 1.7 2.1 V
VDDI2C(RST) VDD I2C Logic Reset VDD Falling, INTVCC Open l 1.7 2.1 V
SENSE Inputs
ISENSE+(HI) 48V SENSE+ Input Current SENSE+, SENSE−, VDD = 48V l 120 170 µA
Shutdown l 2 µA
ISENSE−(HI) 48V SENSE− Input Current SENSE+, SENSE−, VDD = 48V l 20 µA
Shutdown l 1 µA

Rev A

For more information [Link] 3

LTC2992
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VDD is from 3V to 100V unless otherwise noted. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ISENSE+(LO) 0V SENSE+ Source Current SENSE+, SENSE− = 0V, VDD = 48V l –10 µA
Shutdown l –1 µA
ISENSE−(LO) 0V SENSE− Source Current SENSE+, SENSE− = 0V, VDD = 48V l –5 µA
Shutdown l –1 µA
ADC
RES Resolution (No Missing Codes) NADC[7] = 1 l 8 Bits
(Note 5) NADC[7] = 0 l 12 Bits
VFS Full-Scale Voltage ∆SENSE (Note 6) l 50.9 51.2 51.5 mV
SENSE+ l 102 102.4 102.8 V
GPIO l 2.042 2.048 2.054 V
LSB LSB Step Size ∆SENSE 200 µV
8-Bit Mode SENSE+ 400 mV
GPIO 8 mV
LSB Step Size ∆SENSE 12.5 µV
12-Bit Mode SENSE+ 25 mV
GPIO 0.5 mV
TUE Total Unadjusted Error (Note 7) ∆SENSE l ±0.8 %
8-Bit Mode SENSE+ l ±0.8 %
GPIO l ±0.8 %
Total Unadjusted Error ∆SENSE l ±0.6 %
12-Bit Mode SENSE+ l ±0.4 %
GPIO l ±0.3 %
VOS Offset Error ∆SENSE, SENSE+, GPIO l ±1 LSB
8-Bit Mode
Offset Error ∆SENSE (C-, I-Grade) l ±2.1 LSB
12-Bit Mode ∆SENSE (H-Grade) l ±3.1 LSB
SENSE+ l ±1.5 LSB
GPIO l ±1.1 LSB
INL Integral Nonlinearity ∆SENSE, SENSE+, GPIO l ±1 LSB
8-Bit Mode
Integral Nonlinearity ∆SENSE l ±3.5 LSB
12-Bit Mode SENSE+, GPIO l ±2 LSB
σT Transition Noise ∆SENSE 0.5 µVRMS
SENSE+ 0.3 mVRMS
GPIO 5 µVRMS
tCONV Conversion Time (Snapshot Mode) ∆SENSE l 3.9 4.1 4.3 ms
8-Bit Mode SENSE+, GPIO l 0.97 1.02 1.08 ms
Conversion Time (Snapshot Mode) ∆SENSE l 62.4 65.6 68.8 ms
12-Bit Mode SENSE+, GPIO l 15.6 16.4 17.2 ms
GPIO
VGPIO(TH) GPIO Pin Input Threshold VGPIO Rising l 1.13 1.23 1.33 V
VGPIO(OL) GPIO Pin Output Low Voltage IGPIO = 8mA l 0.15 0.4 V
IGPIO GPIO Pin Input Current VDD = 48V, GPIO = 3V l 0 ±1 μA
I2C Interface (VDD = 48V)
VADR(H) ADR0, ADR1 Input High Threshold l 1.8 2.4 2.7 V
VADR(L) ADR0, ADR1 Input Low Threshold l 0.3 0.6 0.9 V
IADR(IN) ADR0, ADR1 Input Current ADR0, ADR1 = 0V, 3V l ±13 μA
IADR(IN,Z) Allowable Leakage When Open l ±7 μA

Rev A

4 For more information [Link]

 LTC2992
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VDD is from 3V to 100V unless otherwise noted. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOD(OL) SDAO, SDAO, Output Low Voltage ISDAO, ISDAO = 8mA l 0.15 0.4 V
ISDA,SCL(IN) SDAI, SDAO, SDAO, SCL Leakage Current SDAI, SDAO, SDAO, SCL = 5V l 0 ±1 μA
VSDA,SCL(TH) SDAI, SCL Input Threshold l 1.5 1.8 2.1 V
VSDA,SCL(CL) SDAI, SCL Clamp Voltage ISDAI, ISCL = 0.5mA, 5mA l 5.9 6.9 V
I2C Interface Timing
fSCL(MAX) Maximum SCL Clock Frequency l 400 kHz
tLOW SCL Low Period l 0.65 1.3 μs
tHIGH SCL High Period l 50 600 ns
tBUF(MIN) Bus Free Time Between STOP/START l 0.12 1.3 μs
Condition
tHD, STA(MIN) Hold Time after (Repeated) START Condition l 140 600 ns
tSU, STA(MIN) Repeated START Condition Setup Time l 30 600 ns
tSU, STO(MIN) STOP Condition Setup Time l 30 600 ns
tHD, DATI(MIN) Data Hold Time Input l −100 0 ns
tHD, DATO(MIN) Data Hold Time Output l 300 600 900 ns
tSU, DAT(MIN) Data Setup Time l 30 100 ns
tSP(MAX) Maximum Suppressed Spike Pulse Width l 50 110 250 ns
tRST Stuck Bus Reset Time SCL or SDAI Held Low l 25 33 ms
CX SCL, SDAI Input Capacitance (Note 5) 5 10 pF

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 4: Internal clamps limit the SCL and SDAI pins to a minimum of
may cause permanent damage to the device. Exposure to any Absolute 5.9V. Driving these pins to voltages beyond the clamp may damage the
Maximum Rating condition for extended periods may affect device part. The pins can be safely tied to higher voltages through resistors that
reliability and lifetime. limit the current below 5mA.
Note 2: All currents into pins are positive. All voltages are referenced to Note 5: Guaranteed by design and not subjected to test.
ground, unless otherwise noted. Note 6: ∆SENSE is defined as VSENSE+ – VSENSE–
Note 3: An internal shunt regulator limits the INTVCC pin to a minimum of Note 7: TUE is the maximum ADC error for any code expressed as a
5.8V. Driving this pin to voltages beyond 5.8V may damage the part. This percentage of full-scale.
pin can be safely tied to higher voltages through a resistor that limits the
current below 35mA.

Rev A

For more information [Link] 5

 LTC2992
TYPICAL PERFORMANCE CHARACTERISTICS

VDD Supply Current INTVCC Supply Current INTVCC Load Regulation

SUPPLY CURRENT (mA)

SHUTDOWN CURRENT (µA) SUPPLY CURRENT (mA)

1.4 1.4 5.2

1.2 1.2
NORMAL NORMAL
5.1
1.0 1.0

INTVCC VOLTAGE (V)

0.8 0.8
5.0
SHUTDOWN CURRENT (µA)

30 45

26 35
4.9
SHUTDOWN SHUTDOWN
22 25

18 15 4.8
0 20 40 60 80 100 2 3 4 5 6 0 2 4 6 8 10
VDD SUPPLY VOLTAGE (V) INTVCC SUPPLY VOLTAGE (V) LOAD CURRENT (mA)
2992 G01 2992 G02 2992 G03

INTVCC Shunt Regulator

INTVCC Line Regulation Load Regulation SENSE Input Current
5.5 6.30 250

5.0 200
INTVCC OUTPUT VOLTAGE (V)

6.25
SENSE+

SENSE CURRENT (µA)

INTVCC VOLTAGE (V)

4.5 150

4.0 6.20 100

3.5 50
6.15
SENSE–
3.0 0

2.5 6.10 –50

0 20 40 60 80 100 0 10 20 30 40 0 20 40 60 80 100
VDD SUPPLY VOLTAGE (V) INTVCC SHUNT CURRENT (mA) SENSE VOLTAGE (V)
2992 G04 2992 G05 2992 G06

ADR Voltage with Current SCL/SDAI Loaded Clamp Voltage GPIO, SDAO, SDAO Loaded Output
Source or Sink vs Load Current Low Voltage vs Load Current
3.0 6.40 0.4

2.5 6.30
0.3
2.0 6.20
VSDA,SCL(CL) (V)

VOD(OL) (V)
VADR (V)

1.5 6.10 0.2

1.0 6.00
0.1
0.5 5.90

0 5.80 0
–10 –5 0 5 10 0.01 0.1 1 10 0 2 4 6 8 10
IADR (µA) ILOAD (mA) IOD (mA)
2992 G07 2992 G08 2992 G09

Rev A

6 For more information [Link]

 LTC2992
TYPICAL PERFORMANCE CHARACTERISTICS
ADC Differential Nonlinearity
ADC Error (GPIO) ADC Integral Nonlinearity (GPIO) (GPIO)
0.50 0.3 0.3
12–BIT MODE 12–BIT MODE 12–BIT MODE

0.2 0.2
0.25
MAX ERROR 0.1 0.1
ADC ERROR (%)

ADC DNL (LSB)

ADC INL (LSB)
0 0.0 0.0
TYPICAL

–0.1 –0.1
–0.25
–0.2 –0.2

–0.50 –0.3 –0.3

0 1024 2048 3072 4096 0 1024 2048 3072 4096 0 1024 2048 3072 4096
CODE CODE CODE
2992 G10 2992 G11 2992 G12

ADC Integral Nonlinearity ADC Differential Nonlinearity

ADC Error (∆SENSE) (∆SENSE) (∆SENSE)
0.75 2.0 1.0
12–BIT MODE 12–BIT MODE 12–BIT MODE
0.50

MAX ERROR 1.0 0.5

0.25
ADC ERROR (%)

ADC DNL (LSB)

ADC INL (LSB)

TYPICAL
0 0 0

–0.25
–1.0 –0.5
–0.50

–0.75 –2.0 –1.0

0 1024 2048 3072 4096 0 1024 2048 3072 4096 0 1024 2048 3072 4096
CODE CODE CODE
2992 G13 2992 G14 2992 G15

ADC Input Signal Attenuation ADC Input Signal Attenuation ADC Input Signal Attenuation
(GPIO) (GPIO, Low Frequencies) (∆SENSE)
0 0 0

–20 –20
–20
REJECTION (dB)

REJECTION (dB)

REJECTION (dB)

–40 –40
–40
–60 –60

–60
–80 –80

–100 –80 –100

0 62.5 125 187.5 250 0 60 120 180 240 0 62.5 125 187.5 250
FREQUENCY (kHz) FREQUENCY (Hz) FREQUENCY (kHz)
2992 G16 2992 G17 2992 G18

Rev A

For more information [Link] 7

LTC2992
TYPICAL PERFORMANCE CHARACTERISTICS
ADC Input Signal Attenuation Current Sense Amplifier Offset Current Sense Amplifier Offset
(∆SENSE, Low Frequencies) Drift Over Temperature Drift Over Input Common Mode
0 25 10
INITIAL CALIBRATION DONE AT 25°C INITIAL CALIBRATION DONE AT VCM = 48V
NO CALIBRATION THEREAFTER NO CALIBRATION THEREAFTER
8 12–BIT MODE
15 12–BIT MODE
–20 CALIBRATION
OFF

OFFSET DRIFT (LSB)

OFFSET DRIFT (LSB)

6
REJECTION (dB)

5 CALIBRATION CALIBRATION
ON OFF
–40 4
–5
2
CALIBRATION
–60 ON
–15
0

–80 –25 –2
0 60 120 180 240 –50 –25 0 25 50 75 100 125 0 25 50 75 100
FREQUENCY (Hz) TEMPERATURE (°C) COMMON MODE VOLTAGE (V)
2992 G19 2992 G20 2992 G21

PIN FUNCTIONS
ADR1, ADR0: I2C Device Address Inputs. Connecting these GPIO4: General Purpose Input/Output (Open Drain).
pins to INTVCC, GND or leaving the pins open configures Configurable to general purpose output, logic input, data
one of nine possible addresses. See Table 3 in Applications converter input or SMBus alert (ALERT). As ALERT, it is
Information section for details. pulled to ground when a fault occurs to alert the host con-
EXPOSED PAD: Exposed Pad may be left open or connected troller. A fault alert is enabled by setting the corresponding
to device ground. For best thermal performance, connect bit in the ALERT registers as shown in Tables 7, 11, 13
to a copper plane with an array of vias. and 15. Tie to ground if unused. See Tables 18 and 19 in
Applications Information section for details.
GND: Device Ground.
INTVCC: Internal Low Voltage Supply Input/Output. This
GPIO1, GPIO2: General Purpose Input/Output (Open pin is used to power internal circuitry. It can be configured
Drain). Configurable to general purpose output, logic in- as a direct input for a low voltage supply, as linear regula-
put, or data converter input. Tie to ground if unused. See tor from a higher voltage supply connected to VDD, or as
Table 18 in Applications Information section for details. a shunt regulator. Connect this pin directly to a 2.7V to
GPIO3: General Purpose Input/Output (Open Drain). 5.8V supply if available. When INTVCC is powered from an
Configurable to general purpose output, logic input, data external supply, connect the VDD pin to INTVCC. If VDD is
converter input or data ready signal (DATAREADY). As connected to a 8V to 100V supply, INTVCC becomes the
DATAREADY, it is latched low or pulses low for 16µs or 5V output of an internal series regulator that can supply
128µs when any of the ADC’s data becomes available. Tie up to 10mA to external circuitry. For even higher supply
to ground if unused. See Table 18 in Applications Informa- voltages or if a floating topology is desired, INTVCC can
tion section for details. be used as a 6.2V shunt regulator. Connect the supply to

Rev A

8 For more information [Link]

 LTC2992
PIN FUNCTIONS
INTVCC through a resistor or current source that limits the SDAO (LTC2992-1 only): Inverted I2C Bus Data Output.
current to less than 35mA. An undervoltage lockout circuit Open-drain output used for sending data back to the
disables the ADC when the voltage at this pin drops below master controller or acknowledging a write operation.
2.5V. Connect a bypass capacitor of 0.1µF or greater from Data is inverted for convenience of opto-isolation. An
this pin to ground. If an external load is present, for loop external pull-up resistor or current source is required. The
stability, use a bypass capacitor of 1µF or greater. See LTC2992-1 cannot be used in nonisolated I2C applications
Flexible Power Supply section. without additional components.
SCL: I2C Bus Clock Input. Data at the SDAI pin is shifted SENSE1+, SENSE2+: Supply Voltage and Current Sense
in or out on rising edges of SCL. This pin is driven by an Input. Used as a voltage supply and current sense input
open-collector output from a master controller. An external for internal current sense amplifier. The voltage at this pin
pull-up resistor or current source is required and can be is monitored by the onboard ADC with a full-scale input
placed between SCL and VDD or INTVCC. The voltage at range of 102.4V. See Figure 19 for recommended Kelvin
SCL is internally clamped to 6.3V typically. connection.
SDAI: I2C Bus Data Input. Used for shifting in address, SENSE1–, SENSE2–: Current Sense Input. Connect an
command or data bits. This pin is driven by an open- external sense resistor between SENSE+ and SENSE–.
collector output from a master controller. An external The differential voltage between SENSE+ and SENSE– is
pull-up resistor or current source is required and can be monitored by the onboard ADC with a full-scale sense
placed between SDAI and VDD or INTVCC. The voltage at voltage of 51.2mV. Tie both SENSE– and SENSE+ together
SDAI is internally clamped to 6.3V typically. Tie to SDAO to a voltage between 0V and 100V if current measurement
for normal I2C operation. is unused.
SDAO (LTC2992 only): I2C Bus Data Output. Open-drain VDD: High Voltage Supply Input. This pin powers an internal
output used for sending data back to the master controller series regulator with input voltages ranging from 3V to
or acknowledging a write operation. An external pull-up 100V and produces 5V at INTVCC when VDD is above 8V.
resistor or current source is required. Tie to SDAI for Connect a bypass capacitor of 0.1µF or greater from this
normal I2C operation. pin to ground if external load is present on the INTVCC pin.
See Flexible Power Supply section.

Rev A

For more information [Link] 9

LTC2992
FUNCTIONAL DIAGRAM
10 9 6 5 11
SDAI SCL ADR0 ADR1 SDAO (LTC2992)
SDAO (LTC2992-1)
6.3V 6.3V DECODER
SENSE1–
1 –
40X VREF
+ 2.048V
I2C
SENSE1+
2 12 I1
IADC1
P1
SENSE2–
16 – – 1.23V
40X
+ + GPIO1
3
12 I2
IADC2
SENSE2+ P2 GPIO2
15 14

VDD 735k 735k GPIO3

8 S1 4
S2
GPIO4
INTVCC 5V 12 G1 13
7 VADC
LDO G2
G3
6.2V 15k 15k
G4 4

I1 + I2
P1 + P2

GND
12
2992 FD

TIMING DIAGRAM

SDA

tSU, DAT tSU, STA tSP

tHD, DATO, tBUF
tHD, DATI tHD, STA tSU, STO
tSP
2992 TD
SCL

tHD, STA

REPEATED START REPEATED START STOP START

CONDITION CONDITION CONDITION CONDITION

Rev A

10 For more information [Link]

 LTC2992
OPERATION
The LTC2992 accurately monitors current, voltage and The GPIO1 to GPIO4 pins are also general purpose inputs
power of two 0V to 100V supplies. An internal linear or general purpose open-drain outputs. In addition, GPIO3
regulator allows the LTC2992 to operate directly from a 3V may be configured as DATAREADY output while GPIO4
to 100V rail, or from an external supply voltage between is also an SMBus alert (ALERT) output. DATAREADY in-
2.7V and 5.8V. Quiescent current is less than 1.6mA in dicates availability of the most recent conversion results
normal operation. Enabling shutdown mode via the I2C from any of the ADCs while ALERT indicates one or more
interface reduces the quiescent current to below 50µA. faults have occurred.
There are three onboard 8-/12-bit ADCs as shown in the Onboard memory stores the minimum and maximum
Functional Diagram. Each supply’s load current is mea- values for each ADC measurement and calculates power
sured with an external current sense resistor connected data by digitally multiplying the stored current and voltage
between SENSE+ and SENSE–. Internal amplifiers gain up data. When the ADC measured value falls outside its pro-
the voltage drop across the sense resistor for monitoring grammed window thresholds, a fault event is logged and
by the IADCs (full-scale 51.2mV). VADC is used for voltage the ALERT (GPIO4) may optionally pull low. The LTC2992
measurements and its input is selectively connected to also calculates the total current and power consumption
SENSE1+, SENSE2+ (full-scale 102.4V) or any of the four of the two monitored supplies.
GPIO pins (full-scale 2.048V). Each conversion takes 33ms
The LTC2992 includes an I2C interface to access the
for the IADCs and 16ms for the VADC in 12-bit mode. The onboard data registers and to program the alert thresh-
conversion time can be shortened by a factor of 16 when old, configuration and control registers. Two three-state
8-bit mode is selected. pins, ADR1 and ADR0, are decoded to allow nine device
The ADCs can be configured to run continuously (continu- addresses (see Table 3). The SDA pin is split into SDAI
ous scan) or on demand (snapshot mode). In continuous (input) and SDAO (output, LTC2992) or SDAO (output,
scan mode, the VADC measures selected voltages of the LTC2992-1) to facilitate opto-isolation. Tie SDAI and SDAO
six inputs in round robin fashion. See the Applications together for normal, nonisolated I2C operation.
Information section for more details. Status bits in the
ADC STATUS register signal new conversion results from
the ADCs have been written into onboard registers.

Rev A

For more information [Link] 11

LTC2992
APPLICATIONS INFORMATION
The LTC2992 offers a compact and complete solution to ers connected to the GPIO1 and GPIO2 pins. See Flexible
monitor power from two supply rails in high side and/or Power Supply section for details.
low side current sensing applications. With an input com- The operation and conversion sequence of the ADCs, mul-
mon mode range of 0V to 100V and a wide input supply tiplier operand and VADC input selections are controlled
operating voltage range from 2.7V to 100V, this device is by the settings in the CTRLA register as shown in Table 1.
ideal for a wide variety of power management applications
including automotive, industrial and telecom infrastructure. The timing sequence for some of these configurations are
The basic application circuit shown in Figure 1 provides shown in Figure 2 (2a to 2f). The timing diagram shown
monitoring of high side currents (5.12A/10.24A full-scale), in Figure 2a illustrates the conversion sequence in the
input voltages (102.4V full-scale) and two external volt- default configuration (CTRLA[7:0]=0x00). Upon power-up
ages (2.048V full-scale), all using internal 12-bit ADCs. (t1), the IADCs will always measure their corresponding
current sense amplifier’s offset (calibration) and then the
Data Converters load current (∆SENSE1/2). Meanwhile, VADC begins mea-
surement of SENSE1+, SENSE2+, GPIO1, GPIO2, GPIO3
The LTC2992 features three ∆∑ A/D converters (ADC) and GPIO4 successively.
that can be configured to 8- or 12-bit. The ∆∑ architec-
ture inherently averages input signals and noise during At t3 a new IADC conversion begins. To generate power,
the measurement period. Two ADCs (IADC1 and IADC2) the most recent voltage data (S1 at t2, S2 at t3) from VADC
monitor the differential voltages between SENSE+ and is stored in a latch as an operand to the adder as shown
SENSE– (∆SENSE) with 51.2mV full-scale to allow accurate in Figure 3. IMOD1 represents IADC1’s modulator which
measurement of load currents across low value shunt converts the load current into a 1-bit data stream. Each
resistors. The third ADC (VADC) monitors two SENSE+ 1 in the bitstream adds to the accumulators the voltage
and four GPIO pins with full-scale of 102.4V for SENSE+ data such that they contain the power values I1 × S1 and
and 2.048V for GPIO. I2 × S2 at the end of the IADC conversions at t5. Voltage
latch content is then updated to the corresponding data
The supply voltage data are derived from SENSE1+ and registers. I1 is added to I2 to generate total current and
SENSE2+ or GPIO1 and GPIO2 depending on the external P1 is added to P2 to generate total power. In the summing
application circuit. SENSE1+ and SENSE2+ are selected process, the least significant bit of the results are truncated.
by default as these are normally connected to the supply Consequently, the summing results need to be shifted one
voltages. In negative supply voltage systems, the supply bit to the left to restore the correct quantity. Note that the
voltages can be measured through external resistive divid-
3.3V
RSENSE1
0.01Ω
VIN1 VOUT1
3V TO 100V 5A
R1 R2 R3 R4
VDD SENSE1+ SENSE1– 2k 2k 2k 2k VDD

MEASURED SDAI SDA

VOLTAGE 1 GPIO1
SDAO
MEASURED LTC2992 µP
GPIO2 SCL SCL
VOLTAGE 2
ALERT
GPIO4 INT0
DATAREADY
GPIO3 INT1
INTVCC GND ADR0 ADR1 SENSE2+ SENSE2– GND
2992 F01

0.1μF
VIN2 VOUT2
0V TO 100V 10A
RSENSE2
0.005Ω

Figure 1. Dual High Side Power Monitor

Rev A

12 For more information [Link]

 LTC2992
APPLICATIONS INFORMATION
calculated LSB (see Design Example section) for current input. Therefore, input signals such as supply rail voltages
and power of both supplies have to match. Otherwise, with average value that varies at less than 5Hz can be ac-
external µP can be used to first compute physical amount curately monitored. Otherwise, the input update rate can
of current and power for each supply and then perform be increased by reducing the number of inputs monitored
the summing. via CTRLA[4:3]. Figure 2c shows only the SENSE+ pins
The LTC2992 measures the current sense amplifier’s being monitored in continuous scan mode with an effec-
input offset to calibrate subsequent IADC measurements. tive update rate of 30Hz. The remaining inputs may be
During offset measurement, IADC cannot capture load monitored by switching to snapshot mode when needed.
current information. By default, such calibration is done A snapshot mode is available to make on-demand mea-
for every IADC conversion as shown in Figure 2a. In most surement of a single selected voltage without power data
applications, the calibration frequency can be reduced by update (SENSE1+, SENSE2+, GPIO1, GPIO2, GPIO3 or
writing to CTRLA register with its CTRLA[7] bit set to 1. GPIO4) or two selected voltages (either SENSE1+ and
A one-off calibration is then performed immediately after SENSE2+, or GPIO1 and GPIO2). To make a snapshot mea-
the I2C write operation as shown in Figure 2b. surement, write the 3-bit code of the desired voltage input
VADC by default monitors six input voltages sequentially to CTRLA[2:0] and 01 to CTRLA[6:5]. After completion of
as shown in Figure 2a with an update rate of 10Hz for each the conversion, the ADCs will halt and the corresponding

Table 1. ADC Configuration Via CTRLA Register

BIT NAME OPERATION
CTRLA[7] Offset Calibration Offset Calibration for Current Measurements
[1] = Calibrate on Demand
[0] = Every Conversion (Default)
CTRLA[6:5] Measurement [11] = Shutdown
Mode [10] = Single Cycle mode
The VADC converts SENSE1+, SENSE2+, GPIO1, GPIO2, GPIO3, GPIO4 once and stops. The IADCs stop after
one conversion.
P1 = SENSE1+ × ∆SENSE1; P2 = SENSE2+ × ∆SENSE2
[01] = Snapshot Mode
Snapshot Initializes Conversion on All 3 ADCs Simultaneously.
VADC Converts the Channel(s) per CTRLA[2:0]
[00] = Continuous Scan Mode (Default)
The Selected Channels for VADC are Defined by CTRLA[4:3]
CTRLA[4:3] Voltage Selection CTRLA[4:3] VADC P1 P2
for Continuous 11 GPIO1, GPIO2, GPIO1 × ∆SENSE1 GPIO2 × ∆SENSE2
Scan Mode GPIO3, GPIO4
10 GPIO1, GPIO2 GPIO1 × ∆SENSE1 GPIO2 × ∆SENSE2
01 SENSE1+, SENSE2+ SENSE1+ × ∆SENSE1 SENSE2+ × ∆SENSE2
00 (Default) SENSE1+, SENSE2+, SENSE1+ × ∆SENSE1 SENSE2+ × ∆SENSE2
GPIO1, GPIO2,
GPIO3, GPIO4
CTRLA[2:0] Voltage Selection CTRLA[2:0] VADC P1 P2
for Snapshot 111 GPIO1, GPIO2 GPIO1 × ∆SENSE1 GPIO2 × ∆SENSE2
Mode
110 SENSE1+, SENSE2+ SENSE1+ × ∆SENSE1 SENSE2+ × ∆SENSE2
101 GPIO4 ∆SENSE1/2 without P1/P2 updates
100 GPIO3
011 GPIO2
010 GPIO1
001 SENSE2+
000 (Default) SENSE1+
Rev A

For more information [Link] 13

LTC2992
APPLICATIONS INFORMATION
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
POWER UP 16.4ms 16.4ms 16.4ms 16.4ms 16.4ms 16.4ms 16.4ms 16.4ms 16.4ms

VADC S1 S2 G1 G2 G3 G4 S1 S2 G1 G2

IADC1 CAL I1 AND P1 CAL I1 AND P1 CAL

IADC2 CAL I2 AND P2 CAL I2 AND P2 CAL

(2a) Continuous Scan Mode with Calibration Every Cycle (Default)

S1, S2, G1, G2, G3, G4: SENSE1+, SENSE2+, GPIO1, GPIO2, GPIO3, and GPIO4
CAL: Calibration of Current Sense Amplifier
I1, I2: ∆SENSE1, ∆SENSE2
P1, P2: POWER1, POWER2

WRITE 0x80 TO WRITE 0x80 TO

CTRLA REGISTER CTRLA REGISTER

VADC S1 S2 G1 G2 G3 G4 S1 S2 S1 S2 G1 G2

IADC1 CAL I1 AND P1 I1 AND P1 I1 AND P1 CAL I1 AND P1

IADC2 CAL I2 AND P2 I2 AND P2 I2 AND P2 CAL I2 AND P2

(2b) Continuous Scan Mode with On-Demand Calibration. CTRLA[7:0] = 0x80

WRITE 0x88 TO WRITE 0x20 TO

CTRLA REGISTER CTRLA REGISTER

VADC S1 S2 S1 S2 S1 S2 VADC S1 IDLE

IADC1 CAL I1 AND P1 I1 AND P1 IADC1 CAL I1 IDLE

IADC2 CAL I2 AND P2 I2 AND P2 IADC2 CAL I2 IDLE

(2c) Continuous Scan Mode with On-Demand (2d) Snapshot Mode for Single Voltage. CTRLA[7:0] = 0x20
Calibration. CTRLA[7:0] = 0x88

WRITE 0x27 TO WRITE 0x40 TO

CTRLA REGISTER CTRLA REGISTER
t1 t2 t3 t4 t5 t6 t7

VADC G1 G2 IDLE VADC S1 S2 G1 G2 G3 G4 IDLE

IADC1 CAL I1 AND P1 IDLE IADC1 CAL I1 AND P1 IDLE

IADC2 CAL I2 AND P2 IDLE IADC2 CAL I2 AND P2 IDLE

2992 F02

(2e) Snapshot Mode for Two Voltages. CTRLA[7:0] = 0x27 (2f) Single Cycle Mode. CTRLA[7:0] = 0x40

Figure 2
Rev A

14 For more information [Link]

 LTC2992
APPLICATIONS INFORMATION
junction temperature rises above 150°C, and the output
VADC
DATA VOLTAGE
LATCH
is protected against accidental shorts. Bypass capacitors
+ POWER1
of 0.1μF, or greater, at both the VDD and INTVCC pins are
ACCUMULATOR
recommended for optimal transient performance. Note that
LATCH operation with high VDD voltages can result in significant
IMOD1 power dissipation, and care is required to ensure that the
maximum operating junction temperature stays below
125°C. For improved thermal resistance, use the DFN
2992 F03

Figure 3. POWER1 Generator Blocks package and solder the exposed pad to a large copper
region on the PCB.
bits in ADC STATUS register (Table 10) are set to indicate
the availability of new data. An alert may be generated at Figure 4a shows the LTC2992 being used to monitor input
the end of a snapshot conversion by setting bit AL4[7:6] supplies that range from 4V to 100V. No separate supply is
in the ALERT4 register (Table 15). To make another snap- needed since VDD can be connected to either of the input
shot measurement, rewrite the CTRLA register. Figure 2d supplies. To prevent loss of operation from either supply’s
shows a snapshot operation of SENSE1+ with no updates failure, VDD is connected to VIN1 and VIN2 via diodes. If
to power data since only single voltage is selected while the LTC2992 is used to monitor input supplies of 0V to
Figure 2e shows combo snapshot operation of GPIO1 and 100V, it can derive power from a wide range separate sup-
GPIO2 with new power data. ply connected to the VDD pin as shown in Figure 4b. The
A single cycle mode allows all six voltages to be measured BAV23CLT1G
RSENSE1

once with a single I2C command. To initiate such mode,

0.01Ω
VIN1
VOUT1
4V TO 100V
write 10 to CTRLA[6:5] as shown in Figure 2f. SENSE1+,
SENSE2+ are updated together with current and power
values at t5. At t7 the conversions are done and the ADCs
SENSE1+ SENSE1–
are halted. VDD
INTVCC
If there is an extended period of I2C communication between C2 LTC2992

the LTC2992 and the controller, some of the ADC result GND
SENSE2+ SENSE2–
may be lost. This is because during the I2C communica-
tion, the ADCs are prevented from updating the internal VIN2
4V TO 100V
VOUT2
registers to avoid corrupting the data. This problem can RSENSE2
0.005Ω 2992 F04a

be overcome by breaking the I2C communication into

(4a) Derives Power from the Supplies Being Monitored
blocks of less than one conversion period (16.4ms for
12-bit mode and 1ms for 8-bit mode).
RSENSE1
0.01Ω
Flexible Power Supply VIN1
0V TO 100V
VOUT1

The LTC2992 can be externally configured to derive power SENSE1+ SENSE1–

from a wide range of supplies. The LTC2992 includes an 3V TO 100V VDD

onboard linear regulator to power the low voltage inter- INTVCC

LTC2992
nal circuitry connected to the INTVCC pin from high VDD C2
GND
SENSE2+ SENSE2–
voltages. The linear regulator operates with VDD voltages
from 3V to 100V, and a shunt regulator is available for VIN2
VOUT2
0V TO 100V
voltages above 100V. The linear regulator produces a 5V RSENSE2
0.005Ω
output capable of supplying 10mA at the INTVCC pin when
2992 F04b

VDD is greater than 8V. The regulator is disabled when the (4b) Derives Power from a Separate Wide Range Supply
Rev A

For more information [Link] 15

LTC2992
APPLICATIONS INFORMATION
RSENSE1 MBR10100
0.01Ω
VIN1 RTN1 RTN
VOUT1
0V TO 100V
MBR10100
SENSE1+ SENSE1– RTN2
2.7V TO 5.8V VDD
R8 R9
LTC2992 1M 1M
INTVCC VDD
GPIO1 INTVCC
GND + – C2
SENSE2 SENSE2
GPIO2 LTC2992 GND
VIN2 R10 R11
VOUT2
0V TO 100V 20k 20k
RSENSE2 SENSE1– SENSE1+ SENSE2– SENSE2+
0.005Ω 2992 F04c

(4c) Derives Power from a Separate Low Voltage Supply MBR10100

VIN2
SENSE+/– pins can be biased independently of the part’s –5V TO –100V RSENSE2
supply voltage. Alternatively, if a low voltage supply is VIN1
MBR10100 0.01Ω
VOUT
present it can be connected to the INTVCC pin, as shown –5V TO –100V
RSENSE1
5A

in Figure 4c, to minimize on-chip power dissipation. When

2992 F05b
0.01Ω

INTVCC is powered from a separate supply, connect VDD (5b) Derives Power from the Supply Monitored in a Low
to INTVCC. Side Current Sense Topology
RSENSE1
0.01Ω MBR10100 RSENSE2 TOP LAYER
VIN1
VOUT1
0V TO 100V
VIN2
RSHUNT SENSE1+ SENSE1–
> 100V INTVCC BOTTOM LAYER
VDD
LTC2992

16
15
14
13
12
11
10
9
C2
GND
SENSE2+ SENSE2–
VOUT

17
VIN2
VOUT2
0V TO 100V
RSENSE2
1
2
3
4
5
6
7
8
0.005Ω 2992 F05a

(5a) Derives Power Through a Low Side Shunt

Regulator in a High Side Current Sense Topology VIN1

Figure 5a shows a high side rail-to-rail power monitor which MBR10100 RSENSE1 2992 F05c

derives power from a separate supply greater than 100V. (5c) Recommended Layout for Figure 5b’s SENSE Pins
The voltage at INTVCC is clamped at 6.3V above ground in Connection
a low side shunt regulator configuration to power the part.
(VOUT) close to the SENSE+ terminal of the sense resistors
In dual feed, low side power monitor applications, the device
with a wide track to prevent excessive potential difference
ground and the current sense inputs are connected to the
between the SENSE+ pins when load current is supplied
diode-ORed output of the input supplies’ negative terminal
entirely by VIN1 or VIN2.
as shown in Figure 5b. Note that the SENSE– pins operate
at a voltage more negative than the device ground. It is Supply Undervoltage Lockout
highly recommended that the SENSE+ pins be operating
at as close to device ground potential as possible so that During power-up, the internal I2C logic and the ADCs
at full-scale the SENSE– pins are limited to 80mV below are enabled when either VDD or INTVCC rises above its
device ground for accurate measurements. A recom- under-voltage lockout threshold (2.7V for VDD and 2.5V
mended layout for Figure 5b’s SENSE pins connection for INTVCC typically). During power-down, the ADCs are
is shown in Figure 5c. Layout the common connection disabled when VDD and INTVCC fall below their respective
Rev A

16 For more information [Link]

 LTC2992
APPLICATIONS INFORMATION
undervoltage lockout thresholds. If VDD or INTVCC remains Configuring the GPIO Pins
above their typical 2.1V I2C reset threshold, the internal I2C
The LTC2992 has four GPIO pins configurable through
logic retains the state before power-down. If VDD or INTVCC
the GPIO IO CONTROL register (Table 18) to be used as
is then increased as in a normal power-up, the ADCs will
general purpose input/output pins. By configuring the
run according to CTRLA register’s setting at that point in
CTRLA register, the voltage at the four GPIO pins can
time. The internal I2C logic is reset when VDD and INTVCC
be measured by the VADC. GPIO1 through GPIO4 have
fall below their respective I2C reset thresholds.
comparators monitoring the voltage on these pins with a
Shutdown Mode threshold of 1.23V typically, the results of which may be
read from bits GS[3:0] in the GPIO STATUS register, as
The LTC2992 includes a low quiescent current shutdown shown in Table 17. An alert may be generated, when GPIO1,
mode, controlled by bits CTRLA[6:5] in the CTRLA register GPIO2 or GPIO3 cross the comparator threshold voltage
(Table 1). Setting CTRLA[6:5]=11 puts the part in shutdown (1.23V typical), by setting bits AL4[3:1], respectively, in
mode, powering down the ADC, internal reference and on- the ALERT4 register.
board linear regulator. The internal I2C bus remains active,
and although the ADR1 and ADR0 pins are disabled, the GPIO1, GPIO2, GPIO3 and GPIO4 can be pulled low as
device will retain the most recently programmed I2C bus general purpose outputs, which are otherwise high im-
pedance. GPIO3 can also be used as a data ready output
address. All onboard registers retain their contents and can
(DATAREADY) to indicate new data from any of the three
be accessed through the I2C interface. To re-enable ADC
conversions, reset bit CTRLA[6:5] in the CTRLA register. ADCs by configuring GIO[5:4] in the GPIO IO CONTROL
The analog circuitry will power up and all registers will register. The output can be in the form of a low pulse with
retain their contents. duration of 16µs or 128µs or a latched low state. The ADC
STATUS register (Table 10) indicates which of the moni-
The onboard linear regulator is disabled in shutdown mode tored voltages has been recently updated. This register is
to conserve power. If the onboard linear regulator is used cleared-on-read, which will also release the GPIO3 from
to power external I2C bus related circuitry such as opto- its latched low state.
couplers or pull-ups, I2C communication will be lost when
the part is shut down. The LTC2992 would then have to GPIO4 is by default an SMBus alert (ALERT) output that
be reset by cycling its power to come out of shutdown. If pulls low when an alert event is present. To pull GPIO4
low IQ mode is not required, ensure 11 cannot be written (ALERT) low in the absence of an alert event, set GC[7]
to CTRLA[6:5] in the CTRLA register during software de- of the GPIO4 CONTROL register (Table 19). Clearing this
velopment. It is recommended that external regulators be bit will release the GPIO4 (ALERT). GC[7] is set whenever
used in such applications if powering down the LTC2992 an alert event occurs. Setting GC[6] will similarly pull
is desirable. As an added layer of protection against this GPIO4 low.
scenario, bit CTRLB[4] in the CTRLB register can be set
I2C Reset
during system configuration to enable the LTC2992 to
automatically exit shutdown mode when the I2C lines To avoid the need of power-cycling the part for a reset,
are low for more than 33ms (which can be a result of LTC2992 features a software reset which is enabled by
accidental shutdown of the LTC2992’s linear regulator setting CTRLB[0] of CTRLB register (Table 6). This bit
powering the I2C). The user can elect to be alerted of this is self-cleared. All internal registers except the present
event by setting bit AL4[4] in the ALERT4 register (Table value data registers are reset to their default states. The
15). Quiescent current drops below 50μA in shutdown ADCs will sample continuously after reset without any
mode with the internal regulator disabled. reconfiguration since this is the default behavior.

Rev A

For more information [Link] 17

LTC2992
APPLICATIONS INFORMATION
Storing Minimum and Maximum Values if the VDD and INTVCC fall below their respective I2C logic
reset threshold.
The LTC2992 compares each measurement including the
calculated power with the stored values in the respective ADC Resolution and Conversion Rate
MIN and MAX registers for each parameter (Table 4). If
the new conversion is beyond the stored minimum or The resolution of the ADCs can be configured to 8-bit by
maximum values, the MIN or MAX registers are updated setting bit NADC[7] of NADC register (Table 9) through an
with the new values. The MIN and MAX registers are I2C write command to speed up ADC conversions.
refreshed only when ADCs update the internal registers. Table 2. ADC Resolution and Conversion Rate
Writing via I2C to the ADC registers does not affect the RESOLUTION 12-BIT 8-BIT
MIN and MAX registers. To initiate a new peak hold cycle NADC[7] 0 1
for all measurements, set CTRLB[3] of CTRLB register Conversion Time SENSE+, GPIO 16.4ms 1.02ms
(Table 6). This bit is self-cleared. For new peak hold cycle ∆SENSE* 65.6ms 4.1ms
of selective measurement, write all 1’s to its MIN regis- LSB Step Size SENSE+ 25mV 400mV
ter and all 0’s to its MAX register via the I2C bus. These GPIO 0.5mV 8mV
registers will be updated when the next respective ADC ∆SENSE 12.5μV 200μV
conversion is done. *Snapshot mode
The LTC2992 also includes MIN and MAX threshold reg- If the resolution is changed while an ADC conversion is
isters (Table 4) for the measured parameters including the in progress, that conversion will be aborted. In continu-
calculated power. At power-up or reset by I2C command, ous scan mode, a new conversion of the same quantity
the MAX threshold registers are set to all 1’s, and MIN will be started with the new resolution and continues in
threshold registers are set to all 0’s, effectively disabling the original sequence. Otherwise, a new snapshot of one,
them. The MIN and MAX threshold registers can be repro- two or multiple quantities (single cycle) will take place.
grammed to any desired value via the I2C bus. Resetting the peak hold registers by setting CTRLB[3] in
the CTRLB register via I2C bus prior to changing the ADC
Fault Alert and Resetting Faults resolution is recommended to ensure integrity of the peak
As soon as a measured quantity falls below the minimum hold values.
threshold or exceeds the maximum threshold, the LTC2992 The data format in 8-bit mode for voltage/current is left
sets the corresponding flag in the FAULT1 (Table 8), FAULT2 justified by four bits and power is left justified by eight bits
(Table 12) and FAULT3 registers (Table 14). Other events with respect to the 12-bit’s format as shown in Figure 6.
such as GPIO state change have their present status in
the GPIO STATUS (Table 17) register and any fault is POWER REGISTER VALUE
latched in the FAULT4 (Table 16) register. The GPIO4 pin MODE BIT
is pulled low if the appropriate bit in the ALERT1 (Table 7), 23:20 19:16 15:12 11:8 7:4 3:0
ALERT2 (Table 11), ALERT3 (Table 13) and ALERT4 (Table 12-bit Data Data Data Data Data Data
15) registers is set when the fault occurs. More details 8-bit Data Data Data Data 0x0 0x0
on the alert behavior can be found in the Alert Response
Protocol section. VOLTAGE/CURRENT REGISTER VALUE
An active fault indication can be reset by writing zeros MODE BIT
to the corresponding FAULT register bits or setting bit 15:12 11:8 7:4 3:0
CTRLB[5] in the CTRLB register. If bit CTRLB[5] is set, 12-bit Data Data Data 0x0
reading the fault register will cause the corresponding 8-bit Data Data 0x0 0x0
register to reset. All FAULT register bits are also cleared Figure 6. Data Format in 12-Bit and 8-Bit Mode

Rev A

18 For more information [Link]

 LTC2992
APPLICATIONS INFORMATION
ADC Status and Data Ready Signal 2. If adjacent GPIO pins have to be used, then decouple
ADC STATUS register (Table 10) indicates availability of the analog signal to device ground near the GPIO pin
new measurement results in the internal registers and is with an external capacitor. Typically, a capacitance of
reset after it is read via I2C bus. Details on configuring 0.1µF should suffice.
GPIO3 as DATAREADY can be found in Configuring the 3. Shield the sensitive signal with ground.
GPIO Pins section. To illustrate the behavior of DATAREADY
4. In a multi-layer PCB, the sensitive signal should be
as new data becomes available, an example in which the
routed mostly sandwiched between two ground layers
ADCs are continuously converting is shown in Figure 7.
and exit next to the part for connection to the pin.
GPIO3 is initially configured to output a 16µs low pulse
with new data as is seen at t4 and t5. As S1 and S2 data A layout example is given in Layout Considerations section
are updated together with I1 and I2 at t5, no GPIO3 pulse for two-layered board design.
is seen at t2 and t3. GPIO3 is then reconfigured to latch I2C Interface
low with new data—this happens at t6. GPIO3 is released
from its latched state when an I2C read command to ADC The LTC2992 includes an I2C/SMBus-compatible interface
STATUS register is done. to provide access to the onboard registers. Figure 8 shows
a general data transfer format using the I2C bus.
Crosstalk Mitigation The LTC2992 is a read/write slave device and supports the
The GPIO pins are general purpose pins that can be used SMBus read byte, write byte, read word and write word
to monitor digital or analog signals. Even with an averaging protocols. The LTC2992 also supports extended read
architecture of the ∆∑ ADCs, crosstalk may still be prob- and write commands that allow reading or writing more
lematic if an application requires monitoring of precision than two bytes of data. When using the read/write word
analog signals and noisy digital signals with the GPIO pins. or extended read and write commands, the bus master
issues an initial register address and the internal register
To preserve measurement accuracy of the analog signals,
address pointer automatically increments by 1 after each
a few measures can be taken:
byte of data is read or written. After the register address
1. Physically separate the clean and noisy signals. For ex- reaches 0x97, it will roll over to 0x00 and continue incre-
ample, the clean signal may be monitored with GPIO1/3 menting. A STOP condition resets the register address
while the noisy signal is monitored with GPIO2/4 on pointer to 0x00. The data formats for the above commands
the other side of the part. are shown in Figure 8 through Figure 14. Note that only

POWER UP
t1 t2 t3 t4 t5 t6 t7 t8

VADC S1 S2 G1 G2 G3 G4 S1 S2

IADC1 CAL I1 AND P1 CAL I1 AND P1

IADC2 CAL I2 AND P2 CAL I2 AND P2

WRITE READ READ WRITE READ

I2C BUSES REG: 0x96 IDLE REG: 0x32 IDLE REG: 0x32 IDLE REG: 0x96 IDLE REG: 0x32 IDLE
DATA: 0x12 DATA: 0x00 DATA: 0x00 DATA: 0x32 DATA: 0xFF

GPIO3
2992 F07
16µs PULSE

Figure 7. Configuring GPIO3 as DATAREADY

Rev A

For more information [Link] 19

LTC2992
APPLICATIONS INFORMATION
the read byte command is available to the 0xE7 and 0xE8 to several LTC2992s simultaneously, regardless of their
(MFR_SPECIAL_ID) registers (Table 4). individual address settings. The LTC2992 will also respond
to the standard SMBus ARA address (0001100)b if the
I2C Device Addressing GPIO4 (ALERT) pin is asserted. See the Alert Response
Nine distinct I2C bus addresses are configurable using Protocol section for more details. The LTC2992 will not
the three-state pins ADR0 and ADR1, as shown in Table respond to the ARA address if no alerts are pending.
3. ADR0 and ADR1 should be tied to INTVCC, to GND, or
left floating (NC) to configure the lower four address bits. Start and Stop Conditions
During low power shutdown, the address select state When the I2C bus is idle, both SCL and SDA are in the high
is latched into memory powered from standby supply. state. A bus master signals the beginning of a transmis-
Address bits a6, a5 and a4 are permanently set to 110 sion with a START condition by transitioning SDA from
and the least significant bit is the R/W bit. In addition, all high to low while SCL stays high. When the master has
LTC2992 devices will respond to a common mass write finished communicating with the slave, it issues a STOP
address (1100110)b; this allows the bus master to write

SDA a6 - a0 b7 - b0 b7 - b0

SCL 1-7 8 9 1-7 8 9 1-7 8 9

S P

START ADDRESS R/W ACK DATA ACK DATA ACK STOP

CONDITION CONDITION
2992 F08

Figure 8. General Data Transfer Over I2C

S ADDRESS W A COMMAND A DATA A P S ADDRESS W A COMMAND A DATA A DATA A P

1 1 0 a3:a0 0 0 b7:b0 0 b7:b0 0 1 1 0 a3:a0 0 0 b7:b0 0 b7:b0 0 b7:b0 0
2992 F09
2992 F10
FROM MASTER TO SLAVE A: ACKNOWLEDGE (LOW) W: WRITE BIT (LOW)
FROM SLAVE TO MASTER A: NOT ACKNOWLEDGE (HIGH) S: START CONDITION Figure 10. Serial Bus SDA Write Word Protocol
R: READ BIT (HIGH) P: STOP CONDITION

Figure 9. Serial Bus SDA Write Byte Protocol

S ADDRESS W A COMMAND A DATA A DATA A ... DATA A P S ADDRESS W A COMMAND A S ADDRESS R A DATA A P
1 1 0 a3:a0 0 0 b7:b0 0 b7:b0 0 b7:b0 0 ... b7:b0 0 1 1 0 a3:a0 0 0 b7:b0 0 1 1 0 a3:a0 1 0 b7:b0 1
2992 F11 2992 F12

Figure 11. Serial Bus SDA Write Page Protocol Figure 12. Serial Bus SDA Read Byte Protocol

S ADDRESS W A COMMAND A S ADDRESS R A DATA A DATA A P

1 1 0 a3:a0 0 0 b7:b0 0 1 1 0 a3:a0 1 0 b7:b0 0 b7:b0 1
2992 F13

Figure 13. Serial Bus SDA Read Word Protocol

S ADDRESS W A COMMAND A S ADDRESS R A DATA A DATA ... DATA A P

1 1 0 a3:a0 0 0 b7:b0 0 1 1 0 a3:a0 1 0 b7:b0 0 b7:b0 ... b7:b0 1
2992 F14

Figure 14. Serial Bus SDA Read Page Protocol

Rev A

20 For more information [Link]

 LTC2992
APPLICATIONS INFORMATION
condition by transitioning SDA from low to high while SCL bytes will be acknowledged by the LTC2992, the register
stays high. The bus is then free for another transmission. address pointer will automatically increment by one, and
data will be written as previously stated. The write opera-
Stuck-Bus Reset tion terminates and the register address pointer resets to
The LTC2992 I2C interface features a stuck-bus reset timer 0x00 when the master sends a STOP condition.
to prevent it from holding the bus lines low indefinitely if
the SCL signal is interrupted during a transfer. The timer Read Protocol
starts when either SCL or SDAI is low, and resets when The master begins a read operation with a START condi-
both SCL and SDAI are pulled high. If either SCL or SDAI tion followed by the 7-bit slave address and the R/W bit
are low for over 33ms, the stuck-bus timer will expire, and set to zero. After the addressed LTC2992 acknowledges
the internal I2C interface and the SDAO pin pull-down logic the address byte, the master then sends a command byte
will be reset to release the bus. Normal communication that indicates which internal register the master wishes to
will resume at the next START command. read. The LTC2992 acknowledges this and then latches the
command byte into its internal register address pointer.
Acknowledge The master then sends a repeated START condition fol-
The acknowledge signal is used for handshaking between lowed by the same 7-bit address with the R/W bit now set
the master and the slave to indicate that the last byte of to 1. The LTC2992 acknowledges and sends the contents
data was received. The master always releases the SDA of the requested register. The transmission terminates
line during the acknowledge clock pulse. The LTC2992 will when the master sends a STOP condition. If the master
pull the SDA line low on the 9th clock cycle to acknowledge acknowledges the transmitted data byte, as in a read word
receipt of the data. If the slave fails to acknowledge by command, the LTC2992 will send the contents of the next
leaving SDA high, then the master can abort the transmis- register. If the master keeps acknowledging, the LTC2992
sion by generating a STOP condition. When the master is will keep incrementing the register address pointer and
receiving data from the slave, the master must acknowledge sending out data bytes. The read operation terminates
the slave by pulling down the SDA line during the 9th clock and the register address pointer resets to 0x00 when the
pulse to indicate receipt of a data byte. After the last byte master sends a STOP condition.
has been received by the master, it will leave the SDA line
high (not acknowledge) and issue a STOP condition to Alert Response Protocol
terminate the transmission. When any of the fault bits in the fault registers (FAULT1,
FAULT2, FAULT3 and FAULT4) are set, a bus alert is gener-
Write Protocol ated if the appropriate bit in the ALERT1, ALERT2, ALERT3
The master begins a write operation with a START condi- or ALERT4 registers has been set. This allows the bus
tion followed by the 7-bit slave address and the R/W bit master to select which faults will generate alerts. At power-
set to zero. After the addressed LTC2992 acknowledges up, all ALERT registers are cleared (no alerts enabled) and
the address byte, the master then sends a command byte the GPIO4 (ALERT) pin is high. If an alert is enabled, the
that indicates which internal register the master wishes to corresponding fault causes the GPIO4 (ALERT) pin to pull
write. The LTC2992 acknowledges this and then latches low. The bus master responds to the alert in accordance
the command byte into its internal register address pointer. with the SMBus alert response protocol by broadcasting
The master then delivers the data byte and the LTC2992 the alert response address (0001100)b, and the LTC2992
acknowledges once more and writes the data into the in- replies with its own address and releases its GPIO4 (ALERT)
ternal register pointed to by the register address pointer. If pin, as shown in Figure 15. The GPIO4 (ALERT) line is also
the master continues sending additional data bytes with a released if CTRLB[7] is set and the LTC2992 is addressed
write word or extended write command, the additional data (see Table 6) by any message. The GPIO4 (ALERT) signal

Rev A

For more information [Link] 21

LTC2992
APPLICATIONS INFORMATION
is not pulled low again until the fault registers indicate a open-drain opto-isolators can use the LTC2992 with the
different fault has occurred or the original fault is cleared SDAI and SDAO pins separated, as shown in Figure 16.
and it occurs again. Note that this means repeated or Connect SDAI to the output of the incoming opto-isolator
continuing faults will not generate additional alerts until with a pull-up resistor to INTVCC or a local 5V supply; con-
the associated fault register bits have been cleared. nect SDAO to the cathode of the outgoing opto-isolator
with a current-limiting resistor in series with the anode.
S
ALERT
RESPONSE R A DEVICE A P
The input and output must be connected together on the
ADDRESS ADDRESS
isolated side of the bus to allow the LTC2992 to participate
0001100 1 0 a7:a0 1 2992 F15 in I2C arbitration. Note that maximum I2C bus speed will
generally be limited by the speed of the opto-couplers
Figure 15. Serial Bus SDA Alert Response Protocol
used in this application.
If two or more LTC2992s on the same bus are generat- Figure 17 shows an alternate connection for use with low
ing alerts when the ARA is broadcast, the bus master speed opto-couplers and the LTC2992-1. This circuit uses
will repeat the alert response protocol until the GPIO4 a limited-current pull-up on the internally clamped SDAI
(ALERT) line is released. Standard I2C arbitration causes pin and clamps the SDAO pin with the input diode of the
the device with the highest priority (lowest address) to outgoing opto-isolator, removing the need to use INTVCC
reply first and the device with the lowest priority (highest for biasing in the absence of a separate low voltage sup-
address) to reply last. ply. For proper clamping:

Opto-Isolating the I2C Bus VIN(MAX) – VSDA,SCL(MIN) VIN(MIN) – VSDA,SCL(MAX) (1)

≤R4 ≤
ISDA,SCL(MAX) ISDA,SCL(MIN)
Opto-isolating a standard I2C device is complicated by the
bidirectional SDA pin. The LTC2992/LTC2992-1 minimize VIN(MAX) – 5.9V VIN(MIN) – 6.9V
≤R4 ≤
this problem by splitting the standard I2C SDA line into SDAI 5mA 0.5mA
(input) and SDAO (output, LTC2992) or SDAO (inverted
output, LTC2992-1). The SCL is an input-only pin and does As an example, a supply that operates from 36V to 72V
not require special circuitry to isolate. For conventional would require the value of R4 to be between 13k and
nonisolated I2C applications, use the LTC2992 and tie 58k. The LTC2992-1 must be used in this application
the SDAI and SDAO pins together to form a standard I2C to ensure that SDAO signal polarity is correct. R4 may
SDA pin. Low speed isolated interfaces that use standard
3.3V VIN
5V 48V 3.3V
R4 R5 R6
R7 R8 R10 R4 R5
4.7k 4.7k 0.82k
0.47k 0.47k 2k 20k 5.1k R6 R7
SCL 0.51k 2k
LTC2992 VDD
SDAI
SCL
SDAI LTC2992-1 VDD
µP µP
1/2 MOCD207M
MOCD207M

SDA SDAO SDA

GND
GND
GND 2992 F17
2992 F16
SDAO
GND 1/2 MOCD207M
1/2 MOCD207M

Figure 16. Opto-Isolation of a 10kHz I2C Interface Between Figure 17. Opto-Isolation of a 1.5kHz I2C Interface Between
LTC2992 and Microcontroller LTC2992-1 and Microcontroller (SCL Omitted for Clarity)
Rev A

22 For more information [Link]

 LTC2992
APPLICATIONS INFORMATION
be split into two or more series connected units to meet Layout Considerations
thermal requirements.
A Kelvin connection between the sense resistor RSNS and
The LTC2992 can also be used with high speed optocou- the LTC2992 is recommended to achieve accurate current
plers with push-pull outputs and inverted logic as shown sensing (Figure 19). The recommended minimum trace
in Figure 18. The incoming opto-isolator draws power from width for 1oz copper foil is 0.02˝ per amp to ensure the
INTVCC, and the data output is connected directly to the trace stays at a reasonable temperature. Using 0.03˝ per
SDAI pin with no pull-up required. Ensure current drawn amp or wider is preferred. Note that 1oz copper exhibits
does not exceed the 10mA maximum capability of the a sheet resistance of about 530μΩ per square. In very
INTVCC pin. The SDAO pin is connected to the cathode of high current applications where the sense resistor can
the outgoing opto-coupler with a current limiting resistor dissipate significant power, the PCB layout should include
connected back to INTVCC. An additional discrete diode good thermal management techniques such as extra vias
is required at the output of the outgoing opto-coupler to and wide metal area. 2oz or thicker copper should be
provide the open-drain pull-down that the I2C requires. considered for such applications. The trace from sense
Finally, the input of the incoming opto-isolator is connected resistors to SENSE+ pins should be as short as possible
back to the output as in the low speed case. to minimize IR drop due to pin current.

VIN
VDD INTVCC
48V
C1 C2 R5 3.3V
1µF 1µF 2k 1/2 ACPL-064L*
LTC2992 VCC

R6 R7
2k 2k
SDAO GND BAT54

1/2 ACPL-064L* VDD

VCC
µP
SDAI
GND ISO_SDA
GND SDA

GND
*:CMOS OUTPUT 2992 F18

Figure 18. Opto-Isolation of a I2C Interface with Low Power, High Speed Opto-Couplers (SCL Omitted for Clarity)

BOTTOM LAYER
VIN1 TOP LAYER VIN2

RSNS1 RSNS2

1 16

TO LOAD1 2 15 TO LOAD2
3 14
4 13
17
5 12
6 11 GND
7 10
VIA
8 9

2992 F19

Figure 19. Recommended PCB Layout

Rev A

For more information [Link] 23

LTC2992
APPLICATIONS INFORMATION
Design Example Choose R10,11 = 1MΩ, and R12,13 = 20kΩ to allow a
input voltage measurement range from 0V to 104.4V.
As a design example, consider a –36V to –72V Advanced
TCA system with I2C current, voltage and power monitors R11+ R13 25.5mV
Voltage of V IN1 = • V GPIO1 =
(See Figure 20). R13 LSB
The load current is either supplied by VIN1 or VIN2 or R10 + R12 25.5mV
Voltage of V IN2 = • V GPIO2 =
both depending on their voltages. Choose similar values R12 LSB
for RSENSE1 and RSENSE2 in accordance to the following
An error term can be added to the voltage results above
equation:
to account for the voltage drop across the N-channel
VFS( ∆ SENSE1,2) MOSFET and sense resistor:
R SENSE1,2 <
ILOAD(MAX) VERROR = ∆VDS of FDS3672 + ∆SENSE
51.2mV The maximum error occurs when the load current is at
R SENSE1,2 < = 10.24mΩ
5A its maximum of 5A. Using the above equation, this works
out to be 160mV with 110mV contribution (see below for
RSENSE1 and RSENSE2 are chosen to be 10mΩ.
calculation) from the FDS3672. Without compensation, this
12.5µV would cause measurement error of 0.45% for VIN = 36V.
Current of V IN1 or V IN2 = = 1.25mA / LSB
R SENSE LTC4354 and LTC4355 low side and high side ideal diode-
OR controllers drive N-channel MOSFETs to minimize the
Total Current = 2.5mA/LSB diode power consumption. The 100V, N-channel MOSFET
We also have to consider the power dissipated in the FDS3672 in the SO-8 package with RDS(ON) = 22mΩ
sense resistors which can be calculated with the follow- (max) is chosen as switches. The maximum voltage drop
ing equation: across it is:
P = (ILOAD)2 • RSENSE ∆VDS = 5A × 22mΩ = 110mV
P = (5A)2 • 10mΩ = 0.25W Since external resistive dividers are used for supply volt-
age measurement, CTRLA register 0x00 is set to 0x10 to
Use at least 0.5W rated sense resistors to ensure thermal continuously monitor GPIO1 and GPIO2.
compliance.
POWER1 = VIN1 • Current of VIN1
Next, select the resistive dividers that measure the supply
voltages VIN1 and VIN2. Note that the voltage drop across POWER1 = 25.5mV • 1.25mA/LSB = 31.875µW/LSB
the N-channel MOSFET and sense resistor is not included POWER2 = 31.875µW/LSB
in the derivation for the following equations.
Total Power = 63.75µW/LSB
R12 VFS(GPIO2) R13 VFS(GPIO1)
< , <
R10 + R12 VIN2 R11+ R13 VIN1
R12 2.048V
< = 0.028
R10 + R12 72V
R13 2.048V
< = 0.028
R11+ R13 72V

Rev A

24 For more information [Link]

 Q3
FDS3672
RTN1 RTN(OUT)
Q4
FDS3672
RTN2 Z1 R3
SMBT70A 91Ω
C2
22nF R4
51k
IN1 GATE1 IN2 GATE2 OUT
Q1
MON1 LTC4355 Q2 PZTA42
MMBT5401
MON2 GND C1 C4 3.3V
0.1µF 0.1µF

R5 R6 R7 R8
R11 R10 R1 R2 0.51k 0.51k 1k 1k VDD
VDD INTVCC
1M 1M 1k 1k VCC

GPIO1 SCL
SCL
GPIO2
APPLICATIONS INFORMATION

SDAI µP
LTC2992

R9 GND
ACPL-064L
12k
0.5W
3.3V

ADR1 VCC
R13 R12 ADR0
20k 20k SDA
VCC
DATAREADY GPIO3 SDAO

For more information [Link]

LTC4354

DA DB GA GB VSS VSS GND INT

ALERT GND
GPIO4
R13 R14 C3
2k 2k ACPL-064L GND
1µF SENSE1– SENSE1+ SENSE2– SENSE2+
2992 F20

VIN2
–36V TO –72V Q5 RSENSE2
FDS3672 0.01Ω

VIN1 VOUT
–36V TO –72V Q6 5A
RSENSE1
FDS3672
0.01Ω

Figure 20. Design Example: Advanced TCA System with I2C Current, Voltage and Power Monitors

25
Rev A
LTC2992
LTC2992
APPLICATIONS INFORMATION
Table 3. Device Addressing
ADDRESS HEX DEVICE
DESCRIPTION ADDRESS* BINARY DEVICE ADDRESSING ADDRESS PINS
7-BIT 8-BIT a6 a5 a4 a3 a2 a1 a0 R/W ADR1 ADR0
Mass Write 66 CC 1 1 0 0 1 1 0 0 X X
Alert Response 0C 19 0 0 0 1 1 0 0 1 X X
0 67 CE 1 1 0 0 1 1 1 0 H L
1 68 D0 1 1 0 1 0 0 0 0 NC H
2 69 D2 1 1 0 1 0 0 1 0 H H
3 6A D4 1 1 0 1 0 1 0 0 NC NC
4 6B D6 1 1 0 1 0 1 1 0 NC L
5 6C D8 1 1 0 1 1 0 0 0 L H
6 6D DA 1 1 0 1 1 0 1 0 H NC
7 6E DC 1 1 0 1 1 1 0 0 L NC
8 6F DE 1 1 0 1 1 1 1 0 L L
H = Tie to INTVCC, NC = No Connect = Open, L = Tie to GND, X = Don’t Care
*8-Bit hexadecimal address with LSB R/W bit = 0
7-Bit hexadecimal address with MSB a7 = 0

Table 4. Register Addresses and Contents

REGISTER READ/ NUMBER
REGISTER NAME ADDRESS DESCRIPTION WRITE OF BYTES* DEFAULT
CTRLA 0x00 Operation Control Register A R/W 1 0x00
CTRLB 0x01 Operation Control Register B R/W 1 0x00
ALERT1 0x02 Selects Which CHANNEL 1 Faults Generate Alerts R/W 1 0x00
FAULT1 0x03 CHANNEL 1 Fault Log R/W 1 0x00
NADC 0x04 ADC Resolution R/W 1 0x00
P1 0x05-0x07 POWER1 Data R/W 3 NA
MAX P1 0x08-0x0A Maximum POWER1 Data R/W 3 NA
MIN P1 0x0B-0x0D Minimum POWER1 Data R/W 3 NA
MAX P1 0x0E-0x10 Maximum POWER1 Threshold to Generate Alert R/W 3 0xFFFFFF
THRESHOLD
MIN P1 0x11-0x13 Minimum POWER1 Threshold to Generate Alert R/W 3 0x000000
THRESHOLD
I1 0x14-0x15 ∆SENSE1 Data R/W 2 NA
MAX I1 0x16-0x17 Maximum ∆SENSE1 Data R/W 2 NA
MIN I1 0x18-0x19 Minimum ∆SENSE1 Data R/W 2 NA
MAX I1 0x1A-0x1B Maximum ∆SENSE1 Threshold to Generate Alert R/W 2 0xFFF0
THRESHOLD
MIN I1 0x1C-0x1D Minimum ∆SENSE1 Threshold to Generate Alert R/W 2 0x0000
THRESHOLD
S1 0x1E-0x1F SENSE1+ Data R/W 2 NA
MAX S1 0x20-0x21 Maximum SENSE1+ Data R/W 2 NA
MIN S1 0x22-0x23 Minimum SENSE1+ Data R/W 2 NA

Rev A

26 For more information [Link]

 LTC2992
APPLICATIONS INFORMATION
Table 4. Register Addresses and Contents (continued)
REGISTER READ/ NUMBER
REGISTER NAME ADDRESS DESCRIPTION WRITE OF BYTES DEFAULT
MAX S1 0x24-0x25 Maximum SENSE1+ Threshold to Generate Alert R/W 2 0xFFF0
THRESHOLD
MIN S1 0x26-0x27 Minimum SENSE1+ Threshold to Generate Alert R/W 2 0x0000
THRESHOLD
G1 0x28-0x29 GPIO1 Data R/W 2 NA
MAX G1 0x2A-0x2B Maximum GPIO1 Data R/W 2 NA
MIN G1 0x2C-0x2D Minimum GPIO1 Data R/W 2 NA
MAX G1 0x2E-0x2F Maximum GPIO1 Threshold to Generate Alert R/W 2 0xFFF0
THRESHOLD
MIN G1 0x30-0x31 Minimum GPIO1 Threshold to Generate Alert R/W 2 0x0000
THRESHOLD
ADC STATUS 0x32 ADC Status Information R 1 NA
RESERVED 0x33 Manufacturer Reserved R 1 0x00
ALERT2 0x34 Selects Which CHANNEL 2 Faults Generate Alerts R/W 1 0x00
FAULT2 0x35 CHANNEL 2 Fault Log R/W 1 0x00
RESERVED 0x36 Manufacturer Reserved R 1 0x00
P2 0x37-0x39 POWER2 Data R/W 3 NA
MAX P2 0x3A-0x3C Maximum POWER2 Data R/W 3 NA
MIN P2 0x3D-0x3F Minimum POWER2 Data R/W 3 NA
MAX P2 0x40-0x42 Maximum POWER2 Threshold to Generate Alert R/W 3 0xFFFFFF
THRESHOLD
MIN P2 0x43-0x45 Minimum POWER2 Threshold to Generate Alert R/W 3 0x000000
THRESHOLD
I2 0x46-0x47 ∆SENSE2 Data R/W 2 NA
MAX I2 0x48-0x49 Maximum ∆SENSE2 Data R/W 2 NA
MIN I2 0x4A-0x4B Minimum ∆SENSE2 Data R/W 2 NA
MAX I2 0x4C-0x4D Maximum ∆SENSE2 Threshold to Generate Alert R/W 2 0xFFF0
THRESHOLD
MIN I2 0x4E-0x4F Minimum ∆SENSE2 Threshold to Generate Alert R/W 2 0x0000
THRESHOLD
S2 0x50-0x51 SENSE2+ Data R/W 2 NA
MAX S2 0x52-0x53 Maximum SENSE2+ Data R/W 2 NA
MIN S2 0x54-0x55 Minimum SENSE2+ Data R/W 2 NA
MAX S2 0x56-0x57 Maximum SENSE2+ Threshold to Generate Alert R/W 2 0xFFF0
THRESHOLD
MIN S2 0x58-0x59 Minimum SENSE2+ Threshold to Generate Alert R/W 2 0x0000
THRESHOLD
G2 0x5A-0x5B GPIO2 Data R/W 2 NA
MAX G2 0x5C-0x5D Maximum GPIO2 Data R/W 2 NA
MIN G2 0x5E-0x5F Minimum GPIO2 Data R/W 2 NA
MAX G2 0x60-0x61 Maximum GPIO2 Threshold to Generate Alert R/W 2 0xFFF0
THRESHOLD

Rev A

For more information [Link] 27

LTC2992
APPLICATIONS INFORMATION
Table 4. Register Addresses and Contents (continued)
REGISTER READ/ NUMBER
REGISTER NAME ADDRESS DESCRIPTION WRITE OF BYTES DEFAULT
MIN G2 0x62-0x63 Minimum GPIO2 Threshold to Generate Alert R/W 2 0x0000
THRESHOLD
G3 0x64-0x65 GPIO3 Data R/W 2 NA
MAX G3 0x66-0x67 Maximum GPIO3 Data R/W 2 NA
MIN G3 0x68-0x69 Minimum GPIO3 Data R/W 2 NA
MAX G3 0x6A-0x6B Maximum GPIO3 Threshold to Generate Alert R/W 2 0xFFF0
THRESHOLD
MIN G3 0x6C-0x6D Minimum GPIO3 Threshold to Generate Alert R/W 2 0x0000
THRESHOLD
G4 0x6E-0x6F GPIO4 Data R/W 2 NA
MAX G4 0x70-0x71 Maximum GPIO4 Data R/W 2 NA
MIN G4 0x72-0x73 Minimum GPIO4 Data R/W 2 NA
MAX G4 0x74-0x75 Maximum GPIO4 Threshold to Generate Alert R/W 2 0xFFF0
THRESHOLD
MIN G4 0x76-0x77 Minimum GPIO4 Threshold to Generate Alert R/W 2 0x0000
THRESHOLD
ISUM 0x78-0x79 (∆SENSE1 + ∆SENSE2) Data R/W 2 NA
MAX ISUM 0x7A-0x7B Maximum (∆SENSE1 + ∆SENSE2) Data R/W 2 NA
MIN ISUM 0x7C-0x7D Minimum (∆SENSE1 + ∆SENSE2) Data R/W 2 NA
MAX ISUM 0x7E-0x7F Maximum (∆SENSE1 + ∆SENSE2) Threshold to Generate Alert R/W 2 0xFFF0
THRESHOLD
MIN ISUM 0x80-0x81 Minimum (∆SENSE1 + ∆SENSE2) Threshold to Generate Alert R/W 2 0x0000
THRESHOLD
PSUM 0x82-0x84 (POWER1 + POWER2) Data R/W 3 NA
MAX PSUM 0x85-0x87 Maximum (POWER1 + POWER2) Data R/W 3 NA
MIN PSUM 0x88-0x8A Minimum (POWER1 + POWER2) Data R/W 3 NA
MAX PSUM 0x8B-0x8D Maximum (POWER1 + POWER2) Threshold to Generate Alert R/W 3 0xFFFFFF
THRESHOLD
MIN PSUM 0x8E-0x90 Minimum (POWER1 + POWER2) Threshold to Generate Alert R/W 3 0x000000
THRESHOLD
ALERT3 0x91 Selects Which GPIO or Total Current/Power Faults Generate R/W 1 0x00
Alerts
FAULT3 0x92 GPIO and Total Current/Power Fault Log R/W 1 0x00
ALERT4 0x93 Selects Which Additional Faults Generate Alerts R/W 1 0x00
FAULT4 0x94 Additional Fault Log R/W 1 0x00
GPIO STATUS 0x95 GPIO Status Information R 1 NA
GPIO IO 0x96 GPIO1,2,3 Input/Output Control Command R/W 1 0x03
CONTROL
GPIO4 CONTROL 0x97 GPIO4 Control Command R/W 1 0x00
MFR_SPECIAL_ID 0xE7 Manufacturer Special ID MSB Data R 1 0x00
MSB
MFR_SPECIAL_ID 0xE8 Manufacturer Special ID LSB Data R 1 0x62
LSB
* For the 2-/3-byte data registers, the MSB value is at the lowest address

Rev A

28 For more information [Link]

 LTC2992
APPLICATIONS INFORMATION
Table 5. CTRLA Register (0x00) – Read/Write
BIT NAME OPERATION
CTRLA[7] Offset Calibration Offset Calibration for Current Measurements
[1] = Calibrate on Demand
[0] = Every Conversion (Default)
CTRLA[6:5] Measurement [11] = Shutdown
Mode [10] = Single Cycle mode
The VADC converts SENSE1+, SENSE2+, GPIO1, GPIO2, GPIO3, GPIO4 once and stops. The IADCs stop after
one conversion.
P1 = SENSE1+ × ∆SENSE1; P2 = SENSE2+ × ∆SENSE2
[01] = Snapshot Mode
Snapshot Initializes Conversion on All 3 ADCs Simultaneously.
VADC Converts the Channel(s) per CTRLA[2:0]
[00] = Continuous Scan Mode (Default)
The Selected Channels for VADC are Defined by CTRLA[4:3]
CTRLA[4:3] Voltage Selection CTRLA[4:3] VADC P1 P2
for Continuous 11 GPIO1, GPIO2, GPIO1 × ∆SENSE1 GPIO2 × ∆SENSE2
Scan Mode GPIO3, GPIO4
10 GPIO1, GPIO2 GPIO1 × ∆SENSE1 GPIO2 × ∆SENSE2
01 SENSE1+, SENSE2+ SENSE1+ × ∆SENSE1 SENSE2+ × ∆SENSE2
00 (Default) SENSE1+, SENSE2+, SENSE1+ × ∆SENSE1 SENSE2+ × ∆SENSE2
GPIO1, GPIO2,
GPIO3, GPIO4
CTRLA[2:0] Voltage Selection CTRLA[2:0] VADC P1 P2
for Snapshot 111 GPIO1, GPIO2 GPIO1 × ∆SENSE1 GPIO2 × ∆SENSE2
Mode
110 SENSE1+, SENSE2+ SENSE1+ × ∆SENSE1 SENSE2+ × ∆SENSE2
101 GPIO4 ∆SENSE1/2 without P1/P2 updates
100 GPIO3
011 GPIO2
010 GPIO1
001 SENSE2+
000 (Default) SENSE1+

Table 6. CTRLB Register (0x01) – Read/Write

BIT NAME OPERATION
CTRLB[7] ALERT Clear Enable Clear ALERT if Device is Addressed by the Master
[1] = Enable
[0] = Disable (Default)
CTRLB[6] Reserved Always Returns 0, Not Writable
CTRLB[5] Cleared on Read Control FAULT Registers Cleared on Read
[1] = Cleared on Read
[0] = Registers Not Affected by Reading (Default)
CTRLB[4] Stuck Bus Timeout Auto Wake Up Allows Part to Exit Shutdown Mode when Stuck Bus Timer is Reached
[1] = Enable
[0] = Disable (Default)
CTRLB[3] Peak Hold Values Reset Reset of Min and Max Registers
[1] = Reset All Min and Max Registers
[0] = Disable Reset of Min and Max Registers (Default)
CTRLB[2:1] Reserved Always Returns 00, Not Writable
CTRLB[0] Reset [1] = Reset All Registers
[0] = Disable Reset (Default)
Rev A

For more information [Link] 29

LTC2992
APPLICATIONS INFORMATION
Table 7. ALERT1 Register (0x02) – Read/Write
BIT NAME OPERATION
AL1[7] Maximum POWER1 Alert Enables Alert When POWER1 > Maximum POWER1 Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
AL1[6] Minimum POWER1 Alert Enables Alert When POWER1 < Minimum POWER1 Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
AL1[5] Maximum ∆SENSE1 Alert Enables Alert When ∆SENSE1 > Maximum ∆SENSE1 Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
AL1[4] Minimum ∆SENSE1 Alert Enables Alert When ∆SENSE1 < Minimum ∆SENSE1 Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
AL1[3] Maximum SENSE1+ Alert Enables Alert When SENSE1+ > Maximum SENSE1+ Threshold
[1] = Enable Alert
[0] = Disable Alert(Default)
AL1[2] Minimum SENSE1+ Alert Enables Alert When SENSE1+ < Minimum SENSE1+ Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
AL1[1] Maximum GPIO1 Alert Enables Alert When GPIO1 > Maximum GPIO1 Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
AL1[0] Minimum GPIO1 Alert Enables Alert When GPIO1 < Minimum GPIO1 Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)

Table 8. FAULT1 Register (0x03) – Read/Write

BIT NAME OPERATION
F1[7] POWER1 Overvalue Fault POWER1 > Maximum POWER1 Threshold
[1] = POWER1 Overvalue Fault Occurred
[0] = No POWER1 Overvalue Fault Occurred (Default)
F1[6] POWER1 Undervalue Fault POWER1 < Minimum POWER1 Threshold
[1] = POWER1 Undervalue Fault Occurred
[0] = No POWER1 Undervalue Fault Occurred (Default)
F1[5] ∆SENSE1 Overvalue Fault ∆SENSE1 > Maximum ∆SENSE1 Threshold
[1] = ∆SENSE1 Overvalue Fault Occurred
[0] = No ∆SENSE1 Overvalue Fault Occurred (Default)
F1[4] ∆SENSE1 Undervalue Fault ∆SENSE1 < Minimum ∆SENSE1 Threshold
[1] = ∆SENSE1 Undervalue Fault Occurred
[0] = No ∆SENSE1 Undervalue Fault Occurred (Default)
F1[3] SENSE1+ Overvalue Fault SENSE1+ > Maximum SENSE1+ Threshold
[1] = SENSE1+ Overvalue Fault Occurred
[0] = No SENSE1+ Overvalue Fault Occurred (Default)
F1[2] SENSE1+ Undervalue Fault SENSE1+ < Minimum SENSE1+ Threshold
[1] = SENSE1+ Undervalue Fault Occurred
[0] = No SENSE1+ Undervalue Fault Occurred (Default)
F1[1] GPIO1 Overvalue Fault GPIO1 > Maximum GPIO1 Threshold
[1] = GPIO1 Overvalue Fault Occurred
[0] = No GPIO1 Overvalue Fault Occurred (Default)
F1[0] GPIO1 Undervalue Fault GPIO1 < Minimum GPIO1 Threshold
[1] = GPIO1 Undervalue Fault Occurred
[0] = No GPIO1 Undervalue Fault Occurred (Default)
Rev A

30 For more information [Link]

 LTC2992
APPLICATIONS INFORMATION
Table 9. NADC Register (0x04) – Read/Write
BIT NAME OPERATION
NADC[7] ADC Resolution Selects ADC Resolution for All ADCs
[1] = 8-Bit
[0] = 12-Bit (Default)
NADC[6:0] Reserved Always Returns 0000000, Not Writable

Table 10. ADC STATUS Register (0x32) – Read Only (Clear-On-Read)

BIT NAME OPERATION
AS[7] IADCs Data Ready [1] = Ready
[0] = Not ready
AS[6] VADC Data Ready [1] = Ready
[0] = Not ready
Check AS[5:0] for the channel information
AS[5] GPIO4 Data Ready [1] = New Data Available
[0] = New Data Not Available
AS[4] GPIO3 Data Ready [1] = New Data Available
[0] = New Data Not Available
AS[3] GPIO2 Data Ready [1] = New Data Available
[0] = New Data Not Available
AS[2] GPIO1 Data Ready [1] = New Data Available
[0] = New Data Not Available
AS[1] SENSE2+ Data Ready [1] = New Data Available
[0] = New Data Not Available
AS[0] SENSE1+ Data Ready [1] = New Data Available
[0] = New Data Not Available

Table 11. ALERT2 Register (0x34) – Read/Write

BIT NAME OPERATION
AL2[7] Maximum POWER2 Alert Enables Alert When POWER2 > Maximum POWER2 Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
AL2[6] Minimum POWER2 Alert Enables Alert When POWER2 < Minimum POWER2 Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
AL2[5] Maximum ∆SENSE2 Alert Enables Alert When ∆SENSE2 > Maximum ∆SENSE2 Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
AL2[4] Minimum ∆SENSE2 Alert Enables Alert When ∆SENSE2 < Minimum ∆SENSE2 Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
AL2[3] Maximum SENSE2+ Alert Enables Alert When SENSE2+ > Maximum SENSE2+ Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
AL2[2] Minimum SENSE2+ Alert Enables Alert When SENSE2+ < Minimum SENSE2+ Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
AL2[1] Maximum GPIO2 Alert Enables Alert When GPIO2 > Maximum GPIO2 Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
AL2[0] Minimum GPIO2 Alert Enables Alert When GPIO2 < Minimum GPIO2 Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
Rev A

For more information [Link] 31

LTC2992
APPLICATIONS INFORMATION
Table 12. FAULT2 Register (0x35) – Read/Write
BIT NAME OPERATION
F2[7] POWER2 Overvalue Fault POWER2 > Maximum POWER2 Threshold
[1] = POWER2 Overvalue Fault Occurred
[0] = No POWER2 Overvalue Fault Occurred (Default)
F2[6] POWER2 Undervalue Fault POWER2 < Minimum POWER2 Threshold
[1] = POWER2 Undervalue Fault Occurred
[0] = No POWER2 Undervalue Fault Occurred (Default)
F2[5] ∆SENSE2 Overvalue Fault ∆SENSE2 > Maximum ∆SENSE2 Threshold
[1] = ∆SENSE2 Overvalue Fault Occurred
[0] = No ∆SENSE2 Overvalue Fault Occurred (Default)
F2[4] ∆SENSE2 Undervalue Fault ∆SENSE2 < Minimum ∆SENSE2 Threshold
[1] = ∆SENSE2 Undervalue Fault Occurred
[0] = No ∆SENSE2 Undervalue Fault Occurred (Default)
F2[3] SENSE2+ Overvalue Fault SENSE2+ > Maximum SENSE2+ Threshold
[1] = SENSE2+ Overvalue Fault Occurred
[0] = No SENSE2+ Overvalue Fault Occurred (Default)
F2[2] SENSE2+ Undervalue Fault SENSE2+ < Minimum SENSE2+ Threshold
[1] = SENSE2+ Undervalue Fault Occurred
[0] = No SENSE2+ Undervalue Fault Occurred (Default)
F2[1] GPIO2 Overvalue Fault GPIO2 > Maximum GPIO2 Threshold
[1] = GPIO2 Overvalue Fault Occurred
[0] = No GPIO2 Overvalue Fault Occurred (Default)
F2[0] GPIO2 Undervalue Fault GPIO2 < Minimum GPIO2 Threshold
[1] = GPIO2 Undervalue Fault Occurred
[0] = No GPIO2 Undervalue Fault Occurred (Default)

Table 13. ALERT3 Register (0x91) – Read/Write

BIT NAME OPERATION
AL3[7] Maximum GPIO3 Alert Enables Alert When GPIO3 > Maximum GPIO3 Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
AL3[6] Minimum GPIO3 Alert Enables Alert When GPIO3 < Minimum GPIO3 Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
AL3[5] Maximum GPIO4 Alert Enables Alert When GPIO4 > Maximum GPIO4 Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
AL3[4] Minimum GPIO4 Alert Enables Alert When GPIO4 < Minimum GPIO4 Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
AL3[3] Maximum (∆SENSE1 + ∆SENSE2) Alert Enables Alert When (∆SENSE1 + ∆SENSE2) > Maximum (∆SENSE1 +
∆SENSE2) Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
AL3[2] Minimum (∆SENSE1 + ∆SENSE2) Alert Enables Alert When (∆SENSE1 + ∆SENSE2) < Minimum (∆SENSE1 +
∆SENSE2) Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
AL3[1] Maximum (POWER1 + POWER2) Alert Enables Alert When (POWER1 + POWER2) > Maximum (POWER1 +
POWER2) Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
AL3[0] Minimum (POWER1 + POWER2) Alert Enables Alert When (POWER1 + POWER2) < Minimum (POWER1 +
POWER2) Threshold
[1] = Enable Alert
[0] = Disable Alert (Default)
Rev A

32 For more information [Link]

 LTC2992
APPLICATIONS INFORMATION
Table 14. FAULT3 Register (0x92) – Read/Write
BIT NAME OPERATION
F3[7] GPIO3 Overvalue Fault GPIO3 > Maximum GPIO3 Threshold
[1] = GPIO3 Overvalue Fault Occurred
[0] = No GPIO3 Overvalue Fault Occurred (Default)
F3[6] GPIO3 Undervalue Fault GPIO3 < Minimum GPIO3 Threshold
[1] = GPIO3 Undervalue Fault Occurred
[0] = No GPIO3 Undervalue Fault Occurred (Default)
F3[5] GPIO4 Overvalue Fault GPIO4 > Maximum GPIO4 Threshold
[1] = GPIO4 Overvalue Fault Occurred
[0] = No GPIO4 Overvalue Fault Occurred (Default)
F3[4] GPIO4 Undervalue Fault GPIO4 < Minimum GPIO4 Threshold
[1] = GPIO4 Undervalue Fault Occurred
[0] = No GPIO4 Undervalue Fault Occurred (Default)
F3[3] (∆SENSE1 + ∆SENSE2) Overvalue Fault (∆SENSE1 + ∆SENSE2) > Maximum (∆SENSE1 + ∆SENSE2) Threshold
[1] = Summed Current Overvalue Fault Occurred
[0] = No Summed Current Overvalue Fault Occurred (Default)
F3[2] (∆SENSE1 + ∆SENSE2) Undervalue Fault (∆SENSE1 + ∆SENSE2) < Minimum (∆SENSE1 + ∆SENSE2) Threshold
[1] = Summed Current Undervalue Fault Occurred
[0] = No Summed Current Undervalue Fault Occurred (Default)
F3[1] (POWER1 + POWER2) Overvalue Fault (POWER1 + POWER2) > Maximum (POWER1 + POWER2) Threshold
[1] = Summed Power Overvalue Fault Occurred
[0] = No Summed Power Overvalue Fault Occurred (Default)
F3[0] (POWER1 + POWER2) Undervalue Fault (POWER1 + POWER2) < Minimum (POWER1 + POWER2) Threshold
[1] = Summed Power Undervalue Fault Occurred
[0] = No Summed Power Undervalue Fault Occurred (Default)

Table 15. ALERT4 Register (0x93) – Read/Write

BIT NAME OPERATION
AL4[7] VADC Data Ready Alert Alert when VADC Data Ready
[1] = Enable
[0] = Disable (Default)
AL4[6] IADC Data Ready Alert Alert when IADCs Data Ready
[1] = Enable
[0] = Disable (Default)
AL4[5] Reserved Always Returns 0, Not Writable
AL4[4] Stuck Bus Time-Out Wakeup Alert Alert if Part Exits Shutdown Mode After Stuck Bus Timer Expires with CTRLB[4] = 1
[1] = Enable Alert
[0] = Disable Alert (Default)
AL4[3] GPIO1 Input Alert [1] = Enable Alert
[0] = Disable Alert (Default)
AL4[2] GPIO2 Input Alert [1] = Enable Alert
[0] = Disable Alert (Default)
AL4[1] GPIO3 Input Alert [1] = Enable Alert
[0] = Disable Alert(Default)
AL4[0] Reserved Always Returns 0, Not Writable

Rev A

For more information [Link] 33

LTC2992
APPLICATIONS INFORMATION
Table 16. FAULT4 Register (0x94) – Read/Write
BIT NAME OPERATION
F2[7:5] Reserved Always Returns 000, Not Writable
F4[4] Stuck Bus Time-Out Wakeup Fault With CTRLB[4] = 1
[1] = Part Exited Shutdown Mode After Stuck Bus Timer Expired
[0] = No Stuck Bus Time-Out Wakeup Fault Occurred (Default)
F4[3] GPIO1 Input Fault [1] = GPIO1 Input was at Alert Level
[0] = GPIO1 Input was not at Alert Level (Default)
Alert Polarity is set in GIO[3] (Table 18)
F4[2] GPIO2 Input Fault [1] = GPIO2 Input was at Alert Level
[0] = GPIO2 Input was not at Alert Level (Default)
Alert Polarity is set in GIO[2] (Table 18)
F4[1] GPIO3 Input Fault [1] = GPIO3 Input was at Alert Level
[0] = GPIO3 Input was not at Alert Level (Default)
Alert Polarity is set in GIO[1] (Table 18)
F4[0] Reserved Always Returns 0, Not Writable

Table 17. GPIO STATUS Register (0x95) – Read Only

BIT NAME OPERATION
GS[7:4] Reserved Always Returns 0000, Not Writable
GS[3] GPIO1 State [1] = GPIO1 High
[0] = GPIO1 Low
GS[2] GPIO2 State [1] = GPIO2 High
[0] = GPIO2 Low
GS[1] GPIO3 State [1] = GPIO3 High
[0] = GPIO3 Low
GS[0] GPIO4 State [1] = GPIO4 High
[0] = GPIO4 Low

Table 18. GPIO IO CONTROL Register (0x96) – Read/Write

BIT NAME OPERATION
GIO[7] GPIO1 Output [1] = Pulls Low
[0] = Hi-Z (Default)
GIO[6] GPIO2 Output [1] = Pulls Low
[0] = Hi-Z (Default)
GIO[5:4] GPIO3 Configuration [11] = Pulls Low when Any of the ADCs Data Becomes Ready, Resets to High
by Reading ADC STATUS Register 0x32
[10] = 128µs Low Pulse when Any of the ADCs Data Becomes Available
[01] = 16µs Low Pulse when Any of the ADCs Data Becomes Available
[00] = General Purpose Input/Output (Default)
GIO[3] GPIO1 Alert Polarity Configuration [1] = Alert on GPIO1 Input High
[0] = Alert on GPIO1 Input Low (Default)
GIO[2] GPIO2 Alert Polarity Configuration [1] = Alert on GPIO2 Input High
[0] = Alert on GPIO2 Input Low (Default)
GIO[1] GPIO3 Alert Polarity Configuration [1] = Alert on GPIO3 Input High (Default)
[0] = Alert on GPIO3 Input Low
GIO[0] GPIO3 Output [1] = Pulls Low (Default)
[0] = Hi-Z

Rev A

34 For more information [Link]

 LTC2992
APPLICATIONS INFORMATION
Table 19. GPIO4 CONTROL Register (0x97) – Read/Write
BIT NAME OPERATION
GC[7] Alert Generated [1] = Alert Generated
[0] = No Alert Generated
Latched to 1 when an Alert is generated and can be cleared via I2C by writing a 0 to it
or setting CTRLB[7] (Table 6) to 1
GC[6] GPIO4 Output [1] = Pulls Low
[0] = Hi-Z (Default)
GC[5:0] Reserved Always Returns 000000, Not Writable

Table 20. Register Data Format – Read/Write: ADC, Min/Max ADC, Min/Max ADC Threshold, ISUM, Min/Max ISUM, Min/Max ISUM
Threshold
12-Bit Mode:
BIT(7) BIT(6) BIT(5) BIT(4) BIT(3) BIT(2) BIT(1) BIT(0)
MSB Register Data(11) Data(10) Data(9) Data(8) Data(7) Data(6) Data(5) Data(4)
LSB Register Data(3) Data(2) Data(1) Data(0) 0 0 0 0

8-Bit Mode:
BIT(7) BIT(6) BIT(5) BIT(4) BIT(3) BIT(2) BIT(1) BIT(0)
MSB Register Data(7) Data(6) Data(5) Data(4) Data(3) Data(2) Data(1) Data(0)
LSB Register 0 0 0 0 0 0 0 0

Table 21. Register Data Format – Read/Write: Power, Min/Max Power, Min/Max Power Threshold, PSUM, Min/Max PSUM, Min/Max
PSUM Threshold
12-Bit Mode:
BIT(7) BIT(6) BIT(5) BIT(4) BIT(3) BIT(2) BIT(1) BIT(0)
MSB2 Register Data(23) Data(22) Data(21) Data(20) Data(19) Data(18) Data(17) Data(16)
MSB1 Register Data(15) Data(14) Data(13) Data(12) Data(11) Data(10) Data(9) Data(8)
LSB Register Data(7) Data(6) Data(5) Data(4) Data(3) Data(2) Data(1) Data(0)

8-Bit Mode:
BIT(7) BIT(6) BIT(5) BIT(4) BIT(3) BIT(2) BIT(1) BIT(0)
MSB2 Register Data(15) Data(14) Data(13) Data(12) Data(11) Data(10) Data(9) Data(8)
MSB1 Register Data(7) Data(6) Data(5) Data(4) Data(3) Data(2) Data(1) Data(0)
LSB Register 0 0 0 0 0 0 0 0

Rev A

For more information [Link] 35

LTC2992
TYPICAL APPLICATIONS
–48V Redundant Feed with Transient Protection to 200V (1.5kHz I2C Interface)
MBR20200*
Q1, PZTA42
RTN1
RSHUNT1
MBR20200* 9.1k
1W
RTN2 R14
RSHUNT2 100Ω
9.1k R3 R4 R1 R2 3.3V
1W 1k 0.51k 2k 2k

C1
R5 R6 1µF R9 R10 R11 R12 R13
VDD INTVCC 0.51k 0.51k 2k 2k 10k
1M 1M MOCD207M VDD

SCL
GPIO1

GPIO2 SCL
SDAI
LTC2992-1 ADR1 µP

ADR0

R7 R8 MOCD207M
20k 20k SDAO SDA

TEMPERATURE
GPIO3
SENSOR ALERT
GPIO4 INT
GND GND

SENSE2– SENSE2+ SENSE1– SENSE1+

2992 TA02

MBR20200*
VIN1
–48V
RSENSE1
MBR20200* 0.01Ω
VIN2 VOUT
–48V 5A
RSENSE2
0.01Ω *APPROPRIATELY SIZED HEAT SINK IS REQUIRED

High Side and Low Side Current Sensing on a Wide Range Supply
RSENSE1
0.01Ω

VDD SENSE1+ SENSE1–

INTVCC
VISHAY C1
NTCS0402E3104*HT 1µF LTC2992
100k AT 25°C ADR0 SDAI
1% I 2C
+ VIN R3 R1 ADR1 SDAO
INTERFACE
7V TO 19.1k 40.2k LOAD
GND SCL
– 100V 1% 1% 5A

GPIO1 GPIO4 ALERT

GPIO2 GPIO3 GP OUTPUT

R4 R2
20k 10k SENSE2– SENSE2+
1% 1%

2992 TA03
RSENSE2
0.01Ω
CODEGPIO
E PE E T(°C) = 41.51 • ( – 0.1233), 20°C < T < 60°C
CODEGPIO2

Rev A

36 For more information [Link]

 LTC2992
TYPICAL APPLICATIONS
Dual 12V High Power Monitor with One Negative Voltage Monitor

RSENSE1 = RESISTOR ARRAY

10 × 5mΩ PARALLEL SENSE RESISTORS
10 × PAIRS OF 1Ω RESISTORS
RSENSE1_1
5mΩ

RSP1_1 RSM1_1
1Ω 1Ω

• • •
RSENSE1_10
5mΩ

RSP1_10 RSM1_10
1Ω 1Ω

RSENSE1
0.5mΩ
VIN1 VOUT1
12V 100A

VNEG
0V TO –60V VDD SENSE1+ SENSE1–

R1 SDAI
640k I2C
1% SDAO
INTERFACE
GPIO1 LTC2992 SCL
R2
GPIO2
17.8k
GPIO4 ALERT
1%
GPIO3 DATAREADY
INTVCC GND ADR0 ADR1 SENSE2+ SENSE2–
C1
1µF

VIN2 VOUT2
12V 100A
RSENSE2
4mV/K VCC 0.5mΩ
VPTAT D+
C2 MEASURES BOARD
LTC2997
470pF TEMPERATURE
1.8V
VREF D–
GND MMBT3904

TEMPERATURE T(°C) = CODEGPIO2/8 – 273.15

VNEG(V) = 36.955 × CODEGPIO1 × GPIO LSB STEP SIZE – 64.7191, –60V < VNEG < 0V 2992 TA04

Rev A

For more information [Link] 37

LTC2992
TYPICAL APPLICATIONS
Power Monitor for 48V, 500W Electric Bike/Scooter

RSENSE2
10A
0.005Ω
DC BRUSHLESS MOTOR
RSENSE1
200mA
0.2Ω
+ 3.3V
48V
– SENSE1+ SENSE1– SENSE2+ SENSE2– R3 R4 R5 R6 VDD
330k 10k 10k 10k
VDD SDAI SDA

SDAO MCU
LTC2992 SCL SCL
ALERT
GPIO4 INT
HEADLIGHT 2992 TA05
GPIO3
RELAY CONTROL
GPIO2 INTVCC GND ADR0 ADR1 GPIO1

C1, 1µF
4mV/K GND

VCC VPTAT D+
R2 C2 MEASURE BOARD
LTC2997
10k 470pF TEMPERATURE
GND D–
MMBT3904
GP OUTPUT

PIN NOT USED IN LTC2997 CIRCUIT: VREF

TEMPERATURE T(°C) = CODEGPI01/8 – 273.15

Rev A

38 For more information [Link]

 LTC2992
TYPICAL APPLICATIONS
Four Quadrant Power Monitor (10kHz I2C Interface)

+ 3.3V
SEPARATE Q1
5V SUPPLY PZTA42
–
R10 R11 R12 R13 R14
VDD R8 R9 0.47k 0.47k 2k 2k 10k
MOCD207M VDD
4.7k 4.7k
R1
1M SCL
R16
100k
GPIO1 SCL
SDAI
R3 µP
Q4*
20k
MMBT2222L
LTC2992-1 R6 R7
ORGND NC 33k 0.82k
(GND PIN MOCD207M
OF LTC2992-1) NC SDAO SDA
Q5*
R2 MMBT2222L
20k
R17 ALERT
GPIO4 INT
100k
GPIO2 ADR1 GND

ADR0

R4 INTVCC
1M C1
1µF ORGND
GND

TEMPERATURE
SENSOR GPIO3 VSS VZ VDD SA
SB
C2 C3
1nF LTC4371 1nF
Q2 Q3
GB GA
BSP297 R15, 10k BSP297
– +
SENSE1 SENSE2 SENSE2– SENSE1+ DB DA

VIN
VOUT PIN NOT USED IN LTC4371 CIRCUIT: FAULTB
–95V TO
RSENSE 5A
100V NC: NO CONNECT
0.01Ω

*MAX EMITTER-BASE BREAKDOWN VOLTAGE OF Q4, Q5 SHOULD BE LESS THAN 7V

|VIN| – |VRSENSE|–|VDS,Q2| 1
CODEGPIO1 = ×
51 GPIO LSB STEP SIZE 2992 TA06

|VIN| – |VDS,Q3| 1
CODEGPIO2 = ×
51 GPIO LSB STEP SIZE

IF CODEGPIO1 > CODEGPIO2, MEASURED VIN = –[CODEGPIO1 × GPIO LSB STEP SIZE × 51]
IF CODEGPIO1 < CODEGPIO2, MEASURED VIN = CODEGPIO2 × GPIO LSB STEP SIZE × 51
VDS,Q2, VDS,Q3 ARE DRAIN TO SOURCE VOLTAGE OF Q2 AND Q3
VRSENSE IS VOLTAGE ACROSS RSENSE

Rev A

For more information [Link] 39

LTC2992
TYPICAL APPLICATIONS
Power Efficiency Meter

SDAI SENSE2–
I2C
SDAO SENSE2+
INTERFACE
SCL INTVCC
CA
LTC2992
0.1µF
ADR1

ADR0
RPU1 RPU4
GND 100k 100k

VDD

SENSE1+ GPIO1

SENSE1– GPIO4 ALERT

GPIO2 GPIO3

VIN
14V TO 100V RSENSE1 + CINA
CINB
10mΩ 0.47µF RUN
100µF MTOP
×4 VIN TG
×2
MODE BOOST
CB RSENSE2
ILIM 0.1µF L1, 33µH 6mΩ VOUT
RPU2 RPU3 SW 12V
LTC3895 5A
100k 100k
BG MBOT +
INTVCC COUTB COUTA
22µF 150µF
CINTVCC CRUMP_EN ×2
0.1µF SENSE+
CSS CSNS
0.1µF 1nF
SS SENSE–

EXTVCC
NDRV RB, 140k
VFB
DRVCC
CDRVCC ITH
4.7µF DRVSET
RDRV FREQ RITH RA
DRVUV 10k 10k
80.6k
GND
OVLO CITHB CEXT
GND 100pF 1µF
RFREQ CITHA
30.1k 4.7nF
GND

GND

2992 TA07
PINS NOT USED IN LTC3895 CIRCUIT:
CLKOUT, PLLIN, PHASMD, PGOOD, VPRG

MTOP, MBOT: BSC520N15NS3G

DEXT: DIODES INC. SMAZ12-13-F
L1: WURTH 7443633300
COUTA: SUNCON 35CE68LX

Rev A

40 For more information [Link]

 LTC2992
TYPICAL APPLICATIONS
Bidirectional 30V to 300V High Side Power Monitor

RSENSE
0.01Ω
VOUT
VIN
5A
3.3V
R11 R1
2k 2k SENSE2– SENSE1+ SENSE1– SENSE2+

C2 R3 R4 R7 R8 R9 R10
Z1* VDD
0.1µF 5k 2k 2k 1k 1k 10k VDD
5.1V

INTVCC SDAI VDD2 VDD1

µP
ADUM1251
NST30010MXV6 C1
SDAO SDA2 SDA1 SDA
0.1µF
LTC2992
GPIO1 SCL SCL2 SCL1 SCL

GPIO2 GND2 GND1

ADR1
R12 R2
374k 5.1k
ADR0
R13 FODM217C
374k INT
GND
ALERT
GPIO4
FAN ON
GND GPIO3
OUTPUT

R11 M1
Q1 100Ω BSP135
2N3904
Q2
MMBT6520L USE GPIO TO MEASURE INPUT VOLTAGE
M3 Q3 SEE TABLE 5
BSP135 2N3904 *DDZ9689, DIODES INC.
R5 R6
10k 10k

2992 TA08

Rev A

For more information [Link] 41

LTC2992
TYPICAL APPLICATIONS

Bipolar Supply Power Monitor (1.5kHz I2C Interface)

RSENSE1
VPOS 0.01Ω
5A
10V TO 20V 3.3V

R4 R5 R6 R7
VDD SENSE1+ SENSE1– R8 R9 R10 R11 R12
15k 3.3k 15k 15k 0.2k 0.2k 2k 2k 10k
MOCD207M VDD
TEMPERATURE
GPIO1 SCL
SENSOR
BAT54*
SCL
SDAI
R1 LTC2992-1 µP
118k
GPIO2
R2 MOCD207M
BAT54* 10k SDAO SDA
GND
C1
1µF ALERT
INTVCC GPIO4 INT
R3 ADR1 GND
10k
ADR0

GPIO3
SENSE2– SENSE2+

VNEG
–10V TO –20V 5A
RSENSE2
0.01Ω

*DIODES ENSURE LTC2992-1’S OPERATION WHEN EITHER SUPPLY FAILS OPEN 2992 TA09

Rev A

42 For more information [Link]

 LTC2992
PACKAGE DESCRIPTION
Please refer to [Link] for the most recent package drawings.

DE Package
16-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1732 Rev Ø)

0.70 ±0.05

3.60 ±0.05 3.30 ±0.05

2.20 ±0.05 1.70 ±0.05

PACKAGE
OUTLINE

0.25 ±0.05
0.45 BSC
3.15 REF

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

R = 0.115 0.40 ±0.10

4.00 ±0.10
TYP
(2 SIDES)
9 16
R = 0.05
TYP

3.30 ±0.10
3.00 ±0.10
(2 SIDES) 1.70 ±0.10 PIN 1 NOTCH
PIN 1 R = 0.20 OR
TOP MARK 0.35 × 45°
(SEE NOTE 6) CHAMFER
(DE16) DFN 0806 REV Ø

8 1
0.200 REF 0.75 ±0.05 0.23 ±0.05
0.45 BSC
3.15 REF
0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

Rev A

For more information [Link] 43

LTC2992
PACKAGE DESCRIPTION
Please refer to [Link] for the most recent package drawings.

MS Package
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev A)

0.889 0.127
(.035 .005)

5.10
(.201) 3.20 – 3.45
MIN (.126 – .136)

4.039 0.102
0.305 0.038 0.50 (.159 .004)
(.0120 .0015) (.0197) (NOTE 3) 0.280 0.076
TYP BSC
16151413121110 9 (.011 .003)
RECOMMENDED SOLDER PAD LAYOUT REF

DETAIL “A” 3.00 0.102

0.254 4.90 0.152
(.118 .004)
(.010) (.193 .006)
0 – 6 TYP (NOTE 4)

GAUGE PLANE

0.53 0.152
1234567 8
(.021 .006) 1.10 0.86
(.043) (.034)
DETAIL “A” REF
MAX
0.18
(.007)
SEATING
PLANE 0.17 – 0.27 0.1016 0.0508
(.007 – .011) (.004 .002)
TYP 0.50
NOTE: (.0197)
MSOP (MS16) 0213 REV A

1. DIMENSIONS IN MILLIMETER/(INCH) BSC

2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

Rev A

44 For more information [Link]

 LTC2992
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 04/18 Corrected DATA Pointers in Figure 7 19

Rev A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For more by
is granted information [Link]
implication or otherwise under any patent or patent rights of Analog Devices. 45
LTC2992
TYPICAL APPLICATION
Bidirectional Wide Range Power Monitor

RSENSE
VIN 0.01Ω
VOUT
3V TO 100V

SENSE2– SENSE1+ SENSE1– SENSE2+

VDD SDAI
BOARD I2C
GPIO1 SDAO
TEMPERATURE LTC2992 INTERFACE
SCL
µP
GPIO2
TEMPERATURE GPIO4 ALERT

GPIO3 DATAREADY
INTVCC GND ADR0 ADR1
2992 TA10

0.1μF

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Rev A

46
D16849-0-4/18(A)
[Link]
For more information [Link]  ANALOG DEVICES, INC. 2017-2018