Chapter 7

Shift Registers
 Applications of Flip Flop

•Registers: (data storage and data movement)

•Shift Registers
•Counters (Ring, Twisted Ring, ripple, Up/ Down, Synchronous)
•Sequence generator

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 Register
• A register is a digital electronic device capable of storing
several bits of data
– Normally made from D-type flip-flops with asynchronous
RESET inputs
– Operates on the bits of the data word in parallel (parallel in /
parallel out)
• Operation
– Data on each data input is stored in the flip-flop on the rising
edge of CLOCK
– The data can be read from the Q outputs
– New data can be reloaded by re-CLOCKing the register
– The register can be cleared (zeroed) by asserting the CLEAR
inputs
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 Shift Register
• A shift register is a sequential logic device made up of
flip-flops that allows parallel or serial loading and
serial or parallel outputs as well as shifting bit by bit.

•Common tasks of shift registers:

– Serial/parallel data conversion
– Time delay
– Ring counter
– Twisted-ring counter or Johnson counter
– Memory device

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 Flip Flop as Storing Element

0 0
1 1

1
0

Clock Pulse Clock Pulse

a) 1 is stored b) 0 is stored

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Data Movement in Shift Register
 Types of Shift Register

1. Serial In Serial Out (SISO)

2. Serial In Parallel Out (SIPO)

3. Parallel In serial Out (PISO)

4. Parallel In Parallel Out (PIPO)

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 Serial-in Serial-out (SISO) shift register
•The shift register, which allows serial input (one bit after the other through a
single data line) and produces a serial output is known as Serial-In Serial-Out
shift register
•Two modes of shifting in SISO one is right shift and another is left shift.
•To delay the digital signal.
•Delay = 1/f X No. of flip-flops

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Example: Design of a 3 bit serial in Serial out shift register

I/P Present state Next state Exit State O/P

I1 At Bt Ct At+1 Bt+1 Ct+1 DA DB DC
0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 0 1
0 0 1 0 0 0 1 0 0 1 0
0 0 1 1 0 0 1 0 0 1 1
0 1 0 0 0 1 0 0 1 0 0
0 1 0 1 0 1 0 0 1 0 1
0 1 1 0 0 1 1 0 1 1 0
0 1 1 1 0 1 1 0 1 1 1
1 0 0 0 1 0 0 1 0 0 0
1 0 0 1 1 0 0 1 0 0 1
1 0 1 0 1 0 1 1 0 1 0
1 0 1 1 1 0 1 1 0 1 1
1 1 0 0 1 1 0 1 1 0 0
1 1 0 1 1 1 0 1 1 0 1
1 1 1 0 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1 1
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K-Map Simplification

0 0 0 0 0 0 0 0

0 0 0 0 1 1 1 1

1 1 1 1 1 1 1 1
1 1 1 1 0 0 0 0

DA = I1 DB = At

ab ab
cd 00 01 11 10 00 01 11 10
cd
00 0 1 1 0
0 00 0 1 1
01
0 0 1 1 01 O/P = Ct
0 1 1 0
11 0 0 1 1 Dc = Bt 11
0 1 1 0
10 0 0 1 1 10 1
0 1 0
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 Serial Output
DA A DB B Dc C

3 Bit Serial In Serial Out Shift Register

Note: For the Serial in Serial Out (Left shift) data input is applied at 3rd flip flop
i.e C flip-flop and out put is taken at A flip flop.

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4 bit serial-in serial-out shift register (Shift Right)

Serial
Clock Pulse
Q ( FF0) Q( FF1) Q( FF2) Q( FF3) Output at
No
FF3
0 0 0 0 0 0
1 1 0 0 0 0
2 0 1 0 0 0
3 0 0 1 0 0
4 0 0 0 1 1
5 0 0 0 0 0

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Serial-in Parallel-out (SIPO) shift register
• The register is loaded with serial data, one bit at a time, with the stored data
being available at the output in parallel form.

• The shift register, which allows serial input (one bit after the other through a
single data line) and produces a parallel output is known as Serial-In Parallel-Out
shift register.

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Example: Design of a 3 bit serial in parallel out shift register

I/P Present state Next state Exit State

I1 At Bt Ct At+1 Bt+1 Ct+1 DA DB DC
0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 0
0 0 1 0 0 0 1 0 0 1
0 0 1 1 0 0 1 0 0 1
0 1 0 0 0 1 0 0 1 0
0 1 0 1 0 1 0 0 1 0
0 1 1 0 0 1 1 0 1 1
0 1 1 1 0 1 1 0 1 1
1 0 0 0 1 0 0 1 0 0
1 0 0 1 1 0 0 1 0 0
1 0 1 0 1 0 1 1 0 1
1 0 1 1 1 0 1 1 0 1
1 1 0 0 1 1 0 1 1 0
1 1 0 1 1 1 0 1 1 0
1 1 1 0 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
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K-Map Simplification

0 0 0 0 0 0 0 0

0 0 0 0 1 1 1 1

1 1 1 1 1 1 1 1
1 1 1 1 0 0 0 0

DA = I1 DB = At

ab
cd 00 01 11 10

00 0 1 1
0
01
0 0 1 1
11 0 0 1 1 Dc = Bt

10 0 0 1 1
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 A B C

DA A DB B Dc C

3 Bit Serial In Parallel Out Shift Register

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 4 bit Serial-in Parallel-out shift register

Clock
QA QB QC QD
Pulse No
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 0 0 0 0
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 Parallel-in Serial out (PISO)shift register
• The parallel-in or serial-in modes are controlled by one more input called a
SHIFT/LOAD input.

• When the SHIFT/LOAD input is held in the logic HIGH state, the circuit behaves
like a serial-in serial-out shift register.

• When the SHIFT/LOAD input is held in the logic LOW state, parallel data input are
loaded in parallel to all flip flops.

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 4 bit Parallel –in Serial -out shift register

• When SHIFT/LOAD = 1 , the circuit is in shifting mode

D0= B0 , D1= Q0, D2=Q1, D3= Q2 and serial output is taken at Q3

• When SHIFT/LOAD = 0 , the circuit is in parallel loading mode

D0= B0 , D1= B1, D2=B1, D3= B2
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 Parallel-in Parallel out (PIPO) shift register
• The shift register, which allows parallel input (data is given separately to each flip
flop and in a simultaneous manner) and also produces a parallel output is known
as Parallel-In parallel-Out shift register.

• The parallel data is loaded simultaneously into the register, and transferred
together to their respective outputs by the same clock pulse.

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Example: Design of a 2 bit parallel in parallel out shift register

Present
I/P Next state Exit State O/P
state
I1 I2 At Bt At+1 Bt+1 DA DB O1 O2
0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 1
0 0 1 0 0 0 0 0 1 0
0 0 1 1 0 0 0 0 1 1
0 1 0 0 0 1 0 1 0 0
0 1 0 1 0 1 0 1 0 1
0 1 1 0 0 1 0 1 1 0
0 1 1 1 0 1 0 1 1 1
1 0 0 0 1 0 1 0 0 0
1 0 0 1 1 0 1 0 0 1
1 0 1 0 1 0 1 0 1 0
1 0 1 1 1 0 1 0 1 1
1 1 0 0 1 1 1 1 0 0
1 1 0 1 1 1 1 1 0 1
1 1 1 0 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1
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K-Map Simplification

0 0 0 0 0 0 0 0

0 0 0 0 1 1 1 1

1 1 1 1 1 1 1 1
1 1 1 1 0 0 0 0

DA = I1 DB = I2

ab ab
cd 00 01 11 10 00 01 11 10
cd
00 0 1 1 0
0 00 0 1 1
01
0 0 1 1 01 O2 = Bt
0 1 1 0
11 0 0 1 1 O1 = At 11
0 1 1 0
10 0 0 1 1 10 1
0 1 0
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2 Bit Parallel In Parallel Out Shift Register

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4 bit Parallel -in, Parallel -out shift register

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 Bidirectional Shift Registers
Data can be shifted either left or right, using a control
line RIGHT/LEFT (or simply RIGHT) to indicate the
direction.
RIGHT/LEFT

Serial
data in

RIGHT.Q0 + D Q D Q Q1 D Q Q2 D Q Q3
RIGHT'.Q2 C C C C

Q0
CLK

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Exercise for practice:

Design of a 2 bit SISO shift register which shifts

from left to right if mode is 1 and right to left if
mode is 0

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 Shift Register as Counter
 A shift register counter is basically a shift register with the
serial output connected back to the serial input to produce
special sequences.
 Two of the most common types of shift register counters, the
Johnson counter and the ring counter

Ring Counter
A ring counter is obtained from a shift register by directly
feeding back the true output of the output flip-flop to the
data input terminal of the input flip-flop

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 Four Bit Four State Ring Counter
• Initially FF A output is set to 1 and rest 3 FF outputs are cleared.

QA QB QC QD

State Name QA QB QC QD
S1 0 0 0 0

S2 1 0 0 0

S3 0 1 0 0

S4 0 0 1 0
S5 0 0 0 1
S6 1 0 0 0
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Johnson counter / Twisted Ring counter
• The Johnson counter is similar to the Ring counter.
• The only difference between the Johnson counter and
the ring counter is that the inverted outcome Q' of the
last flip flop is passed to the first flip flop as an input.
• The remaining work of the Johnson counter is the same
as a ring counter.
• The Johnson counter is also referred to as the Creeping
counter.
• Number of unique sates are 2 time the number of
bits(flip flops)
• For 4 bits there 4*2 = 8 unique states

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 Twisted Ring counter/ Johnson counter

State
Q1 Q2 Q3 Q4
Name
0 0 0 0 0
8 unique
1 1 0 0 0
Sates
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1 30
Exercise: Design of 4 bit Johnsons Counter
Present state Next state Exit State
At Bt Ct Et At+1 Bt+1 Ct+1 Et+1 DA DB Dc DE
0 0 0 0 1 0 0 0 1 0 0 0
0 0 0 1 0 0 0 0 0 0 0 0
0 0 1 0 X X X X X X X X
0 0 1 1 0 0 0 1 0 0 0 1
0 1 0 0 X X X X X X X X
0 1 0 1 X X X X X X X X
0 1 1 0 X X X X X X X X
0 1 1 1 0 0 1 1 0 0 1 1
1 0 0 0 1 1 0 0 1 1 0 0
1 0 0 1 X X X X X X X X
1 0 1 0 X X X X X X X X
1 0 1 1 X X X X X X X X
1 1 0 0 1 1 1 0 1 1 1 0
1 1 0 1 X X X X X X X X
1 1 1 0 1 1 1 1 1 1 1 1
1 1 1 1 0 1 0 0 0 1 1 1
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K-Map Simplification

1 0 0 X 0 0 0 X

X X 0 X X X 0 X

1 X 0 1 1 X 1 1

1 X 1 X X X
X X

DA = E DB = A

0 0 1 X
0 0 0 X
X X 1 X
X X 1 X
0 X 1 1
Dc = B
1 X 1 1 0 X
X X
0 X X X
DE = C
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4 bit Johnsons Counter

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 Practice Exercises

1. On the fifth clock pulse, a 4-bit Johnson sequence is

Q0 = 0, Q1 = 1, Q2 = 1, and Q3 = 1. On the sixth clock
pulse what will be the sequence ?
2. A bidirectional 4-bit shift register is storing the nibble
1101. Its right/ left input is HIGH. The nibble 1011 is
waiting to be entered on the serial data-input line. After
three clock pulses, the shift register is storing.
3. In a 6-bit Johnson counter sequence there are a total of
how many states, or bit patterns?
4. The bit sequence 10011100 is serially entered (right-
most bit first) into an 8-bit parallel out shift register that
is initially clear. What are the Q outputs after four clock
pulses?
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Thank You !!

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