RFM73 V2.

0
Low Power High Performance 2.4 GHz GFSK Transceiver
Features

 2400-2483.5 MHz ISM band operation  VDD  VSS IREF

 Support 250Kbps, 1Mbps and 2 Mbps air RFP
data rate
 Programmable output power 11
VDDPA
 Low power consumption
 Tolerate +/- 60ppm 16 MHz crystal
 Variable payload length from 1 to32bytes
 Automatic packet processing
 6 data pipes for 1:6 star networks
 1.9V to 3.6V power supply
 4-pin SPI interface with maximum 8MHz
clock rate
 Compact 20-pin 4x4mm QFN package
6 7 8 9 10

IRQ VDD VSS XTALP XTALN

Applications

 Wireless PC peripherals  Remote controls

 Wireless mice and  Consumer electronics
keyboards  Home automation
 Wireless gamepads  Toys
 Wireless audio  Personal health and entertainment
 VOIP and wireless headsets

Block Diagram
Interface
SPI

RFP Rx FIFO CSN

FM
RFN Data Slicer SCK
Demodulator
MOSI
MISO
Integrated Packet
Power
TDD RF Processing & IRQ
Management CE
Transceiver State Control
Register
banks

Gaussian
FM Modulator
shaping
Tx FIFO

Page 1 of 26
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

Table of Contents

1 General Description ................................................................................................................. 3

2 Abbreviations .......................................................................................................................... 4
3 Pin Information ....................................................................................................................... 5
4 State Control ........................................................................................................................... 6
4.1 State Control Diagram ............................................................................................................... 6
4.2 Power Down Mode.................................................................................................................... 7
4.3 Standby-I Mode ......................................................................................................................... 7
4.4 Standby-II Mode........................................................................................................................ 7
4.5 TX Mode ................................................................................................................................... 7
4.6 RX Mode ................................................................................................................................... 8
5 Packet Processing .................................................................................................................... 8
5.1 Packet Format ............................................................................................................................ 8
5.1.1 Preamble........................................................................................................................... 9
5.1.2 Address............................................................................................................................. 9
5.1.3 Packet Control .................................................................................................................. 9
5.1.4 Payload ........................................................................................................................... 10
5.1.5 CRC ................................................................................................................................ 10
5.2 Packet Handling ...................................................................................................................... 10
6 Data and Control Interface .................................................................................................... 11
6.1 TX/RX FIFO ........................................................................................................................... 11
6.2 Interrupt ................................................................................................................................... 11
6.3 SPI Interface ............................................................................................................................ 12
6.3.1 SPI Command ................................................................................................................ 12
6.3.2 SPI Timing ..................................................................................................................... 13
7 Register Map ......................................................................................................................... 15
7.1 Register Bank 0 ....................................................................................................................... 15
7.2 Register Bank 1 ....................................................................................................................... 21
8 Electrical Specifications ......................................................................................................... 22
9 Typical Application Schematic............................................................................................... 23
10 Package Information.............................................................................................................. 24
11 Order Information ................................................................................................................. 26
12 Solder Information……………………………………………………………………………………..26
13 Contact Information ............................................................................................................... 27

Page 2 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

1 General Description
RFM73 is a GFSK transceiver operating in resolution of the RF channel frequency is
the world wide ISM frequency band at 2400- 1MHz.
2483.5 MHz. Burst mode transmission and up
to 2Mbps air data rate make them suitable for A transmitter and a receiver must be
applications requiring ultra low power programmed with the same RF channel
consumption. The embedded packet frequency to be able to communicate with
processing engines enable their full operation each other.
with a very simple MCU as a radio system.
Auto re-transmission and auto acknowledge The output power of RFM73 is set by the
give reliable link without any MCU RF_PWR bits in the RF_SETUP register.
interference.
Demodulation is done with embedded data
RFM73 operates in TDD mode, either as a slicer and bit recovery logic. The air data rate
transmitter or as a receiver. can be programmed to 250Kbps, 1Mbps or
2Mbps by RF_DR_HIGH and RF_DR_LOW
The RF channel frequency determines the register. A transmitter and a receiver must be
center of the channel used by RFM73. The programmed with the same setting.
frequency is set by the RF_CH register in
register bank 0 according to the following In the following chapters, all registers are in
formula: F0= 2400 + RF_CH (MHz). The register bank 0 except with explicit claim.

Interface
SPI

RFP Rx FIFO CSN

FM
RFN Data Slicer SCK
Demodulator
MOSI
MISO
Integrated Packet
Power
TDD RF Processing & IRQ
Management CE
Transceiver State Control
Register
banks

Gaussian
FM Modulator
shaping
Tx FIFO

Figure 1 RFM73 Chip Block Diagram

Page 3 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

2 Abbreviations
ACK Acknowledgement
ARC Auto Retransmission Count
ARD Auto Retransmission Delay
CD Carrier Detection
CE Chip Enable
CRC Cyclic Redundancy Check
CSN Chip Select Not
DPL Dynamic Payload Length
FIFO First-In-First-Out
GFSK Gaussian Frequency Shift Keying
GHz Gigahertz
LNA Low Noise Amplifier
IRQ Interrupt Request
ISM Industrial-Scientific-Medical
LSB Least Significant Bit
MAX_RT Maximum Retransmit
Mbps Megabit per second
MCU Microcontroller Unit
MHz Megahertz
MISO Master In Slave Out
MOSI Master Out Slave In
MSB Most Significant Bit
PA Power Amplifier
PID Packet Identity Bits
PLD Payload
PRX Primary RX
PTX Primary TX
PWD_DWN Power Down
PWD_UP Power Up
RF_CH Radio Frequency Channel
RSSI Received Signal Strength Indicator
RX Receive
RX_DR Receive Data Ready
SCK SPI Clock
SPI Serial Peripheral Interface
TDD Time Division Duplex
TX Transmit
TX_DS Transmit Data Sent
XTAL Crystal

Page 4 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

3 Pin Information

Figure 2 RFM73 pin assignments (top view)

Table1 RFM73 pin functions

Page 5 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

4 State Control
4.1 State Control Diagram

 Pin signal: VDD, CE RFM73 has built-in state machines that

 SPI register: PWR_UP, PRIM_RX, control the state transition between different
EN_AA, NO_ACK, ARC, ARD modes.
 System information: Time out, ACK
received, ARD elapsed, ARC_CNT, TX When auto acknowledge feature is disabled,
FIFO empty, ACK packet transmitted, state transition will be fully controlled by
Packet received MCU.

Power Down

PWR_UP=1
PWR_UP=0
Start up time 1.5ms

Standby-I
TX FIFO not empty
CE=1 for more than 15us
Time out or ACK received
ARD elapsed and ARC_CNT<ARC
TX setting 130us

TX finished
CE=0
TX FIFO not empty
RX CE=1 TX
TX setting 130us

TX FIFO empty
Standby-II CE=1

EN_AA=1
NO_ACK=0
RX setting 130us

Figure 3 PTX (PRIM_RX=0) state control diagram

Page 6 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

Figure 4 PRX (PRIM_RX=1) state control diagram

4.2 Power Down Mode 4.4 Standby-II Mode

In power down mode RFM73 is in sleep In standby-II mode more clock buffers are
mode with minimal current consumption. SPI active than in standby-I mode and much more
interface is still active in this mode, and all current is used. Standby-II occurs when CE is
register values are available by SPI. Power held high on a PTX device with empty TX
down mode is entered by setting the PWR_UP FIFO. If a new packet is uploaded to the TX
bit in the CONFIG register to low. FIFO in this mode, the device will
automatically enter TX mode and the packet is
transmitted.
4.3 Standby-I Mode

By setting the PWR_UP bit in the CONFIG 4.5 TX Mode

register to 1 and de-asserting CE to 0, the
device enters standby-I mode. Standby-I mode  PTX device (PRIM_RX=0)
is used to minimize average current
consumption while maintaining short start-up The TX mode is an active mode where the
time. In this mode, part of the crystal oscillator PTX device transmits a packet. To enter this
is active. This is also the mode which the mode from power down mode, the PTX device
RFM73 returns to from TX or RX mode when must have the PWR_UP bit set high,
CE is set low. PRIM_RX bit set low, a payload in the TX
FIFO, and a high pulse on the CE for more
than 10µs.

Page 7 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

The PTX device stays in TX mode until it high, PRIM_RX bit set high and the CE pin
finishes transmitting the current packet. If CE set high. Or PRX device can enter this mode
= 0 it returns to standby-I mode. If CE = 1, the from TX mode after transmitting an
next action is determined by the status of the acknowledge packet when EN_AA=1 and
TX FIFO. If the TX FIFO is not empty the NO_ACK=0 in received packet.
PTX device remains in TX mode, transmitting
the next packet. If the TX FIFO is empty the In this mode the receiver demodulates the
PTX device goes into standby-II mode. It is signals from the RF channel, constantly
important to never stay in TX mode for more presenting the demodulated data to the packet
than 4ms at one time. processing engine. The packet processing
engine continuously searches for a valid
If the auto retransmit is enabled (EN_AA=1) packet. If a valid packet is found (by a
and auto acknowledge is required matching address and a valid CRC) the
(NO_ACK=0), the PTX device will enter TX payload of the packet is presented in a vacant
mode from standby-I mode when ARD slot in the RX FIFO. If the RX FIFO is full,
elapsed and number of retried is less than the received packet is discarded.
ARC.
The PRX device remains in RX mode until the
 PRX device (PRIM_RX=1) MCU configures it to standby-I mode or
power down mode.
The PRX device will enter TX mode from RX
mode only when EN_AA=1 and NO_ACK=0 In RX mode a carrier detection (CD) signal is
in received packet to transmit acknowledge available. The CD is set to high when a RF
packet with pending payload in TX FIFO. signal is detected inside the receiving
frequency channel. The internal CD signal is
filtered before presented to CD register. The
4.6 RX Mode RF signal must be present for at least 128 µs
before the CD is set high.
 PRX device (PRIM_RX=1)
 PTX device (PRIM_RX=0)
The RX mode is an active mode where the
RFM73 radio is configured to be a receiver. The PTX device will enter RX mode from TX
To enter this mode from standby-I mode, the mode only when EN_AA=1 and NO_ACK=0
PRX device must have the PWR_UP bit set to receive acknowledge packet.

5 Packet Processing
5.1 Packet Format
The packet format has a preamble, address, packet control, payload and CRC field.

Preamble1byte Address3~5byte Packet Control 9/0bit Payload0~32byte CRC2/1byte

PayloadLength6bit PID2bit NO_ACK1bit

Figure 5 Packet Format

Page 8 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

5.1.1 Preamble No other data pipe can receive data until a

complete packet is received by a data pipe that
The preamble is a bit sequence used to detect 0 has detected its address. When multiple PTX
and 1 levels in the receiver. The preamble is devices are transmitting to a PRX, the ARD
one byte long and is either 01010101 or can be used to skew the auto retransmission so
10101010. If the first bit in the address is 1 the that they only block each other once.
preamble is automatically set to 10101010 and
if the first bit is 0 the preamble is
automatically set to 01010101. This is done to 5.1.3 Packet Control
ensure there are enough transitions in the
preamble to stabilize the receiver. When Dynamic Payload Length function is
enabled, the packet control field contains a 6
bit payload length field, a 2 bit PID (Packet
5.1.2 Address Identity) field and, a 1 bit NO_ACK flag.
 Payload length
This is the address for the receiver. An address The payload length field is only used if the
ensures that the packet is detected by the target Dynamic Payload Length function is enabled.
receiver. The address field can be configured
to be 3, 4, or 5 bytes long by the AW register.  PID
The 2 bit PID field is used to detect whether
The PRX device can open up to six data pipes the received packet is new or retransmitted.
to support up to six PTX devices with unique PID prevents the PRX device from presenting
addresses. All six PTX device addresses are the same payload more than once to the MCU.
searched simultaneously. In PRX side, the data The PID field is incremented at the TX side
pipes are enabled with the bits in the for each new packet received through the SPI.
EN_RXADDR register. By default only data The PID and CRC fields are used by the PRX
pipe 0 and 1 are enabled. device to determine whether a packet is old or
new. When several data packets are lost on the
Each data pipe address is configured in the link, the PID fields may become equal to the
RX_ADDR_PX registers. last received PID. If a packet has the same PID
as the previous packet, RFM73 compares the
Each pipe can have up to 5 bytes configurable CRC sums from both packets. If the CRC
address. Data pipe 0 has a unique 5 byte sums are also equal, the last received packet is
address. Data pipes 1-5 share the 4 most considered a copy of the previously received
significant address bytes. The LSB byte must packet and discarded.
be unique for all 6 pipes.
 NO_ACK
To ensure that the ACK packet from the PRX The NO_ACK flag is only used when the auto
is transmitted to the correct PTX, the PRX acknowledgement feature is used. Setting the
takes the data pipe address where it received flag high, tells the receiver that the packet is
the packet and uses it as the TX address when not to be auto acknowledged.
transmitting the ACK packet.
The PTX can set the NO_ACK flag bit in the
On the PRX, the RX_ADDR_Pn, defined as Packet Control Field with the command:
the pipe address, must be unique. On the PTX W_TX_PAYLOAD_NOACK. However, the
the TX_ADDR must be the same as the function must first be enabled in the
RX_ADDR_P0 on the PTX, and as the pipe FEATURE register by setting the
address for the designated pipe on the PRX.

Page 9 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

EN_DYN_ACK bit. When you use this option, 5.1.5 CRC

the PTX goes directly to standby-I mode after
transmitting the packet and the PRX does not The CRC is the error detection mechanism in
transmit an ACK packet when it receives the the packet. The number of bytes in the CRC is
packet. set by the CRCO bit in the CONFIG register.
It may be either 1 or 2 bytes and is calculated
5.1.4 Payload over the address, Packet Control Field, and
Payload.
The payload is the user defined content of the
8 2
packet. It can be 0 to 32 bytes wide, and it is The polynomial for 1 byte CRC is X + X +
transmitted on-air as it is uploaded X + 1. Initial value is 0xFF.
16 12
(unmodified) to the device. The polynomial for 2 byte CRC is X + X +
5
X + 1. Initial value is 0xFFFF.
The RFM73 provides two alternatives for
handling payload lengths, static and dynamic No packet is accepted by receiver side if the
payload length. The static payload length of CRC fails.
each of six data pipes can be individually set.

The default alternative is static payload length. 5.2 Packet Handling

With static payload length all packets between
a transmitter and a receiver have the same RFM73 uses burst mode for payload
length. Static payload length is set by the transmission and receive.
RX_PW_Px registers. The payload length on
the transmitter side is set by the number of The transmitter fetches payload from TX FIFO,
bytes clocked into the TX_FIFO and must automatically assembles it into packet and
equal the value in the RX_PW_Px register on transmits the packet in a very short burst
the receiver side. Each pipe has its own period with 1Mbps or 2Mbps air data rate.
payload length.
After transmission, if the PTX packet has the
Dynamic Payload Length (DPL) is an NO_ACK flag set, RFM73 sets TX_DS and
alternative to static payload length. DPL gives an active low interrupt IRQ to MCU. If
enables the transmitter to send packets with the PTX is ACK packet, the PTX needs
variable payload length to the receiver. This receive ACK from the PRX and then asserts
means for a system with different payload the TX_DS IRQ.
lengths it is not necessary to scale the packet
length to the longest payload. The receiver automatically validates and
disassembles received packet, if there is a
With DPL feature the RFM73 can decode the valid packet within the new payload, it will
payload length of the received packet write the payload into RX FIFO, set RX_DR
automatically instead of using the RX_PW_Px and give an active low interrupt IRQ to MCU.
registers. The MCU can read the length of the
received payload by using the command: When auto acknowledge is enabled
R_RX_PL_WID. (EN_AA=1), the PTX device will
automatically wait for acknowledge packet
In order to enable DPL the EN_DPL bit in the after transmission, and re-transmit original
FEATURE register must be set. In RX mode packet with the delay of ARD until an
the DYNPD register has to be set. A PTX that acknowledge packet is received or the number
transmits to a PRX with DPL enabled must of re-transmission exceeds a threshold ARC. If
have the DPL_P0 bit in DYNPD set. the later one happens, RFM73 will set
MAX_RT and give an active low interrupt

Page 10 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

IRQ to MCU. Two packet loss counters accessible through the SPI by using dedicated
(ARC_CNT and PLOS_CNT) are incremented SPI commands. A TX FIFO in PRX can store
each time a packet is lost. The ARC_CNT payload for ACK packets to three different
counts the number of retransmissions for the PTX devices. If the TX FIFO contains more
current transaction. The PLOS_CNT counts than one payload to a pipe, payloads are
the total number of retransmissions since the handled using the first in first out principle.
last channel change. ARC_CNT is reset by The TX FIFO in a PRX is blocked if all
initiating a new transaction. PLOS_CNT is pending payloads are addressed to pipes where
reset by writing to the RF_CH register. It is the link to the PTX is lost. In this case, the
possible to use the information in the MCU can flush the TX FIFO by using the
OBSERVE_TX register to make an overall FLUSH_TX command.
assessment of the channel quality.
The RX FIFO in PRX may contain payload
The PTX device will retransmit if its RX FIFO from up to three different PTX devices.
is full but received ACK frame has payload. .
A TX FIFO in PTX can have up to three
As an alternative for PTX device to auto payloads stored.
retransmit it is possible to manually set the
RFM73 to retransmit a packet a number of The TX FIFO can be written to by three
times. This is done by the REUSE_TX_PL commands, W_TX_PAYLOAD and
command. W_TX_PAYLOAD_NO_ACK in PTX mode
and W_ACK_PAYLOAD in PRX mode. All
When auto acknowledge is enabled, the PRX three commands give access to the TX_PLD
device will automatically check the NO_ACK register.
field in received packet, and if NO_ACK=0, it
will automatically send an acknowledge The RX FIFO can be read by the command
packet to PTX device. If EN_ACK_PAY is set, R_RX_PAYLOAD in both PTX and PRX
and the acknowledge packet can also include mode. This command gives access to the
pending payload in TX FIFO. RX_PLD register.

The payload in TX FIFO in a PTX is NOT

removed if the MAX_RT IRQ is asserted.
6 Data and Control Interface
In the FIFO_STATUS register it is possible to
6.1 TX/RX FIFO read if the TX and RX FIFO are full or empty.
The TX_REUSE bit is also available in the
The data FIFOs are used to store payload that FIFO_STATUS register. TX_REUSE is set by
is to be transmitted (TX FIFO) or payload that the SPI command REUSE_TX_PL, and is
is received and ready to be clocked out (RX reset by the SPI command:
FIFO). The FIFO is accessible in both PTX W_TX_PAYLOAD or FLUSH TX.
mode and PRX mode.
6.2 Interrupt
There are three levels 32 bytes FIFO for both
TX and RX, supporting both acknowledge
In RFM73 there is an active low interrupt
mode or no acknowledge mode with up to six
(IRQ) pin, which is activated when TX_DS
pipes.
IRQ, RX_DR IRQ or MAX_RT IRQ are set
 TX three levels, 32 byte FIFO high by the state machine in the STATUS
 RX three levels, 32 byte FIFO register. The IRQ pin resets when MCU writes
'1' to the IRQ source bit in the STATUS
Both FIFOs have a controller and are register. The IRQ mask in the CONFIG

Page 11 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

register is used to select the IRQ sources that to low transition on CSN.
are allowed to assert the IRQ pin. By setting
one of the MASK bits high, the corresponding In parallel to the SPI command word applied
IRQ source is disabled. By default all IRQ on the MOSI pin, the STATUS register is
sources are enabled. shifted serially out on the MISO pin.

The 3 bit pipe information in the STATUS The serial shifting SPI commands is in the
register is updated during the IRQ pin high to following format:
low transition. If the STATUS register is read
during an IRQ pin high to low transition, the  <Command word: MSB bit to LSB bit
pipe information is unreliable. (one byte)>
 <Data bytes: LSB byte to MSB byte,
MSB bit in each byte first> for all
registers at bank 0 and register 9 to
6.3 SPI Interface register 14 at bank 1
 <Data bytes: MSB byte to LSB byte,
6.3.1 SPI Command
MSB bit in each byte first> for register 0
to register 8 at bank 1
The SPI commands are shown in Table 2.
Every new command must be started by a high

Command
# Data
Command name word Operation
bytes
(binary)
1 to 5 Read command and status registers. AAAAA =
R_REGISTER 000A AAAA 5 bit Register Map Address
LSB byte first
Write command and status registers. AAAAA = 5
1 to 5
W_REGISTER 001A AAAA bit Register Map Address
LSB byte first
Executable in power down or standby modes only.
Read RX-payload: 1 – 32 bytes. A read operation
1 to 32 always starts at byte 0. Payload is deleted from FIFO
R_RX_PAYLOAD 0110 0001
LSB byte first after it is read. Used in RX mode.

1 to 32 Write TX-payload: 1 – 32 bytes. A write operation

W_TX_PAYLOAD 1010 0000 always starts at byte 0 used in TX payload.
LSB byte first
FLUSH_TX 1110 0001 0 Flush TX FIFO, used in TX mode
Flush RX FIFO, used in RX mode
Should not be executed during transmission of
FLUSH_RX 1110 0010 0
acknowledge, that is, acknowledge package will not
be completed.
Used for a PTX device
Reuse last transmitted payload. Packets are repeatedly
retransmitted as long as CE is high.
TX payload reuse is active until
REUSE_TX_PL 1110 0011 0
W_TX_PAYLOAD or FLUSH TX is executed. TX
payload reuse must not be activated or deactivated
during package transmission

Page 12 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

This write command followed by data 0x73 activates

the following features:
• R_RX_PL_WID
• W_ACK_PAYLOAD
• W_TX_PAYLOAD_NOACK

A new ACTIVATE command with the same data

deactivates them again. This is executable in power
down or stand by modes only.

The R_RX_PL_WID, W_ACK_PAYLOAD, and

ACTIVATE 0101 0000 1
W_TX_PAYLOAD_NOACK features registers are
initially in a deactivated state; a write has no effect, a
read only results in zeros on MISO. To activate these
registers, use the ACTIVATE command followed by
data 0x73. Then they can be accessed as any other
register. Use the same command and data to
deactivate the registers again.

This write command followed by data 0x53 toggles

the register bank, and the current register bank
number can be read out from REG7 [7]
Read RX-payload width for the top
R_RX_PL_WID 0110 0000 R_RX_PAYLOAD in the RX FIFO.
Used in RX mode.
Write Payload to be transmitted together with ACK
packet on PIPE PPP. (PPP valid in the range from 000
1 to 32 to 101). Maximum three ACK packet payloads can be
W_ACK_PAYLOAD 1010 1PPP pending. Payloads with same PPP are handled using
LSB byte first
first in - first out principle. Write payload: 1– 32
bytes. A write operation always starts at byte 0.

W_TX_PAYLOAD_NO 1 to 32 Used in TX mode. Disables AUTOACK on this

1011 0000 specific packet.
ACK LSB byte first
No Operation. Might be used to read the STATUS
NOP 1111 1111 0 register
Table 2 SPI command

6.3.2 SPI Timing

SC K

CS N

W r i t e t o S P I r e g i s t e r:
MOSI x C7 C6 C5 C4 C3 C2 C1 C0 x D7 D6 D5 D4 D3 D2 D1 D0 x

MISO HI-Z S7 S6 S5 S4 S3 S2 S1 S0 0 0 0 0 0 0 0 0 Hi-Z

R e a d f r o m S P I r e g i s t e r:
x C7 C6 C5 C4 C3 C2 C1 C0 x
MOSI
x S7 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0 x
MISO

Figure 6 SPI timing

Page 13 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

Cn: SPI command bit

Sn: STATUS register bit
Dn: Data Bit (LSB byte to MSB byte, MSB bit in each byte first)

Note: The SPI timing is for bank 0 and register 9 to 14 at bank 1. For register 0 to 8 at bank 1, the byte
order is inversed that the MSB byte is R/W before LSB byte.

Figure 7 SPI NOP timing diagram

Symbol Parameters Min Max Units

Tdc Data to SCK Setup 10 ns
Tdh SCK to Data Hold 20 ns
Tcsd CSN to Data Valid 38 ns
Tcd SCK to Data Valid 55 ns
Tcl SCK Low Time 40 ns
Tch SCK High Time 40 ns
Fsck SCK Frequency 0 8 MHz
Tr,Tf SCK Rise and Fall 100 ns
Tcc CSN to SCK Setup 2 ns
Tcch SCK to CSN Hold 2 ns
Tcwh CSN Inactive time 50 ns
Tcdz CSN to Output High Z 38 ns
Table 3 SPI timing parameter

Page 14 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

7 Register Map
There are two register banks, which can be toggled by SPI command “ACTIVATE” followed with
0x53 byte, and bank status can be read from Bank0_REG7 [7].

7.1 Register Bank 0

Address Reset
Mnemonic Bit Type Description
(Hex) Value
00 CONFIG Configuration Register
Reserved 7 0 R/W Only '0' allowed
MASK_RX_DR 6 0 R/W Mask interrupt caused by RX_DR
1: Interrupt not reflected on the IRQ pin
0: Reflect RX_DR as active low interrupt
on the IRQ pin
MASK_TX_DS 5 0 R/W Mask interrupt caused by TX_DS
1: Interrupt not reflected on the IRQ pin
0: Reflect TX_DS as active low interrupt
on the IRQ pin
MASK_MAX_RT 4 0 R/W Mask interrupt caused by MAX_RT
1: Interrupt not reflected on the IRQ pin
0: Reflect MAX_RT as active low
interrupt on the IRQ pin
Enable CRC. Forced high if one of the bits
EN_CRC 3 1 R/W
in the EN_AA is high
CRCO 2 0 R/W CRC encoding scheme
'0' - 1 byte
'1' - 2 bytes
PWR_UP 1 0 R/W 1: POWER UP, 0:POWER DOWN
PRIM_RX 0 0 R/W RX/TX control,
1: PRX, 0: PTX

01 EN_AA Enable „Auto Acknowledgment‟ Function

Reserved 7:6 00 R/W Only '00' allowed
ENAA_P5 5 1 R/W Enable auto acknowledgement data pipe 5
ENAA_P4 4 1 R/W Enable auto acknowledgement data pipe 4
ENAA_P3 3 1 R/W Enable auto acknowledgement data pipe 3
ENAA_P2 2 1 R/W Enable auto acknowledgement data pipe 2
ENAA_P1 1 1 R/W Enable auto acknowledgement data pipe 1
ENAA_P0 0 1 R/W Enable auto acknowledgement data pipe 0

02 EN_RXADDR Enabled RX Addresses

Reserved 7:6 00 R/W Only '00' allowed
ERX_P5 5 0 R/W Enable data pipe 5.
ERX_P4 4 0 R/W Enable data pipe 4.
ERX_P3 3 0 R/W Enable data pipe 3.
ERX_P2 2 0 R/W Enable data pipe 2.
ERX_P1 1 1 R/W Enable data pipe 1.
ERX_P0 0 1 R/W Enable data pipe 0.

Page 15 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0
03 SETUP_AW Setup of Address Widths
(common for all data pipes)
Only '000000' allowed
Reserved 7:2 000000 R/W
RX/TX Address field width
AW 1:0 11 R/W
'00' - Illegal
'01' - 3 bytes
'10' - 4 bytes
'11' - 5 bytes
LSB bytes are used if address width is
below 5 bytes

04 SETUP_RETR Setup of Automatic Retransmission

ARD 7:4 0000 R/W Auto Retransmission Delay
„0000‟ – Wait 250 us
„0001‟ – Wait 500 us
„0010‟ – Wait 750 us
……..
„1111‟ – Wait 4000 us
(Delay defined from end of transmission to
start of next transmission)
Auto Retransmission Count
ARC 3:0 0011 R/W „0000‟ –Re-Transmit disabled
„0001‟ – Up to 1 Re-Transmission on fail
of AA
……
„1111‟ – Up to 15 Re-Transmission on fail
of AA

05 RF_CH RF Channel
Reserved 7 0 R/W Only '0' allowed
RF_CH 6:0 0000010 R/W Sets the frequency channel

06 RF_SETUP RF Setup Register

Reserved 7:6 0 R/W Only '00' allowed
Set Air Data Rate. See RF_DR_HIGH for
RF_DR_LOW 5 0 R/W
encoding.
PLL_LOCK 4 0 R/W Force PLL lock signal. Only used in test
Set Air Data Rate.
Encoding: RF_DR_LOW, RF_DR_HIGH:
RF_DR_HIGH 3 1 R/W
„00‟ – 1Mbps
„01‟ – 2Mbps (default)
„10‟ – 250Kbps
„11‟ – 2Mbps
Set RF output power in TX mode
RF_PWR[1:0]
RF_PWR[1:0] 2:1 '00' – -10 dBm
11 R/W
'01' – -5 dBm
'10' – 0 dBm
'11' – 5 dBm
Setup LNA gain
LNA_HCURR 0 1 R/W 0:Low gain(20dB down)
1:High gain

Status Register (In parallel to the SPI

07 STATUS command word applied on the MOSI pin,
the STATUS register is shifted serially out
on the MISO pin)
RBANK 7 0 R Register bank selection states. Switch

Page 16 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0
register bank is done by SPI command
“ACTIVATE” followed by 0x53
0: Register bank 0
1: Register bank 1
RX_DR 6 0 R/W Data Ready RX FIFO interrupt
Asserted when new data arrives RX FIFO
Write 1 to clear bit.
TX_DS 5 0 R/W Data Sent TX FIFO interrupt
Asserted when packet transmitted on TX.
If AUTO_ACK is activated, this bit is set
high only when ACK is received.
Write 1 to clear bit.
Maximum number of TX retransmits
MAX_RT 4 0 R/W interrupt
Write 1 to clear bit. If MAX_RT is
asserted it must be cleared to enable
further communication.
RX_P_NO 3:1 111 R Data pipe number for the payload
available for reading from RX_FIFO
000-101: Data Pipe Number
110: Not used
111: RX FIFO Empty
TX_FULL 0 0 R TX FIFO full flag.
1: TX FIFO full
0: Available locations in TX FIFO

08 OBSERVE_TX Transmit observe register

Count lost packets. The counter is
PLOS_CNT 7:4 0000 R
overflow protected to 15, and discontinues
at max until reset. The counter is reset by
writing to RF_CH.

Count retransmitted packets. The counter

ARC_CNT 3:0 0000 R is reset when transmission of a new packet
starts.

09 CD
Reserved 7:1 000000 R
CD 0 0 R Carrier Detect

Receive address data pipe 0. 5 Bytes

0A RX_ADDR_P0 39:0 0xE7E7E R/W
maximum length. (LSB byte is written
7E7E7
first. Write the number of bytes defined by
SETUP_AW)
Receive address data pipe 1. 5 Bytes
0B RX_ADDR_P1 39:0 0xC2C2C R/W
maximum length. (LSB byte is written
2C2C2
first. Write the number of bytes defined by
SETUP_AW)
Receive address data pipe 2. Only LSB
0C RX_ADDR_P2 7:0 0xC3 R/W
MSB bytes is equal to
RX_ADDR_P1[39:8]
Receive address data pipe 3. Only LSB
0D RX_ADDR_P3 7:0 0xC4 R/W
MSB bytes is equal to
RX_ADDR_P1[39:8]
Receive address data pipe 4. Only LSB.
0E RX_ADDR_P4 7:0 0xC5 R/W
MSB bytes is equal to
RX_ADDR_P1[39:8]
Receive address data pipe 5. Only LSB.
0F RX_ADDR_P5 7:0 0xC6 R/W
MSB bytes is equal to

Page 17 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0
RX_ADDR_P1[39:8]
Transmit address. Used for a PTX device
only.
10 39:0 0xE7E7E R/W (LSB byte is written first)
TX_ADDR
7E7E7 Set RX_ADDR_P0 equal to this address to
handle automatic acknowledge if this is a
PTX device

11 RX_PW_P0
Reserved 7:6 00 R/W Only '00' allowed
Number of bytes in RX payload in data
pipe 0 (1 to 32 bytes).
0: not used
RX_PW_P0 5:0 000000 R/W
1 = 1 byte
…
32 = 32 bytes

12 RX_PW_P1
Reserved 7:6 00 R/W Only '00' allowed
Number of bytes in RX payload in data
pipe 1 (1 to 32 bytes).
RX_PW_P1 5:0
0: not used
000000 R/W
1 = 1 byte
…
32 = 32 bytes

13 RX_PW_P2
Reserved 7:6 00 R/W Only '00' allowed
Number of bytes in RX payload in data
RX_PW_P2 R/W pipe 2 (1 to 32 bytes).
5:0 000000
0: not used
1 = 1 byte
…
32 = 32 bytes

14 RX_PW_P3
Reserved 7:6 00 R/W Only '00' allowed
Number of bytes in RX payload in data
5:0 000000 pipe 3 (1 to 32 bytes).
0: not used
RX_PW_P3 R/W
1 = 1 byte
…
32 = 32 bytes

15 RX_PW_P4
Reserved 7:6 00 R/W Only '00' allowed
Number of bytes in RX payload in data
pipe 4 (1 to 32 bytes).
0: not used
RX_PW_P4 5:0 000000 R/W
1 = 1 byte
…
32 = 32 bytes

16 RX_PW_P5
Reserved 7:6 00 R/W Only '00' allowed
RX_PW_P5 000000 Number of bytes in RX payload in data
5:0 pipe 5 (1 to 32 bytes).
R/W
0: not used
1 = 1 byte

Page 18 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0
…
32 = 32 bytes

17 FIFO_STATUS FIFO Status Register

Reserved 7 0 R/W Only '0' allowed
Reuse last transmitted data packet if set
TX_REUSE 6 0 high.
The packet is repeatedly retransmitted as
R long as CE is high. TX_REUSE is set by
the SPI command REUSE_TX_PL, and is
reset by the SPI command
W_TX_PAYLOAD or FLUSH TX
TX FIFO full flag
TX_FULL 5 0 R
1: TX FIFO full; 0: Available locations in
TX FIFO
TX FIFO empty flag.
TX_EMPTY 4 1 R 1: TX FIFO empty
0: Data in TX FIFO
Reserved 3:2 00 R/W Only '00' allowed
RX FIFO full flag
RX_FULL 1 0 R 1: RX FIFO full
0: Available locations in RX FIFO
RX FIFO empty flag
RX_EMPTY 0 1 R 1: RX FIFO empty
0: Data in RX FIFO
Written by separate SPI command ACK
N/A ACK_PLD 255:0 X W
packet payload to data pipe number PPP
given in SPI command
Used in RX mode only
Maximum three ACK packet payloads can
be pending. Payloads with same PPP are
handled first in first out.
Written by separate SPI command TX data
pay-load register 1 - 32 bytes. This register
N/A TX_PLD 255:0 X W
is implemented as a FIFO with three
levels.
Used in TX mode only
N/A RX_PLD 255:0 X R Read by separate SPI command
RX data payload register. 1 - 32 bytes.
This register is implemented as a FIFO
with three levels.
All RX channels share the same FIFO.

1C DYNPD Enable dynamic payload length

Reserved 7:6 0 R/W Only „00‟ allowed
Enable dynamic payload length data pipe
DPL_P5 5 0 R/W
5.
(Requires EN_DPL and ENAA_P5)
Enable dynamic payload length data pipe
DPL_P4 4 0 R/W
4.
(Requires EN_DPL and ENAA_P4)
Enable dynamic payload length data pipe
DPL_P3 3 0 R/W
3.
(Requires EN_DPL and ENAA_P3)
Enable dynamic payload length data pipe
DPL_P2 2 0 R/W
2.
(Requires EN_DPL and ENAA_P2)
DPL_P1 1 0 R/W Enable dynamic payload length data pipe
1.

Page 19 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

(Requires EN_DPL and ENAA_P1)

Enable dynamic payload length data pipe
DPL_P0 0 0 R/W
0.
(Requires EN_DPL and ENAA_P0)

1D FEATURE R/W Feature Register

Reserved 7:3 0 R/W Only „00000‟ allowed
EN_DPL 2 0 R/W Enables Dynamic Payload Length
EN_ACK_PAY 1 0 R/W Enables Payload with ACK
Enables the W_TX_PAYLOAD_NOACK
EN_DYN_ACK 0 0 R/W
command
Note: Don’t write reserved registers and registers at other addresses in register bank 0

Table 4 Register Bank 0

Page 20 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

7.2 Register Bank 1

Address Reset
(Hex) Mnemonic Bit Value Type Description
00 31:0 0 W Must write with 0x404B01E2
01 31:0 0 W Must write with 0xC04B0000
02 31:0 0 W Must write with 0xD0FC8C02
0x
03 31:0 03001200 W Must write with 0x99003941
Must write with 0xD99E860B
04 31:0 0 W For single carrier mode:0xD99E8621
Sensitivity in RX mode
0: Normal mode
1: High sensitivity mode(different CD
RX_SEN 21 0 W detection values)
RF output power in TX mode:
0:Low power(-30dB down)
TX_PWR 20 1 W 1:Normal power
Must write with 0x24067FA6(Disable
05 31:0 0 W RSSI)
RSS I Threshold for CD detect
1Mbps/250Kbps:-91dBm
RSSI_TH 29:26 1001 W 2Mbps:-84dBm
RSSI measurement:
0:Enable
RSSI_EN 18 0 W 1:Disable
06 31:0 0 W Reserved
07 31:0 0 W Reserved
Register bank selection states. Switch
register bank is done by SPI command
“ACTIVATE” followed by 0x53
0: Register bank 0
RBANK 7 R 1: Register bank 1
Chip ID:
08 Chip ID 31:0 0 R 0x00000063(RFM73)
09 0 Reserved
0A 0 Reserved
0B 0 Reserved
Please initialize with 0x05731200
0C 31:0 0 W For 120us mode:0x00731200
26:24 101 PLL Settling time:
101:130us
000:120us
9 1 Compatible mode:
0:Static compatible
1:Dynamic compatible
0D NEW_FEATURE 31:0 0 Please initialize with 0x0080B436
0E RAMP 87:0 NA W Ramp curve
Please write with
0xFFEF7DF208082082041041
Note: Don’t write reserved registers and no definition registers in register bank 1

Table 5 Register Bank 1

Page 21 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

8 Electrical Specifications
Name Parameter (Condition) Min Typical Max Unit Comment
Operating Condition
VDD Voltage 1.9 3.0 3.6 V
TEMP Temperature -20 +27 +70 ºC
Digital input Pin
VIH High level 0.7VDD 5.25 V
VIL Low level VSS 0.3VDD V
Digital output Pin
VOH High level (IOH=-0.25mA) VDD- 0.3 VDD V
VOL Low level(IOL=0.25mA) 0 0.3 V
Normal condition
IVDD Power Down current 2.5 uA
IVDD Standby-I current 50 uA
IVDD Standby-II current 330 uA
Normal RF condition
FOP Operating frequency 2400 2527 MHz
FXTAL Crystal frequency 16 MHz
RFSK Air data rate 250 2000 Kbps
Transmitter
PRF Output power -40 0 3 dBm
PBW Modulation 20 dB bandwidth(2Mbps) 2.5 MHz
PBW Modulation 20 dB bandwidth (1Mbps) 1.3 MHz
PBW Modulation 20 dB bandwidth (250Kbps) 960 KHz
PRF1 Out of band emission 2 MHz -20 dBm
PRF2 Out of band emission 4 MHz -40 dBm
IVDD Current at -40 dBm output power 11 mA
IVDD Current at -30 dBm output power 11 mA
IVDD Current at -25 dBm output power 12 mA
IVDD Current at -10 dBm output power 13 mA
IVDD Current at -5 dBm output power 15 mA
IVDD Current at 0 dBm output power 17 mA
IVDD Current at 5 dBm output power 23 mA
Receiver
IVDD Current (2Mbps) 22 mA
IVDD Current (1Mbps) 22 mA
IVDD Current (250Kbps) 22 mA
Max Input 1 E-3 BER 10 dBm
RXSENS 1 E-3 BER sensitivity (2Mbps) -87 dBm High Sen mode
RXSENS 1 E-3 BER sensitivity (1Mbps) -90 dBm High Sen mode
RXSENS 1 E-3 BER sensitivity (250Kbps) -97 dBm High Sen mode
C/ICO Co-channel C/I (2Mbps) 3 dB
C/I1ST ACS C/I 2MHz (2Mbps) -5 dB
C/I2ND ACS C/I 4MHz (2Mbps) -25 dB
C/I3RD ACS C/I 6MHz (2Mbps) -25 dB
C/ICO Co-channel C/I (1Mbps) 3 dB
C/I1ST ACS C/I 1MHz (1Mbps) 4 dB
C/I2ND ACS C/I 2MHz (1Mbps) -25 dB
C/I3RD ACS C/I 3MHz (1Mbps) -20 dB
C/ICO Co-channel C/I (250Kbps) 1 dB
C/I1ST ACS C/I 1MHz (250Kbps) -11 dB
C/I2ND ACS C/I 2MHz (250Kbps) -15 dB
C/I3RD ACS C/I 3MHz (250Kbps) -28 dB

Table 6 Electrical Specifications

Page 22 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

9 Typical Application Schematic

Figure 8 RFM73 typical application schematic

Page 23 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

10 Package Information
Figure 9 RFM73 SMD PACKAGE

Page 24 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

Figure 10 RFM73 DIP PACKAGE

Page 25 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

11 Order Information

Table 7 RFM73 order information

12 Solder Information
 Solder Method: Not supported reflow soldering, recommend to use hand solder .

 The Selection of Soldering tools

According to both our soldering experiment and customers‟

feedback, we don‟t find that it results in obvious effect on soldering
and products‟ fuctions by using open soldering pens(i.e. common
soldering pens without closed-loop temperature control). However,
considering the requirements of lead-free soldering and its
productivity improvement, we suggest that you should use
thermostatic soldering pen with closed-loop temperature control and
select appropriate solder tip. Please kindly note that big solder tips,
according to the feedback from customers, obviously bring about
low efficiency of soldering and increase the possibility of short-
circuit.

 The Selection of Soldering Materials

——Sn96.5%/Ag3.0%/Cu0.5%
——Sn96.5%/Ag3.5%
The wireless modules we provide are green products in complete
accordance with the lead-free requirement; therefore, we suggest
you should use environment-friendly lead-free soldering tin. We
recommend two alloyed soldering tins as below to match the no-
clean rosin(core and additive rosin):
——Sn96.5%/Ag3.0%/Cu0.5%
——Sn96.5%/Ag3.5%

Page 26 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]
 RFM73 V2.0

13 Contact Information

This document may contain preliminary information and is subject to

change by Hope Microelectronics without notice. Hope Microelectronics
assumes no responsibility or liability for any use of the information
contained herein. Nothing in this document shall operate as an express or
HOPE MICROELECTRONICS CO.,LTD implied license or indemnity under the intellectual property rights of Hope
Add: 2/F, Building 3, Pingshan Private Microelectronics or third parties. The products described in this document
Enterprise Science and Technology are not intended for use in implantation or other direct life support
Park, Lishan Road, XiLi Town, Nanshan applications where malfunction may result in the direct physical harm or
District, Shenzhen, Guangdong, China injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT
Tel: 86-755-82973805 NOT LIMITED TO, THE IMPLIED WARRANTIES OF MECHANTABILITY
Fax: 86-755-82973550 OR FITNESS FOR A ARTICULAR PURPOSE, ARE OFFERED IN THIS
Email: sales@[Link] DOCUMENT.
Website: [Link]
[Link] ©2006, HOPE MICROELECTRONICS CO.,LTD. All rights reserved.

Page 27 of 27
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@[Link] [Link]