FDD8880

September 2004

FDD8880
N-Channel PowerTrench® MOSFET
30V, 58A, 9mΩ
General Description Features
This N-Channel MOSFET has been designed specifically to • r DS(ON) = 9mΩ, V GS = 10V, ID = 35A
improve the overall efficiency of DC/DC converters using
either synchronous or conventional switching PWM • r DS(ON) = 12mΩ, V GS = 4.5V, I D = 35A
controllers. It has been optimized for low gate charge, low
r DS(ON) and fast switching speed. • High performance trench technology for extremely low
r DS(ON)

• Low gate charge

Applications
• High power and current handling capability
• DC/DC converters

D
D
G
G
S
D-PAK
TO-252 S
(TO-252)
MOSFET Maximum Ratings T C = 25°C unless otherwise noted
Symbol Parameter Ratings Units
V DSS Drain to Source Voltage 30 V
V GS Gate to Source Voltage ±20 V
Drain Current
Continuous (T C = 25 o C, V GS = 10V) (Note 1) 58 A
ID Continuous (T C = 25 o C, V GS = 4.5V) (Note 1) 51 A
Continuous (T amb = 25 o C, VGS = 10 V, with Rθ JA = 52 o C/W) 13 A
Pulsed Figure 4 A
E AS Single Pulse Avalanche Energy (Note 2) 53 mJ
Power dissipation 55 W
PD
Derate above 25 o C 0.37 W/ o C
oC
TJ, T STG Operating and Storage Temperature -55 to 175

Thermal Characteristics
o C/W
Rθ JC Thermal Resistance Junction to Case TO-252 2.73
o C/W
Rθ JA Thermal Resistance Junction to Ambient TO-252 100
Rθ JA Thermal Resistance Junction to Ambient TO-252, 1in 2 copper pad area 52 o C/W

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity
FDD8880 FDD8880 TO-252AA 13” 12mm 2500 units

©2004 Fairchild Semiconductor Corporation FDD8880 Rev. B1

 FDD8880
Electrical Characteristics TC = 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics
B VDSS Drain to Source Breakdown Voltage ID = 250µA, V GS = 0V 30 - - V
V DS = 24V - - 1
IDSS Zero Gate Voltage Drain Current µA
V GS = 0V T C = 150 o C - - 250
IGSS Gate to Source Leakage Current V GS = ±20V - - ±100 nA

On Characteristics
V GS(TH) Gate to Source Threshold Voltage V GS = VDS , I D = 250µA 1.2 - 2.5 V
ID = 35A, V GS = 10V - 0.007 0.009
ID = 35A, V GS = 4.5V - 0.009 0.012
rDS(ON) Drain to Source On Resistance Ω
ID = 35A, V GS = 10V,
- 0.013 0.015
T J = 175 o C

Dynamic Characteristics
CISS Input Capacitance - 1260 - pF
V DS = 15V, V GS = 0V,
COSS Output Capacitance - 260 - pF
f = 1MHz
CRSS Reverse Transfer Capacitance - 150 - pF
RG Gate Resistance V GS = 0.5V, f = 1MHz - 2.3 - Ω
Qg(TOT) Total Gate Charge at 10V V GS = 0V to 10V - 23 31 nC
Qg(5) Total Gate Charge at 5V V GS = 0V to 5V - 13 17 nC
V DD = 15V
Qg(TH) Threshold Gate Charge V GS = 0V to 1V - 1.3 1.7 nC
ID = 35A
Qgs Gate to Source Gate Charge - 3.8 - nC
Ig = 1.0mA
Qgs2 Gate Charge Threshold to Plateau - 2.5 - nC
Qgd Gate to Drain “Miller” Charge - 5.0 - nC

Switching Characteristics (V GS = 10V)

tO N Turn-On Time - - 147 ns
td(ON) Turn-On Delay Time - 8 - ns
tr Rise Time V DD = 15V, I D = 35A - 91 - ns
td(OFF) Turn-Off Delay Time V GS = 10V, R GS = 10Ω - 38 - ns
tf Fall Time - 32 - ns
tOFF Turn-Off Time - - 108 ns

Drain-Source Diode Characteristics

ISD = 35A - - 1.25 V
V SD Source to Drain Diode Voltage
ISD = 15A - - 1.0 V
trr Reverse Recovery Time ISD = 35A, dI SD /dt = 100A/µs - - 27 ns
QRR Reverse Recovered Charge ISD = 35A, dI SD /dt = 100A/µs - - 14 nC

Notes:
1: Package current limitation is 35A.
2: Starting TJ = 25°C, L = 0.14mH, I A S = 28A, VD D = 27V, VGS = 10V.

©2004 Fairchild Semiconductor Corporation FDD8880 Rev. B1

 FDD8880
Typical Characteristics TC = 25°C unless otherwise noted

1.2 60
CURRENT LIMITED
BY PACKAGE
POWER DISSIPATION MULTIPLIER

1.0 50

ID , DRAIN CURRENT (A)

0.8 40
VGS = 10V

0.6 30

VGS = 4.5V
0.4 20

0.2 10

0 0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175

TC , CASE TEMPERATURE (o C) TC , CASE TEMPERATURE (o C)

Figure 1. Normalized Power Dissipation vs Case Figure 2. Maximum Continuous Drain Current vs
Temperature Case Temperature

2
DUTY CYCLE - DESCENDING ORDER
0.5
1
0.2
0.1
0.05
THERMAL IMPEDANCE

0.02
Zθ JC , NORMALIZED

0.01
PDM

0.1

t1
t2
NOTES:
DUTY FACTOR: D = t1 /t 2
SINGLE PULSE PEAK TJ = P DM x Z θJC x RθJC + TC
0.01
10 -5 10-4 10 -3 10 -2 10-1 10 0 101
t, RECTANGULAR PULSE DURATION (s)

Figure 3. Normalized Maximum Transient Thermal Impedance

500
TRANSCONDUCTANCE TC = 25 o C
MAY LIMIT CURRENT FOR TEMPERATURES
IN THIS REGION ABOVE 25oC DERATE PEAK
ID M, PEAK CURRENT (A)

V GS = 10V CURRENT AS FOLLOWS:

I = I25 175 - TC
VGS = 4.5V 150

100

30
10 -5 10 -4 10 -3 10-2 10-1 100 101
t, PULSE WIDTH (s)

Figure 4. Peak Current Capability

©2004 Fairchild Semiconductor Corporation FDD8880 Rev. B1

 FDD8880
Typical Characteristics TC = 25°C unless otherwise noted

1000 500
If R = 0
t AV = (L)(IAS )/(1.3*RATED BVDSS - VD D)
If R ≠ 0

IA S, AVALANCHE CURRENT (A)

10µs t AV = (L/R)ln[(I AS *R)/(1.3*RATED BVDSS - V DD ) +1]
100 100
ID , DRAIN CURRENT (A)

100µs STARTING TJ = 25 o C
10
OPERATION IN THIS
AREA MAY BE 10
LIMITED BY r DS(ON)
1ms
1 STARTING TJ = 150o C
SINGLE PULSE 10ms
TJ = MAX RATED DC
TC = 25 o C
0.1 1
1 10 60 0.01 0.1 1 10
V D S, DRAIN TO SOURCE VOLTAGE (V) t A V, TIME IN AVALANCHE (ms)

Figure 5. Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability

80 80
PULSE DURATION = 80 µs
DUTY CYCLE = 0.5% MAX V GS = 5V
VDD = 15V
I D, DRAIN CURRENT (A)

60 60
ID , DRAIN CURRENT (A)

VGS = 4V
VGS = 10V

40 40

T J = 25 o C
VGS = 3V

20 20
TC = 25o C
PULSE DURATION = 80 µs
TJ = 175o C TJ = -55 o C
DUTY CYCLE = 0.5% MAX
0
0
0 0.25 0.5 0.75 1.0
1.5 2.0 2.5 3.0 3.5 4.0
V GS , GATE TO SOURCE VOLTAGE (V) V D S, DRAIN TO SOURCE VOLTAGE (V)

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

25 1.8
PULSE DURATION = 80 µs PULSE DURATION = 80µs
ID = 35A DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE

1.6
r DS( ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)

20
ON RESISTANCE

1.4

15 1.2

ID = 1A
1.0
10

0.8

VGS = 10V, ID = 35A

5 0.6
2 4 6 8 10 -80 -40 0 40 80 120 160 200
V GS, GATE TO SOURCE VOLTAGE (V) TJ , JUNCTION TEMPERATURE (o C)

Figure 9. Drain to Source On Resistance vs Gate Figure 10. Normalized Drain to Source On
Voltage and Drain Current Resistance vs Junction Temperature

©2004 Fairchild Semiconductor Corporation FDD8880 Rev. B1

 FDD8880
Typical Characteristics TC = 25°C unless otherwise noted

1.2 1.10
VGS = V D S, ID = 250µA I D = 250µA

NORMALIZED DRAIN TO SOURCE

BREAKDOWN VOLTAGE
1.0 1.05
THRESHOLD VOLTAGE
NORMALIZED GATE

0.8 1.00

0.6 0.95

0.4 0.90
-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200

TJ , JUNCTION TEMPERATURE ( o C) TJ , JUNCTION TEMPERATURE (o C)

Figure 11. Normalized Gate Threshold Voltage vs Figure 12. Normalized Drain to Source
Junction Temperature Breakdown Voltage vs Junction Temperature

2000 10
VDD = 15V
VGS , GATE TO SOURCE VOLTAGE (V)

CISS = CGS + CGD

8
1000
C, CAPACITANCE (pF)

COSS ≅ CDS + C GD
CRSS = CGD 6

WAVEFORMS IN
2 DESCENDING ORDER:
ID = 35A
VGS = 0V, f = 1MHz ID = 1A

100 0
0.1 1 10 30 0 5 10 15 20 25
V D S, DRAIN TO SOURCE VOLTAGE (V) Qg , GATE CHARGE (nC)

Figure 13. Capacitance vs Drain to Source Figure 14. Gate Charge Waveforms for Constant
Voltage Gate Current

©2004 Fairchild Semiconductor Corporation FDD8880 Rev. B1

 FDD8880
Test Circuits and Waveforms

VDS
BVDSS

L tP
VD S

VARY t P TO OBTAIN IAS

+
VD D
REQUIRED PEAK I AS RG
VDD
VGS -

DUT

tP
0V IAS
0.01Ω 0

tA V

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

VD S

VDD Q g(TOT)

VD S VGS
L
VGS = 10V
VGS Qg(5)
+
Qgs2
VD D VGS = 5V
-

DUT
VGS = 1V
I g(REF)
0
Qg(TH)
Qgs Qgd

Ig(REF)
0

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

VD S t ON t OFF

t d(ON) td(OFF)

RL tr tf
VDS
90% 90%

+
VGS
VDD
10% 10%
- 0

DUT 90%
RGS
V GS 50% 50%
PULSE WIDTH
V GS 10%
0

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

©2004 Fairchild Semiconductor Corporation FDD8880 Rev. B1

 FDD8880
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJ M, and the 125
thermal resistance of the heat dissipating path determines RθJA = 33.32+ 23.84/(0.268+Area) EQ.2
the maximum allowable device power dissipation, P DM, in an
application. Therefore the application’s ambient RθJA = 33.32+ 154/(1.73+Area) EQ.3
100
temperature, T A (o C), and thermal resistance R θJA ( o C/W)
must be reviewed to ensure that T JM is never exceeded.

RθJ A ( oC/W)
Equation 1 mathematically represents the relationship and
75
serves as the basis for establishing the rating of the part.

(T –T )
JM A (EQ. 1)
P D M = ----------------------------- 50
R θJA

In using surface mount devices such as the TO-252 25

package, the environment in which it is applied will have a 0.01 0.1 1 10
significant influence on the part’s current and maximum (0.0645) (0.645) (6.45) (64.5)
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors: AREA, TOP COPPER AREA in 2 (cm 2)
Figure 21. Thermal Resistance vs Mounting
1. Mounting pad area onto which the device is attached and Pad Area
whether there is copper on one side or both sides of the
board.

2. The number of copper layers and the thickness of the

board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width, the

duty cycle and the transient thermal response of the part,
the board and the environment they are in.

Fairchild provides thermal information to assist the

designer’s preliminary application evaluation. Figure 21
defines the Rθ JA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.

Thermal resistances corresponding to other copper areas

can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.

23.84
R θJA = 33.32 + ------------------------------------- (EQ. 2)
( 0.268 + Area )
Area in Inches Squared

154
R θJA = 33.32 + ---------------------------------- (EQ. 3)
( 1.73 + Area)
Area in Centimeters Squared

©2004 Fairchild Semiconductor Corporation FDD8880 Rev. B1

 FDD8880
PSPICE Electrical Model
.SUBCKT FDD8880 2 1 3 ; rev April 2004
Ca 12 8 9.5e-10
Cb 15 14 9.5e-10 LDRAIN
Cin 6 8 1.15e-9 DPLCAP 5 DRAIN
2
10
Dbody 7 5 DbodyMOD RLDRAIN
RSLC1
Dbreak 5 11 DbreakMOD DBREAK
51
Dplcap 10 5 DplcapMOD RSLC2
+
5 ESLC 11
51
Ebreak 11 7 17 18 33.15 -
Eds 14 8 5 8 1 50 +
-
Egs 13 8 6 8 1 17 DBODY
6 RDRAIN
ESG EBREAK 18
Esg 6 10 6 8 1 8
EVTHRES -
Evthres 6 21 19 8 1 + 16
+ 19 - 21
Evtemp 20 6 18 22 1 MWEAK
LGATE EVTEMP 8
GATE RGATE + 18 - 6
It 8 17 1 1 MMED
9 20 22
RLGATE MSTRO
Lgate 1 9 5.3e-9 LSOURCE
CIN SOURCE
Ldrain 2 5 1.0e-9 8 7 3
Lsource 3 7 1.7e-9
RSOURCE
RLSOURCE
RLgate 1 9 53 S1A S2A
12 RBREAK
RLdrain 2 5 10 13 14 15 17 18
RLsource 3 7 17 8 13
S1B S2B RVTEMP
Mmed 16 6 8 8 MmedMOD 13 CB 19
Mstro 16 6 8 8 MstroMOD CA
14 IT -
+ +
Mweak 16 21 8 8 MweakMOD VBAT
6 5
EGS EDS +
8 8
Rbreak 17 18 RbreakMOD 1 - - 8
Rdrain 50 16 RdrainMOD 3.2e-3 22
Rgate 9 20 2.2 RVTHRES
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 3.2e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD

Vbat 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*170),5))}

.MODEL DbodyMOD D (IS=2E-12 IKF=10 N=1.01 RS=3.76e-3 TRS1=8e-4 TRS2=2e-7

+ CJO=4.8e-10 M=0.55 TT=1e-17 XTI=2)
.MODEL DbreakMOD D (RS=0.2 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=5.5e-10 IS=1e-30 N=10 M=0.45)

.MODEL MmedMOD NMOS (VTO=2.0 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.2)
.MODEL MstroMOD NMOS (VTO=2.5 KP=170 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=1.69 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=22 RS=0.1)

.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-8e-7)

.MODEL RdrainMOD RES (TC1=1.8e-3 TC2=8e-6)
.MODEL RSLCMOD RES (TC1=9e-4 TC2=1e-6)
.MODEL RsourceMOD RES (TC1=5e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-1e-3 TC2=-8.2e-6)
.MODEL RvtempMOD RES (TC1=-2.6e-3 TC2=2e-7)

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3.5)

.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.3 VOFF=-0.8)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.8 VOFF=-1.3)
.ENDS

Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.

©2004 Fairchild Semiconductor Corporation FDD8880 Rev. B1

 FDD8880
SABER Electrical Model
rev April 2004
template FDD8880 n2,n1,n3
electrical n2,n1,n3

{
var i iscl
dp..model dbodymod = (isl=2e-12,ikf=10,nl=1.01,rs=3.76e-3,trs1=8e-4,trs2=2e-7,cjo=4.8e-10,m=0.55,tt=1e-17,xti=2)
dp..model dbreakmod = (rs=0.2,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=5.5e-10,isl=10e-30,nl=10,m=0.45)
m..model mmedmod = (type=_n,vto=2.0,kp=10,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.5,kp=170,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.69,kp=0.05,is=1e-30, tox=1,rs=0.1) LDRAIN
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3.5) DPLCAP 5 DRAIN
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-4) 2
10
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.3,voff=-0.8) RLDRAIN
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.8,voff=-1.3) RSLC1
[Link] n12 n8 = 9.5e-10 51
RSLC2
[Link] n15 n14 = 9.5e-10
ISCL
[Link] n6 n8 = 1.15e-9
50 DBREAK
-
[Link] n7 n5 = model=dbodymod
6 RDRAIN
[Link] n5 n11 = model=dbreakmod ESG 8 11
[Link] n10 n5 = model=dplcapmod EVTHRES DBODY
+ 16
+ 19 - 21
MWEAK
LGATE EVTEMP 8
[Link] n11 n7 n17 n18 = 33.15 GATE RGATE + 18 - 6 EBREAK
[Link] n14 n8 n5 n8 = 1 1 22 MMED
9 +
[Link] n13 n8 n6 n8 = 1 20
MSTRO 17
RLGATE
[Link] n6 n10 n6 n8 = 1 18 LSOURCE
[Link] n6 n21 n19 n8 = 1 CIN - SOURCE
8 7
[Link] n20 n6 n18 n22 = 1 3
RSOURCE
RLSOURCE
[Link] n8 n17 = 1
S1A S2A
12 RBREAK
13 14 15
[Link] n1 n9 = 5.3e-9 17 18
8 13
[Link] n2 n5 = 1.0e-9
S1B S2B RVTEMP
[Link] n3 n7 = 1.7e-9
13 CB 19
CA
14 IT -
[Link] n1 n9 = 53 + +
6 5 VBAT
[Link] n2 n5 = 10 EGS EDS
8 8 +
[Link] n3 n7 = 17 - - 8
22
[Link] n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u RVTHRES
[Link] n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
[Link] n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

[Link] n17 n18 = 1, tc1=8.3e-4,tc2=-8e-7

[Link] n50 n16 = 3.2e-3, tc1=1.8e-3,tc2=8e-6
[Link] n9 n20 = 2.2
res.rslc1 n5 n51 = 1e-6, tc1=9e-4,tc2=1e-6
res.rslc2 n5 n50 = 1e3
[Link] n8 n7 = 3.2e-3, tc1=5e-3,tc2=1e-6
[Link] n22 n8 = 1, tc1=-1e-3,tc2=-8.2e-6
[Link] n18 n19 = 1, tc1=-2.6e-3,tc2=2e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

[Link] n22 n19 = dc=1

equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/170))** 5))
}
}

©2004 Fairchild Semiconductor Corporation FDD8880 Rev. B1

 FDD8880
PSPICE Thermal Model JUNCTION
th
REV 23 April 2004

FDD8880T

CTHERM1 TH 6 8e-4
CTHERM2 6 5 1e-3
CTHERM3 5 4 2.5e-3 RTHERM1 CTHERM1
CTHERM4 4 3 2.6e-3
CTHERM5 3 2 8e-3
CTHERM6 2 TL 1.5e-2
6
RTHERM1 TH 6 1.44e-1
RTHERM2 6 5 1.9e-1
RTHERM3 5 4 3.0e-1
RTHERM2 CTHERM2
RTHERM4 4 3 4.0e-1
RTHERM5 3 2 5.7e-1
RTHERM6 2 TL 5.8e-1
5

SABER Thermal Model

SABER thermal model FDD8880T
template thermal_model th tl RTHERM3 CTHERM3
thermal_c th, tl
{
ctherm.ctherm1 th 6 =8e-4
4
ctherm.ctherm2 6 5 =1e-3
ctherm.ctherm3 5 4 =2.5e-3
ctherm.ctherm4 4 3 =2.6e-3
ctherm.ctherm5 3 2 =8e-3 RTHERM4 CTHERM4
ctherm.ctherm6 2 tl =1.5e-2

rtherm.rtherm1 th 6 =1.44e-1
rtherm.rtherm2 6 5 =1.9e-1 3
rtherm.rtherm3 5 4 =3.0e-1
rtherm.rtherm4 4 3 =4.0e-1
rtherm.rtherm5 3 2 =5.7e-1
RTHERM5 CTHERM5
rtherm.rtherm6 2 tl =5.8e-1
}

RTHERM6 CTHERM6

tl CASE

©2004 Fairchild Semiconductor Corporation FDD8880 Rev. B1

TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
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CoolFET™ FRFET™ MicroFET™ PowerTrench SuperSOT™-6
CROSSVOLT™ GlobalOptoisolator™ MicroPak™ QFET SuperSOT™-8
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ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. I12