Application Note 76

May 1999
OPTI-LOOP Architecture Reduces Output Capacitance and
Improves Transient Response
John Seago

INTRODUCTION WHAT IS LOOP COMPENSATION?

Removing output capacitors saves money and board Loop compensation is the adjustment of the control loop
space. Linear Technology’s OPTI-LOOPTM architecture frequency response to assure loop stability and optimize
allows you to use the output capacitors of your choice and the transient response of the power supply. The frequency
compensate the control loop for optimum transient response is determined by the gain and phase of the loop’s
response and loop stability. Figure 1 shows the dramatic reaction to load current changes at all frequencies. A Bode
improvement possible with the OPTI-LOOP architecture. plot is used to show the gain and phase of the frequency
With the improvement shown in Figure 1, less capacitance response.
is required or less expensive capacitors can be used. Load
dynamics and supply tolerances will predict the minimum LOOP COMPENSATION BASICS
output capacitance required. The quality of loop compen-
sation determines how close you can get to this minimum This application note contains a brief refresher course in
capacitance requirement in a real world system. control loop basics. Frequency response is characterized
by the effects of poles and zeros. Each pole has a corner
One of the least understood areas of power supply design frequency, caused by a resistance and capacitance, that
is control loop compensation. Because of this, some determines the beginning of a 20dB/decade drop in volt-
manufacturers provide loop compensation inside the regu- age gain. The pole also causes the phase to decrease by
lator IC. Internal compensation works best with one set of 90°, starting roughly one decade before the corner fre-
operating conditions and is sensitive to output capacitor quency and ending about one decade after the corner
characteristics. Consequently, more expensive output frequency. A zero has the opposite effect of a pole. It
capacitors may be required to stabilize the loop because of causes the gain to increase by 20dB/decade starting at its
the sensitivities of the internal IC compensation. The “RC” corner frequency and it adds 90° of phase shift,
OPTI-LOOP architecture is intended to allow circuit starting one decade before the corner frequency and
designers to squeeze the most performance out of the ending one
output capacitors of their choice. decade after the corner frequency. The effects of poles and
zeros are additive, so that two poles at the same frequency
OPTI -LOOP
cause a 40dB/decade roll-off in gain and a 180° phase shift
over two decades. If a pole and zero occur at the same
OUTPUT VOLTAGE (50mV/DIV)

COMPENSATION
COUT = 1500µF
frequency, their effects cancel.
The crossover frequency of the loop determines the band-
COMPETITION
width and transient response of the power supply. The
crossover frequency is the frequency at which the loop
VIN = 15V
VO = 1.6V
gain is one (0dB). The higher the crossover frequency, the
IO = 30mA to 7A faster the power supply can respond to changes in load
COUT = 1500µF
current.
TIME (10µs/DIV)
DSOL8 F01

Figure 1. Improved Transient Response with , LTC and LT are registered trademarks of Linear Technology Corporation.
OPTI-LOOP Architecture OPTI-LOOP is a trademark of Linear Technology Corporation.

AN76-1
Application Note 76
In a voltage mode DC/DC switching regulator system, the over temperature and component values differ from unit to
buck inductor and output capacitor form a double pole at unit in production, causing the loop’s voltage gain and
their resonant frequency, causing a 40dB/decade gain phase to vary accordingly. If the component values cause
roll-off and 180° phase shift. Since the inductor’s effect on the phase to go to zero when the voltage gain is one, the
a current mode control loop is largely cancelled by the regulator will oscillate. The goal is to provide the best gain
current loop, it is generally easier to compensate a current and phase margins with the highest crossover frequency
mode regulator than a voltage mode regulator. possible. A high crossover frequency results in a quick
response to load current changes whereas high gain at low
The first requirement of loop compensation is stability. If
frequencies results in fast settling of the output voltage.
the error amplifier’s feedback becomes positive when the
Nonideal components and amplifier gain limitations gen-
loop gain equals one, the regulator will oscillate. A loop
erally force a trade-off between high crossover frequency
oscillation appears as a sine wave riding on the DC output
and large stability margins.
voltage at the unity-gain frequency of the control loop.
This oscillation will generally occur in the frequency range
of 1kHz to 20kHz. Don’t confuse switching frequency THE CONTROL LOOP
ripple or higher frequency ringing with a loop instability. Figure 2 shows the simplified control loop for the LTC ®1628
If a network analyzer is available, stability margins can be and LTC1735/LTC1736 current mode, synchronous buck
determined by measuring the gain and phase of the loop regulators. The control loop has both DC gain and AC
and observing the resulting Bode plot. The phase margin frequency response characteristics. The DC loop consists
is the difference between the signal phase and – 360° of the feedback resistors, the error amplifier, the DC
when the voltage gain is one (0dB). A 60° phase margin is resistance of the ITH pin components, the current com-
preferred, but 45° is usually acceptable. The gain margin parator, the sense resistor and the load resistor. The AC
is the amount of negative gain present when the signal loop consists of the DC loop plus the output capacitor,
phase is zero (– 360°). A gain margin of – 10dB is normally capacitors C1 and C2 and the AC impedance of the ITH pin
considered acceptable. Generous gain and phase margins components.
are very important because actual component values vary

SWITCH
NODE
TOP
MOSFET INDUCTOR RSENSE OUTPUT
INPUT

30k SENSE + SENSE –

TG + R1 C1
CURRENT (10mV TO 65mV)
MOSFET COMP 30k 0V TO 75mV
CONTROL – VOSENSE
BG LOGIC
BOTTOM (0.3V TO 2.2V) +
CIN 0.3V TO 2.4V COUT RLOAD
MOSFET ERROR
AMP
ITH – 0.8V

gm = 1.4mS
C4 R3
(LTC1735/LTC1736) R2 C2
LTC1628 C3
AN76 F02

MODULATOR ERROR AMPLIFIER

Figure 2. Basic Control Loop of Current Mode, Switching Regulator

AN76-2
 Application Note 76
DC GAIN gm(MOD) = (VRSENSE(MAX)/RSENSE)/∆VITH(MAX)
DC gain is the small-signal loop gain under static test = (0. 075V/0.015Ω)/2.1V = 2.38S
conditions. Load regulation is determined by DC gain, so AV(MOD) = gm(MOD)RLOAD = (2.38S)(3.3V/3A)
the higher the gain, the lower the change in output voltage
for a given DC load current variation. The DC gain is the = 2.62 = 8.4dB
product of the feedback resistor attenuation, the error DC Gain = (AV(FB))( AV(EA))(AV(MOD))
amplifier voltage gain and modulator gain. The modulator
consists of the current comparator, the MOSFETs and = (0.242)(4592)(2.62) = 2911 = 69.3dB
their drivers, the inductor, sense resistor, output capacitor
and load resistance: basically the power path. FREQUENCY RESPONSE
The feedback divider attenuation is: Frequency response is the loop’s reaction to perturbations
at all frequencies and is shown as gain and phase mea-
AV(FB) = VREF/ VOUT
surements on a Bode plot. The output capacitor and load
where: VREF is 0.8V for products in the LTC1735 family and resistance largely determine where the error amplifier
VOUT is the output voltage of the power supply. poles and zeros need to be placed for optimum transient
The error amplifier voltage gain is: response and loop stability.

AV(EA) = gm(EA)ZITH Output Capacitor Pole and Zero

where: gm(EA) is the transconductance of the error ampli- The gain at very low frequencies is equal to the DC gain.
fier, 1.4mS for products in the the LTC1735 family and Normally the first departure from that gain is the pole
ZITH is the output impedance of the error amplifier in created by the load resistance and the output capacitance.
parallel with any impedance connected to the ITH pin. The corner frequency of this pole is:
The transconductance of the modulator must be deter- fP = 1/(2πRLCOUT)
mined before calculating the modulator gain. The modu-
where: RL is the load resistance and COUT is the output
lator transconductance is:
capacitance.
gm(MOD) = (VRSENSE(MAX)/RSENSE)/∆VITH(MAX)
Notice that as the output current goes down, the equiva-
where: VRSENSE(MAX) is listed in the data sheet as 75mV, lent load resistance goes up, causing the pole frequency to
RSENSE is the value of the current sense resistor and decrease. The same is true when the output capacitance
∆VITH(MAX) is 2.1V for the no-load to full-load output increases, that is, the pole frequency moves lower.
voltage swing of the error amplifier.
The amount of phase margin is largely determined by the
The DC voltage gain of the modulator is: zero formed by the output capacitance and capacitor ESR.
AV(MOD) = gm(MOD)RLOAD The corner frequency of this zero is:

where: gm(MOD) is the transconductance of the modulator fZ = 1/(2πESR • COUT)

and RLOAD = VOUT/IOUT. It is interesting to note that doubling the number of like
As an example, the DC gain for the LTC1735/LTC1736 or output capacitors will lower the pole frequency by half but
the LTC1628 providing 3A at 3.3V is: will not change the zero frequency of the output capacitor.
This is true because, as the capacitance doubles, the ESR
AV(FB) = VREF /VOUT = 0.8V/ 3.3V = 0.242 = – 12.3 dB is halved, yet the load resistance remains the same.
AV(EA) = gm(EA)ZITH = (1.4mS)(3.28M) = 4592 = 73.2 dB Consequently, the product of RL and COUT goes up, but the
product of ESR and COUT remains the same. It is desirable
where: 3.28M is the typical output impedance of the error that the crossover frequency be higher than the ESR zero
amplifier without any external DC loading on the ITH pin.

AN76-3
Application Note 76
frequency because the phase shift of the ESR zero is very Aluminum electrolytic capacitors are often selected for
helpful in achieving adequate phase margin. both the input and output of very low cost power supplies.
Figure 3 shows a 3kHz pole for a 47µF, 6.3V, 0.05Ω
Different types of capacitors have different amounts of
Specialty Polymer capacitor. Figure 4 shows a 120Hz pole
ESR per µF of capacitance. The ESR of the output capacitor
for a 1200µF, 6.3V, 0.05Ω aluminum electrolytic capaci-
determines the output ripple voltage under static load
tor. In order to maintain the 0.05Ω ESR required to meet
conditions and greatly affects the output response to
the output ripple requirement, the aluminum electrolytic
transient loads. For a 3A output, the inductor ripple current
capacitor requires 25 times the capacitance of the Spe-
should be about 1AP-P. Therefore, the output capacitor
ESR should be about 0.05Ω for a 50mV P-P output voltage cialty Polymer capacitor, causing the aluminum electro-
lytic capacitor to have a pole frequency at 4% of the
ripple. The difference in frequency response between
specialty polymer capacitor.
Panasonic’s Specialty Polymer output capacitors and alu-
minum electrolytic output capacitors, with 0.05Ω of ESR, The loop compensation must be quite different when
is shown in Figures 3 and 4. aluminum electrolytic capacitors are used. It is unlikely
that fixed internal compensation will work well with both
40
types of capacitors. Although bandwidth will suffer when
1 1
47µF f =
6.3V
Z 2πESR(C
OUT)
fP =
2πRLCOUT
aluminum electrolytic capacitors are used, using an OPTI-
30
0.05Ω LOOP architecture, the loop can be optimized for their use
20
RL = 1.1Ω and stable operation achieved. The high ESR zero fre-
10 45 quency of the Specialty Polymer capacitors makes the
PHASE (DEG)

fP =
GAIN (dB)

308Hz 3.08kHz 677.6kHz

0 0 loop more difficult to compensate, but the bandwidth will
–10 –45 be significantly higher as a result of the extra effort.
30.8kHz
–20 6.77kHz –90
The Modulator
–30 GAIN fZ = 67.76kHz –135
PHASE
–40
The modulator controls the inductor current as a function
1 10 100 1k 10k 100k 1M of the amplified error signal from the error amplifier. The
FREQUENCY (Hz)
AN76 F03
transconductance of the modulator, calculated earlier, is
Figure 3. Frequency Response of Specialty Polymer determined by the maximum current allowed through the
Capacitor Used in 3.3V, 3A Power Supply Output sense resistor divided by the maximum voltage swing of
the error amplifier output at the ITH pin. The product of the
modulator transconductance and the load resistance is
40
1200µF fZ = 1
fP =
1 the modulator gain for DC. The frequency response of the
30 6.3V
0.048Ω
2πESR(COUT) 2πRLCOUT modulator is determined by multiplying the modulator
20 RL = 1.1Ω gain at DC times the frequency response of the output
10 fP = 45 capacitor and the load resistance. This is the same as
PHASE (DEG)
GAIN (dB)

12Hz 120Hz 27.6kHz

0 0
changing the 0dB gain reference on Figures 3 and 4 to the
modulator gain level. Consequently, the frequency
–10 –45
response of the modulator is primarily determined by the
–20 276Hz 1.2kHz –90
output capacitor and the load resistance.
–30 GAIN fZ = 2.76kHz –135
PHASE
–40
1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
AN76 F04

Figure 4. Frequency Response of Aluminum Electrolytic

Capacitor Used in 3.3V, 3A Power Supply Output

AN76-4
 Application Note 76
The Error Amplifier improve the high frequency response. This zero tends to
produce a positive-going bump in the phase plot. Ideally,
The error amplifier provides most of the loop gain. After
the peak of this bump is centered over the loop’s crossover
selecting the output capacitor, the control loop is compen-
frequency. The R1, C1 zero is located at:
sated by tailoring the frequency response of the error
amplifier. It has a transconductance of 1.4mS and an fZ = 1/(2πR1C1)
output resistance of 3MΩ, so it provides a low frequency The pole created by R2 and C2 is generally not critical for
gain of 4600 or 73dB. The loop gain is the product of the loop stability. It is frequently set at one half to one third of
error amplifier gain and the modulator gain, so the fre- the switching frequency and is primarily used for noise
quency response of the error amplifier, the output capaci- filtering rather than loop compensation. The effect of C2 is
tor and load resistor determine the frequency normally countered by the value of R3. The R2, C2 pole
response of the loop. frequency can be calculated by:
The AC behavior of the error amplifier is determined by C1, fP = 1/(2πR2C2)
C2, C3, C4, R1, R2 and R3 as shown in Figure 2. The
following relationships are given as a first approximation,
since there is some interaction between the parts. As an ITH PIN COMPONENT VALUES
example, the low frequency pole of the error amplifier is Selecting the best values for the loop compensation com-
the dominant pole and is determined primarily by C3 and ponents is not as simple as selecting pole and zero
the output resistance of the error amplifier as shown by: frequencies for the ideal crossover frequency. Several
fP = 1/(2πRO(EA)C3) other factors should be taken into account. The slew rate
and amplitude of the load transient largely determine the
However, R3 and C4 have a small effect on the actual ESR requirement of the output capacitor. The amount of
corner frequency, since the series combination of C3 and capacitance used at the output is primarily determined by
R3 are in parallel with C4, which is in parallel with RO(EA). the type of capacitor used and partially determined by the
Although all three impedances interact, the resistance of load transient characteristics.
R3 is small compared to the impedance of C3 at the pole
frequency, so its effect is small. The same is true of C4. PCB-generated noise can have a considerable effect on the
Since the value of C4 is normally small compared to C3, operation of a power supply. Problems caused by PCB
the primary effect is determined by C3. noise should be corrected by layout improvements but
this is not always possible. Proper decoupling and loop
Resistor R3 adds a zero to the frequency response to bandwidth limiting can significantly reduce the effects of
control gain in the midfrequency range. This zero fre- PCB noise on regulator operation. However, reducing loop
quency is: bandwidth will also reduce dynamic performance.
fZ = 1/(2πR3C3) Good transient response and PCB noise reduction are
Capacitor C4 adds a pole to reduce very high frequency opposing requirements when determining the values of
gain. Although frequently unnecessary for loop stability, the ITH pin components. The final loop compensation
C4 helps to filter the effects of PCB noise and output ripple must have good stability margins. There are no equations
voltage from the loop. It is desirable to have the error that will yield component values to optimize the loop
amplifier gain be less than zero dB at the switching transient response, give good PCB noise reduction and
frequency. The high frequency pole created by C4 is: provide the required stability margins. The equations
given for pole and zero frequencies are handy references
fP = 1/(2πR3C4) for predicting the effect a part change will have on the
The high frequency zero created by C1 and R1 can be very frequency response. Although gain can be calculated
important for transient load applications. Capacitor C1 reasonably accurately, phase calculations tend to have
provides phase lead and acts like a speed-up capacitor to large errors because of the many parasitics in the power
output voltage changes, so it tends to “short-out” R1 and path.

AN76-5
Application Note 76
The best procedure for optimizing the compensation com- goal is to obtain the best possible response from the
ponent values in your circuit is to start with the values that chosen power path components. If this doesn’t meet the
are recommended in the regulator data sheet. This will system requirements, the only solution is to add more
generally result in a stable, but probably less than optimal output capacitors (to reduce ESR) or lower the inductor
loop compensation. Check the output for any signs of loop value and live with the increased output ripple.
oscillation. If the loop is oscillating, try raising the value of In most cases, the final values selected for the loop
C4 to a large value, 0.01uF. This will most likely produce compensation components will be a compromise
a very sluggish but stable system to begin testing. Connect between the best transient performance and the best PCB
the load pulse test circuit of Figure 8 to the board and apply noise performance. Obviously, improving the board lay-
load steps approximately 25% of full load to see how the out to decrease PCB noise is preferred over reducing loop
loop responds to these perturbations. bandwidth. The OPTI-LOOP architecture lets the designer
If the response is not as desired, remove the ITH pin decide how to optimize his circuit and still meet loop
components R3, C3 and C4. Connect an RC substitution stability requirements. The final value set must provide
box, through a short twisted pair of wires, between the ITH adequate stability margins.
pin and SGND of the regulator. It is a good idea to
terminate the wires from the RC substitution box with a LARGE-SIGNAL vs SMALL-SIGNAL RESPONSE
47pF capacitor located at C4. Set the substitution box for As the load conditions change, the loop rapidly responds
a series RC connection. Then, by adjusting the values of R to the new requirements. The amount and rate of load
and C, you can dial in the optimal response. Read the change determines whether the loop response is called a
section “The Effect of Loop Compensation Components large-signal response or a small-signal response. The
on Large-Signal Transients” presented later and use difference between large-signal and small-signal response
Figures 9 through 21 as a guide in determining which way is whether the control loop maintains control of the output.
to vary R and C. Often this can be seen by looking at the output of the error
Avoid excessive ringing in the transient waveform. Point C amplifier. If the ITH pin voltage is between 0.3V and 2.4V,
in Figures 6 and 7 shows a single overshoot bump that is the loop is normally in control of the output and the load
acceptable. Two bumps constitute ringing which indicates variation creates a small-signal response. If the ITH pin
poor phase margin. Once satisfactory compensation is voltage is less than 0.3V or equal to 2.4V, the error
obtained, install the selected component values on the amplifier is “railed” and the regulator is not operating in a
board and verify the performance is similar to what was linear region. An exception to the 0.3V to 2.4V rule is when
obtained with the RC box. Due to the effects of noise the error amplifier is in slew limit. When the error amplifier
pickup and parasitics, there may be a little difference in the is in slew limit, it does not control the loop because the
behavior of the system using the substitution box com- load transient is occurring faster than the error amplifier
pared to using real parts on the board. can respond, so the output capacitors satisfy the transient
current until the inductor current can “catch up.” During
If stability margins cannot be measured, stable perfor- static operation the voltage on the ITH pin should be
mance can be predicted if each compensation component between 0.3V and 2.2V and is proportional to the load
value can be doubled or halved without causing excessive current.
ringing in the transient waveform. The last step in the
frequency compensation process should be to individu- The rules of loop compensation only apply to linear
ally change the values of C1, C2, C3, C4 and R3 to 50% and operation. Large-signal response temporarily takes the
to 200% of their final value. If one value causes excessive loop out of operation. However, the loop must respond
ringing because of this change, compensation component gracefully going into and out of large-signal response.
values should be revaluated. Large-signal response occurs when the amplitude and
rate of load current change are beyond what the supply can
One thing to keep in mind is that no amount of fiddling with respond to. The wider the loop bandwidth, the faster the
the compensation will make up for having inadequate load transient the loop can respond to.
output capacitors for the desired transient response. The

AN76-6
 Application Note 76
The regulator’s large-signal response is determined by the Most 3.3V supplies power digital and memory circuits
ESR of the output capacitor, the inductance of the induc- where the transients are fast, short in duration and vary
tor, the input voltage and the bandwidth of the control from miliamps to amps. The majority of digital circuit and
loop. When the load change requires a large-signal memory transients should be handled by local decoupling
response from the regulator, the slew rate of the error capacitors at each IC. Local IC decoupling slows down and
amplifier is very important. If R3 is too small or capacitors averages the actual transient load requirements of each
C3 or C4 are too large, it will take longer for the error IC so that the power supply control loop can handle the
amplifier’s output voltage to rail. During the time between perturbations.
the application of the load transient and the turn-on of the
top MOSFET, the output capacitor must supply all of the Core Voltage Supply
current required by the load. Current supplied by the The transient requirements of modern CPU core supplies
output capacitor develops a voltage drop across the ESR require large-signal response from the regulator. Conse-
that subtracts from the output voltage. The lower the ESR, quently, the entire core voltage supply should be opti-
the lower the voltage loss when the output capacitor mized for the needs of the CPU. The core voltage supply
supplies load current. should be located as close to the CPU as possible, operate
After the top MOSFET turns on, the higher the input voltage at the highest frequency possible with the lowest value of
and the lower the buck inductor value, the faster the output inductor possible and it should take its input power from
voltage will return to normal. The relationship of voltage, the 5V power supply rather than the raw battery voltage. By
current and inductance is shown as: operating the CPU regulator from the 5V supply, it can
switch at a much higher frequency with a lower inductor
L ∆I value and higher efficiency. By keeping the voltage step-
∆t =
EL down ratio relatively small, the loop dynamics can be
optimized.
where: EL is equal to VIN – VOUT, L = inductance value,
∆I = the inductor current change during ∆t, where ∆t = the Figure 5 shows the LTC1736 used as a core voltage
time required for the inductor current to increase to the regulator capable of supplying 10.2A from a 5V input
new load current level. supply at an output voltage selected by the five VID control
lines. Typical output voltages range from 1.3V to 1.6V.
A lower inductor value produces a higher output current Figure 6 shows a close-up of the large-signal response of
slew rate at the expense of higher output voltage ripple. the LTC1736 at the load. The load current changes from
0.2A to 10.2A in about 80ns. Point A shows the effect of
POWER SUPPLY TRANSIENT RESPONSE ESL and trace inductance between the power supply and
System Supplies the load. Point B shows the effect of the ESR of the output
capacitors and Point C shows where the buck inductor
One of the most important applications of the OPTI-LOOP current starts to supply load current.
architecture is loop compensation in transient load appli-
cations. The system supply in most products today Figure 7 shows a picture of the output voltage when the
includes 5V and 3.3V. Most load transients on 5V supplies load current rapidly changes from 10.2A to 0.2A. When the
are caused by digital circuits and motors. Digital circuit load current changes from full load to light load, the
transients are short in duration and vary from a few inductor current cannot change instantaneously so it
miliamps to several amps in amplitude. Load transients discharges its stored energy into the output capacitor,
caused by floppy drives and other motors range in current developing a voltage drop across the capacitor ESR and
from 0.5A to several amps during a period of 50ms to producing an ESL spike due to the fast change of the load
seconds, depending on how long it takes the motor to spin current. The ESL spike and the voltage drop across the
up. A properly designed circuit with adequate bandwidth ESR cause a temporary rise in output voltage.
can easily handle motor load transients.

AN76-7
Application Note 76

PGOOD R6, 100k

R7, 100k

C11
+ C12 + C13 INPUT
U1 150µF 150µF
LTC1736 0.1µF 5V
6.3V 6.3V
C6, 39pF 1 24 Q1, FDS6680A
COSC TG LOCATE
C7, 0.1µF 2 23 C8, 0.22µF R4 OUTPUT
RUN/SS BOOST CAPACITORS
0.004Ω 1.6V AT 10.2A
C3, 330pF 3 22 NEAR LOAD
ITH SW
C4, 100pF R3, 33k 4 21 D1 L1 R5 C18, C19
C16, C17
FCB VIN
CMDSH-3 0.78µH 10Ω
VOSENSE + 47µF +
180µF
5 20 10V
SGND INT VCC 4V
6 19
+ C9 C10 X5R
X2
C5, 1000pF
PGOOD BG 4.7µF 1µF Q2, Q3 + C14, C15 X2
7 18 FDS6680A 180µF
SENSE– PGND X2 4V
8 17
C2, 47pF SENSE + EXT VCC X2
C1,47pF 9 16
VFB VID VCC D2
10 15 MBRS340T3
VOSENSE VID4 VID4 C12, C13 = PANASONIC EEFUEOJ151R
11 14 C14 TO C17 = PANASONIC EEFUEOG181R
VID0 VID3 VID3 C18, C19 = TAIYO YUDEN LMK550BJ476KM
12 13 VID
VID1 VID2 VID2 L1 = COILCRAFT D05022-781HC
INPUT
R4 = IRC LRF2512-01-R004-J
VID1 U1 = LINEAR TECHNOLOGY LTC1736CG
VID0

AN76 F05

Figure 5. Core Voltage Supply with VID Control

C
B A

1.6V 1.6V
C
50mV/DIV 50mV/DIV
B

A: INDUCTANCE SPIKE A: INDUCTANCE SPIKE

B: ESR VOLTAGE DROP B: ESR VOLTAGE
C: INDUCTOR CURRENT TO LOAD C: INDUCTOR CURRENT = LOAD CURRENT
1µs/DIV 1µs/DIV
AN76 F06 AN76 F07

Figure 6. Close-Up View of Output Voltage During Figure 7. Close-Up View of Output Voltage During
Low Current-to-High Current Transistion High Current-to-Low Current Transistion

AN76-8
 Application Note 76
Inductance Delays Transient Response Measuring Transient Response
The load transient amplitude primarily determines the ESR Transient response should be measured across a ceramic
required for the output capacitors. However, the induc- capacitor as close to the input power pins of the CPU or
tance between the output capacitors and the CPU deter- other dynamic load as possible. Good high frequency
mines the initial voltage sag at the CPU. This inductance is measurement techniques are required. A common prac-
made up of the ESL of the output capacitors, trace induc- tice is to solder bus wire leads to the ends of a 1µF
tance and connector inductance. capacitor nearest the power pins on the CPU. Extend these
The core voltage regulator should be located very close to bus wire leads up from the board about 0.5". Disassemble
the CPU but some of the output capacitors should be the scope probe by removing the grabber so that the
located even closer. The trace lengths should be abso- ground ring and center pin are exposed. Carefully touch
lutely as short as possible between the power inputs of the the ground ring to the bus wire connected to the ground
CPU and the body of the bulk ceramic capacitors. These side of the 1µF capacitor and touch the probe center pin to
ceramic capacitors should be selected to supply the lead- the bus wire connected to the other side of the 1µF
ing edge transient current while the ESL of the other capacitor. This measurement technique will avoid most of
capacitors delays their contribution to the new load the signal pickup common to oscilloscope measurements
requirement. Additional low ESR tantalum or Specialty in noisy environments. Remember to check the transient
Polymer capacitors should be placed as close as possible response over the full range of input voltages and possible
to the ceramic capacitors. The rest of the output capacitors load current changes.
should be very close to the output of the core voltage For preliminary testing, try using the load pulser circuit
regulator, but still less than 0.5" away from the filter shown in Figure 8. It can be modified to test a wide variety
capacitors located at the CPU. of power supply circuits. Resistor R2 sets the minimum
A simple calculation shows the delaying effect of induc- load current while both R1 and R2 determine the maxi-
mum load current. Resistor R4 provides a 50Ω termina-
tance at transient speeds.
tion for the square wave generator that drives Q1. The slew
XL = 2πfL rate control, R3, controls the rate at which current is taken
where: XL is the impedance of inductance, f is the fre- from the power supply under test.
quency equal to 1/(actual load transition time) and L is the For breadboard testing with the load pulser, change the
inductance of interest. values of R1, R2 and R3 as required. Measure the transient
An XL of 1.25Ω can be calculated using the general rule of response across the last output capacitor using the raised-
20nH per inch of trace length, two 0.5" traces and a 100ns bus-wire and disassembled-scope-probe measurement
transition time. Since package inductances and trace technique.
inductance are in series with the ESR, the delaying effect R1
2.2Ω
of XL and ESR add to cause the leading edge voltage sag TO 3.3V 5W
SLEW RATE
at the load. After ESL and the trace inductance charge up OUTPUT
A CONTROL
to the output current, the voltage drop across the ESR R2 Q1
2.2Ω IRLZ44
continues to decrease the output voltage. The effects of 10W R3 R4 PULSE GENERATOR
10k 51Ω 100Hz TO 1kHz, 5V
ESR and XL are shown at points A and B in both Figures 6 GND AN76 F08

and 7. Clearly, series inductance must be very low (less

than 1nH) for these designs to operate successfully. Figure 8. Load Pulser Circuit

AN76-9
Application Note 76
The load pulser is a very simple circuit that can be used for
general purpose loop response testing. The disadvantage TRANSIENT CURRENT
0.2A TO 10.2A
of this circuit is the amount of inductance in the switched-
current loop. This inductance slows the load current slew
rate and causes ringing on the rising and falling edges.
This simple test circuit is useful for observing the settling 1.6V
50mV/DIV
performance of the control loop but will not give good
information on absolute transient response amplitude. A
much more sophisticated test setup is required to evaluate
this behavior. The best transient response testing can be
done with the real load on the final PCB. AN76 F09

Another benefit of the OPTI-LOOP architecture is that Figure 9. Transient Response with Normal
simple passive component value changes can be made to Compensation Values Shown on Schematic
fine tune the transient response and loop compensation
on the final board, at any point in the development pro- 50
gram, without board modifications. 40
LTC1736
VIN = 5V
C3 = 330pF
30 C4 = 100pF 180
The Effect of Loop Compensation Components on C1 = 47pF PHASE
20 MARGIN 120
Large-Signal Transients R3 = 33k

PHASE (DEG)
GAIN (dB)
47.1°
10 60
The circuit shown in Figure 5 was used to demonstrate the 0 CROSSOVER 0
effect of individually changing the loop compensation –10
FREQUENCY = 55kHz
–60
GAIN MARGIN
component values by a factor of 10. Figure 9 shows the –20 = –9.5dB –120
normal transient response with the values shown in the –30 – 180
schematic. The frequency response of this circuit is shown –40
in the Bode plot of Figure 10. The Bode plot indicates that 1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
this circuit has been optimized for fast transient response. AN76 F10

Figure 10. Bode Plot of LTC1736 Circuit

Figures 11 and 12 show the effects of changing C3 to 10pF
and 3300pF, respectively. This capacitor normally deter-
mines the low frequency pole of the error amplifier. As the
capacitance value goes down, the pole frequency goes up. TRANSIENT CURRENT
0.2A TO 10.2A
Figure 11 shows a slight additional ringing as the over-
shoot returns to normal. Figure 12 shows the effect of
decreasing the low frequency pole, thereby reducing the
low frequency gain. Although the peak-to-peak amplitude 50mV/DIV 1.6V

of the transient didn’t change, it took much longer for the

loop to return the output to normal. The Figure 13 Bode
plot shows that increasing C3 to 3300pF caused the phase
margin to drop from 47° down to 33° and decreased the
gain margin to – 7dB. AN76 F11

Figure 11. Transient Response with C3

Changed from 330pF to 10pF

AN76-10
 Application Note 76
TRANSIENT CURRENT
0.2A TO 10.2A
TRANSIENT CURRENT
0.2A TO 10.2A

50mV/DIV 1.6V

50mV/DIV 1.6V

AN76 F14

AN76 F12 Figure 14. Transient Response with R3

Changed from 33k to 330k
Figure 12. Transient Response with C3
Changed from 330pF to 3300pF

50
LTC1736
40 VIN = 5V TRANSIENT CURRENT
C3 = 3300pF 0.2A TO 10.2A
30 C4 = 100pF 180
C1 = 47pF PHASE 120
20
R3 = 33k MARGIN
PHASE (DEG)
GAIN (dB)

10 33° 60

0 CROSSOVER 0 50mV/DIV 1.6V

FREQUENCY = 56kHz
–10 GAIN MARGIN –60
= –7dB
–20 –120

–30 – 180

–40
1 10 100 1k 10k 100k 1M
AN76 F15
FREQUENCY (Hz)
AN76 F13

Figure 15. Transient Response with R3

Figure 13. Bode Plot of LTC1736 Circuit Changed from 33k to 3.3k
with C3 Changed from 330pF to 3300pF

50
LTC1736
40 VIN = 5V
Figures 14 and 15 show the effects of changing R3 to 330k 30
C3 = 330pF
C4 = 100pF 180
and 3.3k, respectively. This resistor sets the midfrequency 20
C1 = 47pF PHASE 120
R3 = 3.3k
PHASE (DEG)

MARGIN
gain and the zero frequency of the error amplifier. Increas-
GAIN (dB)

10 20.4° 60
ing R3 to 330k increased the midfrequency gain and 0 CROSSOVER 0
decreased the zero frequency without much effect on the –10
FREQUENCY = 28.8kHz
–60
transient response. Decreasing R3 to 3.3k increased the –20 –120
zero frequency and decreased the midfrequency gain, –30
GAIN MARGIN
– 180
= –26dB
which caused high frequency ringing and an increase in –40
peak-to-peak transient response. The high frequency ring- 1 10 100 1k 10k 100k 1M
FREQUENCY (Hz)
ing is an indication that the phase margin is dangerously AN76 F16

low. Figure 16 shows a phase margin of 20.4° and a gain Figure 16. Bode Plot of LTC1736 Circuit
margin of – 26dB. This increase in gain margin cannot with R3 Changed from 33k to 3.3k
improve circuit stability with a phase margin of 20.4°.

AN76-11
Application Note 76
Figures 17 and 18 show the effects of changing C4 to 10pF
and 1000pF, respectively. This capacitor normally deter- TRANSIENT CURRENT
0.2A TO 10.2A
mines the high frequency pole of the error amplifier.
Decreasing C4 to 10pF increased the high frequency pole
but had little effect on the transient response. This will
make the circuit more susceptible to noise however. By 50mV/DIV 1.6V
increasing C4 to 1000pF, the high frequency pole
decreased so far that the peak-to-peak transient response
doubled, with significant high frequency ringing on the
rising and falling edges of the transient waveform. Figure
19 shows a phase margin of 14.4°, about 30% of the phase - DSOL8 F18

margin obtained when C4 = 100pF. Figure 18. Transient Response with C4

Changed from 100pF to 1000pF
Figures 20 and 21 show the effects of changing C1 to 5pF
and 470pF. This capacitor provides a little phase lead to
50
improve transient response. No change is apparent when LTC1736
the value drops to 5pF but a slight improvement in peak- 40 VIN = 5V
C3 = 330pF
to-peak transient response can be observed when the 30 C4 = 1000pF 180
C1 = 47pF
value is increased to 470pF. 20
R3 = 33k
PHASE 120

PHASE (DEG)
MARGIN

GAIN (dB)
10 14.4° 60
These waveforms show the type of changes that occur as
0 CROSSOVER 0
one value is changed at a time. No damage will occur to the FREQUENCY = 18.6kHz
–10 –60
circuit or the load if the incremental changes are within a
–20 –120
10-to-1 range. If the top feedback resistor is open, the GAIN MARGIN
–30 – 180
connection to the VOSENSE pin is opened or the ITH pin is = –24dB
–40
pulled high, the output voltage will increase until it equals 1 10 100 1k 10k 100k 1M
the input voltage. Care should be taken to avoid this FREQUENCY (Hz)
AN76 F19

condition because output capacitors can be damaged, Figure 19. Bode Plot of LTC1736 Circuit
load resistors overtaxed or CPUs destroyed. with C4 Changed from 100pF to 1000pF

TRANSIENT CURRENT TRANSIENT CURRENT

0.2A TO 10.2A 0.2A TO 10.2A

50mV/DIV 1.6V 50mV/DIV 1.6V

AN76 F17 DSOL8 F20

Figure 17. Transient Response with C4 Figure 20. Transient Response with C1
Changed from 100pF to 10pF Changed from 47pF to 5pF

AN76-12
 Application Note 76
TRANSIENT CURRENT Oscilloscope photos and Bode plots are included in
0.2A TO 10.2A
Figures 22 and 23, illustrating the benefit of the OPTI-
LOOP architecture for the LTC1628 5V output using the
basic circuit in Figure 24. The compensation components
50mV/DIV 1.6V are changed as indicated in each figure for different values
and types of output capacitor. The top two waveforms in
each photo are the output voltage at the vertical sensitivity
indicated in the top left corner and the output current at 1
ampere per division with a time scale of 100µs per divi-
AN76 F21
sion. The lower two traces are the same as above but at a
Figure 21. Transient Response with C1 time scale of 5µs per division. A 0.5A to 2A load step is
Changed from 47pF to 470pF used for a typical transient condition. The expanded scale
indicates the response time of the switching regulator is
Common Values for System Supply Compensation normally several microseconds. A 47µF capacitor having
low ESR offers a very acceptable output capacitor solution
The dual version of the LTC1735, the LTC1628, shares the
in applications requiring lowest cost and/or size. A 100µF
identical control circuitry of the LTC1735 and as such, has
capacitor can be used where an extra margin of stability
some distinct advantages over previous system power
and low ripple voltage are required. The 150µF to 220µF
(5V and 3.3V) solutions. In addition, the LTC1628 oper-
capacitance may be required in applications that require
ates the two controller top switches 180° out of phase to
extremely low ESR for zero to full designed load current
minimize RMS input current. Since the system power
transient steps. Using two small 47µF capacitors provide
requirements are less stringent than the CPU core require-
stability, low ESR and a margin of safety in the event of a
ments, OPTI-LOOP architecture allows the use of signifi-
single capacitor failure.
cantly smaller output capacitors than were previously
required. Special Polymer capacitors offer extremely low Table 1 lists suggested OPTI-LOOP compensation values
ESR but have less capacitance density than other capaci- for other types of output capacitors. Figure 24 was also
tor types. OPTI-LOOP compensation provides the key to used to verify the selected values in Table 1. Final compen-
using the small capacitance values while providing ex- sation value selection should be fine tuned after the PC
tremely good performance, small physical size, and low layout is done since the quality of the layout will affect the
overall cost. loop behavior.

AN76-13
Application Note 76
47µF Panasonic SP 100µF Panasonic SP 150µF Panasonic SP

VO = 5V VO = 5V VO = 5V
100mV/DIV 50mV/DIV 50mV/DIV
IO IO IO
1A/DIV 1A/DIV 1A/DIV

VO = 5V VO = 5V VO = 5V
100mV/DIV 50mV/DIV 50mV/DIV
IO IO IO
1A/DIV 1A/DIV 1A/DIV

60 180 60 180 60 180

50 160 50 160 50 160

GAIN
40 120 40 120 40 120

30 90 30 90 30 90
PHASE (DEG)

PHASE (DEG)
PHASE (DEG)
PHASE GAIN PHASE
GAIN (dB)

GAIN (dB)
GAIN (dB)

20 60 20 60 20 60
PHASE GAIN
10 30 10 30 10 30

0 VIN = 15V 0 0 VIN = 15V 0 0 VIN = 15V 0

VO = 5V VO = 5V VO = 5V
–10 –30 –10 –30 –10 –30
IO = 3A IO = 3A IO = 3A
–20 C8 = 470pF –60 –20 C8 = 220pF –60 –20 C8 = 100pF –60
R8 = 6.8k R8 = 15k R8 = 15k
–30 –90 –30 –90 –30 –90
100 1k 10k 100k 1M 100 1k 10k 100k 1M 100 1k 10k 100k 1M
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)
AN76F22a2 AN76F22b2 AN76F22c2

Figure 22. LTC1628 Transient Response and Frequency Response with Panasonic SP Capacitors

47µF Sanyo OS-CON 120µF Sanyo OS-CON 220µF Sanyo OS-CON

VO = 5V VO = 5V VO = 5V
100mV/DIV 50mV/DIV 50mV/DIV
IO IO
IO
1A/DIV 1A/DIV
1A/DIV

VO = 5V VO = 5V VO = 5V
100mV/DIV 50mV/DIV 50mV/DIV
IO IO IO
1A/DIV 1A/DIV 1A/DIV

60 180 60 180 60 180

50 160 50 160 50 160

40 120 40 120 40 120

30 90 30 90 30 90
PHASE (DEG)

PHASE (DEG)
PHASE (DEG)
GAIN (dB)

GAIN (dB)
GAIN (dB)

20 60 20 60 20 60
PHASE GAIN PHASE GAIN PHASE
GAIN
10 30 10 30 10 30

0 VIN = 15V 0 0 VIN = 15V 0 0 VIN = 15V 0

VO = 5V VO = 5V VO = 5V
–10 –30 –10 –30 –10 –30
IO = 3A IO = 3A IO = 3A
–20 C8 = 330pF –60 C8 = 150pF –20 C8 = 100pF –60
–20 –60
R8 = 10k R8 = 10k R8 = 10k
–30 –90 –30 –90 –30 –90
100 1k 10k 100k 1M 100 1k 10k 100k 1M 100 1k 10k 100k 1M
FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)
AN76F23a2 AN76F23b2 AN76F23c2

Figure 23. LTC1628 Transient Response and Frequency Response with Sanyo OS-CON Capacitors

AN76-14
 C5,0.1µF
1 28
RUN/SS1 FLTCPL
C13,180pF L1,8µH
R9 2 27 R1,0.015Ω VOUT1
1M SENSE + TG1 5V
C11 4A PK
1000pF 3 26
SENSE1– SW1
R5 R3,105k,1% C3
20k,1% 4 25 0.1µF Q1a
VOSENSE1 BOOST1
Q1b D1
R12 5 24 MBRM
1M FREQSET VIN 140T3
6 23 R11,10Ω
STBYMD BG1
C1,150µF,6V
R10 7 22 C18 +
FCB EXTVCC D3 22µF
1M C7,100pF U1 0.1µF
R7,15k 50V SP CAP
8 LTC1628 21 + C16
ITH1 INTVCC GND
C9 C15 4.7µF C2,180µF,4V
33pF 9 20 1µF D4 +
SGND PGND
C20 C21 C19 SP CAP VIN
TP1 0.01µF × 3 10 19 5V TO
3.3V 3.3VOUT BG2 30V
LDO C10 C8,100pF Q2a Q2b
R8,15k 33pF 11 18 D2
ITH2 BOOST2 MBRM
C4
12 17 0.1µF 140T3
TP2
5V VOSENSE2 SW2
R6,20k,1% R4,63.4k,1% 13 16 L2,8µH R2,0.015Ω VOUT2
SENSE2– TG2 3.3V
C12 4A PK
1000pF 14 15
SENSE2+ RUN/SS2
C6,0.1µF
C14,180pF

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
AN76 F22

SWITCHING FREQUENCY = 300kHz

D3, D4 = CMDSH-3TR
L1, L2 = SUMIDA CEP123-8ROMC
Q1, Q2 = FDS8936A

Figure 24. Dual Output System Supply for 5V and 3.3V

Application Note 76

AN76-15
Application Note 76

Table 1. Output Capacitor and Compensation on DC236A (LTC1628 Demo Board)

Test Conditions: VIN =15V, VOUT = 3.3V/3A,
Switching Frequency = 265kHz, Load Step = 1.5A to 2.6A
Compensation
Output Capacitor C13,C14 C7,C8 R7,R8 C9,C10
Panasonic SP 47µF/6.3V*1 27pF 100pF 22k 33pF
Sanyo Oscon 47µF/6.3V*1 27pF 470pF 15k 33pF
Sanyo Poscap TPC 150µF/4V*1 27pF 100pF 22k 33pF
Sanyo Poscap TPC 100µF/6V*1 27pF 100pF 22k 33pF
Sanyo Poscap TPC 68µF/10V*1 27pF 100pF 22k 33pF
AVX Tantalum TPS 220µF/6.3V+10µF Ceramic 27pF 100pF 33k 33pF
Test Conditions: VIN =15V, VOUT = 3.3V/3A,
Switching Frequency = 265kHz, Load Step = 0A to 2A
Panasonic SP 56µF/4V*1 100pF 150pF 15k 33pF
Test Conditions: VIN =15V, VOUT = 3.3V/3A,
Switching Frequency = 265kHz, Load Step = 0.5A to 3A
Panasonic SP*2 56µF/4V+10µF Ceramic 27pF 100pF 22k 33pF
Sanyo Oscon 150µF/6.3V+10µF Ceramic 27pF 100pF 22k 33pF
Sanyo Poscap TPC 150µF/4V*1 + Cer 10µF*2 27pF 100pF 33k 33pF
Sanyo Poscap TPB 150µF/6.3V*2 + Cer 10µF*2 27pF 100pF 33k 33pF
AVX Tantalum TPS 220µF/6.3V*1 + Cer 10µF*1 27pF 100pF 33k 33pF
AVX Tantalum TPS 330µF/6.3V*1+ Cer 10µF*1 27pF 100pF 33k 33pF

CONCLUSION
Control loop compensation is a very involved subject. The inside a regulator IC can lead to loop oscillation under
ability to improve the output voltage transient response is certain conditions is valid, since the loop frequency
quite valuable. Optimizing circuit performance for tran- response varies so much with different types of output
sient load applications without constraints on output capacitors. The OPTI-LOOP architecture provides the
capacitors allows the designer to get the most out of the mechanism for obtaining the maximum performance from
power components. The fear that fixed compensation the lowest cost power supply.

an76 LT/TP 0599 4K • PRINTED IN USA

Linear Technology Corporation
AN76-16 1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● [Link]  LINEAR TECHNOLOGY CORPORATION 1999