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TMS4464 Dynamic RAM Overview

The document discusses different types of memory including ROM, EPROM, SRAM, and DRAM. It describes the common components of memory devices including address, data, selection, and control pins. It provides details on ROM, EPROM, SRAM, and DRAM operation and refresh requirements. Examples of 2716 EPROM and TMS4464 DRAM chips are described.

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0% found this document useful (0 votes)
59 views19 pages

TMS4464 Dynamic RAM Overview

The document discusses different types of memory including ROM, EPROM, SRAM, and DRAM. It describes the common components of memory devices including address, data, selection, and control pins. It provides details on ROM, EPROM, SRAM, and DRAM operation and refresh requirements. Examples of 2716 EPROM and TMS4464 DRAM chips are described.

Uploaded by

720manas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Microprocessors & Interfacing

Memory Interface
BITS Pilani Dr. Gargi Prabhu
Pilani Campus
Department of CS & IS
Common types of memory

• Read-only memory (ROM)


• Flash memory (EEPROM)
• Static random access memory (SRAM)
• Dynamic random access memory (DRAM)

BITS Pilani, Pilani Campus


Memory Device

Pin connections common to


all memory devices are:
• Address inputs
• Data outputs or input/
outputs
• Some type of selection
input
• At least one control input
used to select a read or
write operation

BITS Pilani, Pilani Campus


Address Connections

• A 1K memory device has 10 address pins (A0–A9)


• 10 address inputs are required to select any of its 1024
memory locations
• It takes a 10-bit binary number (1024 different combinations)
to select any single location on a 1024-location device

BITS Pilani, Pilani Campus


Data Connections

• All memory devices have a set of data outputs or


input/outputs.

• The data connections are the points at which data are entered
for storage or extracted for reading.

• Data pins on memory devices are labeled D0 through D7 for


an 8-bit-wide memory

• An 8-bit-wide memory device is often called a byte-wide


memory

BITS Pilani, Pilani Campus


Selection Connections

• Each memory device has an input—sometimes more than


one—that selects or enables the memory device.
• This type of input is most often called a chip select (CS’ ), chip
enable (CE’ ), or simply select ( S’) input.
• RAM memory generally has at least one CS’ or S’ input, and
ROM has at least one CE’ .
• If the CS’,S’,CE’ or input is active (a logic 0), the memory
device performs a read or write operation; if it is inactive (a
logic 1), the memory device cannot do a read or a write
because it is turned off or disabled.
• If more than one connection is present, all must be activated
to read or write data

BITS Pilani, Pilani Campus


Control Connections

• All memory devices have some form of control input or


inputs.
• A ROM usually has only one control input, while a RAM often
has one or two control inputs.
ROM - output enable (OE’) or gate (G’)
- OE’ and CE’ are both active, output is enabled

RAM – R/W’ along with CS’ – can read and write


- WE’ and OE’( or G’) – can read and write

BITS Pilani, Pilani Campus


ROM

• Read-only memory (ROM) permanently stores programs and


data that are resident to the system and must not change
when power supply is disconnected.

• Known as nonvolatile memory

• ROM is often used to store firmware, BIOS, and other critical


system software that needs to be permanently stored and not
modified during normal operation

BITS Pilani, Pilani Campus


EPROM

• EPROM (erasable programmable read-only memory), a type


of ROM, is more commonly used when software must be
changed often

• EPROM is erasable if exposed to high-intensity ultraviolet light


for about 20 minutes or so, depending on the type of EPROM

• EPROMs are used in applications where occasional updates or


changes to the stored data are necessary but not frequent
enough to warrant the use of EEPROM or flash memory.

BITS Pilani, Pilani Campus


2716, 2K*8 EPROM

BITS Pilani, Pilani Campus


How chip is connected

BITS Pilani, Pilani Campus


The timing diagram of 2716 EPROM

BITS Pilani, Pilani Campus


Memory Access Time

• TACC is measured from the appearance of the address at the


address inputs until the appearance of the address at the
address output

• Basic speed of EPROM is 450 ns

• Wait states are required to ensure smooth operations.

BITS Pilani, Pilani Campus


Static RAM

• Static RAM memory devices retain data for as long as DC


power is applied.
• Because no special action (except power) is required to retain
stored data, these devices are called static memory.
• Also called volatile memory because they will not retain data
without power.

BITS Pilani, Pilani Campus


Dynamic RAM (DRAM) Memory

• DRAM is essentially the same as SRAM, except that it retains


data for only 2 or 4 ms on an integrated capacitor
• In DRAM, the entire contents of the memory are refreshed
with 256 reads in a 2- or 4-ms interval
• Refreshing also occurs during a write, a read, or during a
special refresh cycle
• DRAM is widely used as the main memory in computers and
other digital devices due to its cost-effectiveness and high
storage capacity.
• Another disadvantage of DRAM memory is that it requires so
many address pins that the manufacturers have decided to
multiplex the address inputs.

BITS Pilani, Pilani Campus


TMS4464, 64K × 4 dynamic RAM

BITS Pilani, Pilani Campus


Address multiplexer for the
TMS4464 DRAM

BITS Pilani, Pilani Campus


References

• [Link]

BITS Pilani, Pilani Campus


BITS Pilani
Pilani Campus

Thank You

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