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MPC5510

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0% found this document useful (0 votes)

136 views54 pages

MPC5510

Uploaded by

Rafael Esteban Nieto Naranjo

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

Freescale Semiconductor Document Number: MPC5510

Data Sheet: Technical Data Rev. 3, 3/2009

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
MAPBGA–208
MAPBGA–225 LQFP–144
QFN12
17
15 mm
mm xx 17
15 mm
mm 20 mm x 20 mm
##_mm_x_##mm

LQFP–176
MPC5510 Microcontroller SOT-343R
24 mm x 24 mm
PKG-TBD

Family Data Sheet

##_mm_x_##mm
TBD ## mm x ## mm

MPC5510 Family Features • Up to 144 configurable general purpose pins supporting

• Single issue, 32-bit CPU core complex (e200z1) input and output operations and 3.0V through 5.5V supply
– Compliant with the Power Architecture™ embedded levels
category • Real-time counter (RTC_API) with clock source from
– Includes an instruction set enhancement allowing external 32-kHz crystal oscillator, internal 32-kHz or
variable length encoding (VLE) for code size footprint 16-MHz oscillator and supporting wake-up with selectable
reduction. With the optional encoding of mixed 16-bit 1-second resolution and > 1-hour timeout, or 1-millisecond
and 32-bit instructions, it is possible to achieve resolution with maximum timeout of one second
significant code size footprint reduction. • Up to eight periodic interrupt timers (PIT) with 32-bit
• Up to 1.5-Mbyte on-chip flash with flash control unit counter resolution
(FCU) • Nexus development interface (NDI) per IEEE-ISTO
• Up to 80 Kbytes on-chip SRAM 5001-2003 Class Two Plus standard
• Memory protection unit (MPU) with up to sixteen region • Device/board test support per Joint Test Action Group
descriptors and 32-byte region granularity (JTAG) of IEEE (IEEE 1149.1)
• Interrupt controller (INTC) capable of handling • On-chip voltage regulator (VREG) for regulation of 5V
selectable-priority interrupt sources input to 1.5V and 3.3V internal supply levels
• Frequency modulated Phase-locked loop (FMPLL) • Optional e200z0, second Power Architecture based I/O
• Crossbar switch architecture for concurrent access to processor with VLE instruction set
peripherals, flash, or RAM from multiple bus masters • Optional FlexRAY controller
• 16-channel enhanced direct memory access controller • Optional external bus interface (EBI) module
(eDMA)
• Boot assist module (BAM) supports internal flash
programming via a serial link (CAN or SCI)
• Timer supports input/output channels providing a range of
16-bit input capture, output compare, and pulse width
modulation functions (eMIOS200)

MPC5566 and MPC5567 products in 496 MAPBGA packages

• Up to 40-channel 12-bit analog-to-digital converter (ADC)
• Up to four serial peripheral interface (DSPI) modules
• Media Local Bus (MLB) emulation logic (works with two
DSPIs, the e200z0, the eDMA, and system RAM to create
a 3-pin or 5-pin 256Fs MLB protocol)
• Up to eight serial communication interface (eSCI) modules
• Up to six enhanced full CAN (FlexCAN) modules with
configurable buffers
• One inter IC communication interface (I2C) module

This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2007-2009. All rights reserved.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the
Table of Contents
1 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .4 Table 13. 5V Low Frequency (32 kHz) Internal RC Oscillator . . . 32

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
1.1 Signal Properties and Multiplexing Summary . . . . . . . . .4 Table 14. FMPLL Electrical Specifications . . . . . . . . . . . . . . . . . 33
1.2 Power and Ground Supply Summary . . . . . . . . . . . . . .15 Table 15. eQADC Conversion Specifications (Operating) . . . . . . 34
1.3 Pinout – 144 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 16. Flash Program and Erase Specifications . . . . . . . . . . . 35
1.4 Pinout – 176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 17. Flash EEPROM Module Life (Full Temperature Range) 35
1.5 Pinout – 208 PBGA. . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 18. Pad AC Specifications (VDDE = 3.0V - 5.5V) . . . . . . . 36
2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Table 19. Reset and Boot Configuration Timing . . . . . . . . . . . . . 37
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Table 20. IRQ/NMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .21 Table 21. JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.2.1 General Notes for Specifications at Maximum Table 22. Nexus Debug Port Timing . . . . . . . . . . . . . . . . . . . . . . 41
Junction Temperature . . . . . . . . . . . . . . . . . . . .21 Table 23. External Bus Operation Timing . . . . . . . . . . . . . . . . . . 43
2.3 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 24. eMIOS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .25 Table 25. DSPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.5 Operating Current Specifications . . . . . . . . . . . . . .27 Table 26. Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.6 I/O Pad Current Specifications . . . . . . . . . . . . . . . . . . .29 Table 27. Revision History of MPC5510 Data Sheet . . . . . . . . . . 53
2.7 Low Voltage Characteristics . . . . . . . . . . . . . . . . . . . . .30
2.8 Oscillators Electrical Characteristics. . . . . . . . . . . . . . .31 List of Figures
2.9 FMPLL Electrical Characteristics . . . . . . . . . . . . . . . . .33 Figure 1. MPC5510 Family Block Diagram . . . . . . . . . . . . . . . . . . 3
2.10 eQADC Electrical Characteristics . . . . . . . . . . . . . . . . .34 Figure 2. MPC5510 Pinout – 144 LQFP . . . . . . . . . . . . . . . . . . . 17
2.11 Flash Memory Electrical Characteristics. . . . . . . . . . . .35 Figure 3. MPC5510 Pinout – 176 LQFP . . . . . . . . . . . . . . . . . . . 18
2.12 Pad AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . .36 Figure 4. MPC5510 Pinout – 208 PBGA . . . . . . . . . . . . . . . . . . . 19
2.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Figure 5. Pad Output Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.13.1 Reset and Boot Configuration Pins . . . . . . . . . .37 Figure 6. Reset and Boot Configuration Timing. . . . . . . . . . . . . . 37
2.13.2 External Interrupt (IRQ) and Non-Maskable Figure 7. IRQ and NMI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Interrupt (NMI) Pins . . . . . . . . . . . . . . . . . . . . .37 Figure 8. JTAG Test Clock Input Timing. . . . . . . . . . . . . . . . . . . . 38
2.13.3 JTAG (IEEE 1149.1) Interface . . . . . . . . . . . . . .38 Figure 9. JTAG Test Access Port Timing . . . . . . . . . . . . . . . . . . . 39
2.13.4 Nexus Debug Interface . . . . . . . . . . . . . . . . . . .41 Figure 10. JTAG JCOMP Timing . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.13.5 External Bus Interface (EBI) . . . . . . . . . . . . . . .43 Figure 11. JTAG Boundary Scan Timing . . . . . . . . . . . . . . . . . . . 40
2.13.6 Enhanced Modular I/O Subsystem (eMIOS) . . .46 Figure 12. Nexus Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.13.7 Deserial Serial Peripheral Interface (DSPI) . . . .47 Figure 13. Nexus TDI, TMS, TDO Timing . . . . . . . . . . . . . . . . . . 42
3 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Figure 14. CLKOUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Figure 15. Synchronous Output Timing . . . . . . . . . . . . . . . . . . . . 44
4.1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Figure 16. Synchronous Input Timing . . . . . . . . . . . . . . . . . . . . . 45
Figure 17. Address Latch Enable (ALE) Timing . . . . . . . . . . . . . 46
List of Tables Figure 18. DSPI Classic SPI Timing — Master, CPHA = 0 . . . . . 48
Table 1. MPC5510 Signal Properties . . . . . . . . . . . . . . . . . . . . . . .4 Figure 19. DSPI Classic SPI Timing — Master, CPHA = 1 . . . . . 48
Table 2. MPC5510 Power/Ground . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 20. DSPI Classic SPI Timing — Slave, CPHA = 0 . . . . . . 49
Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . .20 Figure 21. DSPI Classic SPI Timing — Slave, CPHA = 1 . . . . . . 49
Table 4. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .21 Figure 22. DSPI Modified Transfer Format Timing — Master,
Table 5. ESD Ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 6. DC Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . .25 Figure 23. DSPI Modified Transfer Format Timing — Master,
Table 7. Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 8. I/O Pad Average DC Current . . . . . . . . . . . . . . . . . . . . . .29 Figure 24. DSPI Modified Transfer Format Timing — Slave, CPHA = 0

MPC5566 and MPC5567 products in 496 MAPBGA packages

Table 9. Low Voltage Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . .30 51
Table 10. 3.3V High Frequency External Oscillator. . . . . . . . . . . .31 Figure 25. DSPI Modified Transfer Format Timing — Slave, CPHA = 1
Table 11. 5V Low Frequency (32 kHz) External Oscillator . . . . . .31 51
Table 12. 5V High Frequency (16 MHz) Internal RC Oscillator . . .32 Figure 26. DSPI PCS Strobe (PCSS) Timing . . . . . . . . . . . . . . . 51

MPC5510 Microcontroller Family Data Sheet, Rev. 3

2 Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the
Oscillators FMPLL VREG
e200z1 Core MPC5510
General Purpose

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
Registers
Integer (32 x 32-bit)
Execution e200z0 Core General Purpose
INTC
Unit Registers
Timers Integer (32 x 32-bit)
Execution
Multiply JTAG Unit
Unit Branch
Unit
NDI Multiply
Instruction Unit Branch
Unit Load/Store Unit
PPC & VLE Unit
Instruction Load/Store
Unit
FlexRay eDMA Unit
VLE
Instruction Bus Data Bus

Crossbar Switch (XBAR)

Private
Instruction Memory Protection Unit (MPU)
Bus

Peripheral Bridge RAM

FCU Controller
EBI

Flash eSCI DSPI FlexCAN SRAM

(ECC) (ECC)

ADC I2C BAM

eMIOS200 SIU PIT

MLB

MPC5566 and MPC5567 products in 496 MAPBGA packages

LEGEND
ADC – Analog to Digital Converter modules FlexRay – Dual Channel FlexRay controller
BAM – Boot Assist Module FMPLL – Frequency Modulated Phase Locked Loop module
EBI – External Bus Interface module I 2C – Inter IC Controller modules
ECC – Error Correction Code INTC – Interrupt Controller module
DSPI – Serial Peripherals Interface controller module JTAG – Joint Test Action Group interface
eDMA – enhanced Direct Memory Controller module MLB – Media Local Bus emulation logic
eMIOS200 – Timed Input Output module NDI – Nexus Debug Interface module
eSCI – Serial Communications Interface modules PIT – Periodic Interrupt Timer module
FCU – Flash Controller Unit SIU – System Integration module
FlexCAN – Controller Area Network controller modules VREG – Voltage Regulator

Figure 1. MPC5510 Family Block Diagram

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 3
Pin Assignments and Reset States

1 Pin Assignments and Reset States

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
Table 1 shows the signal properties for each pin on the MPC5510. For all port pins, which have an associated pad configuration
register (SIU_PCRn register) to control its pin properties, the “Supported Pin Functions” column lists the functions associated
with the programming of the SIU_PCRn[PA] bit field in the following order: GPIO, Function1, Function2 and Function3. If
fewer than three functions plus GPIO are supported by a given pin, then the unused functions begin with Function3, then
Function2, then Function1. Note that the GPIO number is the same number as the corresponding pad configuration register
(SIU_PCRn) number.
Table 1. MPC5510 Signal Properties

Package Pin
GPIO Status Status
Pin Supported I/O Pad4 Locations
(PCR) 2 Description Voltage3 During After
Name Functions Type Type
Num1 Reset5 Reset5
144 176 208

Port A (16)

PA0 GPI I
PA0 0 VDDA AE + IH — — 9 9 E3
AN0 eQADC Analog Input I

PA1 GPI I
PA1 1 VDDA AE + IH — — 8 8 E2
AN1 eQADC Analog Input I

PA2 GPI I
PA2 2 VDDA AE + IH — — 7 7 E1
AN2 eQADC Analog Input I

PA3 GPI I
PA3 3 VDDA AE + IH — — 6 6 D3
AN3 eQADC Analog Input I
PA4 GPI I
PA4 4 VDDA AE + IH — — 5 5 D2
AN4 eQADC Analog Input I

PA5 GPI I
PA5 5 VDDA AE + IH — — 4 4 D1
AN5 eQADC Analog Input I

PA6 GPI I
PA6 6 VDDA AE + IH — — 3 3 C2
AN6 eQADC Analog Input I
PA7 GPI I
PA7 7 VDDA AE + IH — — 2 2 C1
AN7 eQADC Analog Input I

PA8 GPI I
PA8 8 VDDA AE + IH — — 143 175 A3
AN8/ANW eQADC Analog Input I

PA9 GPI I

MPC5566 and MPC5567 products in 496 MAPBGA packages

PA9 9 VDDA AE + IH — — 142 174 C4
AN9/ANX eQADC Analog Input I
PA10 GPI I
PA10 10 VDDA AE + IH — — 140 172 D5
AN10/ANY eQADC Analog Input I

PA11 GPI I
PA11 11 VDDA AE + IH — — 139 171 C5
AN11/ANZ eQADC Analog Input I

PA12 GPI I
PA12 12 VDDA AE + IH — — 138 170 B5
AN12 eQADC Analog Input I
PA13 GPI I
PA13 13 VDDA AE + IH — — 137 169 A5
AN13 eQADC Analog Input I

PA14 GPI I
PA14 14 AN14 eQADC Analog Input I VDDA AE + IH — — 136 167 D6
EXTAL326 32 kHz Crystal Oscillator Input I

MPC5510 Microcontroller Family Data Sheet, Rev. 3

4 Freescale Semiconductor
Pin Assignments and Reset States

Table 1. MPC5510 Signal Properties (continued)

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the
Package Pin
GPIO Status Status
Pin Supported I/O Pad4 Locations
(PCR) 2 Description Voltage3 During After
Name 1 Functions Type Type

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
Num Reset5 Reset5
144 176 208

PA15 GPI I
PA15 15 AN15 eQADC Analog Input I VDDA AE + IH — — 135 165 C6
XTAL326 32 kHz Crystal Oscillator Output O

Port B (16)

PB0 GPIO I/O

AN28 eQADC Analog Input7 I
PB0 16 VDDE1 A + SH — — 134 162 C7
eMIOS16 eMIOS Channel O
PCS_C5 DSPI_C Peripheral Chip Select O
PB1 GPIO I/O
AN29 eQADC Analog Input7 I
PB1 17 VDDE1 A + SH — — 133 161 D7
eMIOS17 eMIOS Channel O
PCS_C4 DSPI_C Peripheral Chip Select O

PB2 GPIO I/O

AN30 eQADC Analog Input7 I
PB2 18 VDDE1 A + SH — — 132 160 A8
eMIOS18 eMIOS Channel O
PCS_C3 DSPI_C Peripheral Chip Select O

PB3 GPIO I/O

PB3 19 AN31 eQADC Analog Input7 I VDDE1 A + SH — — 131 159 B8
PCS_C2 DSPI_C Peripheral Chip Select O

PB4 GPIO I/O

PB4 20 AN32 eQADC Analog Input7 I VDDE1 A + SH — — 130 158 C8
PCS_C1 DSPI_C Peripheral Chip Select O

PB5 GPIO I/O

PB5 21 AN33 eQADC Analog Input7 I VDDE1 A + SH — — 129 157 D8
PCS_C0 DSPI_C Peripheral Chip Select I/O

PB6 GPIO I/O

PB6 22 AN34 eQADC Analog Input7 I VDDE1 A + SH — — 128 156 A9
SCK_C DSPI_C Clock I/O

PB7 GPIO I/O

PB7 23 AN35 eQADC Analog Input7 I VDDE1 A + SH — — 127 153 B9
SOUT_C DSPI_C Data Output O

PB8 GPIO I/O

PB8 24 AN36 eQADC Analog Input7 I VDDE1 A + SH — — 126 152 C9

MPC5566 and MPC5567 products in 496 MAPBGA packages

SIN_C DSPI_C Data Input I

PB9 GPIO I/O

AN37 eQADC Analog Input7 I
PB9 25 VDDE1 A + SH — — 125 151 D9
CNTX_D CAN_D Transmit O
PCS_B4 DSPI_B Peripheral Chip Select O

PB10 GPIO I/O

AN38 eQADC Analog Input7 I
PB10 26 VDDE1 A + SH — — 124 150 A10
CNRX_D CAN_D Receive I
PCS_B3 DSPI_B Peripheral Chip Select O
PB11 GPIO I/O
AN39 eQADC Analog Input7 I
PB11 27 VDDE1 A + SH — — 123 149 B10
eMIOS19 eMIOS Channel O
PCS_B5 DSPI_B Peripheral Chip Select O

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 5
Pin Assignments and Reset States

Table 1. MPC5510 Signal Properties (continued)

PB12 GPIO I/O

PB12 28 TXD_G SCI_G Transmit O VDDE1 SH — — — 164 A7
PCS_B4 DSPI_B Peripheral Chip Select O
PB13 GPIO I/O
PB13 29 RXD_G SCI_G Receive I VDDE1 SH — — — 163 B7
PCS_B3 DSPI_B Peripheral Chip Select O
PB14 GPIO I/O
PB14 30 VDDE1 SH — — — 148 C10
TXD_H SCI_H Transmit O

PB15 GPIO I/O

PB15 31 VDDE1 SH — — — 147 A11
RXD_H SCI_H Receive I

Port C (16)

PC0 GPIO I/O

eMIOS0 eMIOS Channel I/O
PC0 32 VDDE1 MH — — 122 146 B11
FR_A_TX_EN FlexRay Channel A Transmit Enable O
AD24 EBI Muxed Address/Data I/O

PC1 GPIO I/O

eMIOS1 eMIOS Channel I/O
PC1 33 VDDE1 MH — — 121 145 C11
FR_A_TX FlexRay Channel A Transmit O
AD16 EBI Muxed Address/Data I/O

PC2 GPIO I/O

eMIOS2 eMIOS Channel I/O
PC2 34 VDDE1 MH — — 120 144 D11
FR_A_RX FlexRay Channel A Receive I
TS EBI Transfer Start I/O

PC3 GPIO I/O

PC3 35 eMIOS3 eMIOS Channel I/O VDDE1 MH — — 117 141 A12
FR_DBG0 FlexRay Debug O

PC4 GPIO I/O

PC4 36 eMIOS4 eMIOS Channel I/O VDDE1 SH — — 116 140 B12
FR_DBG1 FlexRay Debug O

PC5 GPIO I/O

PC5 37 eMIOS5 eMIOS Channel I/O VDDE1 SH — — 115 139 C12
FR_DBG2 FlexRay Debug O

MPC5566 and MPC5567 products in 496 MAPBGA packages

PC6 GPIO I/O
PC6 38 eMIOS6 eMIOS Channel I/O VDDE1 SH — — 114 138 D12
FR_DBG3 FlexRay Debug O

PC7 GPIO I/O

PC7 39 eMIOS7 eMIOS Channel I/O VDDE1 SH — — 113 137 A13
FR_B_RX FlexRay Channel B Receive I

PC8 GPIO I/O

eMIOS8 eMIOS Channel I/O
PC8 40 VDDE1 MH — — 112 136 B13
FR_B_TX FlexRay Channel B Transmit O
AD15 EBI Muxed Address/Data I/O
PC9 GPIO I/O
eMIOS9 eMIOS Channel I/O
PC9 41 VDDE1 MH — — 111 135 C13
FR_B_TX_EN FlexRay Channel B Transmit Enable O
AD14 EBI Muxed Address/Data I/O

MPC5510 Microcontroller Family Data Sheet, Rev. 3

6 Freescale Semiconductor
Pin Assignments and Reset States

Table 1. MPC5510 Signal Properties (continued)

PC10 GPIO I/O

eMIOS10 eMIOS Channel I/O
PC10 42 VDDE1 SH — — 110 134 A14
PCS_C5 DSPI_C Peripheral Chip Select O
SCK_D DSPI_D Clock I/O

PC11 GPIO I/O

eMIOS11 eMIOS Channel I/O
PC11 43 VDDE1 SH — — 109 133 B14
PCS_C4 DSPI_C Peripheral Chip Select O
SOUT_D DSPI_D Serial Out O

PC12 GPIO I/O

eMIOS12 eMIOS Channel I/O
PC12 44 VDDE1 SH — — 108 132 B16
PSC_C3 DSPI_C Peripheral Chip Select O
SIN_D DSPI_D Serial In I
PC13 GPIO I/O
eMIOS13 eMIOS Channel I/O
PC13 45 VDDE1 SH — — 107 131 C15
PCS_A5 DSPI_A Peripheral Chip Select O
PCS_D0 DSPI_D Peripheral Chip Select O

PC14 GPIO I/O

eMIOS14 eMIOS Channel I/O
PC14 46 VDDE1 SH — — 106 130 C16
PCS_A4 DSPI_A Peripheral Chip Select O
PCS_D1 DSPI_D Peripheral Chip Select O

PC15 GPIO I/O

eMIOS15 eMIOS Channel I/O
PC15 47 VDDE1 SH — — 105 129 D14
PCS_A3 DSPI_A Peripheral Chip Select O
PCS_D2 DSPI_D Peripheral Chip Select O

Port D (16)

PD0 GPIO I/O

PD0 48 CNTX_A CAN_A Transmit O VDDE1 SH — — 104 128 D15
PCS_D3 DSPI_D Peripheral Chip Select O

PD1 GPIO I/O

PD1 49 CNRX_A CAN_A Receive I VDDE1 SH — — 103 127 D16
PCS_D4 DSPI_D Peripheral Chip Select O

PD2 GPIO I/O

CNRX_B CAN_B Receive I
BOOTCFG GPI
PD2 50 eMIOS10 eMIOS Channel O VDDE1 SH 102 126 E14

MPC5566 and MPC5567 products in 496 MAPBGA packages

(Pulldown) (Pulldown)
BOOTCFG Boot Configuration I
PCS_D5 DSPI_D Peripheral Chip Select O
PD3 GPIO I/O
PD3 51 CNTX_B CAN_B Transmit O VDDE1 SH — — 101 125 E15
eMIOS11 eMIOS Channel O
PD4 GPIO I/O
PD4 52 CNTX_C CAN_C Transmit O VDDE1 SH — — 100 124 E16
eMIOS12 eMIOS Channel O
PD5 GPIO I/O
PD5 53 CNRX_C CAN_C Receive I VDDE1 SH — — 99 123 F13
eMIOS13 eMIOS Channel O

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 7
Pin Assignments and Reset States

Table 1. MPC5510 Signal Properties (continued)

PD6 GPIO I/O

PD6 54 TXD_A SCI_A Transmit O VDDE1 SH — — 98 122 F14
eMIOS14 eMIOS Channel O
PD7 GPIO I/O
PD7 55 RXD_A SCI_A Receive I VDDE1 SH — — 97 121 F15
eMIOS15 eMIOS Channel O
PD8 GPIO I/O
PD8 56 TXD_B SCI_B Transmit O VDDE1 SH — — 94 118 G13
SCL_A I2C Serial Clock Line I/O
PD9 GPIO I/O
PD9 57 RXD_B SCI_B Receive I VDDE1 SH — — 93 117 F16
SDA_A I2C Serial Data Line I/O
PD10 GPIO I/O
PCS_B2 DSPI_B Peripheral Chip Select O
PD10 58 VDDE1 SH — — 92 116 G14
CNTX_F CAN_F Transmit O
NMI0 NMI Input for Z1 Core I

PD11 GPIO I/O

PCS_B1 DSPI_B Peripheral Chip Select O
PD11 59 VDDE1 SH — — 91 115 G15
CNRX_F CAN_F Receive I
NMI1 NMI Input for Z0 Core I

PD12 GPIO I/O

PD12 60 PCS_B0 DSPI_B Peripheral Chip Select I/O VDDE1 SH — — 90 114 H14
eMIOS9 eMIOS Channel O

PD13 GPIO I/O

PD13 61 SCK_B DSPI_B Clock I/O VDDE1 SH — — 89 113 H15
eMIOS8 eMIOS Channel O

PD14 GPIO I/O

PD14 62 SOUT_B DSPI_B Data Output O VDDE1 SH — — 88 110 J14
eMIOS7 eMIOS Channel O

PD15 GPIO I/O

PD15 63 SIN_B DSPI_B Data Input I VDDE1 SH — — 87 107 K14
eMIOS6 eMIOS Channel O

Port E (16)

MPC5566 and MPC5567 products in 496 MAPBGA packages

PE0 GPIO I/O
PCS_A2 DSPI_A Peripheral Chip Select O
PE0 64 VDDE1 SH — — 86 106 K16
eMIOS5 eMIOS Channel O
MLBCLK MLB Clock I

PE1 GPIO I/O

PCS_A1 DSPI_A Peripheral Chip Select O
PE1 65 eMIOS4 eMIOS Channel O VDDE1 MH — — 85 103 L14
MLBSI / MLB Signal In (5-pin) / I
MLBSIG MLB Bi-directional Signal (3-pin) I/O
PE2 GPIO I/O
PCS_A0 DSPI_A Peripheral Chip Select I/O
PE2 66 eMIOS3 eMIOS Channel O VDDE1 MH — — 84 101 L15
MLBDI / MLB Data In (5-pin) / I
MLBDAT MLB Bi-directional Data (3-pin) I/O

MPC5510 Microcontroller Family Data Sheet, Rev. 3

8 Freescale Semiconductor
Pin Assignments and Reset States

Table 1. MPC5510 Signal Properties (continued)

PE3 GPIO I/O

SCK_A DSPI_A Clock I/O
PE3 67 eMIOS2 eMIOS Channel O VDDE1 MH — — 83 100 M13
MLBSO / MLB Signal Out (5-pin) / O
MLBSIG_BUFEN MLB Signal Level Shifter Enable (3-pin) O

PE4 GPIO I/O

SOUT_A DSPI_A Data Out O
PE4 68 eMIOS1 eMIOS Channel O VDDE1 MH — — 82 98 N14
MLBDO / MLB Data Out (5-pin) / O
MLBDAT_BUFEN MLB Data Level Shifter Enable (3-pin) O

PE5 GPIO I/O

SIN_A DSPI_A Data In I
eMIOS0 eMIOS Channel O
PE5 69 VDDE1 MH — — 81 97 M15
MLB_SLOT / MLB Slot Debug / O
MLB_SIGOBS / MLB Clock Adjust Observe Signal / O
MLB_DATOBS MLB Clock Adjust Observe Data O

PE6 GPIO I/O

PE6 70 VDDE3 MH — — 67 83 P13
CLKOUT System Clock Output O

PE7 71 PE7 GPIO I/O VDDE1 SH — — — — H13

PE8 72 PE8 GPIO I/O VDDE1 SH — — — — H16

PE9 72 PE9 GPIO I/O VDDE1 SH — — — — J13

PE10 74 PE10 GPIO I/O VDDE1 SH — — — 112 J16

PE11 75 PE11 GPIO I/O VDDE1 SH — — — 111 J15

PE12 76 PE12 GPIO I/O VDDE1 SH — — — 109 K13

PE13 77 PE13 GPIO I/O VDDE1 SH — — — 108 L13

PE14 78 PE14 GPIO I/O VDDE1 SH — — — 102 L16

PE15 79 PE15 GPIO I/O VDDE1 SH — — — 99 M14

Port F (16)

PF0 GPIO I/O

PF0 80 RD_WR EBI Read/Write I/O VDDE3 MH — — 66 82 N12
EVTI8 Nexus Event In I

MPC5566 and MPC5567 products in 496 MAPBGA packages

PF1 GPIO I/O
TA EBI Transfer Acknowledge I/O
PF1 81 VDDE3 MH — — 65 81 P12
MLBCLK MLB Clock I
EVTO8 Nexus Event Out O

PF2 GPIO I/O

AD8 EBI Muxed Address/Data I/O
ADDR8 EBI Non Muxed Address O
PF2 82 VDDE3 MH — — 64 80 R12
MLBSI / MLB Signal In (5-pin) / I
MLBSIG MLB Bi-Directional Signal (3-pin) I/O
MSEO8 Nexus Message Start/End Out O

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 9
Pin Assignments and Reset States

Table 1. MPC5510 Signal Properties (continued)

PF3 GPIO I/O

AD9 EBI Muxed Address/Data I/O
ADDR9 EBI Non Muxed Address O
PF3 83 VDDE3 MH — — 63 79 T12
MLBDI / MLB Data In (5-pin) / I
MLBDAT MLB Bi-directional Data (3-pin) I/O
MCKO8 Nexus Message Clock Out O

PF4 GPIO I/O

AD10 EBI Muxed Address/Data I/O
ADDR10 EBI Non Muxed Address O
PF4 84 VDDE3 MH — — 59 74 T10
MLBSO / MLB Signal Out (5-pin) / O
MLBSIG_BUFEN MLB Signal Level Shifter Enable (3-pin) O
MDO08 Nexus Message Data Out O

PF5 GPIO I/O

AD11 EBI Muxed Address/Data I/O
ADDR11 EBI Non Muxed Address O
PF5 85 VDDE3 MH — — 58 72 R9
MLBDO / MLB Data Out (5-pin) / O
MLBDAT_BUFEN MLB Data Level Shifter Enable (3-pin) O
MDO18 Nexus Message Data Out O

PF6 GPIO I/O

AD12 EBI Muxed Address/Data I/O
ADDR12 EBI Non Muxed Address O
PF6 86 MLB_SLOT / MLB Slot Debug / O VDDE3 MH — — 57 68 T8
MLB_SIGOBS / MLB Clock Adjust Observe Signal / O
MLB_DATOBS MLB Clock Adjust Observe Data O
MDO28 Nexus Message Data Out O
PF7 GPIO I/O
AD13 EBI Muxed Address/Data I/O
PF7 87 VDDE3 MH — — 56 66 P8
ADDR13 EBI Non Muxed Address O
MDO38 Nexus Message Data Out O

PF8 GPIO I/O

AD14 EBI Muxed Address/Data I/O
PF8 88 VDDE2 MH — — 55 65 N8
ADDR14 EBI Non Muxed Address O
MDO48 Nexus Message Data Out O

PF9 GPIO I/O

AD15 EBI Muxed Address/Data I/O
PF9 89 VDDE2 MH — — 54 64 T7
ADDR15 EBI Non Muxed Address O

MPC5566 and MPC5567 products in 496 MAPBGA packages

MDO58 Nexus Message Data Out O
PF10 GPIO I/O
CS1 EBI Chip Select O
PF10 90 VDDE2 MH — — 52 62 R7
TXD_C SCI_C Transmit O
MDO68 Nexus Message Data Out O

PF11 GPIO I/O

CS0 EBI Chip Select O
PF11 91 VDDE2 MH — — 51 61 P7
RXD_C SCI_C Receive I
MDO78 Nexus Message Data Out O

PF12 GPIO I/O

TS EBI Transfer Start I/O
PF12 92 VDDE2 MH — — 50 60 N7
TXD_D SCI_D Transmit O
ALE EBI Address Latch Enable O

MPC5510 Microcontroller Family Data Sheet, Rev. 3

10 Freescale Semiconductor
Pin Assignments and Reset States

Table 1. MPC5510 Signal Properties (continued)

PF13 GPIO I/O

PF13 93 OE EBI Output Enable O VDDE2 MH — — 49 59 R6
RXD_D SCI_D Receive I
PF14 GPIO I/O
WE0 EBI Write Enable O
PF14 94 VDDE2 MH — — 45 55 P6
BDIP EBI Burst Data In Progress O
CNTX_D CAN_D Transmit O

PF15 GPIO I/O

WE1 EBI Write Enable O
PF15 95 VDDE2 MH — — 44 54 N6
TEA EBI Transfer Error Acknowledge I/O
CNRX_D CAN_D Receive I

Port G (16)

PG0 GPIO I/O

PG0 96 AD16 EBI Muxed Address/Data I/O VDDE2 MH — — 43 51 P5
eMIOS16 eMIOS Channel I/O

PG1 GPIO I/O

AD17 EBI Muxed Address/Data I/O
PG1 97 VDDE2 MH — — 42 50 T4
eMIOS17 eMIOS Channel I/O
SIN_C DSPI_C Serial In I

PG2 GPIO I/O

AD18 EBI Muxed Address/Data I/O
PG2 98 VDDE2 MH — — 41 49 R4
eMIOS18 eMIOS Channel I/O
SOUT_C DSPI_C Serial Out O

PG3 GPIO I/O

AD19 EBI Muxed Address/Data I/O
PG3 99 VDDE2 MH — — 40 48 P4
eMIOS19 eMIOS Channel I/O
SCK_C DSPI_C Serial Clock I/O
PG4 GPIO I/O
AD20 EBI Muxed Address/Data I/O
PG4 100 VDDE2 MH — — 39 47 T3
eMIOS20 eMIOS Channel I/O
PCS_C0 DSPI_C Peripheral Chip Select I/O

PG5 GPIO I/O

PG5 101 AD21 EBI Muxed Address/Data I/O VDDE2 MH — — 38 46 R3
eMIOS21 eMIOS Channel I/O

MPC5566 and MPC5567 products in 496 MAPBGA packages

PG6 GPIO I/O
PG6 102 AD22 EBI Muxed Address/Data I/O VDDE2 MH — — 37 45 T2
eMIOS22 eMIOS Channel I/O

PG7 GPIO I/O

AD23 EBI Muxed Address/Data I/O
PG7 103 VDDE2 MH — — 36 44 R1
eMIOS23 eMIOS Channel I/O
RXD_C SCI_C Receive I

PG8 GPIO I/O

PG8 104 AD24 EBI Muxed Address/Data I/O VDDE2 MH — — 35 43 P2
PCS_A4 DSPI_A Peripheral Chip Select O

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 11
Pin Assignments and Reset States

Table 1. MPC5510 Signal Properties (continued)

PG9 GPIO I/O

AD25 EBI Muxed Address/Data I/O
PG9 105 VDDE2 MH — — 34 42 N3
PCS_A3 DSPI_A Peripheral Chip Select O
TXD_C SCI_C Transmit O

PG10 GPIO I/O

PG10 106 AD26 EBI Muxed Address/Data I/O VDDE2 MH — — 30 38 N2
PCS_A2 DSPI_A Peripheral Chip Select O

PG11 GPIO I/O

PG11 107 AD27 EBI Muxed Address/Data I/O VDDE2 MH — — 29 37 N1
PCS_A1 DSPI_A Peripheral Chip Select O

PG12 GPIO I/O

PG12 108 AD28 EBI Muxed Address/Data I/O VDDE2 MH — — 28 36 M4
PCS_A0 DSPI_A Peripheral Chip Select I/O

PG13 GPIO I/O

PG13 109 AD29 EBI Muxed Address/Data I/O VDDE2 MH — — 27 35 M3
SCK_A DSPI_A Clock I/O

PG14 GPIO I/O

PG14 110 AD30 EBI Muxed Address/Data I/O VDDE2 MH — — 26 34 M2
SOUT_A DSPI_A Data Out O
PG15 GPIO I/O
PG15 111 AD31 EBI Muxed Address/Data I/O VDDE2 MH — — 25 33 M1
SIN_A DSPI_A Data In I

Port H (16)

PH0 GPIO I/O

AN27 eQADC Analog Input7 I
PH0 112 VDDE2 A + SH — — 24 32 L3
eMIOS20 eMIOS Channel O
SCL_A I2C_A Serial Clock I/O
PH1 GPIO I/O
AN26 eQADC Analog Input7 I
PH1 113 VDDE2 A + SH — — 23 31 L2
eMIOS21 eMIOS Channel O
SDA_A I2C_A Serial Data I/O

PH2 GPIO I/O

AN25 eQADC Analog Input7 I
PH2 114 VDDE2 A + MH — — 22 30 L1

MPC5566 and MPC5567 products in 496 MAPBGA packages

eMIOS22 eMIOS Channel O
CS3 EBI Chip Select O

PH3 GPIO I/O

AN24 eQADC Analog Input7 I
PH3 115 VDDE2 A + MH — — 21 29 K4
eMIOS23 eMIOS Channel O
CS2 EBI Chip Select O
PH4 GPIO I/O
AN23 eQADC Analog Input7 I
PH4 116 VDDE2 A + SH — — 20 28 K3
TXD_E SCI_E Transmit O
MA2 eQADC External Mux Address O

PH5 GPIO I/O

AN22 eQADC Analog Input7 I
PH5 117 VDDE2 A + SH — — 19 24 J3
RXD_E SCI_E Receive I
MA1 eQADC External Mux Address O

MPC5510 Microcontroller Family Data Sheet, Rev. 3

12 Freescale Semiconductor
Pin Assignments and Reset States

Table 1. MPC5510 Signal Properties (continued)

PH6 GPIO I/O

PH6 118 AN21 eQADC Analog Input7 I VDDE2 A + SH — — 18 23 J2
TXD_F SCI_F Transmit O
PH7 GPIO I/O
PH7 119 AN20 eQADC Analog Input7 I VDDE2 A + SH — — 17 22 J1
RXD_F SCI_F Receive I
PH8 GPIO I/O
AN19 eQADC Analog Input7 I
PH8 120 VDDE2 A + SH — — 14 17 H1
CNTX_E CAN_E Transmit O
MA0 eQADC External Mux Address O

PH9 GPIO I/O

PH9 121 AN18/ANT eQADC Analog Input7 I VDDE2 A + SH — — 13 14 G2
CNRX_E CAN_E Receive I

PH10 GPIO I/O

PH10 122 AN17/ANS eQADC Analog Input7 I VDDE2 A + SH — — 12 12 F4
CNRX_F CAN_F Receive I

PH11 GPIO I/O

PH11 123 AN16/ANR eQADC Analog Input7 I VDDE2 A + SH — — 11 11 F3
CNTX_F CAN_F Transmit O
PH12 GPIO I/O
PH12 124 VDDE2 SH — — — — F2
PCS_D5 DSPI_D Peripheral Chip Select O

PH13 125 PH13 GPIO I/O VDDE2 SH — — — — F1

PH14 GPIO I/O
PH14 126 VDDE2 MH — — — 53 T5
WE2 EBI Write Enable O

PH15 GPIO I/O

PH15 127 VDDE2 MH — — — 52 R5
WE3 EBI Write Enable O

Port J (16)

PJ0 GPIO I/O

PJ0 128 VDDE3 MH — — — — N11
AD0 EBI Muxed Address/Data I/O

PJ1 GPIO I/O

PJ1 129 VDDE3 MH — — — — P11
AD1 EBI Muxed Address/Data I/O

MPC5566 and MPC5567 products in 496 MAPBGA packages

PJ2 GPIO I/O
PJ2 130 VDDE3 MH — — — — N10
AD2 EBI Muxed Address/Data I/O
PJ3 GPIO I/O
PJ3 131 VDDE3 MH — — — — R10
AD3 EBI Muxed Address/Data I/O

PJ4 GPIO I/O

PJ4 132 VDDE3 MH — — — 75 P10
AD4 EBI Muxed Address/Data I/O

PJ5 GPIO I/O

PJ5 133 VDDE3 MH — — — 73 T9
AD5 EBI Muxed Address/Data I/O
PJ6 GPIO I/O
PJ6 134 VDDE3 MH — — — 69 P9
AD6 EBI Muxed Address/Data I/O

PJ7 GPIO I/O

PJ7 135 VDDE3 MH — — — 67 R8
AD7 EBI Muxed Address/Data I/O

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 13
Pin Assignments and Reset States

Table 1. MPC5510 Signal Properties (continued)

PJ8 GPIO I/O

PJ8 136 VDDE2 SH — — — 27 K2
PCS_D4 DSPI_D Peripheral Chip Select I/O

PJ9 GPIO I/O

PJ9 137 VDDE2 SH — — — 26 K1
PCS_D3 DSPI_D Peripheral Chip Select I/O

PJ10 GPIO I/O

PJ10 138 VDDE2 SH — — — 25 J4
PCS_D2 DSPI_D Peripheral Chip Select I/O
PJ11 GPIO I/O
PJ11 139 VDDE2 SH — — — 19 H3
PCS_D1 DSPI_D Peripheral Chip Select I/O

PJ12 GPIO I/O

PJ12 140 VDDE2 SH — — — 18 H2
PCS_D0 DSPI_D Peripheral Chip Select I/O

PJ13 GPIO I/O

PJ13 141 VDDE2 SH — — — 16 G4
SCK_D DSPI_D Clock I/O
PJ14 GPIO I/O
PJ14 142 VDDE2 SH — — — 15 G3
SOUT_D DSPI_D Serial Out O

PJ15 GPIO I/O

PJ15 143 VDDE2 SH — — — 13 G1
SIN_D DSPI_D Serial In I

Port K (2)

PK0 GPIO I
PK0 144 VDDA AE + IH — — — 168 B6
EXTAL32 32 kHz Crystal Oscillator Input I

PK1 GPIO I
PK1 145 VDDA AE + IH — — — 166 A6
XTAL32 32 kHz Crystal Oscillator Output O

Miscellaneous Pins (9)

EXTAL Main Crystal Oscillator Input I

EXTAL — VDDSYN AE EXTAL 75 91 N16
EXTCLK External Clock Input I

XTAL — XTAL Main Crystal Oscillator Output O VDDSYN AE XTAL 74 90 P16

TMS — TMS JTAG Test Mode Select Input I VDDE3 SH TMS (Pull Up) 72 88 T15
TCK — TCK JTAG Test Clock Input I VDDE3 IH TCK (Pull Down) 71 87 R14
9
TDO — TDO JTAG Test Data Output O VDDE3 MH TDO (Pull Up ) 70 86 T14

MPC5566 and MPC5567 products in 496 MAPBGA packages

TDI — TDI JTAG Test Data Input I VDDE3 IH TDI (Pull Up) 69 85 R13
JCOMP — JCOMP JTAG Compliancy I VDDE3 IH JCOMP (Pull Down) 68 84 T13
10
TEST — TEST Test Mode Select I VDDE3 IH TEST 62 78 R11

RESET — RESET External Reset I/O VDDE2 SH RESET (Pull Up) 10 10 E4

1 The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number.
2
This column lists the functions associated with the programming of the SIU_PCRn[PA] bit field in the following order: GPIO, function
1, function 2, and function 3. The unused functions by a given pin begin with function 3, then function 2, then function 1.
3
These are nominal voltages. Each segment provides the power and ground for the given set of I/O pins.
4 Pad types: SH - Bi-directional slow speed pad with input hysteresis; MH - Bi-directional medium speed pad with input hysteresis; IH

- Input only pad with input hysteresis; AE/A - Analog pad.

5 A dash for the function in this column denotes the input and output buffer are turned off.

MPC5510 Microcontroller Family Data Sheet, Rev. 3

14 Freescale Semiconductor
Pin Assignments and Reset States

6
Port A[14:15]—EXTAL32 and XTAL32 functions only apply on the 144LQFP. These functions are on PortK[0:1] for the 176LQFP and
208BGA. In the 176 LQFP and 208 BGA packages, activity on PA14 should be minimized if the 32kHz XTAL is enabled.

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the
7
This analog input pin has reduced analog-to-digital conversion accuracy compared to PA0–PA15. See eQADC spec #11 (Total
Unadjusted Error for single ended conversions with calibration) for further notes on this.

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
8
The NEXUS function is selected when the JTAG TAP controller is enabled via the JCOMP pin and the appropriate bits in the NP
PCR register. The value of the PA field in the associated PCR register has no effect on the pin function when the NEXUS function
is selected.
9
Pullup is enabled only when JCOMP is negated.
10
Always connect the TEST pin to Ground (Vss).

1.2 Power and Ground Supply Summary

Table 2. MPC5510 Power/Ground

Pin Package Pin Locations

Function Description Voltage1
Name 144 176 208
VDDR Voltage Regulator Supply 5.0 V 46 56 T6
VDDA Analog Power 5.0 V A2
144 176
VRH2 eQADC Voltage Reference High 5.0 V B3
VSSA Analog Ground – A4
3
141 173
VRL eQADC Voltage Reference Low – B4
REFBYPC eQADC Reference Bypass Capacitor VSSA 1 1 B1
VPP4 Flash Program/Erase Power 5.0 V 78 94 P15
5
VDDSYN Clock Synthesizer Power 3.3 V 73 89 R16
VSSSYN Clock Synthesizer Ground – 76 92 M16
105,120, A15,D10,E13,
VDDE1 96,119
3.3 V – 143,155 G16,K15
External I/O Power
VDDE2 5.0 V 16,33,48 21,41,58 H4,L4,N5,P1
VDDE3 61 71,77 N9,T11
104,119, Shorted to VSS in
VSSE1 95,118
142,154 the package
Shorted to VSS in
VSSE2 External I/O Ground – 15,32,47 20,40,57
the package
Shorted to VSS in
VSSE3 60 70,76
the package
VDD335

MPC5566 and MPC5567 products in 496 MAPBGA packages

3.3 V I/O Power
5, 6
3.3 V 77 93 N15
VFLASH Flash Read Power
A1,A16,B2,B15,
VDD5 Internal Logic Power 31,53,79 39,63,95
R2,R15,T1,T16
1.5 V
Shorted to VDD in
VDDF5 Flash Internal Logic Power 79 95
the package
C3,C14,D4,D13,
G7-G10,H7-H10,
VSS Ground
J7-J10,K7-K10,
– 80 96 N4,N13,P3,P14
Shorted to VSS in
VSSF Flash Internal Logic Ground
the package
1
These are nominal voltages.
2
VRH is shorted to VDDA in the 144LQFP and 176 LQFP packages.

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 15
Pin Assignments and Reset States

3
VRL is shorted to VSSA in the 144LQFP and 176 LQFP packages.
4
VPP requires 5V for program/erase operations, but may be 0-5V otherwise. VPP should not go high

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the
or low when the device is in Sleep mode.
5
Voltage generated from internal voltage regulator and no external connection or load allowed

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
except the required bypass capacitors.
6 V
FLASH is shorted to VDD33 in the package.

MPC5566 and MPC5567 products in 496 MAPBGA packages

MPC5510 Microcontroller Family Data Sheet, Rev. 3

16 Freescale Semiconductor
1.3

CS3/eMIOS22/AN25/PH2
CS2/eMIOS23/AN24/PH3
RXD_F/AN20/PH7
MA0/CNTX_E/AN19/PH8

RXD_C/eMIOS23/AD23/PG7
SCK_A/AD29/PG13
SIN_A/AD31/PG15
CNTX_F/AN16/ANR/PH11

PCS_A4/AD24/PG8
TXD_C/PCS_A3/AD25/PG9
VDD
PCS_A2/AD26/PG10
PCS_A1/AD27/PG11
PCS_A0/AD28/PG12
SOUT_A/AD30/PG14
SCL_A/eMIOS20/AN27/PH0
SDA_A/eMIOS21/AN26/PH1
MA2/TXD_E/AN23/PH4
MA1/RXD_E/AN22/PH5
CNRX_E/AN18/ANT/PH9
AN0/PA0
AN1/PA1

TXD_F/AN21/PH6
CNRX_F/AN17/ANS/PH10
AN2/PA2
AN3/PA3
AN4/PA4
AN5/PA5
AN6/PA6
AN7/PA7

RESET

VDDE2
VSSE2
VDDE2
VSSE2
REFBYPC

9
8
7
6
5
4
3
2
1

36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

Freescale Semiconductor
eMIOS22/AD22/PG6 37 144 VDDA/VRH
eMIOS21/AD21/PG5 38 143 PA8/AN8/ANW
PCS_C0/eMIOS20/AD20/PG4 39 142 PA9/AN9/ANX
SCK_C/eMIOS19/AD19/PG3 40 141 VSSA/VRL

* Denotes active during RESET only

SOUT_C/eMIOS18/AD18/PG2 41 140 PA10/AN10/ANY
SIN_C/eMIOS17/AD17/PG1 42 139 PA11/AN11/ANZ
eMIOS16/AD16/PG0 43 138 PA12/AN12
CNRX_D/TEA/WE1/PF15 44 137 PA13/AN13
CNTX_D/BDIP/WE0/PF14 45 136 PA14/AN14/EXTAL32
VDDR 46 135 PA15/AN15/XTAL32
Pinout – 144 LQFP

VSSE2 47 134 PB0/AN28/eMIOS16/PCS_C5

VDDE2 48 133 PB1/AN29/eMIOS17/PCS_C4
RXD_D/OE/PF13 49 132 PB2/AN30/eMIOS18/PCS_C3
ALE/TXD_D/TS/PF12 50 131 PB3/AN31/PCS_C2
MDO7/RXD_C/CS0/PF11 51 130 PB4/AN32/PCS_C1
MDO6/TXD_C/CS1/PF10 52 129 PB5/AN33/PCS_C0
VDD 53 128 PB6/AN34/SCK_C
MDO5/ADDR15/AD15/PF9 54 127 PB7/AN35/SOUT_C
MDO4/ADDR14/AD14/PF8 55 126 PB8/AN36/SIN_C
MDO3/ADDR13/AD13/PF7 56 125 PB9/AN37/CNTX_D/PCS_B4

144 LQFP
MDO2/MLB_SLOT/ADDR12/AD12/PF6 57 124 PB10/AN38/CNRX_D/PCS_B3
MDO1/MLBDO/ADDR11/AD11/PF5 58 123 PB11/AN39/eMIOS19/PCS_B5
MDO0/MLBSO/ADDR10/AD10/PF4 59 122 PC0/eMIOS0/FR_A_TX_EN/AD24
VSSE3 60 121 PC1/eMIOS1/FR_A_TX/AD16
VDDE3 61 120 PC2/eMIOS2/FR_A_RX/TS
TEST 62 119 VDDE1
MCKO/MLBDI/ADDR9/AD9/PF3 63 118 VSSE1
MSEO/MLBSI/ADDR8/AD8/PF2 64 117 PC3/eMIOS3/FR_DBG0
EVTO/MLBCLK/TA/PF1 65 116 PC4/eMIOS4/FR_DBG1
EVTI/RD_WR/PF0 66 115 PC5/eMIOS5/FR_DBG2
CLKOUT/PE6 67 114 PC6/eMIOS6/FR_DBG3
JCOMP 68 113 PC7/eMIOS7/FR_B_RX

Figure 2. MPC5510 Pinout – 144 LQFP

TDI 69 112 PC8/eMIOS8/FR_B_TX/AD15
TDO 70 111 PC9/eMIOS9/FR_B_TX_EN/AD14

MPC5510 Microcontroller Family Data Sheet, Rev. 3

TCK 71 110 PC10/eMIOS10/PCS_C5/SCK_D
TMS 72 109 PC11/eMIOS11/PCS_C4/SOUT_D

73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108

VPP

XTAL
VSSE1
VDDE1

VSSSYN

VDDSYN
VSS/VSSF
VDD/VDDF

VDD33/VFLASH

EXTAL/EXTCLK
PD8/TXD_B/SCL_A
PD9/RXD_B/SDA_A

PD15/SIN_B/eMIOS6
PD6/TXD_A/eMIOS14

PD13/SCK_B/eMIOS8
PD7/RXD_A/eMIOS15
PD0/CNTX_A/PCS_D3
PD1/CNRX_A/PCS_D4

PD12/PCS_B0/eMIOS9
PD3/CNTX_B/eMIOS11

PD14/SOUT_B/eMIOS7
PD4/CNTX_C/eMIOS12
PD5/CNRX_C/eMIOS13

PE1/PCS_A1/eMIOS4/MLBSI
PE2/PCS_A0/eMIOS3/MLBDI
PE3/SCK_A/eMIOS2//MLBSO
PD10/PCS_B2/CNTX_F/NMI0
PD11/PCS_B1/CNRX_F/NMI1

PE4/SOUT_A/eMIOS1/MLBDO
PE0/PCS_A2/eMIOS5/MLBCLK
PC12/eMIOS12/PCS_C3/SIN_D

PE5/SIN_A/eMIOS0/MLB_SLOT
PC15/eMIOS15/PCS_A3/PCS_D2
PC14/eMIOS14/PCS_A4/PCS_D1
PC13/eMIOS13/PCS_A5/PCS_D0

PD2/CNRX_B/eMIOS10/BOOTCFG*/PCS_D5
Pin Assignments and Reset States

17
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the
United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
MPC5566 and MPC5567 products in 496 MAPBGA packages
18
1.4
eMIOS22/AD22/PG6 45
eMIOS21/AD21/PG5 46
PCS_C0/eMIOS20/AD20/PG4 47
SCK_C/eMIOS19/AD19/PG3 48
SOUT_C/eMIOS18/AD18/PG2 49
SIN_C/eMIOS17/AD17/PG1 50
eMIOS16/AD16/PG0

CS3/eMIOS22/AN25/PH2
CS2/eMIOS23/AN24/PH3
PCS_D4/PJ8
PCS_D3/PJ9
PCS_D2/PJ10
RXD_F/AN20/PH7
PCS_D1/PJ11
PCS_D0/PJ12
MA0/CNTX_E/AN19/PH8
SCK_D/PJ13
SOUT_D/PJ14
SIN_D/PJ15
CNTX_F/AN16/ANR/PH11

RXD_C/eMIOS23/AD23/PG7
SCK_A/AD29/PG13
SIN_A/AD31/PG15

PCS_A4/AD24/PG8
TXD_C/PCS_A3/AD25/PG9
VDD
PCS_A2/AD26/PG10
PCS_A1/AD27/PG11
PCS_A0/AD28/PG12
SOUT_A/AD30/PG14
SCL_A/eMIOS20/AN27/PH0
CNRX_E/AN18/ANT/PH9
CNRX_F/AN17/ANS/PH10

SDA_A/eMIOS21/AN26/PH1
MA2/TXD_E/AN23/PH4
MA1/RXD_E/AN22/PH5
AN0/PA0
AN1/PA1

TXD_F/AN21/PH6
AN2/PA2
AN3/PA3
AN4/PA4
AN5/PA5
AN6/PA6
AN7/PA7

RESET

VDDE2
VSSE2
VDDE2
VSSE2
REFBYPC
51
WE3/PH15 52
WE2/PH14 53

9
8
7
6
5
4
3
2
1

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
CNRX_D/TEA/WE1/PF15 54
CNTX_D/BDIP/WE0/PF14 55 176 VDDA/VRH
VDDR 56 175 PA8/AN8/ANW
VSSE2 57 174 PA9/AN9/ANX
VDDE2 58 173 VSSA/VRL
RXD_D/OE/PF13 59 172 PA10/AN10/ANY
ALE/TXD_D/TS/PF12 60 171 PA11/AN11/ANZ
Pin Assignments and Reset States

MDO7/RXD_C/CS0/PF11 61 170 PA12/AN12

MDO6/TXD_C/CS1/PF10 62 169 PA13/AN13
VDD 63 168 PK0/EXTAL32
MDO5/ADDR15/AD15/PF9 64 167 PA14/AN14
Pinout – 176 LQFP

MDO4/ADDR14/AD14/PF8 65 166 PK1/XTAL32

MDO3/ADDR13/AD13/PF7 66 165 PA15/AN15
AD7/PJ7 67 164 PB12/TXD_G/PCS_B4
MDO2/MLB_SLOT/ADDR12/AD12/PF6 68 163 PB13/RXD_G/PCS_B3
AD6/PJ6 69 162 PB0/AN28/eMIOS16/PCS_C5
VSSE3 70 161 PB1/AN29/eMIOS17/PCS_C4
VDDE3 71 160 PB2/AN30/eMIOS18/PCS_C3
MDO1/MLBDO/ADDR11/AD11/PF5 72 159 PB3/AN31/PCS_C2
AD5/PJ5 73 158 PB4/AN32/PCS_C1

176 LQFP
MDO0/MLBSO/ADDR10/AD10/PF4 74 157 PB5/AN33/PCS_C0
AD4/PJ4 75 156 PB6/AN34/SCK_C
VSSE3 76 155 VDDE1
VDDE3 77 154 VSSE1
VSUP/TEST 78 153 PB7/AN35/SOUT_C
MCKO/MLBDI/ADDR9/AD9/PF3 79 152 PB8/AN36/SIN_C
MSEO/MLBSI/ADDR8/AD8/PF2 80 151 PB9/AN37/CNTX_D/PCS_B4
EVTO/MLBCLK/TA/PF1 81 150 PB10/AN38/CNRX_D/PCS_B3
EVTI/RD_WR/PF0 82 149 PB11/AN39/eMIOS19/PCS_B5
CLKOUT/PE6 83 148 PB14/TXD_H
JCOMP 84 147 PB15/RXD_H
TDI 85 146 PC0/eMIOS0/FR_A_TX_EN/AD24
TDO 86

Figure 3. MPC5510 Pinout – 176 LQFP

145 PC1/eMIOS1/FR_A_TX/AD16
TCK 87 144 PC2/eMIOS2/FR_A_RX/TS
TMS 88 143 VDDE1

MPC5510 Microcontroller Family Data Sheet, Rev. 3

125
126
127
128
129
130
131
132

105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124

89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
142 VSSE1
141 PC3/eMIOS3/FR_DBG0
140 PC4/eMIOS4/FR_DBG1
139 PC5/eMIOS5/FR_DBG2

VPP
PE15
PE14
PE13
PE12
PE11
PE10

XTAL
VSSE1
VSSE1

138 PC6/eMIOS6/FR_DBG3
VDDE1
VDDE1

VSSSYN

VDDSYN
137 PC7/eMIOS7/FR_B_RX

VSS/VSSF
VDD/VDDF
136 PC8/eMIOS8/FR_B_TX/AD15

VDD33/VFLASH
135 PC9/eMIOS9/FR_B_TX_EN/AD14

EXTAL/EXTCLK
134 PC10/eMIOS10/PCS_C5/SCK_D
PD8/TXD_B/SCL_A
PD9/RXD_B/SDA_A

133 PC11/eMIOS11/PCS_C4/SOUT_D
PD15/SIN_B/eMIOS6
PD6/TXD_A/eMIOS14

PD13/SCK_B/eMIOS8
PD7/RXD_A/eMIOS15
PD0/CNTX_A/PCS_D3
PD1/CNRX_A/PCS_D4

PD12/PCS_B0/eMIOS9
PD3/CNTX_B/eMIOS11

PD14/SOUT_B/eMIOS7
PD4/CNTX_C/eMIOS12
PD5/CNRX_C/eMIOS13

PE1/PCS_A1/eMIOS4/MLBSI

PE2/PCS_A0/eMIOS3/MLBDI
PE3/SCK_A/eMIOS2//MLBSO
PD10/PCS_B2/CNTX_F/NMI0
PD11/PCS_B1/CNRX_F/NMI1

PE4/SOUT_A/eMIOS1/MLBDO
PE0/PCS_A2/eMIOS5/MLBCLK
PC12/eMIOS12/PCS_C3/SIN_D

PE5/SIN_A/eMIOS0/MLB_SLOT

* Denotes active during RESET only

PC15/eMIOS15/PCS_A3/PCS_D2
PC14/eMIOS14/PCS_A4/PCS_D1
PC13/eMIOS13/PCS_A5/PCS_D0

PD2/CNRX_B/eMIOS10/BOOTCFG*/PCS_D5

Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the
United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
MPC5566 and MPC5567 products in 496 MAPBGA packages
Pin Assignments and Reset States

1.5 Pinout – 208 PBGA

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
A VDD VDDA PA8 VSSA PA13 PK1 PB12 PB2 PB6 PB10 PB15 PC3 PC7 PC10 VDDE1 VDD A

REF
B BYPC VDD VRH VRL PA12 PK0 PB13 PB3 PB7 PB11 PC0 PC4 PC8 PC11 VDD PC12 B

C PA7 PA6 VSS PA9 PA11 PA15 PB0 PB4 PB8 PB14 PC1 PC5 PC9 VSS PC13 PC14 C

D PA5 PA4 PA3 VSS PA10 PA14 PB1 PB5 PB9 VDDE1 PC2 PC6 VSS PC15 PD0 PD1 D

E PA2 PA1 PA0 RESET VDDE1 PD2 PD3 PD4 E

208 PBGA Ball Map
PH13 PH12 PH11 PH10
(as viewed from top through the package) PD5 PD6 PD7 PD9
F F

G PJ15 PH9 PJ14 PJ13 VSS VSS VSS VSS PD8 PD10 PD11 VDDE1 G

H PH8 PJ12 PJ11 VDDE2 VSS VSS VSS VSS PE7 PD12 PD13 PE8 H

J PH7 PH6 PH5 PJ10 VSS VSS VSS VSS PE9 PD14 PE11 PE10 J

K PJ9 PJ8 PH4 PH3 VSS VSS VSS VSS PE12 PD15 VDDE1 PE0 K

L PH2 PH1 PH0 VDDE2 PE13 PE1 PE2 PE14 L

M PG15 PG14 PG13 PG12 PE3 PE15 PE5 VSSSYN M

N PG11 PG10 PG9 VSS VDDE2 PF15 PF12 PF8 VDDE3 PJ2 PJ0 PF0 VSS PE4 VDD33 EXTAL N

P VDDE2 PG8 VSS PG3 PG0 PF14 PF11 PF7 PJ6 PJ4 PJ1 PF1 PE6 VSS VPP XTAL P

R PG7 VDD PG5 PG2 PH15 PF13 PF10 PJ7 PF5 PJ3 TEST PF2 TDI TCK VDD VDDSYN R

T VDD PG6 PG4 PG1 PH14 VDDR PF9 PF6 PJ5 PF4 VDDE3 PF3 JCOMP TDO TMS VDD T

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Figure 4. MPC5510 Pinout – 208 PBGA

MPC5566 and MPC5567 products in 496 MAPBGA packages

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 19
Electrical Characteristics

2 Electrical Characteristics

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications for the MCU.

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
2.1 Maximum Ratings
Table 3. Absolute Maximum Ratings1

Num Characteristic Symbol Min Max2 Unit

1 5.0V Voltage Regulator Reference Voltage VDDR – 0.3 6.5 V

2 5.0V Analog Supply Voltage (reference to VSSA) VDDA – 0.3 6.5 V
3 5.0V Flash Program/Erase Voltage VPP – 0.3 6.5 V
4 3.3V – 5.0V External I/O Supply Voltage 3 V
VDDE14 – 0.3 6.5
VDDE24 – 0.3 6.5
VDDE34 – 0.3 6.5
5 DC Input Voltage 5 VIN –1.06 6.57 V
6 VREF Differential Voltage VRH – VRL – 0.3 5.5 V
7 VRH to VDDA Differential Voltage VRH – VDDA – 5.5 5.5 V
8 VRL to VSSA Differential Voltage VRL – VSSA – 0.3 0.3 V
9 VDDR to VDDA Differential Voltage VDDR – VDDA – VDDA 0.3 V
10 8
Maximum DC Digital Input Current (per pin, applies to all IMAXD –2 2 mA
digital MH, SH, and IH pins)
11 Maximum DC Analog Input Current 9 (per pin, applies to all IMAXA –3 3 mA
analog AE and A pins)
12 Storage Temperature Range TSTG – 55.0 150.0 oC

13 Maximum Solder Temperature 10 TSDR — 260.0 oC

14 Moisture Sensitivity Level 11 MSL — 3

1
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only,
and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or
cause permanent damage to the device.
2 Absolute maximum voltages are currently maximum burn–in voltages. Absolute maximum specifications for device stress have

not yet been determined.

MPC5566 and MPC5567 products in 496 MAPBGA packages

3 All functional non-supply I/O pins are clamped to V
SS and VDDE.
4 V , V , and V are separate power segments and may be powered independently with no differential voltage
DDE1 DDE2 DDE3
constraints between the power segments.
5
AC signal over and undershoot of the input voltages of up to +/– 2.0 volts is permitted for a cumulative duration of 60 hours
over the complete lifetime of the device (injection current does not need to be limited for this duration).
6 Internal structures will hold the input voltage above -1.0 volt if the injection current limit of 2mA is met.
7 Internal structures hold the input voltage below this maximum voltage on all pads powered by V
DDE supplies, if the maximum
injection current specification is met (2 mA for all pins) and VDDE is within Operating Voltage specifications.
8 Total injection current for all pins (including both digital and analog) must not exceed 25mA.
9
Total injection current for all analog input pins must not exceed 15mA.
10
Solder profile per CDF-AEC-Q100.
11 Moisture sensitivity per JEDEC test method A112.

MPC5510 Microcontroller Family Data Sheet, Rev. 3

20 Freescale Semiconductor
Electrical Characteristics

2.2 Thermal Characteristics

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
Value
Num Characteristic Symbol Unit
208 MAPBGA 176 LQFP 144 LQFP

1 Junction to Ambient 1, 2 RθJA °C/W 44 38 43

Natural Convection
(Single layer board)
2 Junction to Ambient 1, 3 RθJA °C/W 27 31 34
Natural Convection
(Four layer board 2s2p)
3 Junction to Ambient 1, 3 RθJMA °C/W 35 30 34
(@200 ft./min., Single layer board)
4 Junction to Ambient 1, 3 RθJMA °C/W 24 25 28
(@200 ft./min., Four layer board 2s2p)
5 Junction to Board 4 RθJB °C/W 16 20 22
6 Junction to Case 5
RθJC °C/W 8 6 7
7 Junction to Package Top 6
ΨJT °C/W 2 2 2
Natural Convection
1 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3 Per JEDEC JESD51-6 with the board horizontal.
4
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5 Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method
(MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
6
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.

2.2.1 General Notes for Specifications at Maximum Junction Temperature

An estimation of the chip junction temperature, TJ, can be obtained from the equation:

MPC5566 and MPC5567 products in 496 MAPBGA packages

TJ = TA + (RθJA × PD) Eqn. 1

where:

TA = ambient temperature for the package (oC) Eqn. 2

RθJA = junction to ambient thermal resistance (oC/W) Eqn. 3

PD = power dissipation in the package (W) Eqn. 4

The supplied thermal resistances are provided based on JEDEC JESD51 series of standards to provide consistent values for
estimations and comparisons. The difference between the values determined on the single-layer (1s) board and on the four-layer
board with two signal layers and a power and a ground plane (2s2p) clearly demonstrate that the effective thermal resistance of

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 21
Electrical Characteristics

the component is not a constant. It depends on the construction of the application board (number of planes), the effective size
of the board which cools the component, how well the component is thermally and electrically connected to the planes, and the

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the
power being dissipated by adjacent components.
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance
between through vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value
obtained on the board with the internal planes is usually appropriate if the application board has one oz (35 micron nominal
thickness) internal planes, the components are well separated, and the overall power dissipation on the board is less than 0.02
W/cm2.
The thermal performance of any component depends strongly on the power dissipation of surrounding components. In addition,
the ambient temperature varies widely within the application. For many natural convection and especially closed box
applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature
near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description
of the local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:

TJ = TB + (RθJB × PD) Eqn. 5

where:

TJ = junction temperature (oC) Eqn. 6

TB = board temperature at the package perimeter (oC/W) Eqn. 7

RθJB = junction to board thermal resistance (oC/W) per JESD51-8 Eqn. 8

PD = power dissipation in the package (W) Eqn. 9

When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made.
The application board should be similar to the thermal test condition, with the component soldered to a board with internal
planes.
Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case
to ambient thermal resistance:

RθJA = RθJC + RθCA Eqn. 10

MPC5566 and MPC5567 products in 496 MAPBGA packages

where:

RθJA = junction to ambient thermal resistance (oC/W) Eqn. 11

RθJC = junction to case thermal resistance (oC/W) Eqn. 12

RθCA = case to ambient thermal resistance (oC/W) Eqn. 13

RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to
ambient thermal resistance, RθCA. For instance, the user can change the air flow around the device, add a heat sink, change the
mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the

MPC5510 Microcontroller Family Data Sheet, Rev. 3

22 Freescale Semiconductor
Electrical Characteristics

device. This description is most useful for packages with heat sinks where some 90% of the heat flow is through the case to the
heat sink to ambient. For most packages, a better model is required.

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the
A more accurate two-resistor thermal model can be constructed from the junction to board thermal resistance and the junction
to case thermal resistance. The junction to case covers the situation where a heat sink will be used or where a substantial amount

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance
when most of the heat is conducted to the printed circuit board. This model can be used for either hand estimations or for a
computational fluid dynamics (CFD) thermal model.
To determine the junction temperature of the device in the application after prototypes are available, the Thermal
Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at
the top center of the package case using the following equation:

TJ = TT + (ΨJT × PD) Eqn. 14

where:

TT = thermocouple temperature on top of the package (oC) Eqn. 15

ΨJT = thermal characterization parameter (oC/W) Eqn. 16

PD = power dissipation in the package (W) Eqn. 17

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects
of the thermocouple wire.

References:
Semiconductor Equipment and Materials International
805 East Middlefield Rd
Mountain View, CA 94043
(415) 964-5111
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at [Link]
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine

MPC5566 and MPC5567 products in 496 MAPBGA packages

Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic
Packaging and Production, pp. 53–58, March 1998.
3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application
in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 23
Electrical Characteristics

2.3 ESD Characteristics

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
Characteristic Symbol Value Unit

ESD for Human Body Model (HBM) 2000 V

HBM Circuit Description R1 1500 Ohm
C 100 pF
ESD for Field Induced Charge Model (FDCM) 500 (all pins)
V
750 (corner pins)
Number of Pulses per pin:
Positive Pulses (HBM) — 1 —
Negative Pulses (HBM) — 1 —
Interval of Pulses — 1 second
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room
temperature followed by hot temperature, unless specified otherwise in the device specification

MPC5566 and MPC5567 products in 496 MAPBGA packages

MPC5510 Microcontroller Family Data Sheet, Rev. 3

24 Freescale Semiconductor
Electrical Characteristics

2.4 DC Electrical Specifications

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
Num Characteristic Symbol Min Max Unit

1a C parts
o
Operating junction temperature range TJ – 40 105 C
Operating ambient temperature range1 TA – 40 85 o
C

1b V parts
o
Operating junction temperature range TJ – 40 120 C
Operating ambient temperature range1 TA – 40 105 o
C

1c M parts2
o
Operating junction temperature range TJ – 40 145 C
Operating ambient temperature range1 TA – 40 125 o
C

2 5.0V Voltage Regulator Reference Voltage VDDR 4.5 5.25 V

3 5.0V Analog Supply Voltage VDDA 4.5 5.25 V

3
4 5.0V Flash Program/Erase Voltage VPP 4.5 5.25 V

5 3.3V – 5.0V External I/O Supply Voltage V

VDDE14,5 3.0 5.5
VDDE24 3.0 5.5
VDDE34 3.0 5.5

6 Pad (SH/MH/IH) Input High Voltage VIH 0.65 × VDDE VDDE + 0.3 V

7 Pad (SH/MH/IH) Input Low Voltage VIL VSS – 0.3 0.35 × VDDE V

8 Pad (SH/MH/IH) Input Hysteresis VHYS 0.1 × VDDE 0.2 × VDDE V

9 Analog (AE/A) Input Voltage VINDC VSSA – 0.3 VDDA + 0.3 V

see note5

10 Slow/Medium I/O Output High Voltage VOH V

IOH = –1.0 mA 0.80 × VDDE —
IOH = –0.2 mA 0.95 × VDDE

11 Slow/Medium I/O Output Low Voltage VOL V

IOL = 1.0 mA — 0.20 × VDDE
IOH = 0.2 mA 0.05 × VDDE

12 Input Capacitance (Digital Pins: Pad type MH,SH, IH with no A or AE) CIN — 7 pF

MPC5566 and MPC5567 products in 496 MAPBGA packages

13 Input Capacitance (Analog Pins: Pad type A, AE, and AE+IH) CIN_A — 10 pF

14 Input Capacitance (Shared digital and analog pins: A with SH or MH) CIN_M — 12 pF

15 Slow/Medium I/O Weak Pull Up/Down Absolute Current 6 IACT 10 170 μA

16 I/O Input Leakage Current 7 IINACT_D – 1.5 1.5 μA

17 DC Injection Current (per pin) IIC – 2.0 2.0 mA

18 8
Analog Input Current, Channel Off (Analog pins AE and AE+IH) IINACT_A – 200 200 nA

19 Analog Input Current (Shared digital and analog pins: A with SH or IINACT_AD –1.5 1.5 μA
MH)

20 VRH to VDDA Differential Voltage VRH – VDDA – 100 100 mV

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 25
Electrical Characteristics

Table 6. DC Electrical Specifications (continued)

21 VRL to VSSA Differential Voltage VRL – VSSA – 100 100 mV

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
22 VSS to VSSA Differential Voltage VSS – VSSA – 100 100 mV

23 VSSSYN to VSS Differential Voltage VSSSYN – VSS –50 50 mV

24 VDDR to VDDA Differential Voltage VDDR – VDDA – 100 100 mV

25 Slew rate on VDDA, VDDR, and VDDE power supply pins9 Vramp 1 100 V/ms

26 Capactive Supply Load Vload nF

VDD 800 —
VDD33 200 —
VDDSYN 200
1
Please refer to Section 2.2.1, “General Notes for Specifications at Maximum Junction Temperature” for more details about the
relation between ambient temperature TA and device junction temperature TJ.
2
M parts can’t go above 66 MHz.
3
VPP can drop to 0 volts during read-only operations and before entry to Sleep mode, to reduce power consumption.
4 VDDE1, VDDE2, and VDDE3 are separate power segments and may be powered independently with no differential voltage
constraints between the power segments.
5 If VDDE1 is below VDDA than the analog input limits (spec #9 (Analog (AE/A) Input Voltage) in Table 6) will be based on the
VDDE1 voltage level.
6 Absolute value of current, measured at VIL and VIH.
7
Weak pull up/down inactive. Measured at VDDE = 5.25 V. Applies to pad types: SH and MH.
8
Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each
8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types: A and AE.
9
This applies to the ramp up rate from 0.3 volts to 3.0 volts.

MPC5566 and MPC5567 products in 496 MAPBGA packages

MPC5510 Microcontroller Family Data Sheet, Rev. 3

26 Freescale Semiconductor
Electrical Characteristics

2.5 Operating Current Specifications

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
Typ1 Typ1 Max1
Num Characteristic Symbol
25C 70C -40–145C Unit
Ambient Ambient Junction

Equations ITOTAL = IDDE + IPP + IDDA + IDDR

IDDE = IDDE1 + IDDE2 + IDDE3
1 VDDE(1,2,3) Current IDDE
VDDE(1,2,3) @ 3.0V - 5.5V
Static2, or when in SLEEP or STOP 1 3 30 µA
Dynamic3 Note 3 Note 3 Note 3 mA
2 VPP Current IPP
VPP @ 0V (All modes) 1 1 1 µA
VPP @ 5.25V
SLEEP mode 15 20 30 µA
STOP mode 15 20 30 µA
RUN mode 1 1 25 mA
3 VDDA Current IDDA
VDDA @ 4.5V - 5.25V
RUN mode4 5 5 10 mA
SLEEP/STOP5 mode with 32KIRC 12 16 26 µA
SLEEP/STOP5 mode with 32KOSC 12 16 28 µA
SLEEP/STOP5 mode with 16MIRC 111 165 225 µA
4 VDDR Current IDDR
VDDR@ 4.5V - 5.25V
SLEEP mode 20 25 360 µA
with XOSC6 (additonal) 500 600 900 µA
with RTC/API (additonal) 1 1 3 µA
each 8K RAM block (additional) 0.8 7 45 µA
STOP mode 170 600 1500 µA
with XOSC6 (additonal) 500 600 900 µA
RUN mode (Using 16 MHz IRC) 30 35 40 mA
RUN mode (Maximum @ 48 MHz)7 50 75 90 mA
RUN mode (Maximum @ 66 MHz)8 105 110 120 mA
RUN mode (Maximum @ 80MHz)9 120 130 135 mA
1
Typ - Nominal voltage levels and functional activity. Max - Maximum voltage levels and functional activity.
2 Static state of pins is when input pins are disabled or not being toggled and driven to a valid input level, output

MPC5566 and MPC5567 products in 496 MAPBGA packages

pins are not toggling or driving against any current loads, and internal pull devices are disabled or not pulling
against any current loads.
3 Dynamic current from pins is application specific and depends on active pull devices, switching outputs, output
capacitive and current loads, and switching inputs. Refer to Table 8 for more information.
4
RUN mode is a typical application with the ADC, 16MIRC, 32KIRC running.
5 SLEEP/STOP mode means that only the listed peripherals are on. All others are diabled.
6
XOSC: optionally enabled in SLEEP and STOP modes (oscillator remains running from crystal but XOSC clock
output disabled).
7 RUN mode condition includes PLL selected as source of system clock, XOSC enabled with 40MHz crystal, all
peripherals enabled, both cores running, and running a typical application using both SRAM and flash.

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 27
Electrical Characteristics

8
RUN mode condition includes PLL selected as source of system clock, XOSC enabled with 40MHz crystal; all
peripheral and cores enabled and running a typical application using both SRAM and flash. Be sure to calculate

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the
the junction temperature, as the maximum current at maximum ambient temperature can exceed the maximum
junction temperature.
9

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
RUN mode condition includes PLL selected as source of system clock, XOSC enabled with 40MHz crystal, all
peripheral and cores enabled and running a typical application using both SRAM and flash. Only for 208
MAPBGA and only 120C junction or lower. Be sure to calculate the junction temperature, as the maximum current
at maximum ambient temperature can exceed the maximum junction temperature

MPC5566 and MPC5567 products in 496 MAPBGA packages

MPC5510 Microcontroller Family Data Sheet, Rev. 3

28 Freescale Semiconductor
Electrical Characteristics

2.6 I/O Pad Current Specifications

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption
is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 8 based on

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load
parameters that fall outside the values given in Table 8.
Table 8. I/O Pad Average DC Current1

Frequency Load2 Slew Rate

Num Pad Type Symbol Voltage (V) Current (mA)
(MHz) (pF) Control
1 Slow IDRV_SH 25 50 5.25 11 8.0
2 (Pad Type SH) 10 50 5.25 01 3.2
3 2 50 5.25 00 0.7
4 2 200 5.25 00 2.4
5 Medium IDRV_MH 50 50 5.25 11 17.3
6 (Pad Type MH) 20 50 5.25 01 6.5
7 3.33 50 5.25 00 1.1
8 3.33 200 5.25 00 3.9
1 These values are estimated from simulation and are not tested. Currents apply to output pins only.
2
All loads are lumped.

MPC5566 and MPC5567 products in 496 MAPBGA packages

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 29
Electrical Characteristics

2.7 Low Voltage Characteristics

1 Power-on-Reset Assert Level 1 VPOR — 0.70 — V

2 Low Voltage Monitor 1.5V 1

Assert Level VLV15A — 1.40 — V
De-assert Level VLV15D — 1.45 —

3 Low Voltage Monitor 3.3V 2

Assert Level VLV33A — 3.05 — V
De-assert Level VLV33D — 3.10 —

4 Low Voltage Monitor Synthesizer 3

Assert Level VLVSYNA — 3.05 — V
De-assert Level VLVSYND — 3.10 —

5 Low Voltage Monitor 5.0V Low Threshold 4

Assert Level VLV5LA 3.30 3.35 3.40 V
De-assert Level VLV5LD 3.35 3.40 3.45

6 Low Voltage Monitor 5.0V 4

Assert Level VLV5A 4.50 4.55 4.70 V
De-assert Level VLV5D 4.55 4.60 4.75

7 Low Voltage Monitor 5.0V High Threshold 4

Assert Level VLV5HA 4.70 4.75 4.80 V
De-assert Level VLV5HD 4.75 4.80 4.85
1 Monitors VDD
2
Monitors VDD33
3 Monitors V
DDSYN
4 Monitors V
DDA

MPC5566 and MPC5567 products in 496 MAPBGA packages

MPC5510 Microcontroller Family Data Sheet, Rev. 3

30 Freescale Semiconductor
Electrical Characteristics

2.8 Oscillators Electrical Characteristics

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
Min. Max.
Num Characteristic Symbol Unit
Value Value
1 Frequency Range1 fref 42 40 MHz
2 Duty Cycle of reference tdc 40 60 %
3 EXTAL Input High Voltage VIHEXT V
External crystal mode 3 VXTAL + 0.4 VDDSYN + 0.3
External clock mode 0.65 x VDDSYN VDDSYN + 0.3
4 EXTAL Input Low Voltage VILEXT V
External crystal mode 3 VDDSYN – 0.3 VXTAL – 0.4
External clock mode VDDSYN – 0.3 0.35 x VDDSYN
5 XTAL Current 4 IXTAL 2 6 mA
6 Total On-chip stray capacitance on XTAL CS_XTAL — 3 pF
7 Total On-chip stray capacitance on EXTAL CS_EXTAL — 3 pF
8 Crystal manufacturer’s recommended CL See crystal See crystal pF
capacitive load specification specification
9 Discrete load capacitance to be connected CL_EXTAL — 2×CL – CS_EXTAL – pF
to EXTAL CPCB_EXTAL5
10 Discrete load capacitance to be connected CL_XTAL — 2×CL – CS_XTAL – pF
to XTAL CPCB_XTAL5
11 Startup Time tstartup — 10 ms
1
Since this is an amplitude controlled oscillator the use of overtone oscillators is not recommended. Only use fundamental
frequency oscillators.
2 When PLL frequency modulation is active, reference frequencies less than 8MHz will distort the modulated waveform and the
effects of this on emissions is not characterized.
3
This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case,
Vextal – Vxtal ≥ 400mV criteria has to be met for oscillator’s comparator to produce output clock.
4
Ixtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
5 CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively

Table 11. 5V Low Frequency (32 kHz) External Oscillator

Min. Max.

MPC5566 and MPC5567 products in 496 MAPBGA packages

Num Characteristic Symbol Unit
Value Value

1 Frequency Range fref32 32 38 kHz

2 Duty Cycle of reference tdc32 40 60 %
3 XTAL32 Current 1
IXTAL32 0.5 3 μA
4 Crystal manufacturer’s recommended CL32 See crystal See crystal pF
capacitive load specification specification
5 Startup Time tstartup — 2 s
1
Ixtal32 is the oscillator bias current out of the XTAL32 pin with both EXTAL32 and XTAL32 pins grounded.

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 31
Electrical Characteristics

Table 12. 5V High Frequency (16 MHz) Internal RC Oscillator

1 Frequency before trim1 Fut 12.8 16 22.3 MHz

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
2 Frequency after loading factory trim2 Ft 15.1 16 16.9 MHz

3 Application trim resolution3 Ts — — ± 0.5 %

4 Application frequency trim step3 Fs — 300 — kHz

5 Start up time St — — 500 ns
1 Across process, voltage, and temperature
2
Across voltage and temperature
3
Fixed voltage and temperature

Table 13. 5V Low Frequency (32 kHz) Internal RC Oscillator

Num Characteristic Symbol Min Typ Max Unit

1 Frequency before trim1 Fut32 20.8 32.0 43.2 kHz

2 Frequency after loading factory trim2 Ft32 26 32.0 38 kHz

3 Application trim resolution3 Ts32 — — ±2 %

4 Application frequency trim step3 Fs32 — 1 — kHz

5 Start up time St32 — — 100 μs
1 Across process, voltage, and temperature
2
Across voltage and temperature
3
Fixed voltage and temperature

MPC5566 and MPC5567 products in 496 MAPBGA packages

MPC5510 Microcontroller Family Data Sheet, Rev. 3

32 Freescale Semiconductor
Electrical Characteristics

2.9 FMPLL Electrical Characteristics

1 System frequency2 fsys kHz

-40 oC ≤ TJ ≤ 120 oC 375 80000 3
-40 oC ≤ TJ ≤ 145 oC 375 66000
2 PLL Reference Frequency (output of predivider) fpllref 4 10 MHz
3 VCO Frequency4 fvco 192 500 MHz
5
4 PLL Frequency fpll MHz
-40 oC ≤ TJ ≤ 120 oC 3 80 3
-40 oC ≤ TJ ≤ 145 oC 3 66
5 Loss of Reference Frequency 6 fLOR 100 1000 kHz
7
6 Self Clocked Mode Frequency fSCM 13 35 MHz
7 PLL Lock Time 8 tlpll — 750 μs
8 Frequency un-LOCK Range fUL – 4.0 4.0 % fsys
9 Frequency LOCK Range fLCK – 2.0 2.0 % fsys
10 CLKOUT Cycle-to-cycle Jitter,9, 10 Cjitter –5 5 % fclkout
9,10, 11
10a CLKOUT Jitter at 10 µs period Cjitter – 0.05 0.05 % fclkout
12,13
11 Frequency Modulation Depth 1% Setting Cmod 0.5 2 %fsys
(fsysMax must not be exceeded)
12 Frequency Modulation Depth 2% Setting 12,13 Cmod 1 3 %fsys
(fsysMax must not be exceeded)
1
VDDSYN = 3.0V to 3.6 V, VSSSYN = 0 V, TA = TL to TH
2
The maximum value is without frequency modulation turned on. If frequency modulation is turned on, the maximum value
(average frequency) must be de-rated by the percentage of modulation enabled.
3 80 MHz is only available in the 208 pin package.
4 Optimum performance is achieved with the highest VCO frequency feasible based on the highest ERFD that results in the desired

PLL frequency.
5 The VCO frequency range is higher than the maximum allowable PLL frequency. The synthesizer control register 2’s enchanced

reduced frequency divider (FMPLL_SYNCR2[ERFD]) in enhanced operation mode must be programmed to divide the VCO
frequency within the PLL frequency range.
6 Loss of reference frequency is the reference frequency detected by the PLL which then transitions into self clocked mode.

MPC5566 and MPC5567 products in 496 MAPBGA packages

7 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below f
LOR.
8 This specification applies to the period required for the PLL to relock after changing the enhanced multiplication factor divider

(EMFD) bits in the synthesizer control register 1 (SYNCR1) in enhanced operation mode.
9 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f .
sys
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage
for a given interval. CLKOUT divider set to divide-by-2.
10 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C
jitter + Cmod.
11 The PLL % jitter reduces with more cycles. 10 µs was picked for a reference point for LIN (100 Kbits), slower speeds will have

even less % jitter.

12 Modulation depth selected must not result in f
sys value greater than the fsys maximum specified value.
13
These depth ranges are obtained by filtering the raw cycle-to-cycle clock frequency data to eliminate the presence of the the
normal clock jitter riding on top of the FM waveform. The allowable modulation rates are 400 kHz to 1 MHz.

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 33
Electrical Characteristics

2.10 eQADC Electrical Characteristics

1 ADC Clock (ADCLK) Frequency1 FADCLK 1 12 MHz

2 Conversion Cycles CC 14+2 (or 16) 14+128 (or 142) ADCLK
cycles
3 Stop Mode Recovery Time2 TSR 20 — μs
4 Resolution — 1.25 — mV
5 INL: 12 MHz ADC Clock3 INL12 — 10 Counts
3
6 DNL: 12 MHz ADC Clock DNL12 — 10 Counts
7 Offset Error with Calibration3 OFFWC — 10 Counts
8 Full Scale Gain Error with Calibration GAINWC — 10 Counts
9 Disruptive Input Injection Current 4, 5, 6, 7 IINJ — ±1 mA
10 Incremental Error due to injection current. All channels have EINJ — ±6 Counts
same 10kΩ < Rs <100kΩ 8
Channel under test has Rs=10kΩ,
IINJ=IINJMAX,IINJMIN
11 Total Unadjusted Error for single ended conversions with TUE — ±10 Counts
calibration3, 9, 10, 11, 12
12 Source Impedance13 RS — 100k Ohm
1
Conversion characteristics vary with FADCLK rate. Reduced conversion accuracy occurs at maximum FADCLK rate. The
maximum value is based on 800KS/s and the minimum value is based on 20MHz oscillator clock frequency divided by a
maximum 16 factor.
2
The specified value is for the case when the 100nF capacitor is not connected to the REFBYPC pin. When the capacitor is
connected to the REFBPYC pin, the recovery time is 10ms.
3 At V
RH – VRL = 5.12 V, one lsb = 1.25 mV = one count.
4 Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater than

VRH and 0x000 for values less than VRL. This assumes that VRH ≤ VDDA and VRL ≥ VSSA due to the presence of the sample
amplifier. Other channels are not affected by non-disruptive conditions.
5 Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do

not affect device reliability or cause permanent damage.

6
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values using VPOSCLAMP = VDDA + 0.5V and VNEGCLAMP = – 0.3 V, then use the larger of the calculated values.

MPC5566 and MPC5567 products in 496 MAPBGA packages

7 Condition applies to two adjacent pads on the internal pad.
8
At VRH – VRL = 5.12 V, one lsb = 1.25 mV = one count. This count error is in addition to the TUE count error.
9
The TUE specification will always be better than the sum of the INL, DNL, offset, and gain errors due to canceling errors.
10
TUE includes all internal device error such as internal reference variation (75% Ref, 25% Ref)
11 Depending on the customer input impedance, the Analog Input Leakage current (DC Electrical specification) may affect the

actual TUE measured on analog channels shared digital pins.

12 It is possible to see up to one additional count added for the 144 pin packages since the VRL and VRH functions are shared

with the VSSA and VDDA, respectively. On Analog pins above PA15, the accuracy effects from adjacent digital port pin activity
is application dependent because of frequency, level, noise, etc.
13 If R is greater than 1 k Ohm, be sure to calculate the affect of pin leakage and use the proper sampling time, to ensure that
S
you get the accuracy required.

MPC5510 Microcontroller Family Data Sheet, Rev. 3

34 Freescale Semiconductor
Electrical Characteristics

2.11 Flash Memory Electrical Characteristics

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
Initial
Num Characteristic Symbol Min Typ Max3 Unit
Max2

1 Double Word (64 bits) Program Time 4 Tdwprogram — 10 — 500 μs

2 Page (128 bits) Program Time 4
Tpprogram — 15 44 500 μs
3 16 Kbyte Block Pre-program and Erase Time T16kpperase — 325 525 5000 ms
4 64 Kbyte Block Pre-program and Erase Time T64kpperase — 525 675 5000 ms
5 128 Kbyte Block Pre-program and Erase Time T128kpperase — 675 1800 7500 ms
6 Minimum operating frequency for program and erase — 25 — — — MHz
operations
7 Wait States Relative to System Frequency Trwsc MHz
PFCRPn[RWSC] = 0b000; PFCRPn[WWSC] = 0b01 — — — 25
PFCRPn[RWSC] = 0b001; PFCRPn[WWSC] = 0b01 — — — 50
PFCRPn[RWSC] = 0b010; PFCRPn[WWSC] = 0b01 — — — 80
8 Recovery Time Trecover
Stop mode exit or STOP bit negated — — — 20 μs
Sleep mode exit (with CRP_RECPTR[FASTREC]=1) 5 — — — 120 μs
1
Typical program and erase times assume nominal supply values and operation at 25 oC.
2
Initial factory condition: < 100 program/erase cycles, nomial supply values and operation at 25 oC.
3 The maximum time is at worst case conditions after the specified number of program/erase cycles. This maximum value is

characterized but not guaranteed.

4
This does not include software overhead.
5 If CRP_RECPTR[FASTREC]=0, then hardware will wait 2340 system clocks before exiting from Sleep mode to account for the

flash recovery time. The default system clock source after Sleep is the 16MIRC. A nominal frequency of 16MHz equates to a
hardware wait of 146μs.

Table 17. Flash EEPROM Module Life (Full Temperature Range)

Num Characteristic Symbol Min Typical1 Unit

1 Number of Program/Erase cycles per block over the operating

temperature range (TJ) P/E cycles
16 Kbyte and 64 Kbyte blocks 100,000 —
128 Kbyte blocks 1000 100,000

MPC5566 and MPC5567 products in 496 MAPBGA packages

2 Data retention Retention — years
Blocks with 0 – 1,000 P/E cycles 20
Blocks with 1,001 – 100,000 P/E cycles 5
1 Typical endurance is evaluated at 25C. Product qualification is performed to the minimum specification. For additional
information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619 “Typical Endurance
for Nonvolatile Memory.”

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 35
Electrical Characteristics

2.12 Pad AC Specifications

Out Delay2, 3 Rise/Fall3, 4

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
Load Drive
Num Pad Type SRC
(ns) (ns) (pF)

1 Slow (SH) 11 39 23 50
120 87 200
01 101 52 50
188 111 200
00 507 248 50
597 312 200
2 Medium (MH) 11 23 12 50
64 44 200
01 50 22 50
90 50 200
00 261 123 50
305 156 200
4 Pull Up/Down (3.6V max) — — 7500 50
5 Pull Up/Down (5.5V max) — — 9500 50
1
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at VDDE
= 3.0V to 5.5V, TA = TL to TH.
2 This parameter is supplied for reference and is not tested. Add a maximum of one system clock to the output delay for delay

with respect to system clock.

3 Delay and rise/fall are measured to 20% or 80% of the respective signal.
4 This parameter is guaranteed by characterization before qualification rather than 100% tested.

VDD/2
Pad

MPC5566 and MPC5567 products in 496 MAPBGA packages

Internal Data Input Signal
Rising Falling
Edge Edge
Out Out
Delay Delay

VOH

VOL
Pad
Output

Figure 5. Pad Output Delay

MPC5510 Microcontroller Family Data Sheet, Rev. 3

36 Freescale Semiconductor
Electrical Characteristics

2.13 AC Timing

Num Characteristic Symbol Min Max Unit

1 RESET Pulse Width tRPW 150 — ns

2 BOOTCFG Setup Time after RESET Valid tRCSU — 100 μs
3 BOOTCFG Hold Time from RESET Valid tRCH 0 — μs

RESET 1

BOOTCFG

3
Figure 6. Reset and Boot Configuration Timing

2.13.2 External Interrupt (IRQ) and Non-Maskable Interrupt (NMI) Pins

Table 20. IRQ/NMI Timing

Num Characteristic Symbol Min Max Unit

1 IRQ/NMI Pulse Width Low tIPWL 3 — tSYS

2 IRQ/NMI Pulse Width High TIPWH 3 — tSYS
3 IRQ/NMI Edge to Edge Time1 tICYC 6 — tSYS

MPC5566 and MPC5567 products in 496 MAPBGA packages

1 Applies when IRQ/NMI pins are configured for rising edge or falling edge events, but not both.

IRQ/NMI

1,2 1,2

Figure 7. IRQ and NMI Timing

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 37
Electrical Characteristics

2.13.3 JTAG (IEEE 1149.1) Interface

1 TCK Cycle Time tJCYC 100 — ns

2 TCK Clock Pulse Width (Measured at VDDE/2) tJDC 40 60 ns
3 TCK Rise and Fall Times (40% – 70%) tTCKRISE — 3 ns
4 TMS, TDI Data Setup Time tTMSS, tTDIS 5 — ns
5 TMS, TDI Data Hold Time tTMSH, tTDIH 25 — ns
6 TCK Low to TDO Data Valid tTDOV — 20 ns
7 TCK Low to TDO Data Invalid tTDOI 0 — ns
8 TCK Low to TDO High Impedance tTDOHZ — 20 ns
9 JCOMP Assertion Time tJCMPPW 100 — ns
10 JCOMP Setup Time to TCK Low tJCMPS 40 — ns
11 TCK Falling Edge to Output Valid tBSDV — 50 ns
12 TCK Falling Edge to Output Valid out of High Impedance tBSDVZ — 50 ns
13 TCK Falling Edge to Output High Impedance tBSDHZ — 50 ns
14 Boundary Scan Input Valid to TCK Rising Edge tBSDST 50 — ns
15 TCK Rising Edge to Boundary Scan Input Invalid tBSDHT 50 — ns
1
These specifications apply to JTAG boundary scan only. JTAG timing specified at VDDE = 3.0V to 5.5V, TA = TL to TH, and CL
= 30pF with SRC = 0b11.

TCK
2
2
3

MPC5566 and MPC5567 products in 496 MAPBGA packages

1 3

Figure 8. JTAG Test Clock Input Timing

MPC5510 Microcontroller Family Data Sheet, Rev. 3

38 Freescale Semiconductor
TDO

TCK
TCK

JCOMP
TMS, TDI

Freescale Semiconductor
7
4

9
5

Figure 10. JTAG JCOMP Timing

Figure 9. JTAG Test Access Port Timing

MPC5510 Microcontroller Family Data Sheet, Rev. 3

10
8
Electrical Characteristics

39
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the
United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
MPC5566 and MPC5567 products in 496 MAPBGA packages
40
TCK

Output

Input
Output

Signals
Signals

Signals
Electrical Characteristics

12
11

14
13

Figure 11. JTAG Boundary Scan Timing

MPC5510 Microcontroller Family Data Sheet, Rev. 3

2.13.4 Nexus Debug Interface

1 MCKO Cycle Time tMCYC 40 — ns

2 MCKO Duty Cycle tMDC 40 60 %
2
3 MCKO Low to MDO Data Valid tMDOV –2 4.0 ns
2
4 MCKO Low to MSEO Data Valid tMSEOV –2 4.0 ns
5 MCKO Low to EVTO Data Valid 2
tEVTOV –2 4.0 ns
6 EVTI Pulse Width tEVTIPW 4.0 — tTCYC
7 EVTO Pulse Width tEVTOPW 1 tMCYC
3
8 TCK Cycle Time tTCYC 40 — ns
9 TCK Duty Cycle tTDC 40 60 %
10 TDI, TMS Data Setup Time tNTDIS, tNTMSS 8 — ns
11 TDI, TMS Data Hold Time tNTDIH, tNTMSH 4 — ns
12 TCK Low to TDO Data Valid tJOV 0 8 ns
1
JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from
50% of MCKO and 50% of the respective signal. Nexus timing specified at VDDE = 3.0V to 5.5V, TA = TL to TH, and CL = 30pF
with SRC = 0b11.
2 MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
3 The system clock frequency needs to be three times faster that the TCK frequency.

MCKO

4 3
5

MDO

MPC5566 and MPC5567 products in 496 MAPBGA packages

MSEO Output Data Valid
EVTO

Figure 12. Nexus Output Timing

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 41
42
TCK

TDO
TMS, TDI
Electrical Characteristics

Figure 13. Nexus TDI, TMS, TDO Timing

MPC5510 Microcontroller Family Data Sheet, Rev. 3

2.13.5 External Bus Interface (EBI)

1 CLKOUT Period2 TC 40.0 — ns

2 CLKOUT duty cycle tCDC 45% 55% TC
3
3 CLKOUT rise time tCRT — — ns
4 CLKOUT fall time tCFT 3
— — ns
5 CLKOUT Positive Edge to Output Signal Invalid or High Z (Hold Time) tCOH 2.0 — ns
6 CLKOUT Positive Edge to Output Signal Valid (Output Delay) tCOV — 10.0 ns
7 Input Signal Valid to CLKOUT Posedge (Setup Time) tCIS 20.0 — ns
8 CLKOUT Posedge to Input Signal Invalid (Hold Time) tCIH 0 — ns
9 ALE Pulse Width High Time tALEPWH 20 — ns
10 ALE Fall to AD Invalid tALEAD 2 — ns
1 EBI timing specified at VDDE = 3.0V to 5.5V, TA = TL to TH, and CL = 50pF with SIU_PCRn[SRC] = 0b11.
2
Initialize SIU_ECCR[EBDF] to meet maximum external bus frequency.
3
Refer to Medium High Voltage (MH) pad AC specification in Table 18.

Voh_f
VDDE/2
Vol_f
CLKOUT

3 2

4
1

Figure 14. CLKOUT Timing

MPC5566 and MPC5567 products in 496 MAPBGA packages

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 43
44
TA

TS
OE

TEA
BUS

BDIP
CS[0:3]

WE[0:3]
RD_WR
SIGNAL
AD[0:31]

OUTPUT
OUTPUT
CLKOUT

ADDR[8:15]
Electrical Characteristics

5
5

VDDE/2
VDDE/2

6
6

6
5
VDDE/2

Figure 15. Synchronous Output Timing

MPC5510 Microcontroller Family Data Sheet, Rev. 3

VDDE/2

TS
TEA
BUS
INPUT

INPUT

RD_WR
SIGNAL
AD[0:31]
CLKOUT

Freescale Semiconductor
VDDE/2
7
7
VDDE/2

VDDE/2

Figure 16. Synchronous Input Timing

8
8

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Electrical Characteristics

45
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the
United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
MPC5566 and MPC5567 products in 496 MAPBGA packages
46
2
1
Num
2.13.6
TS

ALE
AD[0:31]
CLKOUT
Electrical Characteristics

eMIOS Input Pulse Width

eMIOS Output Pulse Width
VDDE/2
9

Characteristic
VDDE/2

VDDE/2

Table 24. eMIOS Timing

Enhanced Modular I/O Subsystem (eMIOS)

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Figure 17. Address Latch Enable (ALE) Timing

tMIPW
tMOPW
Symbol

1
4
Min

—
—
Max
Unit

tCYC
tCYC

2.13.7 Deserial Serial Peripheral Interface (DSPI)

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
66 MHz
Num Characteristic Symbol Unit
Min Max

1 SCK Cycle TIme2,3 tSCK 60 — ns

4
2 PCS to SCK Delay tCSC 20 — ns
3 After SCK Delay5 tASC 20 — ns
4 SCK Duty Cycle tSDC tSCK/2 tSCK/2 ns
–2ns + 2ns
5 Slave Access Time tA — 25 ns
(SS active to SOUT driven)
6 Slave SOUT Disable Time tDIS — 25 ns
(SS inactive to SOUT High-Z or invalid)
7 PCSx to PCSS time tPCSC 4 — ns
8 PCSS to PCSx time tPASC 5 — ns
9 Data Setup Time for Inputs tSUI
Master (MTFE = 0) 35 — ns
Slave 5 — ns
Master (MTFE = 1, CPHA = 0)6 5 — ns
Master (MTFE = 1, CPHA = 1) 35 — ns
10 Data Hold Time for Inputs tHI
Master (MTFE = 0) –4 — ns
Slave 10 — ns
Master (MTFE = 1, CPHA = 0)6 26 — ns
Master (MTFE = 1, CPHA = 1) –4 — ns
11 Data Valid (after SCK edge) tSUO
Master (MTFE = 0) — 15 ns
Slave — 35 ns
Master (MTFE = 1, CPHA=0) — 30 ns
Master (MTFE = 1, CPHA=1) — 15 ns
12 Data Hold Time for Outputs tHO
Master (MTFE = 0) –15 — ns
Slave 5.5 — ns
Master (MTFE = 1, CPHA = 0) 0 — ns

MPC5566 and MPC5567 products in 496 MAPBGA packages

Master (MTFE = 1, CPHA = 1) –15 — ns
1 DSPI timing specified at VDDE = 3.0V to 5.5V, TA = TL to TH, and CL = 50pF with SRC = 0b11.
2 The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated
based on two MPC55xx devices communicating over a DSPI link.
3
The actual minimum SCK Cycle Time is limited by pad performance.
4
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]
5 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]
6
This number is calculated assuming the SMPL_PT bit field in DSPI_MCR is set to 0b10.

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 47
48
Electrical Characteristics

SIN

SOUT

SIN
(CPOL=1)

SOUT
(CPOL=1)

(CPOL=0)
PCSx
PCSx

(CPOL=0)

SCK Output
SCK Output

9
2

9
First Data
10
4

First Data

First Data
4

Data
Data

Data
Data
1

11
Last Data

Last Data

11
3

Last Data
Last Data

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Figure 19. DSPI Classic SPI Timing — Master, CPHA = 1
Figure 18. DSPI Classic SPI Timing — Master, CPHA = 0

SIN

(CPOL=1)

SIN
SCK Input
(CPOL=0)
SCK Input

(CPOL=0)
SCK Input
(CPOL=1)
SCK Input

SOUT
SOUT

5
2

9
5

9
4

First Data

First Data
10

First Data
4

10
First Data
12

Data
Data

Data
Data
1

11
3

Last Data
Last Data

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Figure 21. DSPI Classic SPI Timing — Slave, CPHA = 1
Figure 20. DSPI Classic SPI Timing — Slave, CPHA = 0

6
6
Electrical Characteristics

49
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the
United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
MPC5566 and MPC5567 products in 496 MAPBGA packages
Electrical Characteristics

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
4 1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)

9 10

SIN First Data Data Last Data

12 11

SOUT First Data Data Last Data

Figure 22. DSPI Modified Transfer Format Timing — Master, CPHA = 0

PCSx

SCK Output
(CPOL=0)

SCK Output
(CPOL=1)
10
9

SIN First Data Data Last Data

12 11

MPC5566 and MPC5567 products in 496 MAPBGA packages

SOUT First Data Data Last Data

Figure 23. DSPI Modified Transfer Format Timing — Master, CPHA = 1

MPC5510 Microcontroller Family Data Sheet, Rev. 3

50 Freescale Semiconductor
Electrical Characteristics

3
2

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
1

SCK Input
(CPOL=0)
4 4

SCK Input
(CPOL=1)
11 12 6
5

SOUT First Data Data Last Data

9 10

SIN First Data Data Last Data

Figure 24. DSPI Modified Transfer Format Timing — Slave, CPHA = 0

SCK Input
(CPOL=0)

SCK Input
(CPOL=1)
11
5 6
12

SOUT First Data Data Last Data

9
10

MPC5566 and MPC5567 products in 496 MAPBGA packages

SIN First Data Data Last Data

Figure 25. DSPI Modified Transfer Format Timing — Slave, CPHA = 1

7 8

PCSS

PCSx

Figure 26. DSPI PCS Strobe (PCSS) Timing

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 51
Package Information

3 Package Information

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the
The latest package outline drawings are available on the product summary pages on our web site:
[Link] The following table lists the package case number per device. Use these numbers in the web

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
page’s “keyword” search engine to find the latest package outline drawings.
Table 26. Package Information

Package Package Case Number

144 LQFP 98ASS23177W

176 LQFP 98ASS23479W

208 MAPBGA 98ARS23882W

4 Product Documentation
Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale Literature Distribution
Center, or through the Freescale world-wide web address at [Link]

MPC5566 and MPC5567 products in 496 MAPBGA packages

MPC5510 Microcontroller Family Data Sheet, Rev. 3

52 Freescale Semiconductor
Product Documentation

4.1 Revision History

United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
Revision Date Substantive Changes

Rev. 0 9/2007 Initial Release. Preliminary content.

Rev. 1 6/2008 (Note: Change descriptions refer to locations in Rev. 0.)

Changed MPC5516 to MPC5510 Family where appropriate.
Modified Figure 1. MPC5510 Family Block Diagram.
Deleted Table 1. MPC5510 Family Comparison, Maximum Feature Set
Deleted Table 2. MPC5510 Peripheral Multiplexing Examples
Corrected PK0 and PK1 pin assignments on 208 MAPBGA (Table 3 and Figure 4).
Modified Table 4, footnote 4.
Modified Table 8. DC Electrical Specifications and table footnotes.
Modified Table 9. Operating Currents and table footnotes.
Modified Table 12. 3.3V High Frequency External Oscillator, row 5.
Modified Table 14. 5V High Frequency (16 MHz) Internal RC Oscillator, row 2.
Modified Table 16. FMPLL Electrical Specifications, row 4.
Modified Table 17. eQADC Conversion Specifications (Operating) and table footnotes.
Modified Table 18. Flash Program and EraseSpecifications, row 5.
Modified Table 19. Flash EEPROM Module Life (Full Temperature Range), row 1
Modified Table 28. Package Information.

Rev. 2 12/2008 (Note: Change descriptions refer to locations in Rev. 1.)

Modified Table 1. MPC5510 Signal Properties: added note to TEST signal.
Modified Table 6. DC Electrical Specifications: rows 1b, 5, 8, 9, 10, 11, 16, 19, 25, and footnotes.
Modified Table 7. Operating Currents: Max column header, rows 1, 2, 3, 4, and footnotes.
Modified Table 9. Low Voltage Monitors: rows 2, 3, 4, 6.
Modified Table 10. 3.3V High Frequence External Oscillator: row 1 added footnote, removed
duplicate footnote #3.
Modified Table 11. 5V Low Frequency (32 kHz) External Oscillator: row 1.
Modified Table 12. 5V High Frequency (16 MHz) Internal RC Oscillator: row 2.
Modified Table 13. 5V Low Frequency (32 kHz) Internal RC Oscillator: row 2.
Modified Table 14. FMPLL Electrical Specifications: rows 1 and 4; added two new rows.
Modified Table 15. eQADC Conversion Specifications (Operating): rows 5, 6, 7, 8, 10, 11, and
footnotes.
Modified Figure 5. Pad Output Delay: moved the dashed horizontal line up so that it crosses the
signal midway between top and bottom.

Rev. 3 3/2009 (Note: Change descriptions refer to locations in Rev. 2.)

MPC5566 and MPC5567 products in 496 MAPBGA packages

Modified Table 4. Thermal Characteristics: all values in 208 MAPBGA column.
Modified Table 6. DC Electrical Specifications: spec #1c, added footnote; spec #25, added
footnote.
Modified Table 7. Operating Currents; spec #5.
Modified Table 9. Low Voltage Monitors; spec #1.
Modified Table 14. FMPLL Electrical Specifications: updated footnote 3; added spec #10a.
Modified Table 15. eQADC Conversion Specifications (Operating): added another footnote.
Modified Table 16: Flash Program and Erase Specifications: updated spec #7.
Modified Figure 5: Pad Output Delay: adjusted lower timing diagram.
Modified Figure 8: JTAG Test Clock Input Timing; updated so that it matches the spec definitions.

MPC5510 Microcontroller Family Data Sheet, Rev. 3

Freescale Semiconductor 53
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the
United States prior to September 2010: MPC551x and MPC5533 products in 208 MAPBGA packages; MPC5534 and MPC5553 products in 208 and 496 MAPBGA packages; MPC5554, MPC5565,
How to Reach Us: Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
Home Page: implied copyright licenses granted hereunder to design or fabricate any integrated
[Link] circuits or integrated circuits based on the information in this document.

Web Support: Freescale Semiconductor reserves the right to make changes without further notice to
[Link] any products herein. Freescale Semiconductor makes no warranty, representation or
USA/Europe or Locations Not Listed: guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor, Inc. Freescale Semiconductor assume any liability arising out of the application or use of any
Technical Information Center, EL516 product or circuit, and specifically disclaims any and all liability, including without
2100 East Elliot Road limitation consequential or incidental damages. “Typical” parameters that may be
Tempe, Arizona 85284 provided in Freescale Semiconductor data sheets and/or specifications can and do vary
1-800-521-6274 or +1-480-768-2130 in different applications and actual performance may vary over time. All operating
[Link]/support parameters, including “Typicals”, must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
Europe, Middle East, and Africa: under its patent rights nor the rights of others. Freescale Semiconductor products are
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+44 1296 380 456 (English) could create a situation where personal injury or death may occur. Should Buyer
+46 8 52200080 (English) purchase or use Freescale Semiconductor products for any such unintended or
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[Link]/support claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
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Japan:
unintended or unauthorized use, even if such claim alleges that Freescale
Freescale Semiconductor Japan Ltd.
Headquarters Semiconductor was negligent regarding the design or manufacture of the part.
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku, RoHS-compliant and/or Pb-free versions of Freescale products have the functionality
Tokyo 153-0064 and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free
Japan
0120 191014 or +81 3 5437 9125 counterparts. For further information, see [Link] or contact your
[Link]@[Link] Freescale sales representative.

MPC5566 and MPC5567 products in 496 MAPBGA packages

Asia/Pacific: For information on Freescale’s Environmental Products program, go to
Freescale Semiconductor China Ltd. [Link]
Exchange Building 23F
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Chaoyang District Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
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© Freescale Semiconductor, Inc. 2007-2009. All rights reserved.
For Literature Requests Only:
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Fax: +1-303-675-2150
LDCForFreescaleSemiconductor@[Link]

Document Number: MPC5510

Rev. 3
3/2009

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