DESIGN AND CONSTRUCTION OF A BROADBAND (1MHZ)

DIGITAL HF TRANSCEIVER FOR MULTICARRIER AND

MULTICHANNEL MODULATIONS
B. Pérez-Díaz†, E. Jiménez-Yguácel†, J. López-Pérez†, I. Pérez-Álvarez†, S. Zazo-Bello*, E.
Mendieta-Otero†
†
Universidad de Las Palmas de Gran Canaria (ULPGC). CeTIC. Dpto. Señales y Comunicaciones.
Las Palmas (Canary Islands). Spain. Tel: +34-928452874, email: bperez@[Link]
* Universidad Politécnica de Madrid (UPM). Dpto. SSR. ETSI de Telecomunicación.
Madrid. Spain. Tel.: +34-915495700 Ext 4042, email: santiago@[Link]

Keywords: HF, broadband transceiver, multicarrier, baseband subsystem is in charge of implementing proper
multichannel. system channelisation.

Abstract Figure 1 shows the digital transceiver receiving section (RX)

block diagram. The transmission section (TX) has the same
This paper describes a broadband (1MHz) digital HF blocks but with an inverse flow signal.
transceiver for the HF band (3-30MHz) specifically designed
for the transmission and reception of multicarrier and
multichannel modulations. The wide modem bandwidth Receiver
antenna
STATION

(1MHz) is not meant for the transmission of a single 1MHz IF to be

digitized
wide signal, since the goal is to achieve flexible transmission RF receiver A/D Digital Signal
processing
D/A
(analog) Converter receiver (DDC) Converter
and reception using several channels with a common standard AUDIO

bandwidth.
Figure 1: Receiving section block diagram
1 Introduction
This paper describes the design and construction of a
All the broadband transceiver blocks are described in this
broadband (1MHz) digital HF transceiver for the HF band (3-
paper, pointing out specific multicarrier modulations aspects.
30MHz), specifically designed for transmission and reception
The transceiver consists of a radio frequency (RF) front-end
of multicarrier and multichannel modulations.
that moves the chosen 1MHz band portion to an intermediate
frequency (IF, 10.7MHz). These front-end implements a
This transceiver is the result of several years of mutual
double conversion superheterodyne architecture based on
collaboration between CeTIC (ULPGC) and GAPS (UPM) on
Direct Digital Synthesis (DDS) oscillators. After the A/D
multicarrier modulations (OFDM and OFDM-CDM) in data
converter stage follows a multichannel Digital Down
and interactive digital voice communications in the HF band,
Converter (DDC) with an 8KHz bandwidth channel. This
leading to the development of HFDVL (High Frequency
multichannel output signal enters into the signal processing
Data+Voice Link) architecture [3]. The last step undertaken
unit implementing the modem OFDM algorithms (data) and
has been the development of a system supporting both high
OFDM-CDM algorithms (interactive digital voice). An Altera
availability and link quality for highly demanding
FPGA (CycloneII EP2C70), a fixed point DSP (Texas
applications, such as RADAR data transmissions [4]. Due to
Instrument TMS32C6416), and software running on a
these restrictions, increased availability and quality, the new
GNU/Linux Personal Computer (PC) comprise the digital
system is based on a combination of multicarrier and
part.
multichannel techniques. Thus, these stringent requirements
have led to the design and construction of a broadband
Figure 2 shows a photograph of the RF front-end and FPGA
transceiver capable of meeting them.
setup. The front-end has been built to fit inside a 19’’
subrack, thus offering a standard and modular structure.
It is important to highlight that the wide modem bandwidth
(1MHz) is not meant for the transmission of a single 1MHz
The paper continues with a description of the analog part (RF
wide signal, since the HF spectrum is highly populated and
front-end), then a description of the digital part (FPGA and
strongly regulated. The goal is to achieve flexible
DSP) and finally a conclusions section.
transmission and reception using several channels with a
common standard bandwidth. The transceiver digital
2 Analog part: RF front-end managed by the control unit, is in charge of keeping a
constant signal power at the input of the A/D converter.
The basic architecture of the wideband RF front-end is that of
a double conversion superheterodyne. [2]. The general block In the transmitter shown in Figure 5, the baseband signal is
diagram for the front-end is shown in Figure 3, while in filtered, amplified when necessary, and translated to first IF.
Figure 4 and Figure 5 more detailed diagrams for the Then the signal is converted to the selected RF frequency
reception and transmission parts are shown, respectively. making use of the output mixer, after having been filtered in
Intermediate frequencies and frequency ranges for the the second IF filter. Lastly, the RF signal is amplified and in-
different comprising modules are also shown in Figure 4 and band filtered to then be sent to the antenna. The Automatic
Figure 5. Level Control (ALC) block keeps a constant power level at
the output, in order not to saturate the power amplifier. The
control unit also manages this block. Due to the power
amplifiers need for at least 5W in order to be able to be
excited, an external pre-amplifier unit has been developed.
This unit is capable of delivering around 8W.

RF filters without any special needs, such as narrow

bandwidths or high Q as the IF filters, are implemented with
capacitors and inductors, both axial and toroidal. 10.7MHz
filters in charge of filtering the output of the D/A converter in
the transmitter or the input of the A/D converter in the
receiver have been acquired in KRFilters [5]. These high
quality filters have very narrow bandwidths at a centre
frequency of 10.7 Mhz (1Mhz and 3 MHz). In the case of the
Figure 2: RF Front-end and FPGA setup 112MHz IF a 1MHz bandwidth Surface Acoustic Wave
(SAW) filter has been selected, as the only kind of filter with
By virtue of being a half-duplex transceiver, there are two such a narrow bandwidth at said centre frequency.
common blocks to receiver and transmitter: local oscillators
and control unit. The control unit manages the front-end and It is important to highlight that the pass-band filter at the
it also interacts with the operator by means of a personal input of the receiver is composed of 4 relay-switched tunable
computer. Moreover, it programs the oscillators in order to pass-band filters. The passive diode ring mixers are all model
change the reception and transmission frequencies, it acts on TUF-1 from Minicircuits.
the different parts of receiver and transmitter in order to
change gains and switch on or off several parts of the circuit, Oscillators unit is based on DDS. Thus, design and
and lastly it switches the TX/RX relay. integration are simplified, while microhertz resolutions, fast
frequency steps, phase control and improved phase noise can
be achieved. The DDS integrated circuit employed has been
Antenna Receiver To FPGA ADC Analog Devices AD995.

In Figure 6 and Figure 7 several pictures of the system

Relay
Control
modules are shown. In Figure 6 part of the RF backplane can
Oscillators
Unit be seen. All digital control signals for the different RF front-
end modules are routed through the backplane bus. All
radiofrequency signals are connected in the subrack front.
The 3U form board (100x160mm) with the two DDS-based
Transmitter From FPGA DAC
oscillators and DIN41612 connector is shown in Figure 7.

The following list summarises the main RF front-end

Figure 3: RF Front-end block diagram
characteristics:
In the receiver depicted in Figure 4, the signal at the antenna
• Double conversion superheterodyne (up-mixing).
is filtered in the HF band (3-30MHz), to be then amplified.
• 1st IF: 112MHz and 2nd IF: 10.7MHz.
The first mixer is in charge of translating the RF frequency to
• Frequency steps: 1Hz.
the selected first IF, by means of the first local oscillator.
• Sensitivity (@1MHz): -70dBm.
Once at first IF, the signal is in-band amplified and then it is
• Microcontroller-based RX, TX, AGC and ALC
mixed with the second local oscillator at the second mixer so
control.
that to be translated to second IF frequency. Just before
• Modular assembly.
entering the A/D converter, the signal is filtered and
• Output power -20dBm.
amplified. The Automatic Gain Control (AGC) circuit,
• External power amplifier (linear class A).
 DAC
ADC

Low Pass
10.7 MHz

BW = 1MHz
10.7 MHz
d 75 dB

AGC
BW 1 MHz
10.7 MHz

122.7 MHz
BW = 1 MHz
112 MHz

DDS
82 - 109 MHz
d 20
dB

PController
CARDS12
BW = 1.0 MHz
112 MHz

Filters 3-30 MHz

Band Pass

PController
CARDS12
122.7 MHz
Image-rejection
Filter 3-30MHz

VGA
DDS

Filters 3-30 MHz

Band Pass
82-109 MHz
RF Amp

ALC

RS232
Filters 3-30MHz
Band Pass

RS232

Antenna
3-30 MHz
Antenna
3-30 MHz

Figure 5: Transmitter block diagram

Figure 4: Receiver block diagram

2.1 Measurements
A capture of a spectrum analyzer’s display, connected at the
output of the frontal IF while a multicarrier signal, with a
centre frequency of 20MHz is being received [1], is shown in
Figure 8. This multicarrier signal has been generated by a
function generator with a multitone function selected. This ANT
RX OL
signal is composed of 9 unmodulated tones spaced 100KHz TX
Control
apart (bandwidth of 900KHz), with a -70dBm level and a
26dB carrier to noise floor ratio. As shown, the output PS

frequency is centred at 10.7MHz, while the function generator

carrier to noise floor ratio has been degradated 4dB only. In Figure 6: RF Front-end subrack 19''
Figure 8 it is also shown how the receiver output signal
exhibits some curvature due to the SAW filter’s frequeny The first step in this process corresponds to the signal
response (112MHz). Thus, tones on the edge of the signal digitalisation by means of an A/D converter. Once digitalised,
have lower values than those central ones. the signal is placed in baseband through a Digital Down
Converter (DDC), and then the output of this converter is
3 Digital part: FGPA and DSP processed in order to recover the information. This final step
of processing can be carried out in a PC or partly or
The RF analog front-end has been described in the preceding completely in a DSP.
section. Both input and output signals in the front-end
correspond to a multicarrier signal centred at a 10.7MHz The design of the digital stage has been carried out
intermediate frequency and with a bandwidth of 1MHz. The implementing the multichannel DDC and Digital Up
next step is to (bidirectionally) translate this signal to Converter (DUC) in a FPGA, while the processing stage has
baseband, to be digitally processed in order to recover its been implemented by a combination of PC and fixed-point
information. DSP. Some parts of this design can be seen in Figure 9.
 3.1 DDC and DUC
The mission of a DDC is to translate the interest frequency
band to baseband and to downsample the digitalised signal.
OL 1 Through a DUC,.the inverse process is achieved.

The basic blocks of a DDC are shown in Figure 10,

DDS 1 comprising at least the following subsystems:
Clock
x A Number Controlled Oscillator (NCO), with I and
Q outputs and two mixers in charge of translating the
DDS 2 interest frequencies to baseband.
x A CIC low-pass filter, with the mission to decimate
OL 2 the signal in order to reduce the sampling rate.
x A FIR filter to compensate the sinc-like response of
the CIC filter. Optionally, it can also decimate the
signal once more.
x A FIR filter to correctly channalise the signal in
Figure 7: Oscillators board order to guarantee the baseband spectral mask
imposed requirements .This last stage of filtering can
be also used to decimate once again the signal, or to
interpolate it, in order to adapt the output sampling
rate of the whole filtering chain.

Figure 10: Monochannel DDC building blocks

The DDC and DUC blocks have been implemented on an

Altera FPGA development kit (CycloneII EP2C70),
comprising A/D and D/A converters. The tools used have
been:
x Altera DSP Builder. It enables simulating the block
Figure 8: IF output 10.7MHz (signal to FPGA A/D) behaviour of the FPGA programmable logic inside
Matlab’s Simulink.
x Altera Megacore. This tool provides a set of
programmable logic blocks optimised for some
signal processing common operations: NCO, CIC,
FIR, FFT, Reed-Solomon and Viterbi coding and
decoding, etc.
x Altera QuartusII. It allows synthesising and
implementing the programmable logic generated by
the aforementioned tools.

Initially, monochannel DDC and DUC were implemented. In

order to turn them into multichannel, the possibility of reusing
structures instead of repeating them was investigated, in order
to save both space and processing time. Reused resources
Figure 9: Altera FPGA and ‘c6416 DSP development board correspond to those of the filtering chain. The elements of this
filtering chain communicate with one another by means of a
proprietary bus by Altera, called Avalon Streaming Interface.
This interface makes it possible to multiplex in time the
different channels, so that to avoid the necessity for repeated
whole structures. Thus, input data for each channel are DUC/DDC
multichannel
packed and multiplexed using a dedicated block, Avalon (FPGA)
Packet Format Converter. This block generates multiplex
signals and data from each individual channel data and
1KW Power
signals. amplifier

Driver
Furthermore, two solutions have been developed to
interconnect the FPGA with the PC, in order to further free
Wattmeter
from processing load the PC where the modem programs are
ran. The first solution corresponds to the usage of the audio Broadband
transceiver
input and output lines (Line IN and Line OUT) in the FPGA
development board, in order to implement an audio codec
capable of communicating with the PC through a commodity
sound card used by the software modem. This option is
capable of processing whichever two channels, sent to the PC
in the left and right channels of the sound card. Figure 11: Broadband digital HF transceiver
The second option, partially implemented at the moment, However, this broadband system introduces a number of
enables the connection of more than two channels, making challenges in its operation. Firstly, it needs to coexist with the
use of the network card coupled to the FPGA development traditional narrowband systems, and so it needs to tackle
board. Thanks to this network card, but also by integrating a arising problems, such as sensitivity of the broadband
microprocessor inside the FPFA (NiosII) equipped with a receiver to strong narrowband signals, requiring the use of
operating system (uClinux), the transmission of the baseband further filtering or signal processing, as those narrow signals
data between the FPGA and the PC is possible, by means of affect receiver AGC silencing it. One more factor to take into
an Ethernet connection. account when working with broadband signals is the low
linearity of commercial power amplifiers. Thus, they generate
The microprocessor inside the FPGA running uClinux intermodulation products dirtying the spectrum and
operating system, also allows controlling both DDC and DUC interfering other users. Moreover, it is necessary to have
through a telnet connection. broadband antennas available capable to work with these
kinds of signals without altering their characteristics.
4 Conclusions
In the frequency spectrum, HF band holds several peculiar Acknowledgements
characteristics, as it enables trans-horizon links with limited We thank AENA for their support and also the Spanish
power and without the need for artificial repeaters. These Educational and Science Ministry under Grant
properties have given rise to many studies aiming to optimise TEC2007-67520-C02-01/02/TCM and
its use and improve its range. However, as HF is a rather TEC2008-06874-C03-3.
hostile environment due to noise but also to the high number
of high power stations, the design of communication systems
working in this band is a challenge. References
[1] Joseph J. Carr. “Practical Radio Frequency Test and
A broadband HF modem as the one developed by the authors’ Measurement: A Technician's Handbook”. Newnes
research groups, with channelisation implemented in (Butterwoth-Heinemann), 1999.
baseband, makes for an excellent tool to study frequency [2] M. Puvaneswari, O. Sidek “Wideband analog front-end
diversity techniques, propagation, etc. It should be kept in for multi-standard software defined radio receiver”,
mind that commercially available modems have a bandwidth IEEE, 2004.
no higher than one hundredth of the aforementioned modem. [3] H. Santana-Sosa et al. “Performance over a Real Link of a
HF Software Radio Modem for Interactive Digital Voice
The whole chain assembly in a 19’’ minirack is shown in Communications”, IRST 2006. London, UK.
Figure 11. An SPE Expert 1K FA commercial amplifier is [4] S. Zazo-Bello et al. “Asynchronous and Variable Data
used as final power stage. Rate OFDM Modem for RADAR Data Transmission”,
Submitted to IRST 2009. Edinburgh, UK.
[5] [Link]