21UECE740 ASIC Design (3-0-0) 3
Contact Hours: 39
Course Learning Objectives (CLOs):
The course focuses on ASIC design flow, challenges in the design, verification
phase, and various circuit examples and widely used ASIC tools.
Course Outcomes (COs):
Description of the Course Outcome: Mapping to POs(1-12)/ PSOs
At the end of the course the student will be able (13,14)
to: Substantial Moderate Slight
Level (3) Level (2) Level (1)
CO-1 Interpretthe types of ASIC design flow - 1 -
and its concepts.
CO-2 Analyzethe challenges in designing - 1,2 3
complicated digital circuits and its
CMOS Implementations.
CO-3 Apply the Partitioning & Floor-planning 3 4 -
Techniques
CO-4 Evaluateplacement and routing 5 - 1,2
techniques forASIC.
CO-5 Design of SOC based Architectures 13,14 12 -
and its applications.
Pre-requisites: FPGA and microcontroller architecture.
Contents:
Unit-I
Introduction To ASICs: Types of ASICs, Full-Custom ASICs, Standard cell
based ASICs, Gate array based ASICs, Channelled gate array, channel-less
gate array, structured gate array, Programmable logic devices (PLD), Field–
programmable gate arrays (FPGA),ASIC Design flow, Economics of ASICs with
Example.
06Hrs
Unit-II
Logic Design: CMOS Implementations, Transistor Sizing, Logical Effort:
Predicting delays, logical areas and logical efficiency, logical paths, Multi stage
cells, Optimum delay, Optimum number of stages, RTL design, Concept of RTL
Linting, Clock domain Crossing.
08Hrs
Unit-III
Partitioning &Floor-planning: Partitioning Methods, Measuring Connectivity,
Constructive and Iterative Partitioning, The Kernighan–Lin Algorithm, The Ratio-
Cut Algorithm. Floor-planning goals and objectives, floor planning tools, I/O and
power planning, clock system planning.
08Hrs
Unit-IV
Placement&Routing: placement goals and objectives, placement
algorithms,iterative placement, Time Driven Placement Algorithm, Global routing
and types, Detailed routing: Left edge Algorithm, Special routing. 08
Hrs
Unit- V
System-On-Chip Design - SoC Design Flow, Platform-based and IP based SoC
Designs, Basic Concepts of Bus-Based Communication Architectures, On-Chip
Communication Architecture Standards, Low-Power SoC Design. 09 Hrs
Activity beyond Syllabus:Seminar on Fabrication Techniques
Reference Books:
1) M.J.S. Smith, “Application Specific Integrated Circuits”, Pearson Education,1/e
2002.
2) Jose E. France, YannisTsividis, “Design of Analog–Digital VLSI Circuits for
Telecommunication and Signal Processing, Prentice Hall, 2/e 1993.
3) Malcolm R Haskard, Lan C, May, “Analog VLSI Design – NMOS and CMOS”,
Prentice Hall, 1998.
4) Hoi-Jun Yoo, KangminLeeandJunKyong Kim, “Low-Power NoC for High-
Performance SoC Design”, CRC Press, 2008
