FEM Level Shifter
No load test results
Simulation vs PCB waveform comparison
Simulation PCB
Trig (ch1)
Trig_inst (ch2)
PA_SW (ch3)
LNA_SW (ch4)
PA_BIAS (ch5)
LNA_BIAS (ch6)
Waveform legend and Test Conditions
S No. Parameter Value
Trig (ch1)
1 Vcc 2.7 V
2 Vio 2.7 V
Trig_inst (ch2)
3 Voh PA -3.4 V
PA_SW (ch3)
4 Voh LNA -2.3 V
5 Vol PA/LNA -5 V LNA_SW (ch4)
6 Voh PASW/ 0V
LNASW
PA_BIAS (ch5)
7 Vol PASW/ -20V
LNASW LNA_BIAS (ch6)
8 VEE -25V
9 Trig Ton/Tperiod 1us/10us
Output voltage levels
S No. Parameter VOH(V) VOL (V)
Trig (ch1)
1 Trig 2.70 0.03
2 Trig_inst 2.81 -0.01
Trig_inst (ch2)
3 PA_SW 0.15 -20.50
PA_SW (ch3)
4 LNA_SW 0.45 -20.05
5 PA_BIAS -3.35 -4.925 LNA_SW (ch4)
6 LNA_BIAS -2.235 -5.055
PA_BIAS (ch5)
LNA_BIAS (ch6)
Level comparison (Sim vs PCB)
Simulation PCB
S No. Parameter
VOH(V) VOL (V) VOH(V) VOL (V)
1 Trig 2.70 0.00 2.70 0.03
2 Trig_inst 2.69 0.06 2.81 -0.01
3 PA_SW -0.06 -19.99 0.15 -20.50
4 LNA_SW -0.06 -19.99 0.45 -20.05
5 PA_BIAS -3.39 -5.00 -3.35 -4.925
6 LNA_BIAS -2.31 -5.00 -2.235 -5.055
Low to high propagation delay (reference trig rising edge)
S No. Signal Delay (ns)
Trig (ch1)
1 Trig_inst 115.12
2 PA_SW 76.69 Trig_inst (ch2)
3 LNA_SW 29.55
PA_SW (ch3)
4 PA_BIAS 64.59
5 LNA_BIAS 34.24 LNA_SW (ch4)
PA_BIAS (ch5)
LNA_BIAS (ch6)
High to low propagation delay (reference trig falling edge)
S No. Signal Delay (ns)
Trig (ch1)
1 Trig_inst 62.67
2 PA_SW 248.24 Trig_inst (ch2)
3 LNA_SW 177.44
PA_SW (ch3)
4 PA_BIAS 100.96
5 LNA_BIAS 199.79 LNA_SW (ch4)
PA_BIAS (ch5)
LNA_BIAS (ch6)
Propagation Delay comparison (Sim vs PCB)
Simulation PCB
S No. Parameter
Tplh (ns) Tphl (ns) Tplh (ns) Tphl (ns)
1 Trig_inst 245.95 49.71 115.12 62.67
2 PA_SW 120.71 231.36 76.69 248.24
3 LNA_SW 13.55 275.64 29.55 177.44
4 PA_BIAS 150.41 143.69 64.59 100.96
5 LNA_BIAS 32.28 228.65 34.24 199.79
Low frequency voltage ripples
● Low frequency ripples seen on
VOL of PA_BIAS and LNA_SW
Trig (ch1)
Trig_inst (ch2)
PA_SW (ch3)
LNA_SW (ch4)
PA_BIAS (ch5)
LNA_BIAS (ch6)
Actions
1. Increase falling edge delay of LNA_SW
2. Increase falling edge delay of PA_BIAS
2. Suppress the ripple on PA_BIAS
Fixed Voltage ripple on PA Bias
Trig (ch1)
Trig_inst (ch2)
PA_SW (ch3)
LNA_SW (ch4)
PA_BIAS (ch5)
LNA_BIAS (ch6)
Fixed Timings
Old Timings New Timings
Trig (ch1)
Trig_inst (ch2)
PA_SW (ch3)
LNA_SW (ch4)
PA_BIAS (ch5)
LNA_BIAS (ch6)
50n
50n 50n 150n 50n
50n 150n 1u 50n
50n
Simulation PCB
S No. Parameter
Tplh (ns) Tphl (ns) Tplh (ns) Tphl (ns)
1 Trig_inst 245.95 49.71 290
260
2 PA_SW 120.71 231.36
3 LNA_SW 13.55 275.64
4 PA_BIAS 150.41 143.69
5 LNA_BIAS 32.28 228.65
PN Junction Fabrication using Selective LASER Melting
P-doped line N-doped line
Bond Wire
Conductive Ink
PN Junction
Fig.2 Wire bonded Junction and its I-V Characteristics
Fig.1 PN Junction bonded to dot-board Fig.3 Commercial 1N4007 Silicon Diode and its I-V Characteristics
SEM Level Shifter 2.0
Power on Instructions
Setup
● Default setup : Vdd = 5V, Vio = 2.7V, Vee = -25V, Voh_lna = -2.3V, Voh_pa = -3.4V
● PA_bias load = 1nF, LNA_bias load = 1nF
Power Sequencing
a. Apply Vdd = 5V to the board (Idd < 10mA, current limit to 50mA)
b. Apply square pulse (100kHz, 10% duty, 0-2.7V levels) to Trig input
c. Verify Trig_inst output is as expected from waveform
d. Apply Vee = -25V (Idd < 70mA, current limit to 100mA)
e. Check all voltage levels of output waveforms, use potentiometers to tune to desired
levels
FEM Level Shifter Revision 2.0
Simulation PCB
Version 2.0 review
1. Multiple RC values have to be changed from simulation, the updated BoM will
be provided.
2. All rise and fall times are within 50ns.
3. Heating of output transistor is fixed with two additional bias resistors that has
to be soldered manually.
