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Overview of MOSFET Scaling
§ Conventional (Dennard) scaling
§ Advanced scaling
10 January 2025 Souvik Mahapatra (EE/IITB) 1
Recap: MOSFET Overview G
S D
§ Four terminal device – Gate (G), Source (S), Drain (D) and B
Substrate or Body (B)
§ All voltages and currents are (conventionally defined) with reference
to the Source terminal
§ Field Effect – voltage applied to the Gate (VGS) induces charges in the
substrate
• Fixed (depletion layer) and mobile (inversion layer)
§ Transport – voltage applied to the Drain (VDS) results in a flow of
mobile inversion layer charges, resulting in drain current (IDS)
§ Ideal MOSFET – no current flows via gate insulator
10 January 2025 Souvik Mahapatra (EE/IITB) 2
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1/10/25
Recap: MOSFET Overview
G § Flow of electrons between source and
drain is controlled by applied gate bias
S D
B § Gate Controlled Switch
Electron Energy Barrier VS=0, VB=0, VS=0, VB=0,
VS=0, VB=0, VG=0, VD=0 VG=0, VD>0 VG>0, VD>0
10 January 2025 Souvik Mahapatra (EE/IITB) 3
Recap: MOSFET Overview
W
G
COX
S D Channel charge Lateral field
L
B ID / W = COX (VG – VT) µ. VD / L
Drain current (log-scale)
Mobility
§ Carrier density, mobility
and electric field
influences ON current
§ Thermionic barrier
influences OFF current VT
ID / W ~ exp (q/kT (VG – VT))
Gate voltage (linear scale)
10 January 2025 Souvik Mahapatra (EE/IITB) 4
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1/10/25
MOSFET Scaling
§ Scale gate / channel length, the distance between Source and Drain
• Higher drain current – higher clock frequency of the chip
§ Scale other dimensions (gate width, spacer and contact dimensions)
• More transistors in a given area – more functionality
G G § Transit time = L / vdrift
S D S L D
L § Switching speed = 1 / Transit time
B B
§ Reduce L to increase speed
• Delay: t = C V / ID
• ID ~ 1/ L
10 January 2025 Souvik Mahapatra (EE/IITB) 5
Evolution of MOSFET Scaling
1000
Leff
L=Node
Pl a n
100
ar § Technology node
FinF
E T used to mean
Size, nm
physical
dimension, not
10 anymore
L used to be in
sync with
L quickly accelerated
technology node L scales again (SCE control), but falls
then saturated (SCE)
behind node numbers
1
0.35um
0.25um
90nm
65nm
45nm
32nm
22nm
14nm
10nm
0.7um
0.5um
1um
7nm
5nm
180nm
130nm
Courtesy: Victor Moroz,
Synopsys
10 January 2025 Souvik Mahapatra (EE/IITB) 6
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1/10/25
Evolution of MOSFET Scaling
1000
Leff
L=Node
Pl a n
100
ar § All features,
FinF
E T channel length,
Size, nm
80’s & 90’s
Proportional scaling
area/layout (spacer,
contact) scale in
10 proportion
1
0.35um
0.25um
90nm
65nm
45nm
32nm
22nm
14nm
10nm
0.7um
0.5um
1um
7nm
5nm
180nm
130nm
Courtesy: Victor Moroz,
Synopsys
10 January 2025 Souvik Mahapatra (EE/IITB) 7
Evolution of MOSFET Scaling
1000
Leff
L=Node
Pl a n
100
ar § Channel length
FinF
E T scaled more than
Size, nm
80’s & 90’s
Proportional scaling
2000+ other features
L scaling
10
1
0.35um
0.25um
90nm
65nm
45nm
32nm
22nm
14nm
10nm
0.7um
0.5um
1um
7nm
5nm
180nm
130nm
Courtesy: Victor Moroz,
Synopsys
10 January 2025 Souvik Mahapatra (EE/IITB) 8
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1/10/25
Evolution of MOSFET Scaling
1000
Leff
L=Node
Pl a n
100
ar § Channel length
FinF
E T scaling stops
Size, nm
80’s & 90’s
Proportional scaling
2000+
2005+
(SCE), area
L scaling
Contact & spacer scaling by spacer
scaling
10 and contact
1
0.35um
0.25um
90nm
65nm
45nm
32nm
22nm
14nm
10nm
0.7um
0.5um
1um
7nm
5nm
180nm
130nm
Courtesy: Victor Moroz,
Synopsys
10 January 2025 Souvik Mahapatra (EE/IITB) 9
Evolution of MOSFET Scaling
1000
Leff
L=Node § Back to channel
100
Pl a n
ar length scaling due
FinF
E T to FinFET (better
Size, nm
80’s & 90’s
Proportional scaling
2000+
2005+
SCE control), also
L scaling
Contact & spacer 2015+ area scaling
scaling Proportional
10 scaling (spacer, contact
etc.) – but channel
length scaling
1 unlikely to
continue
0.35um
0.25um
90nm
65nm
45nm
32nm
22nm
14nm
10nm
0.7um
0.5um
1um
7nm
5nm
180nm
130nm
Courtesy: Victor Moroz,
Synopsys
10 January 2025 Souvik Mahapatra (EE/IITB) 10
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MOSFET Scaling – Historical Trend G
S D
§ Dimensions (e.g., gate length, gate oxide thickness) B
reduce from one to next technology node IBM
§ Supply voltage (gate, drain) also reduce, but less
that feature sizes
§ High electric field à Short Channel Effects
Feature size (Microns)
CPU Transistor count
CPU Transistor count
Gate oxide thickness
Intel Intel
(nm SiO2)
Year of fabrication Year of fabrication
10 January 2025 Souvik Mahapatra (EE/IITB) 11
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MOSFET Scaling and Short Channel Effects G
S D
§ Ideal (constant field) versus practical scaling B
• In reality, supply voltage scales less than
device dimensions
§ Short Channel Effects:
• Threshold Voltage roll off
• Drain Induced Barrier Lowering
• Punch Through
• Channel Length Modulation
• Velocity saturation (mobility degradation
due to high lateral field)
§ Device design, mitigation of short channel effects
10 January 2025 Souvik Mahapatra (EE/IITB) 12
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1/10/25
A Simplified View of MOSFET Short Channel Effect
§ Ideal: No influence of G G
Drain on Source barrier S D S D
B B
§ Short L: Drain causes
additional Source barrier
lowering
VS=0, VB=0,
§ Loss of Gate control VG=0, VD=0
VS=0, VB=0,
VG>0, VD>0
10 January 2025 Souvik Mahapatra (EE/IITB) 13
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Scaling – Power Problem G
S D
§ In reality: Supply voltage B
scales less than device
dimensions
§ Increase in dynamic power
§ Dramatic increase in standby
power Intel
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1/10/25
Advanced Scaling Concepts and Issues G
S D
§ Mobility enhancement due to B
mechanical strain
§ High-K Metal Gate technology
§ Architecture changes to mitigate
Short Channel Effects Intel
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Advanced Scaling Examples
Strain - mobility HKMG - leakage FinFET - SCE
Intel
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1/10/25
Advanced Scaling Examples
§ Tall and narrow fins (mechanical stability, variation)
§ Improvement in gate oxide process
§ Node names have no
resemblance to ANY
physical dimensions
at present, it is just a
marketing metric
2011 (Intel) 2014 (Intel) 2019 (Intel) Intel 7nm Intel 4nm Intel 3nm
L=26nm L=20nm L=18nm (2022) (2023) (2024)
W=10nm (avg.) W=8nm (avg.) W=7nm (avg.)
H=34nm H=42nm H=50nm
10 January 2025 Souvik Mahapatra (EE/IITB) 17
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Future of Scaling
§ FinFET scaling is coming to an end
§ Gate All Around Stacked Nanosheets are promising alternative
§ In future, NMOS and PMOS are
proposed to be vertically
stacked (as opposed to them
being side by side now) to
further enhance area scaling
§ Power delivery via the FET
backside (as opposed to top
IBM side with signal lines now) is
another area of interest
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