ChapterSix:

The Memory Unit

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In this chapter:
 Computer Memory system overview
- Introduction
- Memory Hierarchy
 Cache Memory
 Main Memory
 External Memory
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Introduction
Memory is an essential component of
computers
 It is used for storing programs and data
It exhibits wide range of type, technology,
organization, performance, and cost
Total capacity: visualized as being
hierarchy of components:
 Internal and
 External
 Introduction . . . 4

Characteristics of Memory Systems

 Location
 Capacity
 Unit of transfer
 Access method
 Performance
 Physical type
 Physical characteristics
 Organization
 Introduction . . . 5

Location:
 Refers to whether it is internal or external to computer
 CPU
-Registers
 Internal:
-main memory, cache
-Directly accessible by CPU
 External – magnetic disks, tapes, optical disks
-Accessible by CPU through I/O module
- also called secondary memory
 Introduction . . . 6

Capacity:
 the amount of information that can be
contained in a memory unit
 For internal memory, typically expressed in
bytes (8 bits) or words (8, 16, 32 bits)
 External, in terms of bytes
Unit of transfer:
 Internal: the no of data lines into and out of
memory
 May be equal to word length or larger (64, 128,
or 256 bits)
 Introduction . . . 7

Related concepts:
 Word: the “natural” unit of organization of memory
-Usually equal to size of integer or instruction length
 Addressable units: Smallest location which can be
uniquely addressed
-Usually a word
 Some systems allow memory addressing at byte level
 For a length of A address bits, no of addressable units N
is 2A = N
 For external memory, transfer is in blocks
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Introduction . . .
Method of access:
 Sequential access:
-Access to records is made in a specific linear
sequence
-Shared read/write mechanism
-Access time – depends on location of data and
current location of read/write mechanism e.g. tape
 Direct access:
-Individual blocks have unique address
-Shared read/write mechanism
-Access by jumping to vicinity plus sequential search
-Access time – depends on location and current
location of read/write mechanism e.g. disk
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Introduction . . .
 Random access:
-Individual addresses identify locations exactly
-Each location – its own (wired) addressing mechanism
-Access time – constant, independent of location or
previous access - e.g. RAM

 Associative
- Data is located based on a portion of its content
- Comparison done simultaneously on all words
- Access time - independent of location or previous
access - e.g. cache
 Introduction . . . 10

Performance:
 Access time (latency)
- For random-access memory:
- time between presenting the address and getting the
valid data
- For non-random-access memory:
- time to position the read/write mechanism
 Memory cycle time
- Applies to random-access memory
- Time may be required for the memory to “recover” before
next access
- Represents (access time + recovery time)
 Introduction . . . 11

 Transfer rate
- Rate at which data can be moved into/out of a memory
unit
- For random-access memory:
- Represents 1 / cycle time
- For non-random-access memory:
TN = TA + N/R
TN = average time to read/write N bits
TA = average access time
N = number of bits
R = transfer rate [bps]
 Introduction . . . 12

Physical Types
 Semiconductor
- RAM
 Magnetic
- Disk, tape
 Optical
- CD, DVD
 Magneto-optical
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Introduction . . .
Physical Characteristics
 Volatility
- Volatile memory
- Information is lost when electrical power is
switched off
- Some semiconductor memories E.g RAM
- Non Volatile memory
- Information once recorded remains without
deterioration
- Electrical power not needed to retain information
- E.g magnetic storage unit
- Non erasable memory
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Introduction . . .
Organization
 Physical arrangement of bits into words
 Not always obvious
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The Memory Hierarchy
The design constraints on a computer's memory can
be summed – 3 questions:
 How much memory?
- Never enough
- Larger memory capacity → more complex
applications will be developed to use it
 How fast?
- Need to keep up with CPU
 How expensive?
- Reasonable with respect to the other components
Can’t have them all!
 The Memory Hierarchy . . . 16

Trade-off among the three cha-cs:

The following relationships hold:

 Faster access time, greater costs per bit

 Greater capacity, smaller costs per bit
 Greater capacity, slower access time

Solution:
 Memory hierarchy
 The Memory Hierarchy . . . 17

Memory hierarchy diagram

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The Memory Hierarchy . . .
Memory hierarchy characteristics, going down
the diagram
 Decreasing cost per bit
 Increasing capacity
 Increasing access time
 Decreasing frequency of access of the memory
by the processor

Hierarchy List
 Registers  L1 Cache  L2 Cache  Main
memory  Disk  Optical  Tape
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The Memory Hierarchy . . .
Hierarchy List
Registers
L1 Cache
L2 Cache
Main memory
Disk cache
Disk
Optical
Tape
 20
The Memory Hierarchy . . .
Locality of Reference Principle
 during the course of the execution of a program,
memory references by the processor tend to
cluster
 e.g. Loops, tables and arrays

Two forms of locality:

 Temporal locality
 Spatial locality
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Cache Memory
Cache memory principles
 Small amount of fast memory
 Sits between main memory and CPU
 May be located on CPU chip or module
 Contains copies of sections of main memory
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Cache Memory . . .
Cache/Main Memory Structure
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Cache Memory . . .
Cache Operation
 CPU requests contents of memory location
 Check cache for this data
 If present
- get from cache (fast)
 If not present
- read required block from main memory to
cache
- deliver data to CPU
 Tags – identify which block of main memory is
in each cache line
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Cache Memory . . .
Cache Read Operation
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Cache Memory . . .
Typical Cache Organization
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Cache Memory . . .
Elements of Cache Design : - used to classify and
differentiate cache architectures
 Cache Size
 Mapping Function
 Replacement Algorithm
 Write Policy
 Line Size
 Number of Caches
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Cache Memory . . .
Cache Size
Factors that influence cache size:
 Cost
- Size small enough – overall cost per bit
close to that of main memory
 Speed
- Size large enough – overall access time
close to that of cache
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Cache Memory . . .
Mapping Function
- To determine which main memory block
currently occupies a cache line:
 Direct
 Associative
 Set Associative
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Cache Memory . . .

For all three cases, assume:

 Cache size = 64KB = 216 bytes
 Cache block (line) size = 4 bytes = 22 bytes
 Main memory size = 16 MB = 224 bytes
 Address length = 24 bits
 Number of cache lines = 216 / 22 = 214 lines
 Number of blocks in main memory =
224 / 22 = 222
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Cache Memory . . .
Direct Mapping:
 Each block of main memory maps to only one
cache line
-if a block is in cache, it must be in a specific line
 Mapping is:
i = j modulo m
i = cache line number
j = main memory block number
m = number of lines in cache
The mapping function: implemented by the
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Cache Memory . . .
Address viewed as having three fields
 Word, line and tag identifier
 Least Significant w bits identify unique word in a
block
 Most Significant s bits specify one of 2s memory block
- The MSBs are split into
- a tag of s-r bits (most significant)
-Stored in the cache along with the data
words of the line
- a cache line field of r bits
- Identifies one of m=2r lines of the cache
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Cache Memory . . .
Address Structure

 24 bit address
 2 bit word identifier (4 byte block)
 22 bit block identifier
- 8 bit tag (=22-14)
- 14 bit slot or line
 No two blocks in the same line have the same Tag field
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Cache Memory . . .
Direct Mapping Cache Organization:
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Cache Memory . . .
Direct Mapping Summary:
 Address length = (s + w) bits
 Number of addressable units = 2s+w words or bytes
 Block size = line size = 2w words or bytes
 Num of blocks in main memory = 2s+w/2w = 2s
 Number of lines in cache = m = 2r
 Size of tag = (s – r) bits
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Cache Memory . . .
Direct Mapping: Advantage and Disadvantage
 Advantage
- Easy to implement
- Inexpensive to implement
- Easy to determine the right cache line
 Disadvantage
- Fixed location for given block
- If a program accesses 2 blocks that map to
the same line repeatedly, cache misses are
very high
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Cache Memory . . .
Associative Mapping:
 A main memory block can go into any line of the
cache
 Memory address is interpreted as tag and word
 Tag – uniquely identifies block of memory
 Each line’s tag is examined for a match
 Cache searching becomes expensive
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Cache Memory . . .
Address structure:
 24 bit address
- w = 2 bit word identifier (here, word = one byte in
the 4 byte block)
- s = 22 bit tag
 22 bit tag stored with each block of data
 Check contents of cache
- Compare tag field in address with every tag entry
in cache
- Least significant 2 bits of address identify which
word (byte) is required from 4-byte data block
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Cache Memory . . .
Cache organization:
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Cache Memory . . .
Associative Mapping Summary:
 Address length = s + w bits
 Num. of addressable units = 2s+w words/ bytes
 Block size = line size = 2w words or bytes
 Num. of blocks in main memory = 2s+w/2w = 2s
 Number of lines in cache = undetermined
 Size of tag = s bits
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Cache Memory . . .
Set Associative Mapping:
 Compromise between direct and associative
 Cache is divided into a number of v sets
 Each set contains a number of k lines
 Mapping (k-way associative mapping) is:
m=v*k
i = j modulo v
i = cache set number
j = main memory block number
m = number of lines in cache
 A given block maps to any line in a given set
 41
Cache Memory . . .
Address structure:
 24 bit address
 memory address viewed as three fields
- Tag, set and word fields
 Use set field (d bits) to determine cache set to
look in
 Compare tag field (s-d MSB bits) to see if we
have a hit
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Cache Memory . . .
K-Way Set Associative Cache organization:
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Cache Memory . . .
Set Associative Mapping Summary:
 Address length = s + w bits
 Num. of addressable units = 2s+w words/bytes
 Block size = line size = 2w words or bytes
 Num. of blocks in main memory = 2s+w/2w = 2s
 Number of lines in set = k
 Number of sets = v = 2d
 Number of lines in cache = k * v = k * 2d
 Size of tag = s - d bits
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Cache Memory . . .
Replacement Algorithm:
 determine which existing block should be
replaced when a new block is brought into the
cache
 There are a number of algorithms
- LRU, FIFO, LFU…
Direct mapping
 No choice, no algorithm needed
 Each block only maps to one line
 Replace that line
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Cache Memory . . .
For associative and set associative mapping:
 Least Recently Used (LRU):
- Replace that block in the set that has been in
the cache longest with no reference to it
 First-In-First-Out:
- Replace block that has been in the cache
longest
 Least Frequently Used (LFU):
- Replace block that has experienced fewest
references
 Random replacement: - Not based on usage
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Cache Memory . . .
Write Policy:
 If a block has been modified in cache, when
should we update the corresponding block in
memory?
 Additional issues
- Other devices (I/O) may write directly to main memory
- Multiple processors may have their own caches
 Write through:
- All writes done in both cache and main memory
 Write back:
- Writes initially done in cache only
- Uses update bits (set to 1) to write to memory
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Cache Memory . . .
Line Size
 How much data should be transferred from
main memory to the cache in a single memory
reference
 Complex relationship between
- Block size
- Hit ratio:
 48
Cache Memory . . .
Number of Caches:
 Increases in circuit densities → caches can be
placed inside processor chip
 Internal caches
- Very short data paths (within the chip)
- Much faster access than through bus
 Multi-level caches
- L1, L2, L3, …
- L1 on-chip, L2 on-board, etc.
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Semiconductor Main Memory
Organization:
 The basic element of a semiconductor memory
is the memory cell
All memory cells share certain properties
 Two stable/semi-stable states representing 1 & 0
 Capable of being written at least once
 Capable of being read multiple times
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Semiconductor Main Memory
Operation of a memory cell:
 The cell has three functional terminals
- Select terminal
- Selects a memory cell for a read or write operation
- Control terminal
- Indicates read or write operation
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Semiconductor Main Memory
Operation of a memory cell
 For writing
- the third terminal provides an electrical
signal that sets the state of the cell to 1 or 0
 For reading
- The third terminal is used to output the
cell’s state
 52
Semiconductor Main Memory
Semiconductor Memory Types
 53
Semiconductor Main Memory
Random-Access Memory(RAM)
 Misuse of term
- all semiconductor memory is random access
 Distinguishing characteristics
- Allows both read and write (electrically)
- Volatile (used as temporary storage only)
 Types
- Static (SRAM)
- Dynamic (DRAM)
 54
Semiconductor Main Memory
Dynamic RAM (DRAM)
 Bits stored as charge in capacitors
 Capacitor charges leak
- Need refreshing even when powered
 Simpler construction compared to SRAM
 Smaller size per bit
 Less expensive
 Slower
 Application
- Main memory
 Essentially an analog device
- Level of charge determines value
 55
Semiconductor Main Memory
Dynamic RAM Structure
 56
Semiconductor Main Memory
DRAM Operation
 Address line active when a bit is read or written
- Transistor  switch
– closed (if voltage is applied to address line, current flows)
– open (no voltage on address line, no current flows)
 Write
- Voltage to bit line: - high for 1, low for 0
- Then signal address line:-transfers charge to capacitor
 Read
- Address line selected – transistor turns on
- Charge from capacitor is fed via bit line to a sense amplifier
– Compares with reference value to determine 0 or 1
- Capacitor charge must be restored
 57
Semiconductor Main Memory
Static RAM
 Bits stored as on/off switches (flip-flop gates)
 No charges to leak
- No refreshing needed while powered
 More complex construction
 Larger per bit
 More expensive
 Faster
- no sense circuitry or charge depletion
 Application - Cache memory
 Digital device
 Can be battery-backed – small battery next to RAM chip,
maintaining data even when power is removed
 58
Semiconductor Main Memory
Static RAM Structure
 59
Semiconductor Main Memory
Static RAM Operation
 Transistor arrangement gives stable logic state
 State 1
- C1 high, C2 low
- T1 T4 off, T2 T3 on
 State 0
- C1 low, C2 high
- T1 T4 on, T2 T3 off
 Address line transistors
- T5 T6 act as switches connecting the cell to bit lines
 Write – apply desired value to B & complement to B
 Read – value is on line B
 60
Semiconductor Main Memory
SRAM vs. DRAM
 Both volatile
- Power needed to preserve data
 DRAM
- Simpler to build, smaller
- More dense
- Less expensive
- Needs refresh
- Used for main memory
 SRAM
- Faster
- Used for cache
 61
Semiconductor Main Memory
Read-Only Memory (ROM)
 Permanent storage
- Nonvolatile
 Can be read but not written on a regular basis
 Written during manufacture stage
- Expensive for small batches
 Applications
- Microprogramming
- Library subroutines (frequently used functions)
- Systems programs (BIOS)
- Function tables
- Embedded systems code
 62
Semiconductor Main Memory
Types of ROM:
 Programmable (PROM)
 Read “mostly” memory
- Erasable Programmable (EPROM)
- Electrically Erasable Programmable
(EEPROM)
- Flash memory
 63
Semiconductor Main Memory
PROM
 Can be written once
- Process performed electrically
- Later than chip fabrication time
 Needs special equipment to program
 Good for flexibility, smaller volume batches
EPROM
 Can be written several times
- Before writing, all content must be erased with ultraviolet light
 Requires programmer equipment
 Very slow to erase
 More expensive than PROM
 64
Semiconductor Main Memory
EEPROM
 Can be written at any time
- With either programmer equipment or by
processor (electrically)
- Only desired bytes are updated
 Slow write times (10 ms compared to 100-200 ns
for read)
 Advantage
- Can be updated in-place, using regular bus
control, address, and data lines
 More expensive than EPROM
 Less dense
 65
Semiconductor Main Memory
Flash Memory
 Intermediate between EPROM and EEPROM
 Electrical erasing technology
 Can erase select blocks (not all content), but not
each byte individually
 High data density (like EPROM)
- Also higher than both SRAM and DRAM
Read Assignment:-Chip Organization, Error correction
 66
External Memory
External memory is a type of computer memory
that is separate from the main memory.
 also known as secondary memory, storage
devices that can retain data when powered off.
 It has a much higher memory capacity than
main memory, but it has slower input/output
access times.
Types:
 Magnetic disk
 Optical
 Magnetic tape
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External Memory
Magnetic disk
 A disk is a circular platter constructed of nonmagnetic
material, called the substrate, coated with a
magnetizable material
 Substrate used to be aluminum – now glass – has the
following advantages
- Improved surface uniformity
- Increases reliability
- Reduction in surface defects
- Reduced read/write errors
- Lower flying heights,
- Better stiffness
- Better shock/damage resistance
 68
External Memory
Magnetic Read and Write Mechanisms
 Recording and retrieval via conductive coil(s)
called head(s)
 May be single read/write head or separate ones
 During read/write, head is stationary while
platter rotates beneath head
 69
External Memory
Write
 Current through coil produces magnetic field
 Pulses sent to head
 Magnetic pattern recorded on surface below
Read (traditional)
 Magnetic field moving relative to coil produces
current
- Analogous to a generator or alternator
 Coil can be the same for read and write
 Used with:
- Floppies , Older hard drives
 70
External Memory
Read (contemporary)
 Separate read head, close to write head
 Partially shielded magneto resistive (MR)
sensor
 Electrical resistance depends on direction of
magnetic field
- Passing current through it results in different
voltage levels for different resistances
 High frequency operation
- Higher storage density and speed
 71
External Memory
Data organization and formatting
 Data is organized on the platter in set of
concentric rings called tracks
 Adjacent tracks are separated by gaps
- minimize error due to misalignment or EM
interference
 Data are transferred to/from disk in sectors
 72
External Memory
Disk data layout
 73
External Memory
Concentric rings or tracks
 Thousands of tracks per platter surface
 Track is same width as head
 Gaps between tracks (intertrack gaps)
- protect data integrity
 Reduce gaps
- increase capacity
- possibly increase errors due to
misalignment of head or interference from
other tracks
 74
External Memory
Tracks divided into sectors
 Minimum block size is one sector
- may have more than one sector per block
 Typically hundreds of sectors per track
 May be fixed or variable in length
- Contemporary systems are fixed-length,
typically 512 bytes
 Gaps between sectors (intratrack or intersector
gaps)
 75
External Memory
Disk velocity
 A bit near the center of a rotating disk passes a
fixed point (head) slower than a bit on the outside
- Bits are not read at the same rate
 Solutions
- Constant angular velocity (CAV)
- Multiple zone recording
 76
External Memory
Constant Angular Velocity (CAV)
 The disk is rotated at a fixed speed
 Information is scanned at the same rate by
increasing the spacing between bits of
information recorded in segments of the disk
 The disk is divided into a number of pie-shaped
sectors and into a series of concentric tracks
- Individual blocks of data can be directly addressed by track and
sector
 Draw back of CAV
- The amount of data that can be stored on the long outer tracks is
the only same as what can be stored on the short inner tracks
 77
External Memory
Multiple zone recording
 Divide disk into concentric zones – typical
number is 16
 Each zone has fixed number of bits (and
sectors) per track
- More bits per track in outer zones
 More complex circuitry to adjust for different
data rates as heads move farther out
 78
External Memory
Disk layout methods
 79
External Memory
Formatting
 Two kinds of formatting
- Low level – allows hard drive to find sectors
- O/S level – allows for file system
 Must be able to identify start of track and sector
 Format disk
- Additional information not available to user
- Marks tracks and sectors
 80
External Memory
Physical characteristics
 Head Motion
 Disk Portability
 Sides
 Platters
 Head Mechanism
Head motion
 Fixed head (old)
- One read-write head per track
- Heads mounted on fixed arm
 81
External Memory
Head motion
 Movable head
- One read-write head per side
- Mounted on a movable arm
- Heads move radially across tracks
Portability
 Removable disk
- Can be removed from drive and replaced with another disk
- Provides unlimited storage capacity
- Easy data transfer between systems
- Examples: floppy, ZIP, Jazz
 Non-removable disk - permanently mounted in the drive
 External Memory 82
Sides
 Single sided (old, cheap)
 Double sided
Platters
 Single platter
 Multiple platter
- One head per platter surface
- Heads are joined and aligned
- Aligned tracks on each platter form cylinders
- Data is striped by cylinder
- Reduces head movement
- Increases speed (transfer rate
 83
External Memory
Disk performance parameters
 Seek time
- Moving head to correct track
 Rotational delay (rotational latency)
- Time for begining of data to reach the head
 Access time
- Access time = Seek time + Rotational delay
 Transfer time
- The actual time to transfer data
 84
External Memory
Total access time
 The total average access time Ta is:

Ta = Ts + 1/2r + b/rN
 where
- Ts = average seek time
- b = number of bytes to transfer
- N = number of bytes on a track
- r = rotation speed in RPS
 85
Optical Memory
CD ROM
 Originally for audio
 680 MB giving over 70 minutes audio
 Polycarbonate coated with highly reflective
coat, usually aluminium
 Data stored as pits
- Read by reflecting laser
 Constant packing density
 Constant linear velocity
 86
Optical Memory
Operation
 87
Optical Memory
Operation
 Information retrieved from a CD-ROM by a low-powered laser
housed in drive unit
 The laser shines through the clear polycarbonate while a motor
spins the disk past it
 The intensity of the reflected light of the laser changes as it
encounters a pit and land (area b/n pits)
- If the laser beam falls on a pit, which has a somewhat rough surface, the light
scatters and a low intensity is reflected back to the source.
- If the laser beam falls on a land, which has a smooth surface, a higher intensity
light is reflected back to the source
 The change between pits and lands is detected by a photo sensor
and converted into a digital signal
- The sensor tests the surface at regular intervals. The beginning or end of a pit
represents a 1; when no change in elevation occurs between intervals, a 0 is
recorded.
 88
Optical Memory
 To achieve greater capacity, information organized on
the CD-ROM as a single spiral track
- Beginning near the center and spiraling out to the outer edge
 Sectors near the outside of the disk are the same length
as those near the inside
- Information is packed evenly across the disk in segments of the
same size
 Data read at the same rate by rotating the disk at a
variable speed --- at a constant linear velocity (CLV)
- The disk rotates more slowly for accesses near the outer edge than
for those near the center
 89
Optical Memory
CD-ROM Format
 Data organized as a sequence of blocks
 A typical block format shown below and contains the following
fields
- Sync – identifies the beginning of a block
- Header – contains block address and mode byte
- Data – user data
- Auxiliary – additional user data in mode 2
- Mode 0 = blank data field
- Mode 1 = 2048 byte data + error correction
- Mode 2 = 2336 byte data
 90
Optical Memory
Optical Memory Summary
 91
Magnetic Tape
Magnetic Tape
 Serial access
 Slow
 Very cheap
 Backup and archive
Recording
 Parallel
- Eg. 9 tracks: 8 data bits + 1 bit parity
 Serial
- Data is written as sequence of bits along each track
- Typical – serpentine recording
- Follow one track until end of tape, then continue
 92
Magnetic Tape
Typical Magnetic Tape Features
Assignment –2 attached via
telegram