SM4085

Power Management IC for TFT LCD TV

Application

Description Features
The SM4085 consists of a VCOM DAC controller, a high  8.6V to 15.9V Input Supply Voltage Range
performance step-up switching regulator, three high  External Boost Converter Control
performance step-down regulators, a negative LDO  Synchronous Buck Regulator for VCC1
regulator, a high performance buck-boost regulator, 8- . 2-bit Programmable Output Voltage: 3.2V ~ 3.5V
channel gamma buffers and a high voltage level-shifter. . 1.5A (min.) SW Current Limit
. 600 kHz (typ.) Switching Frequency
The HVDD step-down DC-DC converter provides regulated
 Buck Regulator for VCC2
supply voltage for the panel source driver ICs. And the . 4-bit Programmable Output Voltage: 1V ~ 1.35V, 1.7V ~
VCC1 and the VCC2 step-down DC-DC converters provide 2.05V
digital logic supply voltage for the system. The temperature . High Side 4A (min.) SW Current Limit
compensated VGH step-up DC-DC converter, the VGL1 . 600kHz (typ.) Switching Frequency
LDO regulator and the temperature compensated VGL2  Synchronous Buck Regulator for HVDD
buck-boost regulator provide the TFT gate driver supply . 4-bit Programmable Output Voltage VDD/2-0.8V ~
VDD/2+0.7V
voltages. The PVCOM controller and 8-channel gamma
. High Side 2.0A (min.) SW Current Limit
buffers provide reference voltage for panel and source . Low Side -2.0A (max.) SW Current Limit
driver ICs. The high voltage level-shifter is fitted for . 1.2 MHz (typ.) Switching Frequency
capacitive loads and works well with panels that contain  Boost Regulator for VGH
row drivers on the panel glass. The high switching . 4-bit Programmable Output Voltage: 20V ~ 35V
frequency of the converter makes it possible to use ultra- . Temperature Compensated Output: 21V ~ 36V
. 1.0A (min.) SW Current Limit
small inductors and ceramic capacitors. The device is
. 600 kHz (typ.) Switching Frequency
optimized for thin-film transistor (TFT) liquid-crystal display
(LCD) applications.
 Low Dropout Regulator for VGL1
. 5-bit Programmable Output Voltage: -8V ~ -1.8V
 Buck-Boost Regulator for VGL2
Applications
. 5-bit Programmable Output Voltage: -20V ~ -4.5V
. 1.2A (min.) SW Current Limit
. 600 kHz (typ.) Switching Frequency
 LCD TV Panels
 Programmable Power-Up Sequence
 Programmable 8-Channel Gamma Buffers
Ordering Information
 High-Voltage Level Shifter
Pb- . -20V ~ 36V Output Rails
Part Temp. Range Package . Logic Level Input
Free
-40°C to 68 QFN  Protection
SM4085 Yes
+85°C 8mm x 8mm . Thermal Shutdown Protection
. Over Load Protection
. Short Circuit Protection
. Over Voltage Protection

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October 2017 – Rev.1.0.1 1 / 44
 SM4085

Pin Assignments

OCP Time1

OCP Time2

RESET
CLK10
OCP1

OCP2

CLK1

CLK2

CLK3

CLK4

CLK5

CLK6

CLK7

CLK8

CLK9
GND

VST
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
GCLK 1 51 ODD(BRST)
MCLK 2 50 EVEN
GST 3 49 VGH_E/O
E/O 4 ● 48 L/S VGH
GND 5 47 VGH
VGL1 6 46 VGH_SW
VGL2 7 45 GND
VGL2_SW
GND
8
9
SM4085 44 VDD
43 HVDD_Vin(VDD)
VGL2_Comp 10 42 HVDD_SW
VIN 11 (Top View) 41 HVDD
GND 12 40 GND
TCOMP_VGH 13 39 GMA_8
TCOMP_VGL2_VCOM 14 38 GMA_7

VL 15 37 GMA_6
SCL 16 36 GMA_5
SDA 17 35 GMA_4

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Boost EN

Shut Down

AVIN

VIN

GND

VCC2_SW

VCC2

RST

VCC1

VCC1_SW

GND

VIN

GND

VCOMDAC

GMA_1

GMA_2

GMA_3

68 pin 8x8x0.85mm 0.4 pitch QFN

Evaluation Board Request

Available

Top Marking Instruction

DEVICE CODE

SM4085 D : FAB site

A : Ass′y site
DAYYWW YY : work year
WW : work week(Lot input week)
SMKIXXX SM : package supplier code
KI : device code for SM4085
XXX : Ass′y Lot serial No.

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 SM4085

Pin Description
Pin Name Description

1 GCLK Level Shifter Input for Gate Clock Pulse Start.

2 MCLK Level Shifter Input for Gate Clock Pulse End.
3 GST Level Shifter Input for Gate Reset or Gate Start.
4 E/O Level Shifter Input for EVEN/ODD toggling.
5 GND Ground for the Level shifter
Negative LDO Output Voltage pin. Place shunt capacitor as close as possible to this
6 VGL1 pin and shunt to GND. This pin should be connected to output capacitor node for stable
operation.
Inverting Buck-Boost Output Voltage Sensing and Level-Shifter Negative Supply
7 VGL2 Voltage pin. Place shunt capacitor as close as possible to this pin and shunt to GND
(PIN 9). This pin should be connected to output capacitor node for stable operation.
Switching Node of Inverting Buck-Boost converter. VGL2_SW pin is the drain of
8 VGL2_SW high-side power P-MOSFET. Long traces of inductor to VGL2_SW pin should be
avoided.
9 GND Ground for the VGL2 buck-boost converter
Compensation pin for buck-boost converter control loop. VGL2_Comp is the output of
10 VGL2_Comp
transconductance error amplifier.
Supply Input for Inverting Buck-Boost Converter. This pin is the source of power P-
11 VIN
MOSFET.
12 GND Analog Ground. Circuitry of IC control parts uses this ground.
13 TCOMP_VGH Temperature Compensation Input pin for VGH.
TCOMP_VGL2_
14 Temperature Compensation Input pin for VGL2 and VCOM.
VCOM
On-chip 5V Regulator Output pin for IC supply. Bypass minimum 1uF of low ESR/ESL
15 VL
ceramic capacitor to GND. This regulator powers internal IC control circuitry.
2
16 SCL Clock Input pin for the I C serial interface.
2
17 SDA Data I/O pin for the I C serial interface.
18 Boost EN External Main Boost Enable pin.
IC Shutdown pin. IC is disabled if pulled-up to logic-high, or enabled if pulled-down to
19 Shut Down
logic-low.
IC Supply Input pin. In addition to using bulk capacitors of sufficient capacity, it is
highly recommended to use the shunt capacitor of low ESR/ESL to bypass high
20 AVIN
frequency noise. Place shunt capacitor as close as possible to this pin and shunt to
GND (PIN 12).
Buck Converter 2 (VCC2) Power Input. This pin is the source of power P-MOSFET of
VCC2 buck converter. In addition to using bulk capacitors of sufficient capacity, it is
21 VIN highly recommended to use the shunt capacitor of low ESR/ESL to bypass high
frequency noise. Place shunt capacitor as close as possible to this pin and shunt to
GND (PIN 22).
22 GND Ground for the VCC2 Buck converter.
Switching Node of Buck Converter 2 (VCC2). VCC2_SW pin is the drain of high-side
23 VCC2_SW power P-MOSFET. Long traces of VCC2_SW pin to inductor and VCC2_SW pin to
rectifying diode should be avoided.
Buck Converter 2 (VCC2) Output Voltage Sensing pin for regulation. This pin should
24 VCC2
be connected to output capacitor node for stable operation.
25 RST Reset Signal Generator Open Drain Output pin.

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 SM4085

Pin Description (continued)

Pin Name Description
Buck Converter 1 (VCC1) Output Voltage Sensing pin for regulation. This pin should
26 VCC1
be connected to output capacitor node for stable operation.
Switching Node of Buck Converter 1 (VCC1). VCC1_SW pin is the drain of high-side
27 VCC1_SW power P-MOSFET and the drain of low-side power N-MOSFET. Long traces of
VCC1_SW pin to inductor and VCC1_SW pin to rectifying diode should be avoided.
28 GND Ground for the VCC1 Buck converter.
Buck Converter 1 (VCC1) Power Input. VIN pin is the source of power P-MOSFET of
VCC1 buck converter. In addition to using bulk capacitors of sufficient capacity, it is
29 VIN highly recommended to use the shunt capacitor of low ESR/ESL to bypass high
frequency noise. Place shunt capacitor as close as possible to this pin and shunt to
GND (PIN 28).
30 GND Ground for the Gamma amp.
31 VCOMDAC VCOMDAC Output pin for external OP-AMP reference.
Programmable Gamma Voltage Outputs. The voltage range is from HVDD to VDD at
32~35 GMA_1 ~ 4
no output current condition.
Programmable Gamma Voltage Outputs. The voltage range is from 0V to HVDD at
36~39 GMA_5 ~ 8
no output current condition.
40 GND Ground for the HVDD Buck converter.
Buck Converter 3 (HVDD) Output Voltage Sensing pin for regulation. This pin should
41 HVDD
be connected to output capacitor node for stable operation.
Switching Node of Buck Converter 3 (HVDD). This pin is the drains of power P-
42 HVDD_SW MOSFET and N-MOSFET. Long traces of HVDD_SW pin to inductor should be
avoided.
Buck Converter 3 (HVDD) Power Input and Internal Regulator Input pin. HVDD_Vin
pin is the source of power P-MOSFET of HVDD buck converter. In addition to using
HVDD_Vin
43 bulk capacitors of sufficient capacity, it is highly recommended to use the shunt
(VDD)
capacitor of low ESR/ESL to bypass high frequency noise. Place shunt capacitor as
close as possible to this pin and shunt to GND (PIN 40).
44 VDD External Boost converter Power Input and Gamma Amp input supply pin.

45 GND Ground for the VGH Boost converter.

Switching Node of VGH Boost Converter. VGH_SW pin is the drain of power N-
46 VGH_SW MOSFET. Long traces of inductor to VGH_SW pin and VGH_SW pin to rectifying diode
should be avoided.
VGH Boost converter Power Input Pin. Place shunt capacitor as close as possible to
47 VGH this pin and shunt to GND. This pin should be connected to output capacitor node for
stable operation.
48 L/S VGH Level-Shifter Positive Supply Voltage pin except ODD and EVEN.
Positive Supply Voltage for ODD and EVEN outputs. Place shunt capacitor as close
49 VGH_E/O
as possible to this pin and shunt to GND.
50 EVEN Level Shifter Output. When E/O pin is toggled, this pin voltage is also toggled.

51 ODD(BRST) Level Shifter Output. When E/O pin is toggled, this pin voltage is also toggled.

52 RESET Level shifter Output to reset GIP block.

53 VST Level Shifter Output for Vertical Start Pulse. The input signal is GST.

54~63 CLK10 ~ CLK1 Level Shifter Outputs for Gate Clocks. High voltage level shifter outputs.

64 GND Ground for the Level shifter.

65 OCP Time2 L/S Over Current Protection Duration Time Set pin for EVEN, ODD.

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 SM4085

Pin Description (continued)

Pin Name Description
66 OCP Time1 L/S Over Current Protection Duration Time Set pin for CLK1~10, VST and RESET
67 OCP2 L/S Over Current Protection Sensing Level Set pin for EVEN and ODD.
68 OCP1 L/S Over Current Protection Sensing Level Set pin for CLK1~10, VST and RESET
69
The exposed pad must be soldered to a large PCB and connected to GND for
(Exposed GND
maximum power dissipation.
PAD)

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 SM4085

Operational Diagram

VCC1
VCC2

SDA
SCL
As close as
possible to
the PIN
VIN L5
VDD
VGH
VL C8
As close as C1 L1 C10
C6 C7
possible to L2
the PIN

VGH_SW
GND

VCC1

GND
VIN

VIN
TCOMP_VGL2
VL

SCL
SDA
VCC1_SW
VIN
VCC2_SW

VCC2
_VCOM
VL
On-chip
5V LDO
TCOMP_VGH VGH
Boost
VCC2 Buck VCC1 Buck VGH
Converter
Controller Controller
VIN or VDD HVDD_Vin(VDD) VIN
VIN
VGL2 As close as possible
L3 HVDD Buck-Boost to the pin
HVDD_SW VGL2_SW
VHVDD Buck Converter VGL2
C9 Controller C12
L4
GND Master GND

HVDD
Controller VGL2
&
RST VGL2_COMP R1 C13
VCC1 I2C Interface
Shut Down
Shut Down*)
VGL1 VGL1 C14
As close as possible VGL1
to the sub-PMIC LDO C11 As close as possible
Boost EN
Exteranl to the pin
L/S VGH
Boost EN Cboost VGH
C2
VDD GCLK
VDD
As close as possible MCLK
C4 to the sub-PMIC
GMA_1 CLK1
DAC
CLK2
C13
CLK3
GMA_2 Level Shifter
DAC
CLK4
C13
GMA_3 CLK5
DAC x10 CLK6
C13 CLK7
GMA_4
DAC CLK8
Source Driver

C13 CLK9
HVDD
AGND_GMA CLK10
GMA_5
DAC OCP1
C13 OCP TIME1
GMA_6
DAC

C13
GMA_7 Level Shifter GST
DAC
RESET
C13
GMA_8 VST
DAC
x2
C13
E/O
AGND_GMA Level Shifter
EVEN

ODD(BRST)
PVCOM VGH_E/O
DAC x2 VGH
Exteranl VCOMDAC C3 As close as possible
OP to the pin
C5 OCP2
AMP
OCP TIME2

As close as Backplane Thermal Pad

possible to
the AMP GND

SM4085
*): IC is disabled if pulled-up to High, or enabled if pulled-down to Low.

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 SM4085

Recommended Components
1)
Capacitor Value
Recommended Value
Symbol Description Tolerance Type
Min. Typ. Max

C1 AVIN Capacitor 1μF - - X5R, X7R

C2 L/S_VGH Input Capacitor 2.2μF - - X5R, X7R

C3 VGH_E/O Input Capacitor 2.2μF - - X5R, X7R

C4 VDD Input Capacitor 2.2μF - - X5R, X7R

C5 VCOMDAC Output Capacitor 10nF - 1μF X5R, X7R

C6 VL Output Capacitor 1μF 2.2μF 4.7μF X5R, X7R

C7 VCC1 Output Capacitor1),4) 30μF - - ±10% X5R, X7R

1),4)
C8 VCC2 Output Capacitor 40μF - - X5R, X7R
1),4)
C9 HVDD Output Capacitor 20μF - - X5R, X7R
1),4)
C10 VGH Output Capacitor 18μF - - X5R, X7R

C11 VGL1 Output Capacitor1),4) 10μF - - X5R, X7R

C12 VGL2 Output Capacitor1),2),4) 20μF - - X5R, X7R

1)
C13 Gamma Output Capacitor - - 560pF X5R, X7R

1)
Inductor Value
Recommended Value
Symbol Description Tolerance Type
Min. Typ. Max
L1 VCC2 Inductor 2.2μH Coil Inductor

L2 VCC1 Inductor 22μH Coil Inductor

L3 HVDD Inductor 10μH ±20% 5)

Coil Inductor

L4 VGL2 Inductor2) 10μH Coil Inductor

L5 VGH Inductor 22μH Coil Inductor

2)3)
VGL2 Compensation Value
Recommended Value
Symbol Description Tolerance Type
Min. Typ. Max

R1 VGL2 Comp Resistor(Series) 56kΩ -

C13 VGL2 Comp Capacitor(Series) 1nF ± 10% X5R, X7R

C14 VGL2 Comp Capacitor(Parallel) 100pF X5R, X7R

Notes
1) It is essential to keep the minimum output capacitor and inductor value for its loop stability.
2) The VGL2 is optimized in discontinuous operation mode with this value.
3) If the VGL2 operates in continuous operation mode, these values should be changed for its loop stability.
4) The maximum 50% derating caused by applying dc voltage and temperature is acceptable as an effective capacitance
for stable operation.
5) The 30% tolerance with the temperature factor is acceptable.

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 SM4085

Absolute Maximum Ratings

Stress(es) beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the
following operational sections of the specifications are not implied. Exposure to absolute maximum rating condition(s) for
extended periods may affect device reliability.

Parameter I/O Lower Limit Upper Limit Unit

VGH, VGH_E/O, L/S_VGH, VGH_SW to GND1) I -0.3 43 V

1)
VGL2 to GND I -22 0.3 V
1)
VGL1 to GND I -10 0.3 V
VGL2_Comp, VCC1_SW, VCC2_SW, VCOMDAC, HVDD_SW, GMA_1 ~
O
GMA_8 to GND1 -0.3 21 V
1)
VIN, HVDD_Vin(VDD), VDD, Shut Down to GND I
VGL2_SW to GND1) I VGL2-0.3 VIN+0.3 V
1)
HVDD to GND O -0.3 12 V
TCOMP_VGH, TCOMP_VGL2_VCOM, GCLK, GST, E/O, MCLK, SCL,
I
SDA, OCP1, OCP2, OCP Time1, OCP Time2 to GND1) -0.3 7 V
VCC1, VCC2, Boost EN, VL, RST to GND1) O
L/S_VGH and VGH_E/O to VGL2 I 57 V
1)
VST, RESET, CLK1 ~ CLK10 to GND O VGL2-0.3 VGH+0.3 V
1)
ODD(BRST), EVEN to GND O VGL2-0.3 VGH_E/O+0.3 V
2)
ESD Human Body Model 2000 V
ESD Machine Model2) 200 V
2)
ESD Charged Device Model 800 V

Continuous Power Dissipation (TA=25°C)3) 4.2 W

Operating Ambient Temperature -40 85 °C
Operating Junction Temperature -40 125 °C
Maximum Junction Temperature 150 °C
Storage Ambient Temperature -65 150 °C
Lead Soldering Temperature (within 10s) 300 °C

Notes
1) GND: all of the GND should be within the limit.
2) Human Body Model (HBM) per JESD22-A114 for all pins, HBM upper limit of SDA, SCL pins is 6kV. Machine Model
(MM) per JESD22-A115 for all pins. Charged device model (CDM) per JESD22-C101 for all pins.
3) Highly depends on the PCB heat dissipation. Tested with the Thermal Characteristics test condition below.

Thermal Characteristics
Parameter Symbol Value Unit
Junction-to-ambient thermal resistance1) ΘJA 23.8 °C/W
Junction-to-case thermal resistance1),2) ΘJC 1 °C/W
3)
Junction-to-top characterization parameter ΨJT 0.3 °C/W
Notes
1) TA=25°C.
2) Measured in still air-free convection condition (conforms to EIA/JESD51-2) on high effective thermal conductivity
JESD51-7 test board. The case point of ΘJC is on the exposed pad.
3) The junction-to-top characterization parameter, ΨJT, estimates using a procedure described in JESD51-2A.

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 SM4085

Electrical Characteristics
VIN = VHVDD_Vin = 12V, VDD = 14.5V, VHVDD = 7.25V, VCC1 = 3.3V, VCC2 = 1.2V, VGH = 28V, VGL1 = - 5V, VGL2 = -15V, TA = TJ, TA =
*) 1)
-40°C ~ 85°C . Typical values are at TA=+25 °C, unless otherwise specified.
*) Specifications over the TA range are guaranteed by design, characterized and correlated with process control.

Parameter Symbol Condition Min. Typ. Max. Unit

GENERAL
VIN Input Voltage Range VS_VIN 8.6 15.9 V
VGL2_SW, VGH_SW,
IS1_AVIN VCCx_SW, HVDD_SW No 5 6 7 mA
switching
AVIN Supply Current
VGL2_SW, VGH_SW,
IS2_AVIN VCCx_SW, HVDD_SW 6.5 7.5 8.5 mA
Switching
VIN Start Threshold Voltage VSTART VIN rising 8 8.3 8.6 V
VSTOP (VIN Stop Threshold
UVLO Hysteresis HYUVLO 0.6 0.8 1 V
Voltage)=VSTART-HYUVLO
Boost EN Pull-up Resistance RBST_EN 22 kΩ
ON-CHIP 5V REGULATOR [VL]
VL Regulation Voltage VL 4.9 5 5.1 V
VL Maximum Output Current IO_VL 45 mA
PROTECTIONS
Thermal Shutdown Temperature2) TSD Temperature rising 150 °C
TSD Release Threshold
Thermal Shutdown Hysteresis2) HYTSD 15 °C
Temperature=TSD-HYTSD
VIN Over-Voltage Protection Threshold
VIN_OVP_H VIN rising 17.4 18 18.6 V
High3)
VIN Over-Voltage Protection Hysteresis3) HYVIN_OVP VIN_OVP_L=VIN_OVP_H-HYVIN_OVP 0.3 0.55 0.8 V
0.75* 0.8* 0.85*
VCC1 Over Load Protection Threshold3) VCC1_OLP V
VVCC1 VVCC1 VVCC1
VCC1 Over Voltage Protection Threshold 1.1* 1.2* 1.3*
VCC1_OVP_H V
High3) VVCC1 VVCC1 VVCC1
0.75* 0.8* 0.85*
VCC2 Over Load Protection Threshold3) VCC2_OLP V
VVCC2 VVCC2 VVCC2
VCC2 Over Voltage Protection Threshold 1.1* 1.2* 1.3*
VCC2_OVP_H V
High3) VVCC2 VVCC2 VVCC2
0.6* 0.7* 0.8*
HVDD Over Load Protection Threshold3) VHVDD_OLP V
VHVDD VHVDD VHVDD
1.2* 1.3* 1.4*
HVDD Over Voltage Protection Threshold3) VHVDD_OVP V
VHVDD VHVDD VHVDD
0.85*
VGH Over Load Protection3) VGH_OLP V
VGH
VGH Over Voltage Protection Threshold
VGH_OVP 38 40 41 V
High3)
3)
VGH Over-Voltage Protection Hysteresis HYVGH_OVP VGH_OVP_L=VGH_OVP-HYVGH_OVP 0.5 1 1.5 V
0.7* 0.8* 0.9*
VGH Diode Open Protection Threshold3) VGH_DOP V
VDD VDD VDD
0.85*
VGL1 Over Load Protection3) VGL1_OLP V
VGL1

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 SM4085

Electrical Characteristics (continued)

VIN = VHVDD_Vin = 12V, VDD = 14.5V, VHVDD = 7.25V, VCC1 = 3.3V, VCC2 = 1.2V, VGH = 28V, VGL1 = - 5V, VGL2 = -15V, TA = TJ, TA =
*) 1)
-40°C ~ 85°C . Typical values are at TA=+25 °C, unless otherwise specified.
*) Specifications over the TA range are guaranteed by design, characterized and correlated with process control.

Parameter Symbol Condition Min. Typ. Max. Unit

PROTECTIONS (continued)
0.05* 0.1* 0.15*
VGL2 Short-Circuit Protection Threshold3) VGL2_SCP V
VGL2 VGL2 VGL2
0.05* 0.1* 0.15*
VGL2 Diode Open Protection Threshold2),3) VGL2_DOP VGL2 start up V
VGL2 VGL2 VGL2
VGL2 Over Voltage Protection Threshold VGL2
VGL2_OVP VGL2 = -15V V
High3) –1
Shut down Protection Enable High Voltage VSHUTDOWN_H after 100us 1.3 V
External Boost Output [VDD]
Output Voltage Range VVDD I2C programmable 13.8 20 V
VDD Power Off Discharge Resistor2),4) RVDD I2C programmable 1100 Ω
BUCK1 CONVERTER [VCC1]
Output Voltage Range VS_B1 I2C programmable 3.2 3.5 V
Default VCC Voltage VB1_DEF 2-bit DATA=01h -2.5% 3.3 2.5% V
Switching Frequency fSW_B1 540 600 660 kHz
Maximum Duty Cycle DMAX_B1 FREQ=600kHz 85 95 %
2)
VIN to VCC1_SW On-Resistance RDS_ON_B1_H IVCC1=500mA 310 450 mΩ
2)
VCC1_SW to GND On-Resistance RDS_ON_B1_L IVCC1=-500mA 230 370 mΩ
VCC1_SW Current Limit ILIM_VCC1_SW 1.5 2.5 A
2),5)
VCC1 Internal Feedback Line Regulation dVVCC1_FB 8.6V≤VIN≤15.9V 0.15 %/V
2)
Load Regulation dVVCC1 IOUT=0 to 500mA 0.5 %/A
2)
Soft-Start Period tSS_B1 420 μs
VCC1 Power Off Discharge Resistor2),4) RVCC1 I2C programmable 300 Ω
ILK_SW1_H VIN=15.9V, VCC1_SW=GND 1 10 μA
VCC1_SW Leakage Current
ILK_SW1_L VCC1_SW=15.9V 1 10 μA
BUCK2 CONVERTER [VCC2]
VS_B2_H 1.0 1.35 V
Output Voltage Range I2C programmable
VS_B2_L 1.7 2.05 V
Default VCC2 Voltage VB2_DEF 4-bit DATA=04h -2% 1.2 2% V
Switching Frequency fSW_B2 540 600 660 KHz
Minimum Duty Cycle2) DMIN_B2 FREQ=600MHz 6 %
VIN to VCC2_SW On-Resistance2) RDS_ON_B2_H IVCC2=500mA 40 100 mΩ
VCC2_SW Current Limit ILIM_B2_H 4 5 A
2),5)
VCC2 Internal Feedback Line Regulation dVVCC2_FB 8.6V≤VIN≤15.9V 0.15 %/V
Load Regulation2) dVVCC2 IOUT=0 ~ 500mA 0.5 %/A
Soft-Start Period2) tSS_B2 420 μs
VCC2_SW Leakage Current ILK_VCC2_SW_H VIN=15.9V, VCC2__SW=GND 1 10 μA

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 SM4085

Electrical Characteristics (continued)

VIN = VHVDD_Vin = 12V, VDD = 14.5V, VHVDD = 7.25V, VCC1 = 3.3V, VCC2 = 1.2V, VGH = 28V, VGL1 = - 5V, VGL2 = -15V, TA = TJ, TA =
*) 1)
-40°C ~ 85°C . Typical values are at TA=+25 °C, unless otherwise specified.
*) Specifications over the TA range are guaranteed by design, characterized and correlated with process control.

Parameter Symbol Condition Min. Typ. Max. Unit

BUCK3 CONVERTER [HVDD]
HVDD_Vin Input Voltage Range VS_HVDD_Vin 8.6 20 V
VDD/2- VDD/2+
Output Voltage Range VS_B3 I2C programmable V
0.8V 0.7V
Default HVDD Voltage VB3_DEF 4-bit DATA=08h -2% VDD/2 2% V
Switching Frequency fSW_B3 1.05 1.2 1.35 MHz
Maximum Duty Cycle DMAX_B3 FREQ=1.2MHz 85 90 %
2)
HVDD_Vin to HVDD_SW On-Resistance RDS_ON_B3_H IHVDD=250mA 320 450 mΩ
HVDD_SW to GND On-Resistance2) RDS_ON_B3_L IHVDD=-250mA 240 380 mΩ
ILIM_B3_H 2.0 2.8 A
HVDD_SW Current Limit
ILIM_B3_L -3.0 -2.0 A
HVDD Internal Feedback Line
dVHVDD_FB 8.6V≤VHVDD_Vin≤15.9V 0.15 %/V
Regulation2),5)
2)
Load Regulation dVHVDD IOUT=0 to 500mA 0.5 %/A
2),4) 2
HVDD Power Off Discharge Resistor RHVDD I C programmable 500 Ω
ILK_HVDD_SW_H VHVDD_Vin=19V, VHVDD_SW=GND 1 10 μA
HVDD_SW Leakage Current
ILK_HVDD_SW_L VHVDD_SW=19V 1 10 μA
VGH BOOST CONVERTER [VGH]
Output Voltage Range (Room
VS_GHR I2C programmable 20 35 V
Temperature)
Output Voltage Range (Low Temp.) VS_GHL 21 36 V
Default VGH Voltage (Room Temp.) VGHH_DEF 4-bit DATA=98h 28 V
-2% +2%
Default VGH Voltage (Low Temp.) VGHL_DEF 4-bit DATA=98h 30 V
Switching Frequency fSW_VGH 540 600 660 kHz
Maximum Duty Cycle DMAX_VGH FREQ=600kHz 85 90 %
2)
VGH_SW to GND On-Resistance RDS_ON_VGH IVGH_SW=-100mA 450 550 mΩ
VGH Current Limit ILIM_VGH 1.0 2.0 A
2),5)
VGH Internal Feedback Line Regulation dVVGH_FB 8.6V≤VIN≤15.9V 0.15 %/V
Load Regulation2) dVVGH IOUT=0 to 300mA 0.5 %/A
2),4) 2
VGH Power Off Discharge Resistor RVGH I C programmable 1.8 kΩ
VGH_SW Leakage Current ILK_VGH VGH_SW=41V 1 10 μA
TEMPERATURE COMPENSATED CONTROLLER
VGH TCOMP Range VTCOMP_VGH 2 3 V
VGL2 & VCOM TCOMP Range VTCOMP_VGL 2 3 V
Linear Dropout Regulator [VGL1]
Output Voltage Range VS_VGL1 I2C programmable -8.0 -1.8 V
Default VGL1 Voltage VVGL1_DEF 5-bit DATA=10h +2% -5.0 -2% V
2)
Dropout Voltage VDROPOUT ILOAD=100mA 10 25 mV
Maximum Output Current ILIM_VGL1 180 200 mA
2)
Short Current Limit ISCP_LIM_VGL1 VGL1 short to GND 50 80 mA

© 2017 Silicon Mitus, Inc. [Link]

October 2017 – Rev.1.0.1 11 / 44
 SM4085

Electrical Characteristics (continued)

VIN = VHVDD_Vin = 12V, VDD = 14.5V, VHVDD = 7.25V, VCC1 = 3.3V, VCC2 = 1.2V, VGH = 28V, VGL1 = - 5V, VGL2 = -15V, TA = TJ, TA =
*) 1)
-40°C ~ 85°C . Typical values are at TA=+25 °C, unless otherwise specified.
*) Specifications over the TA range are guaranteed by design, characterized and correlated with process control.

Parameter Symbol Condition Min. Typ. Max. Unit

Linear Dropout Regulator [VGL1] (continued)
VGL1 Internal Feedback Line
dVVGL1_FB 8.6V≤VIN≤15.9V 0.15 %/V
Regulation2),5)
Load Regulation dVVGL1 IOUT=0 to 100mA, VGL1=-5V 0.05 %/mA
Output Capacitance for Stability3) COUT_OUTP 10 μF
2)
VGL1 Soft Start Period SSVGL1 1.65 ms
2),4) 2
VGL1 Power Off Discharge Resistor RVGL1 I C programmable 300 Ω
INVERTING BUCK-BOOST CONVERTER [VGL2]
Output Voltage Range VS_VGL2 I2C programmable -20 -4.5 V
Default VGL2 Voltage (Room Temp.) VVGL2_DEF1 5-bit DATA=15h -15 V
+2% -2%
Default VGL2 Voltage (High Temp.) VVGL2_DEF2 5-bit DATA=0Bh -10 V
Switching Frequency fSW_BB 540 600 660 kHz
Maximum Duty Cycle DMAX_BB FREQ=600kHz 85 90 %
Error Amplifier Transconductance GmVGL2 200 400 600 μS
VGL2_SW On-Resistance2) RDS_ON_BB IVGL2=500mA 450 600 mΩ
2)
Current Sense Transresistance GCS_VGL2 0.5 0.7 0.9 V/A
VGL2_SW Current Limit ILIM_VGL2_SW Duty=55% 1.2 1.7 A
VGL2_SW Leakage Current ILK_VGL2_SW VIN=15.9V, VGL2_SW=GND 1 10 μA
VGL2 Internal Feedback Line
dVVGL2_FB 8.6V≤VIN≤15.9V 0.15 %/V
Regulation2),5)
Load Regulation2) dVVGL2 IOUT=0 to 300mA 0.5 %/A
Soft-Start Period2) tSS_VGL2 3.3 ms
PROGRAMMABLE VCOMDAC CONTOLLER
9-bit DATA (Step=391, 120 510
VCOMDAC Output Voltage Range VO_PV1 V
RES=VDD/1023) *RES *RES
Output Accuracy VACC_VC 9-bit DATA = 000h ~ 186h -50 50 mV
ANALOG GAMMA BUFFER CHANNELS
VACC_G_1 9-bit DATA=23h ~ DDh -50 50 mV
Output Accuracy Default code @30mA Sinking
VACC_G_2 -80 80 mV
& Sourcing
Gamma Buffer Continuous Output
IGMA_O Default code 15 30 mA
Current2)
Integral Nonlinearity Error2),6) INLG -1 1 LSB
2),7)
Differential Nonlinearity Error DNLG -0.5 0.5 LSB
2)
Common Mode Rejection Ratio CMRRG 70 dB
Power Supply Rejection Ratio2) PSRRG 85 dB
RST SIGNAL GENERATOR [RST]
VVCC1
RST Logic Output Low Voltage VRST_L @ 1mA sourcing current V
*0.2
RST Leakage Current ILK_RST VRST=3.6V 1 10 μA
HIGH VOLTAGE LEVEL SHIFTER
L/S_VGH, VGH_E/O Input Voltage Range VS_VGH 15 36 V
VGL2 Input Voltage Range VS_VGL2 -20 -4.5 V
Level shifter Output Operating Range2),8) VOP |VGH-VGL2| 57 V

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12 / 44 October 2017 – Rev.1.0.1
 SM4085

Electrical Characteristics (continued)

VIN = VHVDD_Vin = 12V, VDD = 14.5V, VHVDD = 7.25V, VCC1 = 3.3V, VCC2 = 1.2V, VGH = 28V, VGL1 = - 5V, VGL2 = -15V, TA = TJ, TA =
*) 1)
-40°C ~ 85°C . Typical values are at TA=+25 °C, unless otherwise specified.
*) Specifications over the TA range are guaranteed by design, characterized and correlated with process control.

Parameter Symbol Condition Min. Typ. Max. Unit

HIGH VOLTAGE LEVEL SHIFTER (continued)
MCLK, GCLK, GST=GND, no
L/S_VGH Supply Current IS_LS_VGH 100 170 250 μA
load
VGH_E/O Supply Current IS_VGH_E/O E/O=GND, no load 50 100 150 μA
MCLK, GCLK, GST, E/O=GND,
VGL2 Supply Current IS_VGL2 100 180 260 μA
no load
L/S_VGH Start Threshold Voltage VSTART_VGH VGH, VGH_E/O rising 18 19 20 V
VSTOP_VGH (VGH Stop Threshold
L/S_VGH UVLO Hysteresis HYUVLO_VGH 14.5 15.6 16.7 V
Voltage)=VSTART_VGH-HYUVLO_VGH
High Side On Resistance (CLK1 ~
VOH_HS_1 IOUT=50mA 12 20 Ω
CLK10)2)
Low Side On Resistance (CLK1 ~ CLK10) 2) VOL_HS_1 IOUT=-50mA 7 14 Ω
High Side On Resistance (All LS Output
VOH_LS_2 IOUT=50mA 20 30 Ω
except CLKs) 2)
Low Side On Resistance (All LS Output
VOL_LS_2 IOUT=-50mA 10 18 Ω
except CLKs) 2)
Propagation Rising Delay (CLK1 ~ CLK10) tDR_LS1 CLOAD=150pF, 50% to 50% 20 40 60 ns
Propagation Rising Delay (All LS Output
tDR_LS2 CLOAD=150pF, 50% to 50% 25 45 70 ns
except CLKs)
Propagation Falling Delay (CLK1 ~ CLK10) tDF_LS1 CLOAD=150pF, 50% to 50% 25 45 65 ns
Propagation Falling Delay (All LS Output
tDF_LS2 CLOAD=150pF, 50% to 50% 30 55 75 ns
except CLKs)
Rise Time (CLK1 ~ CLK10) tR_LS_1 CLOAD=150pF, 10% to 90% 20 40 ns
Rise Time (All LS Output except CLKs) tR_LS_2 CLOAD=150pF, 10% to 90% 25 55 ns
Fall Time (CLK1 ~ CLK10) tF_LS_1 CLOAD=150pF, 90% to 10% 20 40 ns
Fall Time (All LS Output except CLKs) tF_LS_2 CLOAD=150pF, 90% to 10% 25 55 ns
Logic Input Bias Current (GCLK, GST, E/O,
IB_LS GCLK, GST, E/O, MCLK=3.3V 1 μA
MCLK)
High Side Current Limit9),10) I LIM_LS_H ROCP1=55kΩ 32.4 40.3 48.2 mA
Low Side Current Limit9),10) I LIM_LS_L ROCP1=55kΩ 32.4 40.3 48.2 mA
Current Limit Detect Time COCP Time1= Open
tOCP1 0.53 0.62 0.72 μs
(CLK1 ~ CLK10, VST, RESET) (except dead time)
Current Limit Detect Time COCP Time2=Open
tOCP2 0.53 0.62 0.72 μs
(EVEN, ODD) (except dead time)
LOGIC INPUT REQUIREMENTS (GCLK, GST, E/O, MCLK, Shutdown)
Logic Input High Voltage VIH_LOGIC 1.3 V
Logic Input Low Voltage VIL_LOGIC 0.8 V
2 2),11)
I C INTERFACE
I2C Logic Input High Threshold Voltage VIH_I2C SDA, SCL 1.3 V
2
I C Logic Input Low Threshold Voltage VIL_I2C SDA, SCL 0.8 V
SDA, SCL Logic Output Low Voltage VOL_I2C @3mA sink current 0.4 V
fSCL_S Standard Mode 100 kHz
SCL Clock Frequency
Fast Mode 400 kHz
2
I C Spike Rejection Filter Pulse Width tSP 0 50 ns

© 2017 Silicon Mitus, Inc. [Link]

October 2017 – Rev.1.0.1 13 / 44
 SM4085

Electrical Characteristics (continued)

VIN = VHVDD_Vin = 12V, VDD = 14.5V, VHVDD = 7.25V, VCC1 = 3.3V, VCC2 = 1.2V, VGH = 28V, VGL1 = - 5V, VGL2 = -15V, TA = TJ, TA =
*) 1)
-40°C ~ 85°C . Typical values are at TA=+25 °C, unless otherwise specified.
*) Specifications over the TA range are guaranteed by design, characterized and correlated with process control.

Parameter Symbol Condition Min. Typ. Max. Unit

2 2),11)
I C INTERFACE (continued)
Standard Mode 4 μs
SCL Clock High Period tSCL_H
Fast Mode 600 ns
Standard Mode 4.7 μs
SCL Clock Low Period tSCL_L
Fast Mode 1.3 μs
Standard Mode 250 ns
I2C Data Setup Time tSU_DAT
Fast Mode 100 ns
Standard Mode 0 3.45 μs
I2C Data Hold Time tHD_DAT
Fast Mode 0 900 ns
20+
Standard Mode 1 μs
0.1*CB
SDA, SCL Rise Time tR_I2C
20+
Fast Mode 300 ns
0.1*CB
20+
Standard Mode 300 ns
0.1*CB
SDA, SCL Fall Time tF_I2C
20+
Fast Mode 300 ns
0.1*CB
Standard Mode 4.7 μs
I2C Bus Free Time Between Stop and Start tBUF
Fast Mode 1.3 μs
Standard Mode 4.7 μs
I2C Repeated Start Condition Setup Time tSU_STA
Fast Mode 600 ns
Standard Mode 4.0 μs
I2C (Repeated) Start Condition Hold Time tHD_STA
Fast Mode 600 ns
Standard Mode 4 μs
I2C Stop Condition Setup Time tSU_STO
Fast Mode 600 ns
I2C Bus Capacitive Load CB 400 pF
SDA Input Capacitance CSDA 10 pF
SCL Input Capacitance CSCL 10 pF
EEPROM Read/Write Endurance 100 cycle
EEPROM Write Time12) 100 ms

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14 / 44 October 2017 – Rev.1.0.1
 SM4085

2
Definition of I C Interface Parameter
repeated
START STOP START
condition condition condition
tBUF
VIH_I2C
SDA ACK
VIL_I2C
tF_I2C tR_I2C tSP tSU_DAT tSU_STA
tSU_DAT

VIH_I2C
SCL 1st 2nd 3rd 9th
VIL_I2C clock clock clock clock
tSCL_L
tHD_STA tHD_DAT tSCL_H tHD_DAT tHD_DAT tSU_STO tHD_STA
S P Sr

Notes
1) The device is not guaranteed to operate outside its operating conditions.
2) Guaranteed by design, characterization and correlation with process controls. Not fully tested in production.
3) When the voltage in the related parameter reaches (stays, remains) between the min and max, it enables protection
function.
2
4) The discharge resistor is enabled or disabled by I C.
5) dVFB ={(VFB,MAX –VFB,MIN)/VFB@VIN=12V}/ΔVIN
6) INL = Max( | [(VGMAx(i) - VGMAx(35) )/ VLSB-IDEAL]-(i-35) | ), i=35~MAX code-35, where, VLSB-IDEAL= [Ideal
VGMAx(MAX code-35)- Ideal VGMAx (35)]/MAX code-70).
7) DNL = Max( | [(VGMAx(i+1) - VGMAx(i)) / VLSB-IDEAL-1]|), i=35~ MAX code-35.
8) The maximum voltage between VGH, VGH_E/O and VGL2 should be less than 55V.
9) ILIM_LS_H&L (Unit: A) = 2216 / ROCP
10) The maximum output current limit of the CLKx is different from the other outputs(VST, Reset, EVEN and ODD).
Refer to the device functional description.
11) Designed and simulated according to I2C specifications except general call support.
12) The time to write the EEPROM is minimum 100ms. In this time, the VGH have to hold its voltage because the VGH is
2
the source power for EEPROM writing. And the I C communication is blocked during EEPROM writing.
EEPROM Write time > 100ms
M L
S S
B B

SCL

SDA
ACK STOP START

© 2017 Silicon Mitus, Inc. [Link]

October 2017 – Rev.1.0.1 15 / 44
 SM4085

Power On-Off Sequence

VSTART = 8.3V VSTOP = 7.5V
VL
VIN
DLY01) (VIN UVLO ↔ VCC1)

EN VCC1 PG
Target x 80%

VCC1 VCC2 PG
Target x 80%

VCC2
DLY11) (VCC2 ↔ RST)
Unknown
Status
VGL2 PG
RSTB
RST target x 50%

VGL1
VGL1 PG
target x 85%

VGL2
DLY21) VGL2 PG
(VCC2 ↔ VGL2) target x 85%

External Boost Converter

Boost EN High Threshold Voltage
HVDD is ½
VDD when
DLY31) VDD Power is off
(VGL2 ↔ Boost EN)

VDD<4V or VL<3.9V
à HVDD & GMA Off
VDD=6V

HVDD GMA_1~GMA_8

VGH UVLO VGH

=19V
Unknown
Status

VDD PG VDD
target x 90%
HVDD PG
target x 100%
HVDD

VCOMDAC
VGH VCOMDAC

E/O input signal

EVEN ODD

Unknown
Status
EVEN and ODD

CLKs & RESET & VST

Notes
1) DLY0 ~ DLY3 time tolerance: +/- 20%.
2) If target voltage doesn’t reach the PG (Power Good) level, next blocks don`t operate.
2
3) If discharge resistors are enabled by I C, then the output voltages are discharged through the discharge resistors
during power off. The discharge resistor bit is shown in Appendix B.
4) At the power off, the EVEN and ODD are discharged naturally.
5) The input voltage of VGH boost converter is the VDD.
6) If VGH < VDD * 0.8, then the VGH block does not operate.

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16 / 44 October 2017 – Rev.1.0.1
 SM4085

Memory Map
MSB LSB
Register Name Address Default value
7 6 5 4 3 2 1 0
VDD VDD Votlage Range 0x00 0x08 X X 0 0 1 0 0 0

VCC1 VCC1 Voltage Range 0x01 0x01 X X X X X X 0 1

VCC2 VCC2 Voltage Range 0x02 0x04 X X X X 0 1 0 0

HVDD HVDD Voltage Range 0x03 0x08 X X X X 1 0 0 0

VGH VGH Voltage Range 0x04 0x98 1 0 0 1 1 0 0 0

VGL1 VGL1 Votlage Range 0x05 0x10 X X X 1 0 0 0 0

VGL2(Room temp.) VGL2 (Room temp.)Voltage Range 0x06 0x15 X X X 1 0 1 0 1

VGL2(Hot temp.) VGL2 (Hot temp.)Voltage Range 0x07 0x0B X X X 0 1 0 1 1

DLY0/1/2/3 Delay 0/1/2/3 0x08 0x15 0 0 0 1 0 1 0 1

GMA_1 Gamma1 Voltage Range 0x09 0xEC 1 1 1 0 1 1 0 0

0x0A 0x01 X X X X X X X 1
GMA_2 Gamma2 Voltage Range
0x0B 0x10 0 0 0 1 0 0 0 0

0x0C 0x01 X X X X X X X 1
GMA_3 Gamma3 Voltage Range
0x0D 0x10 0 0 0 1 0 0 0 0

GMA_4 Gamma4 Voltage Range 0x0E 0x82 1 0 0 0 0 0 1 0

Gamma
GMA_5 Gamma5 Voltage Range 0x0F 0x9D 1 0 0 1 1 1 0 1

0x10 0x00 X X X X X X X 0
GMA_6 Gamma6 Voltage Range
0x11 0x64 0 1 1 0 0 1 0 0

0x12 0x00 X X X X X X X 0
GMA_7 Gamma7 Voltage Range
0x13 0x64 0 1 1 0 0 1 0 0

GMA_8 Gamma8 Voltage Range 0x14 0x13 0 0 0 1 0 0 1 1

0x15 0x00 X X X X X X X 0
VCOM VCOM Voltage Range
0x16 0xDF 1 1 0 1 1 1 1 1

VCOM Operation Discaharging, Temp Comp 0x17 0x07 X X X 0 0 1 1 1

VGH/VGL Protection &

VGH/VGL Protection, L/S Option 0x18 0x04 X X X X X 1 0 0
L/S option

CR Control Register 0xFF - 0 0 X X X X X 0

Control Register Data

→ 0x00: When read from DAC Register
→ 0x01: When read from EEPROM
→ 0x40: When write data (VCOM data in DAC Register) to EEPROM
→ 0x80: When write data (All data in DAC Register) to EEPROM
X : Don`t care bit.

© 2017 Silicon Mitus, Inc. [Link]

October 2017 – Rev.1.0.1 17 / 44
 SM4085

I2C Operations
Device Address(Slave Address)
(MSB) Device Address (LSB)
0 1 0 0 0 0 0 R/W

Write operation
DATA Write to DAC
Device Address R/W SACK DAC Address SACK Data SACK
START STOP
0 1 0 0 0 0 0 0 0 0x00 ~ 0x18 0 D7 D6 D5 D4 D3 D2 D1 D0 0
DATA are written to DAC Address

DATA Write to EEPROM

Device Address R/W SACK DAC Address SACK Data SACK
START STOP
0 1 0 0 0 0 0 0 0 0x00 ~ 0x18 0 D7 D6 D5 D4 D3 D2 D1 D0 0

Device Address R/W SACK Control Register Address SACK Control Register Data SACK
START STOP
0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0

Example
A) DAC Register Writing
DAC Address 0x15 = Data 0x00, DAC Address 0x16 = Data 0xDF
Device Address R/W SACK DAC Address(0x15) SACK Data(0x00) SACK
START STOP
0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0

Device Address R/W SACK DAC Address(0x16) SACK Data(0xDF) SACK

START STOP
0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 1 0 1 1 1 1 1 0

B) DAC Register Writing - Address Auto-Increment

DAC Address 0x15 = Data 0x00, DAC Address 0x16 = Data 0xDF
Device Address R/W SACK DAC Address(0x15) SACK Data(0x00) SACK Data(0xDF) SACK
START STOP
0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 0

C) EEPROM Writing
DAC Address 0x15 = Data 0x00, DAC Address 0x16 = Data 0xDF
Device Address R/W SACK DAC Address(0x15) SACK Data(0x00) SACK
START STOP
0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0

Device Address R/W SACK DAC Address(0x16) SACK Data(0xDF) SACK

START STOP
0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 1 0 1 1 1 1 1 0

Device Address R/W SACK Control Register Address(0xFF) SACK Control Register Data(0x40) SACK
START STOP
0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0

D) EEPROM Writing - Address Auto-Increment

DAC Address 0x15 = Data 0x00, DAC Address 0x16 = Data 0xDF
Device Address R/W SACK DAC Address(0x15) SACK Data(0x00) SACK Data(0xDF) SACK
START STOP
0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 0

Device Address R/W SACK Control Register Address(0xFF) SACK Control Register Data(0x40) SACK
START STOP
0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0

Read operation
DATA Read from DAC or EEPROM
Device Address R/W SACK Control Register Address SACK 0x00 : Read from DAC register SACK
START STOP
0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0x01 : Read from EEPROM 0

Device Address R/W SACK DAC Address SACK

START
0 1 0 0 0 0 0 0 0 0x00 ~ 0x18 0

repeated Device Address R/W SACK Data MNACK

STOP
START 0 1 0 0 0 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1

Example
A) DAC Register Reading [VGL2 (0x06)]
Device Address R/W SACK Control Register Address SACK Control Register Data SACK
START STOP
0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0

Device Address R/W SACK DAC Address SACK

START
0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0

repeated Device Address R/W SACK Data MNACK

STOP
START 0 1 0 0 0 0 0 1 0 X X X X X X X X 1

B) EEPROM Reading [VGL2 (0x06)]

Device Address R/W SACK Control Register Address SACK Control Register Data SACK
START STOP
0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0

Device Address R/W SACK DAC Address SACK

START
0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0

repeated Device Address R/W SACK Data MNACK

STOP
START 0 1 0 0 0 0 0 1 0 X X X X X X X X 1

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18 / 44 October 2017 – Rev.1.0.1
 SM4085

Device Functional Description 3. VGL1 Over Load Protection

If the VGL1 voltage rises above target voltage*0.85 (typ.),
Under Voltage Lock Out the current limit is changed to 200mA typically. If the
The under voltage lockout (UVLO) circuit is included with a overload condition is removed, the VGL1 is re-established.
built-in hysteresis. The internal bias block is turned on and
all blocks are ready to operate according to the power-up
4. HVDD Over Load Protection
sequence when the VIN voltage rises above VSTART (typ.
8.3V). And all blocks shut down when the VIN falls below If the HVDD voltage drops below target voltage*0.7 (typ.),
VSTOP (typ. 7.5V). There is a typical 0.8V hysteresis for the switching frequency and current limit are changed. In
reliable operation. When the VIN is lower than the UVLO this situation switching frequency is changed to target*1/2
stop voltage (VSTOP), all converters are turned off except and current limit is turned to target*0.6 (typ.). In addition the
Buck3 converter because of 1/2 VDD voltage tracking. Boost_EN is set logic low. If the overload condition is
removed, the HVDD is re-established.

Protections 5. VGH Over Load Protection

The SM4085 has the following protection functions to
If the VGH voltage drops below target voltage*0.85 (typ.),
protect the IC and external circuits in abnormal conditions.
the current limit is changed and the Boost_EN is set logic
Thermal Shut Down low. If the overload condition is removed, the VGH is re-
The SM4085 includes a Thermal Shut Down (TSD) established.
function. This function protects the IC from overheating
caused by excessive power dissipation. An internal Short Circuit Protection
temperature sensor continuously monitors the junction
1. VCC1 Short Circuit Protection
temperature. If the temperature exceeds about 150°C, the
IC will shut down its operation until it cools down to the safe If the VCC1 output is shorted to GND, the switching
temperature at which point the IC will resume operation. Its frequency and current limit are changed. In this situation
hysteresis is approximately 15°C. At TSD condition, all switching frequency is turned to target*1/4 and current limit
blocks are shut down immediately. is changed to target*0.3. If the abnormal condition (short to
GND) is removed, the VCC1 is re-established according to
the power-up sequence.
Shutdown Function
2
The SM4085 has a shutdown function which is set by I C’s
programmed status and the state of Shut down pin. If the 2. VCC2 Short Circuit Protection
2
shutdown function is enabled by I C and the state of If the VCC2 output is shorted to GND, the switching
shutdown pin is high state during over 100us, then all frequency and current limit are changed. In this situation
converters stop switching until power-off. This function is switching frequency is changed to target*1/4 and current
enabled above VSTART_VGH. limit is turned to target*0.3 If the abnormal condition (short
to GND) is removed, the VCC2 is re-established according
Over Load Protection to the power-up sequence.

1. VCC1 Over Load Protection

3. VGL1 Short Circuit Protection
If the VCC1 voltage drops below target voltage*0.8 (typ.),
If the VGL1 output is shorted to GND, the current limit is
the switching frequency and current limit are changed. In
changed to 50mA typically. If the abnormal condition (short
this situation switching frequency is changed to target*1/2
to GND) is removed, the VGL1 is re-established according
and current limit is turned to target*0.6 (typ.). If the
to the power-up sequence.
overload condition is removed, the VCC1 is re-established.

4. VGL2 Short Circuit Protection

2. VCC2 Over Load Protection
If the VGL2 output is shorted to GND or the VGL2 voltage
If the VCC2 voltage drops below target voltage*0.8 (typ.), rises above target voltage*0.1 (typ.), the switching
the switching frequency and current limit are changed. In frequency and limit voltage of VGL2_Comp are changed. In
this situation switching frequency is changed to target*1/2 this situation, switching frequency is changed to target*1/4
and current limit is turned to target*0.6 (typ.). If the and limit voltage of VGL2_Comp is turned to 1.4V. If the
overload condition is removed, the VCC2 is re-established. abnormal condition (short to GND or overload) is removed,

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October 2017 – Rev.1.0.1 19 / 44
 SM4085

VGL2 is re-established according to the power-up

sequence. At this time switching frequency is target*1/4
18V(typ)
until VGL2 > target voltage*0.1 (typ.) and after then it 17.45V(typ)

operates with target switching frequency. AVIN

VCC1

5. HVDD Short Circuit Protection

VCC2
If the HVDD voltage drops below 1.6V, the switching
frequency and current limit are changed and the state of
DLY1
Boost_EN is set logic-low until the VDD falls to 3.9V. In this RST
period, the switching frequency is changed to target*1/4
and current limit is changed to target*0.43. When the VDD
touches 3.9V, then the state of Boost_EN is set logic high VGL2
DLY2

to restart VDD block. At this time, if the HVDD voltage does

not reach normal range, the Buck3 converter and VGL1

Boost_EN are turned off until the VDD falls to 3.9V again. If
Boost EN DLY3
the HVDD reaches the normal range, the HVDD buck
converter and the VGH boost converter are re-established HVDD

according to the power-up sequence. VGH

L/S outputs
Over Voltage Protection

1. VCC1 and VCC2 Over Voltage Protection

Figure 1. A simple sequence of the VIN Over Voltage
If the VCC1 and the VCC2 rise above target voltage*1.2 Protection
(typ.), the SW1 and the SW2 stop switching.

2. HVDD Over Voltage Protection VGH / VGL2 Protection On/Off Function

If the HVDD rise above target voltage*1.3 (typ.), the HVDD The SM4085 has the on/off function of VGH and VGL2
buck converter stops switching and the Boost_EN is set protections by changing the register bit of address 0x18h
logic low. as shown in Table 1.

3. VGL2 Over Voltage Protection Table 1. VGH / VGL2 Protection Off Function
DAC Address
If the VGL2 falls under target - 1V (typ.), the VGL2 buck- 18h
(BIN)
boost converter stops switching. VGH/VGL2
xxxxxx0xb Protection ON
Protection
xxxxxx1xb ON/OFF Protection OFF
4. VGH Over Voltage Protection
If the VGH rise above 40V (typ.), the VGH boost converter
stops switching. Output Discharge Resistor
The SM4085 have discharge resistors in the output of
VDD, HVDD, VGH, VCC1 and VGL1. These resistors are
5. VIN Over Voltage Protection 2
enabled and disabled by I C. If the discharge resistor is
If the AVIN (Pin number 20) rises above 18V typically, all
enabled, at the point of the VSTOP (=VSTART - HYUVLO), the
converters stop switching. When the VIN voltage drops
discharge resistors is turned on. The relationship of
below 17.45V (typ.), all converters operate according to the
discharge resistor and code is shown in Appendix D. And
power-up sequence as shown in Figure 1. However, if the
the values of discharge resistor are shown in Table 2.
output of external Boost converter remains in VDD OVP
state, it only activates up to VGL1 block in power-up
sequence. Table 2. The Value of Discharge Resistor
Block Discharge Resistor Value
VDD 1100Ω
HVDD 500Ω
VCC1 300Ω
VGH 1800Ω
VGL1 300Ω

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20 / 44 October 2017 – Rev.1.0.1
 SM4085

Delay Time at Power-on Sequence VIN

The SM4085 has delay time to control power-on sequence.
The Power-up sequence is shown in page 15.
EA_OUT VCC1_SW
VCC1
Delay 0 (DLY0)
When power is on, the VIN rises and touches VSTART. At this Ramp
time, delay 0 is counted by programmed delay 0 time. And
then internal enable is enabled. The delay 0 time is
2
programmable with range from 0ms to 16ms by I C and its
step size is shown in Appendix B. The programmed delay Figure 2. Buck1 (VCC1) Voltage Mode Forced
time is changed a little by the variation rate of main Synchronous Converter
oscillator frequency.
Soft Start
A soft start function is to limit inrush current which can
Delay 1 (DLY1) deteriorate components at start-up. The internal reference
The RST signal is generated after the VCC2 power good voltage of the VCC1 buck controller ramps up slowly to the
signal is generated with the programmed delay 1 time. The target voltage for 420μs (typ.). Therefore, the output
delay 1 time is programmable with range from 0ms to 15ms voltage of VCC1 buck converter and the inductor current
2
by I C and its step size is shown in Appendix B. The increase slowly.
programmed delay time is changed a little by the variation
rate of main oscillator frequency.
Buck2 converter [VCC2]
Delay 2 (DLY2) The buck2 converter of the SM4085 employs voltage mode
The VGL2 buck-boost converter is enabled after the VCC2 asynchronous control. It operates in Pulse Width
power good signal is generated with the programmed delay Modulation (PWM) with a fixed frequency (600kHz). The
2 time. The delay 2 time is programmable with range from actual PWM signal in a voltage mode regulator is
2
0ms to 15ms by I C and its step size is shown in Appendix generated by a comparator triggering on a voltage ramp as
B. The programmed delay time is changed a little by the shown in Figure 3. The ramp signal is generated from a
variation rate of main oscillator frequency. clock signal. The relationship of VCC2 voltage and data for
selected codes is shown in Appendix B.
VIN
Delay 3 (DLY3)
The Boost_EN is set logic high after the VGL2 power good
signal is generated with programmed delay 3. The delay 3 EA_OUT
2
time is programmable with range from 0ms to 30ms by I C VCC2_SW VCC2
and its step size is shown in Appendix B. The programmed Ramp
delay time is changed a little by the variation rate of main
oscillator frequency.

Buck1 Converter [VCC1] Figure 3. Buck2 (VCC2) Voltage Asynchronous

The VCC1 buck converter of the SM4085 employs voltage Converter
mode forced synchronous control. It operates in Pulse
Discontinuous Conduction Mode of VCC2 Buck2
Width Modulation (PWM) with a fixed frequency (600kHz). Converter (With Pulse Skipping Mode)
The actual PWM signal in a voltage mode regulator is The buck operates either in continuous conduction mode
generated by a comparator triggering on a voltage ramp as (CCM) or discontinuous conduction mode (DCM). It
shown in Figure 2. The ramp signal is generated from a depends on the load current and input voltage. In a voltage
clock signal. When the error amplifier output (EA_OUT) is mode PWM controller, the duty cycle is altered and based
less than the voltage ramp, the high side switch is off and on error between reference voltage and output feedback
the low side switch is on. And this control method can deal voltage so that the output voltage of the converter is very
with negative load. The internal switches have current limits nearly equal to the desired value. If the switch on time is
of +1.5A (min.) less than 60 ns (typical min. on time at room temp.)

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October 2017 – Rev.1.0.1 21 / 44
 SM4085

because of a very light load condition or a large gap voltage of the VGL1 ramps up slowly to the target voltage
between input voltage and output voltage, the VCC2 buck for 1.65ms (typ.).
converter enters pulse-skipping mode. In this mode, the
VCC2 buck converter prevents the switching operation one
or more switching cycles to prevent the output voltage from Buck-Boost converter [VGL2]
rising above the regulated voltage. The VGL2 buck-boost controller of the SM4085 employs
peak current mode control with internal slope
Soft Start compensation and operates in Pulse Width Modulation
(PWM) operation. The actual PWM signal (d) in a peak
A soft start function is to limit inrush current which can
current mode regulator is generated by a comparator
deteriorate components at startup. The internal reference
triggering on the switch current information as shown in
voltage of the VCC2 buck controller ramps up slowly to the
Figure 6. This switch current information is a sum of sensed
target voltage for 420μs (typ.). Therefore, the output
voltage of VCC2 buck converter and the inductor current switch current (iVGL2_SW’=GCS×iVGL2_SW) and slope
increase slowly. compensation ramp (Ma) which prevents the sub-harmonic
oscillation in peak current mode control. When the internal
VCC1 and VCC2 Start Up error amplifier output is less than the switch current
information, the switch is off and the duty of the driver
The buck1 (VCC1) converter is enabled when the internal
circuitry is determined. VGL2 buck-boost converter can
EN is enable. This converter output supplies the power to
operate in asynchronous mode with a freewheeling diode.
the buck2 (VCC2) converter. And the buck2 (VCC2) is
enabled after the buck1 (VCC1) power good signal. VIN VGL2_SW VGL2
iVGL2_SW iSW
VIN d

High Side GCS

UVLO Start Gate Driver L
Clock siganl

DLY0 Q
internal EN R +
+
+ slope compensation
VCC1 (Ma)
-
External VCOMP

VCC2
Figure 6. Current Mode Buck-boost Converter
Operation
Figure 4. VCC1 and VCC2 start up
Soft Start
A soft start function is to limit inrush current which can
Low Dropout Voltage Regulator [VGL1]
deteriorate components at startup. The internal reference
The SM4085 includes an LDO for VGL1 with adjustable
voltage of the VGL2 buck-boost controller ramps up slowly
output, and it can supply current up to 200 mA (typ.). The
2 to the target voltage for 3.3ms (typ.). Therefore, the output
output voltage is adjusted by using I C interface.
voltage of VGL2 buck-boost converter and the inductor
VGL1
current increase slowly.
VREF Internal
Feedback
sensing Temperature Compensated VGL2
The VGL2 voltage can be adjusted by using an NTC
resistor connected
VGL2

Table 3. Temperature Compensated VGH Condition

Figure 5. LDO Adjustment Circuit
TCOMP_VGL2_VCOM Voltage VGL2 Voltage

TCOMP_VGL2_VCOM < 2V VGL2_HT

Soft Start
A soft start function is to limit inrush current which can 2V < TCOMP_VGL2_VCOM < 3V VGL2_HT < VGL2 < VGL2_RT
deteriorate components at startup. The internal reference 3V < TCOMP_VGL2_VCOM VGL2_RT

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22 / 44 October 2017 – Rev.1.0.1
 SM4085

VIN

TCOMP_VGL2 VL
_VCOM
14 15

RNH VGL2

Delay3
RNL VDD
RNTC (External Boost
Converter Output)

Figure 7. Temperature Compensated

TCOMP_VGL2_VCOM Circuitry
External Boost Converter Boost EN
High Threshold Voltage
VGL2 by
VGL2_RT VGL2_HT
TCOMP_VGL2_VCOM
Figure 10. VDD Start-up Sequence with External Boost
converter Output
VGL2

Buck3 Controller [HVDD]

In the application, there are positive and negative load in
the HVDD block. To handle these, the buck3 converter
employs voltage mode forced synchronous control. This
T1 T2 Temp.
Increase
converter is powered by HVDD_Vin. It operates in Pulse
Figure 8. Temperature Compensated VGL2 Graph Width Modulation (PWM) with a fixed frequency of 1.2MHz.
HVDD_Vin

Temp.
Increase
VTCOMP_VGL2_VCOM

EA_OUT HVDD_SW
HVDD
VL
Typ.
5V
Ramp
3V

2V
Figure 11. Buck3 (HVDD) Voltage Mode Forced
Synchronous Converter
T1 T2 Temp.
Increase
HVDD Start Up
Figure 9. TCOMP_VGL2_VCOM Voltage Graph with
NTC Circuitry The buck3 converter is enabled after the VGL2 power good
signal is generated with the programmed delay3 time along
with the Boost EN voltage as shown in Figure 12.
External Boost Converter Enable Controller
When the power good signal from the VGL2 block is VDD
asserted and the programmed Delay3 time has passed, the
Boost EN pin is set logic high and then external boost Delay 3
HVDD
converter starts switching.
Boost EN

VGL2

Figure 12. Buck3 (HVDD) Start-up Sequence

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October 2017 – Rev.1.0.1 23 / 44
 SM4085

Soft Start Clock signal

A soft start function is to limit inrush current which can
deteriorate components at startup. The internal reference
VRAMP
voltage of the HVDD buck controller ramps up slowly to the
target voltage according to VDD voltage. Therefore, the
VCOMP
output voltage of HVDD buck converter and the inductor
current increase slowly.
Internal
VGATE
HVDD Output Voltage Range
VVGH_SW duty VOUT+Vdiode drop
Basically, HVDD output voltage is half of VDD voltage.
2
However, HVDD output voltage could be changed by I C.
The relationship of HVDD voltage and data for selected
codes is shown in Table 4 and Appendix B.
iL
Table 4. HVDD Voltage Range Relationship for Selected
Codes
HVDD IVGH_SW
DAC Address (HEX) 03h
SETTING DATA (HEX) HVDD value iD
00h VDD(VDD)/2-0.8
01h VDD(VDD)/2-0.7
02h VDD(VDD)/2-0.6 Figure 13. Voltage Mode Boost Converter Operation in
︙ ︙ DCM
05h VDD(VDD)/2-0.3
L iL
06h VDD(VDD)/2-0.2 iD
VGH
07h VDD(VDD)/2-0.1
iVGH_SW
08h VDD(VDD)/2 Clock siganl
09h VDD(VDD)/2+0.1
S
︙ ︙ Q
0Eh VDD(VDD)/2+0.6 R
0Fh VDD(VDD)/2+0.7 VRAMP +
VCOMP -

Temperature Compensated VGH Boost Figure 14. Voltage Mode Boost Converter
Converter
There is a single voltage feedback path with pulse-width
The temperature compensated VGH boost controller of the
modulation performed by comparing the voltage error
SM4085 employs voltage mode control and operates in
signal with a constant ramp waveform. A single feedback
Pulse Width Modulation (PWM) operation with the default
loop design is easier to design and analyze. A large
frequency of 600 kHz. To increase the stability, it usually
amplitude ramp waveform provides good noise margin for a
operates in discontinuous conduction mode. The actual
stable modulation. But any change in line or load must be
PWM signal in a voltage mode regulator is generated by a
sensed as an output changes and then corrected by the
comparator triggering on a voltage ramp as shown in
feedback loop. This means slow response. The output filter
Figure 13. This ramp is generated from a clock signal and
adds two poles in continuous conduction mode to the
its maximum voltage and minimum voltage are fixed. When
control loop, requiring either a dominant pole lower
the error amplifier output (internal signal) is less than the
frequency roll-off at the error amplifier or an added zero in
voltage ramp, the switch is off and the duty of the driver
the compensation. But the VGH boost converter of the
circuitry is determined as shown in Figure 14.
SM4085 usually operates in discontinuous conduction
mode, so the output filter adds only a single pole to the
control loop. This allows simpler compensation. The VGH
boost controller of the SM4085 is internally compensated
for the discontinuous conduction mode operation. If the
VGH boost converter operates in continuous conduction
mode by increasing the load or decreasing the input
voltage, it will be unstable.

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24 / 44 October 2017 – Rev.1.0.1
 SM4085

Discontinuous Conduction Mode of VGH Boost

Converter (Asynchronous mode)
The boost operates either in continuous conduction mode TCOMP_VGH VL
(CCM) or discontinuous conduction mode (DCM). 13 15
Continuous conduction mode (CCM) means that the
inductor current in the energy transfer never goes to zero RNH
between switching cycles. In discontinuous conduction
mode (DCM) the current goes to zero during part of the
RNL RNTC
switching cycle. It depends on the load current. The ringing
seen during DCM operation occurs because of inductor
and parasitic capacitance in the PCB layout and so on. This Figure 16. Temperature Compensated TCOMP_VGH
phenomenon is normal operation. Circuitry

Inductor current
VGH_LT VGH by
VGH_RT
TCOMP_VGH

0A

Inductor voltage VGH

0V T1 T2 Temp.
Ringing due to inductor Increase
and parasitic capacitance Figure 17. Temperature Compensated VGH Graph
Time
VTCOMP_VGH
Figure 15. Discontinuous conduction mode waveform

VL
Temperature Compensated VGH Typ.
5V
The VGH voltage can be adjusted by using an NTC resistor
connected to RNTC pin according to the external 3V VTCOMP_VGH

temperature. This is realized by changing the internal

2V
reference voltage using an NTC resistor. The internal
reference voltage is determined by Table 5. The VGH
voltage range has 2 levels (VGH_LT, VGH_RT) and 1 T1 T2 Temp.
sloped range (VGH by VTCOMP_VGH) over temperature. The Increase
Figure 18. TCOMP_VGH Voltage Graph with NTC
VGH voltage is VGH_RT when TCOMP_VGH voltage is
Circuitry
lower than 2V (typ. 2.0V) and VGH_LT when TCOMP_VGH
voltage is higher than 3V (typ. 3.0V). Its circuitry is shown For example, TCOMP circuitry is made up as like Figure
in Figure 16. 19 . And If VGH_RT=28V and VGH_LT=30V are set, and
then temperature compensated VGH graph is shown in
Table 5. Temperature Compensated VGH Condition Figure 20.
TCOMP_VGH Voltage VGH Voltage

TCOMP_VGH < 2V VGH_RT

TCOMP_VGH VL
2V < TCOMP_VGH < 3V VGH_RT < VGH < VGH_LT
13 15
3V < TCOMP_VGH VGH_LT

47kΩ

120kΩ ECTH100505
437J 4050FST

Figure 19. Temperature Compensated TCOMP Circuitry

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October 2017 – Rev.1.0.1 25 / 44
 SM4085

⁞ - ⁞ ⁞ -
VGH_LT=30V
30V VDD- VDD-
17Eh - -
(RES*1)V (RES*129)V
VDD-
17Fh - VDD -
(RES*128)V
29V

Setting GMA_5 GMA_6 GMA_7 GMA_8

VGH_RT=28V
28V Address 0Fh 10h / 11h 12h / 13h 14h
-3℃ -28℃
(HEX) (8-bit) (9-bit) (9-bit) (8-bit)
-20℃ -10℃ 0℃ 10℃ 20℃ 30℃ Temp. Resolution
HVDD/511 HVDD/511 HVDD/511 HVDD/511
Increase (RES)
Figure 20. Temperature Compensated VGH Graph HVDD- HVDD- HVDD- HVDD-
00h
(RES*255)V (RES*383)V (RES*511)V (RES*511)V
HVDD- HVDD- HVDD- HVDD-
VGH Start Up 01h
(RES*254)V (RES*382)V (RES*510)V (RES*510)V
The VGH boost converter is enabled after the HVDD power ⁞ ⁞ ⁞ ⁞ ⁞
good signal and VDD (VDD) power good signal are HVDD- HVDD- HVDD- HVDD-
FEh
generated. However, the VGH boost converter does not (RES*1)V (RES*129)V (RES*257)V (RES*257)V
HVDD- HVDD- HVDD-
operate immediately due to output voltage stability of VDD FFh HVDD
(RES*128)V (RES*256)V (RES*256)V
and HVDD. The input voltage of VGH boost converter has ⁞ - ⁞ ⁞ -
to use the VDD in case of Figure 21. Because if VVGH < HVDD- HVDD-
17Eh - -
VVDD * 0.8(min), then the VGH block does not operate. (RES*1)V (RES*129)V
HVDD-
17Fh - HVDD -
(RES*128)V

5ms
(Typ.) VGH
SWO
GP1 GP2
VDD (SWO-HVDD)*3/4+HVDD
GP3
HVDD (SWO-HVDD)*1/2+HVDD
GP4
(SWO-HVDD)*1/4+HVDD

Figure 21. VGH Start-up Sequence HVDD

(HVDD-GND)*3/4
I2C Programmable 8-Channel Gamma Buffers (HVDD-GND)*1/2
GN5

There are 8-channel gamma buffers in the SM4085. The GN6

2
gamma voltages are programmed by I C. Each channel (HVDD-GND)*1/4

has the 8-bit or 9-bit resolution DAC and its step are (VDD- GN8 GN7
GND
HVDD)/511 (GMA_1~4 resolution) and HVDD/511 (GMA_5 Figure 22. Gamma Output Structure
~ 8 resolution). The tolerance of gamma voltage is less
than ±50mV. The relationship of GMA voltage and data for
I2C Programmable VCOMDAC Controller
selected codes is shown in Table 6 and Appendix C.
The SM4085 has the VCOMDAC to provide the reference
voltage to the external operational amplifiers. The
Table 6. GMA Voltage & Data Relation for Selected 2
VCOMDAC voltage is programmed by I C. Its step is also
Codes
VDD/1023. The VCOMDAC also has the 9-bit DAC, but
Setting GMA_P1 GMA_P2 GMA_P3 GMA_P4
does not use entire 9-bit data range unlike gamma buffers.
Address 09h 0Ah / 0Bh 0Ch / 0Dh 0Eh
(HEX) (8-bit) (9-bit) (9-bit) (8-bit) The relation of VCOMDAC voltage and data for selected
Resolution
(SWO- (SWO- (SWO- (SWO- codes is shown in Table 7 and Appendix E. And VCOM
HVDD) HVDD) HVDD) HVDD)
(RES)
/511 /511 /511 /511 range selection is shown in Appendix E. The tolerance of
VDD- VDD- VDD- VDD- VCOMDAC voltage is also less than ±50mV.
00h
(RES*255)V (RES*383)V (RES*511)V (RES*511)V
VDD- VDD- VDD- VDD-
01h
(RES*254)V (RES*382)V (RES*510)V (RES*510)V Table 7. VCOM DAC Voltage and Data Relation for
⁞ ⁞ ⁞ ⁞ ⁞ Selected Codes (391 step)
PVCOM
VDD- VDD- VDD- VDD-
FEh DAC Address
(RES*1)V (RES*129)V (RES*257)V (RES*257)V 15h, 16h
VDD- VDD- VDD- (HEX)
FFh VDD SETTING
(RES*128)V (RES*256)V (RES*256)V PVCOM
DATA (HEX)

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26 / 44 October 2017 – Rev.1.0.1
 SM4085

00-00h VDD(VDD)*(120/1023) High Room

00-01h VDD(VDD)*(121/1023) Temperature Temperature
00-02h VDD(VDD)*(122/1023)
00-03h VDD(VDD)*(123/1023) VCOM+RES*16
xxxx1111 RES=VDD/1023
︙ ︙ VCOM+RES*14 xxxx1110
VCOM+RES*12 xxxx1101
01-84h VDD(VDD)*(508/1023)
VCOM+RES*10 xxxx1100
01-85h VDD(VDD)*(509/1023) xxxx1011
VCOM+RES*8
01-86h VDD(VDD)*(510/1023) VCOM+RES*6 xxxx1010
xxxx1001
The SM4085 has temperature compensated VCOMDAC. VCOM+RES*4
xxxx1000
VCOM+RES*2
The VCOMDAC voltage can be adjusted by using an NTC VCOM(Default) xxxx0111
VCOM-RES*2 xxxx0110
resistor connected to TCOMP_VGL2_VCOM pin according VCOM-RES*4 xxxx0101
to the external temperature. The temperature compensated VCOM-RES*6 xxxx0100
VCOM-RES*8 xxxx0011
VCOM function is only available in the below circuit (Figure VCOM-RES*10 xxxx0010
xxxx0001
23). VCOM-RES*12
xxxx0000
VCOM-RES*14

TCOMP_VGL2_
TCOMP_VGL2 VL VCOM Voltage
_VCOM 3V
14 15

2V
RNH

High temp. Room temp.

RNL RNTC Figure 24. VCOM Temperature Compensation

Figure 23. Temperature Compensated TCOMP Circuitry

The temperature compensated VCOMDAC voltage is

2
programed by I C (Address 18h) shown in Figure 24 and
Appendix D. If address 18h is xxxx0111b, temperature
compensated VCOM voltage is same VCOM voltage. In
this case, temperature compensated VCOM is not operated
whatever TCOMP_VGL2_VCOM voltage is changed.

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October 2017 – Rev.1.0.1 27 / 44
 SM4085

Level shifter
Gate Output
The SM4085 has 8-channel or 10-channel gate CLK outputs. The number of output channels and output mode are
2
programmed by I C shown in Appendix D. Simply explains about the operation of level shifter, each gate output of high side
switch is turned on by turns at the rising edge of GCLK. And at the falling edge of MCLK, each gate output of low side
switch is turned on by turns (Detailed description about operation is in the PAGE 31). Figure 25 is the power on sequence of
the A type 10ch output mode.
Table 8. The Register Code of The A-Type
Channel DAC Address = 18h

Type xxxxx0xxb xxxxx1xxb

A Type A Type
xxxxxxx0b
DAC Address 8ch output mode 10ch output mode
= 18h B Type B Type
xxxxxxx1b
8ch output mode 10ch output mode
E/O

GST

GCLK

MCLK

CLK5

CLK4

CLK3

CLK2

CLK1

CLK10

CLK9

CLK8

CLK7

CLK6

VST

RESET

EVEN

ODD
(BRST)

Figure 25. Level Shifter Normal Operation with 10 channel - Power On sequence for A-type

Note. The power-on sequence for the A- type 8ch: CLK4 à CLK3 à CLK2 à CLK1 à CLK8 à CLK7 à CLK6 à CLK5

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28 / 44 October 2017 – Rev.1.0.1
 SM4085

Figure 26 is the timing chart for the end of the frame for A-type 10ch output mode

EO

GST

GCLK

MCLK

CLK5

CLK4

CLK3

CLK2

CLK1

CLK10

CLK9

CLK8

CLK7

CLK6

VST

RESET

EVEN

ODD
(BRST)
Figure 26. Level Shifter Normal Operation with 10 channel – End of The Frame for A-type

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October 2017 – Rev.1.0.1 29 / 44
 SM4085

The following Figure 27 is the power on sequence of the B-type 10ch output mode. EVEN is fixed to VGL2 at start-up and
VST and RESET output operation condition at B-type is different from A-type.

Table 9. The Register Code of The B-Type

Channel DAC Address = 18h

Type xxxxx0xxb Type

A Type A Type
xxxxxxx0b
DAC Address 8ch output mode 10ch output mode
= 18h B Type B Type
xxxxxxx1b
8ch output mode 10ch output mode

E/O

GST

GCLK

MCLK

CLK5

CLK4

CLK3

CLK2

CLK1

CLK10

CLK9

CLK8

CLK7

CLK6

VST

RESET

EVEN

ODD
(BRST)
Figure 27. Level Shifter Normal Operation with 10 channels - Power On Sequence for B-type

Note) The power-on sequence for the B- type 8ch: CLK4 à CLK3 à CLK2 à CLK1 à CLK8 à CLK7 à CLK6 à CLK5

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30 / 44 October 2017 – Rev.1.0.1
 SM4085

Figure 28 is the power on sequence of the B-type 10ch output mode.

E/O

GST

GCLK

MCLK

CLK5

CLK4

CLK3

CLK2

CLK1

CLK10

CLK9

CLK8

CLK7

CLK6

VST

RESET

EVEN

ODD
(BRST)
Figure 28. Level Shifter Normal Operation with 10 channels – End of The Frame for B-type

© 2017 Silicon Mitus, Inc. [Link]

October 2017 – Rev.1.0.1 31 / 44
 SM4085

Level shifter CLKx Output

EO
The level shifter has 4 input signals (GCLK, MCLK, E/O
and GST) and 5 kinds of output (CLK1~10, EVEN, ODD,
EVEN
RESET and VST). Each of the level shifter outputs has
ODD
the current limit circuit. Figure 29 is one of the level (BRST)
shifter output block diagram.
Figure 31. The EVEN & ODD Output of A-Type

Table 10. A-Type Interface

L/S_VGH
Edge EVEN ODD
PMSENSE
E/O Rising Low High à Low
PMMAIN E/O Falling Low à High Low
ILIM_H
E/O Rising High à Low Low
MCLK E/O Falling Low Low à High
Level Shifter IS_P
Output GCLK
L/S
IS_N Contorl
At B-type, the EVEN is fixed to VGL2 and only ODD
ILIM_L (BRST) is decided by E/O signal. The ODD (BRST) is
also set to LOW by GST rising edge. Figure 32 and
Table 11 shows this operation.
NMMAIN NMSENSE

EO

VGL2
EVEN
Figure 29. Level Shifter Block Diagram
ODD
(BRST)
The one of the level shifter outputs (CLKx) goes to VGH
GST
level from VGL level when PMMAIN switch is turned on by Figure 32. The ODD Output of B-Type
GCLK rising edge, and maintains VGH level until NMMAIN
switch is turned on by MCLK falling edge. The CLK goes Table 11. B-Type Interface
to VGL level by MCLK falling edge. This is how the CLK Edge EVEN ODD
is working by GCLK and MCLK. Refer to the Figure 30 . E/O Rising Low(No change) High à Low
E/O Falling Low(No change) Low
STEP STEP
1 2 E/O Rising Low(No change) Low
E/O Falling Low(No change) Low à High
GST Rising Low(No change) Low
GCLK

Level shifter VST / RESET Output

MCLK
The VST and RESET output depend on L/S interface (A-
type or B-type). For the VST output, it reacts to GST high
and GCLK low condition at A-type. At B-type, it operates
when the both GST and MCLK are high. For RESET
CLK output, it reacts to both GST and GCLK high condition at
Figure 30. Level Shifter Output Sequence A-type. At B-type, it operates when the GST is high and
MCLK is low. The duration of the GCLK low signal should
Level shifter EVEN / ODD Output be longer than the duration of GST high at A-type and the
duration of the MCLK high should be longer than the
The status of EVEN and ODD output change according
duration of GST high at B-type to prevent from
to the L/S interface (A-type or B-type). E/O signal
malfunction by any glitch. Refer to the Figure 33 and
decides the phase between EVEN and ODD at A-type.
Figure 34 for this operation
Figure 31 and Table 10 show this operation.

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32 / 44 October 2017 – Rev.1.0.1
 SM4085

GST
GST

GCLK
E/O
MCLK
GCLK
VST

RESET
VST
Figure 33. The VST & RESET Output of A-Type

GST Reset
Figure 37. VST / Reset Operation at Abnormal
GCLK
Condition.
MCLK

VST
Level Shifter Output Over Current Protection
The level shifter has its own over current function for the
RESET
safe operation of the panel and IC itself. The current limit
Figure 34. The VST & RESET Output of B-Type
level is decided by ROCP1 & ROCP2 and the detecting time
is decided by COCP Time1 & COCP Time2. Once the level shifter
Power Off
gets into OCP condition, all of the level shifter outputs
Once VIN voltage touches VSTOP, all the level shifter become high-Z status. With the next VST signal, the
outputs discharge to VGL2 except for EVEN and ODD high-Z status is released and the outputs go to its default
which are naturally discharged to GND. This operation is level. If the level shifter is still in the OCP condition, it
regardless of L/S interface (A-type or B-type) becomes high-Z status again when the over current is
sensed. After the device counts this operation 3 times
continuously, the SM4085 is shut down at the state of the
Abnormal Condition
VST generating.
If GST signal is rising when E/O signal is high, the state
of the level shifter is abnormal. The level shifter outputs
under the abnormal condition are as shown below. OCP Current Level
(Figure 35 ~ Figure 37). The abnormal condition can be All of the level shifter output have over-current-protection
released by GST high under E/O low level. (OCP) function. The current level of the OCP is decided
by external ROCP1 & ROCP2. The external resistor at OCP1
pin (ROCP1) decides the OCP level of the CLK1~CLK10,
GST Reset and VST. The resistor at OCP2 pin (ROCP2)
decides the OCP level of the EVEN and ODD. The
E/O
current which is generated by ROCPX is converted to the
EVEN
OCP detecting voltage for internal circuit. Even if the
VGH_E/O VGH_E/O
OCP current level is too high due to the wrong selection
VGL2 of the ROCPX, the internal clamp circuit limits the current
VGH_E/O
to maximum level. The maximum current limit level of the
each level shifter output is decided as Table 12 and the
VGL2
ODD OCP level according to setting ROCPX is shown in Table
Figure 35. E/O Operation at Abnormal Condition.
13. The OCP operation is described in Figure 38 and
Figure 39. The current limit level tends to be not linear
GST when the current limit level set by ROCPX is closer to its
E/O maximum level due to its saturation characteristics.
Accordingly the measured current level could be smaller
than calculated level.
GCLK
Table 12. OCP current level
CLK1~ CLK 10 RESET, VST EVEN, ODD

SET ROCP1 ROCP2

CLK
Max IOCP 200mA (typ.) 105mA (typ.) 105mA (typ.)
Figure 36. CLK Operation at Abnormal Condition.
LS current limit = 2216 / ROCP

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October 2017 – Rev.1.0.1 33 / 44
 SM4085

Table 13. OCP level according to ROCP Table 14. OCP detecting time according to COCP TimeX
250
Current Limit Level(mA)

200 OCP Detecting

150
HIGH-Z
tOCP
100

50 COCP_Time tOCP COCP_Time tOCP

0pF 0.62 100pF 5.67
0
0 50 100 150 200
2pF 0.65 120pF 6.90
ROCP(kohm) 5pF 0.70 150pF 8.74
10pF 0.78 180pF 10.58
CLK VST, Reset, EVEN, ODD
15pF 0.85 220pF 13.03
ROCP
CLK1~10 VST/Reset EVEN/ODD 18pF 0.90 270pF 16.10
TYP 22pF 0.96 330pF 19.77
36kΩ 61.6 61.6 61.6 27pF 1.20 390pF 23.45
39kΩ 56.8 56.8 56.8
33pF 1.57 470pF 28.36
43kΩ 51.5 51.5 51.5
47pF 2.43 560pF 33.87
47kΩ 47.1 47.1 47.1
56pF 2.98 680pF 41.23
51kΩ 43.5 43.5 43.5
68pF 3.71 820pF 49.81
56kΩ 39.6 39.6 39.6
unit μs(TYP.) unit μs(TYP.)
59kΩ 37.6 37.6 37.6
62kΩ 35.7 35.7 35.7
60
68kΩ 32.6 32.6 32.6
75kΩ 29.5 29.5 29.5 50
82kΩ 27.0 27.0 27.0
91kΩ 24.4 24.4 24.4 40
100kΩ
time(us)

22.2 22.2 22.2

30
110kΩ 20.1 20.1 20.1
120kΩ 18.5 18.5 18.5 20
130kΩ 17.0 17.0 17.0
150kΩ 14.8 14.8 14.8 10
180kΩ 12.3 12.3 12.3
0
200kΩ 11.1 11.1 11.1
0 200 400 600 800
220kΩ 10.1 10.1 10.1 COCP_Time(pF)
unit mA mA mA
tOCP

OCP detecting time

OCP operation could come into effect under wrong
current information such as unexpected spike current
component even if it is not in real abnormal condition. In
order to monitor the real abnormal current component
generated by the pin short or defective panel, the OCP
detecting time should be well controlled. The capacitor
values at OCP Time1 & OCP Time2 pin decide the OCP
detecting time. The OCP detect time and operation
according to setting COCP TimeX are shown in Table 14 and
Figure 38 ~ Figure 39. When the device detects the over
current during the normal operation, the charging current
starts to flow into the COCP TimeX. All the outputs become
high-Z state when OCP Timex voltage of the capacitor
touches 1.95V (typ.). The time for high-Z status is longer
than tOCP which is the least sensing time to make the
level shifter outputs high-Z status due to its internal logic
delay. The position of the COCP TimeX in the PCB and the
IC internal parasitic capacitance have an effect on OCP
detecting time slightly. The time should be well optimized
for its stable operation in the each PCB condition.

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34 / 44 October 2017 – Rev.1.0.1
 SM4085

GCLK

MCLK

HIGH-Z

VCLK

The current level of

OCP is set by ROCP

ICLK
HIGH-Z trigger level
touching

1.95V : HIGH-Z trigger level of L/S output

VCOCP_Time
Slope of VCOCP Time
is set by COCP Time

Figure 38. OCP operation according to ROCP and COCP Time (Touching OCP Trigger Level)

GCLK

MCLK

VCLK

The current level of

OCP is set by ROCP

ICLK
HIGH-Z trigger level
No touching

1.95V : HIGH-Z trigger level of L/S output

VCOCP_Time
Slope of VCOCP Time
is set by COCP Time

Figure 39. OCP operation according to ROCP and COCP Time (No touching OCP Trigger Level)

© 2017 Silicon Mitus, Inc. [Link]

October 2017 – Rev.1.0.1 35 / 44
 SM4085

OCP dead time

MCLK
OCP dead time is necessary to ignore peak current that
occurs when the level shifter outputs charge the pixel of
GST
the panel. If it is high enough to touch the current limit
level, unexpected OCP operation would occur. The dead
time is decided by the rising and the falling of the GCLK, CLK
MCLK and GST condition for the level shifter output
CLK1~CLK10. The definition of the dead time
Dead-Time
(CLK1~CLK10) according to the GCLK, MCLK and GST
conditions are as below. In addition the VST has its own Figure 42. CLK Falling Dead Time #1
internal dead time. (MCLK rising earlier)

Table 15. CLK Dead Time Duration

Definition of Dead time duration MCLK
Dead Time
Which one is next to CLK?
GST
CLK Rising GCLK falling or MCLK rising edge

CLK Falling MCLK rising or GST rising

CLK

GCLK
Dead-Time

MCLK Figure 43. CLK Falling Dead Time #2

(GST rising earlier)

CLK

Dead-Time

Figure 40. CLK Rising Dead Time #1

(GCLK falling earlier)

GCLK

MCLK

CLK

Dead-Time

Figure 41. CLK Rising Dead Time #2

(MCLK rising earlier)

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36 / 44 October 2017 – Rev.1.0.1
 SM4085

Appendix A

SWO(VDD) VGL2 (Room temp) VGL2 (Hot temp)

DAC Address DAC Address DAC Address

00h 06h 07h
(HEX) (HEX) (HEX)

SETTING SETTING SETTING SETTING

SWO (VDD) SWO (VDD) VGL2LT VGL2HT
DATA (HEX) DATA (HEX) DATA (HEX) DATA (HEX)
00h - 20h 16.9V 00h -4.5V 00h -4.5V
01h 13.8V 21h 17.0V 01h -5.0V 01h -5.0V
02h 13.9V 22h 17.1V 02h -5.5V 02h -5.5V
03h 14.0V 23h 17.2V 03h -6.0V 03h -6.0V
04h 14.1V 24h 17.3V 04h -6.5V 04h -6.5V
05h 14.2V 25h 17.4V 05h -7.0V 05h -7.0V
06h 14.3V 26h 17.5V 06h -7.5V 06h -7.5V
07h 14.4V 27h 17.6V 07h -8.0V 07h -8.0V
08h 14.5V 28h 17.7V 08h -8.5V 08h -8.5V
09h 14.6V 29h 17.8V 09h -9.0V 09h -9.0V
0Ah 14.7V 2Ah 17.9V 0Ah -9.5V 0Ah -9.5V
0Bh 14.8V 2Bh 18.0V 0Bh -10.0V 0Bh -10.0V
0Ch 14.9V 2Ch 18.1V 0Ch -10.5V 0Ch -10.5V
0Dh 15.0V 2Dh 18.2V 0Dh -11.0V 0Dh -11.0V
0Eh 15.1V 2Eh 18.3V 0Eh -11.5V 0Eh -11.5V
0Fh 15.2V 2Fh 18.4V 0Fh -12.0V 0Fh -12.0V
10h 15.3V 30h 18.5V 10h -12.5V 10h -12.5V
11h 15.4V 31h 18.6V 11h -13.0V 11h -13.0V
12h 15.5V 32h 18.7V 12h -13.5V 12h -13.5V
13h 15.6V 33h 18.8V 13h -14.0V 13h -14.0V
14h 15.7V 34h 18.9V 14h -14.5V 14h -14.5V
15h 15.8V 35h 19.0V 15h -15.0V 15h -15.0V
16h 15.9V 36h 19.1V 16h -15.5V 16h -15.5V
17h 16.0V 37h 19.2V 17h -16.0V 17h -16.0V
18h 16.1V 38h 19.3V 18h -16.5V 18h -16.5V
19h 16.2V 39h 19.4V 19h -17.0V 19h -17.0V
1Ah 16.3V 3Ah 19.5V 1Ah -17.5V 1Ah -17.5V
1Bh 16.4V 3Bh 19.6V 1Bh -18.0V 1Bh -18.0V
1Ch 16.5V 3Ch 19.7V 1Ch -18.5V 1Ch -18.5V
1Dh 16.6V 3Dh 19.8V 1Dh -19.0V 1Dh -19.0V
1Eh 16.7V 3Eh 19.9V 1Eh -19.5V 1Eh -19.5V
1Fh 16.8V 3Fh 20.0V 1Fh -20.0V 1Fh -20.0V

© 2017 Silicon Mitus, Inc. [Link]

October 2017 – Rev.1.0.1 37 / 44
 SM4085

Appendix B
VGH_LT (Low temp) VGH_RT (Room temp.) HVDD VCC2 VGL1
DAC Address DAC Address DAC Address DAC Address DAC Address
04h 04h 03h 02h 05h
(HEX) (HEX) (HEX) (HEX) (HEX)
SETTING SETTING SETTING SETTING SETTING
VGHLT VGHHT HVDD VCC2 VGL
DATA (HEX) DATA (HEX) DATA (HEX) DATA (HEX) DATA (HEX)
0000xxxxb 21V xxxx0000b 20V 00h SWO/2-0.8V 00h 1.00V 00h -1.8V
0001xxxxb 22V xxxx0001b 21V 01h SWO/2-0.7V 01h 1.05V 01h --2.0V
0010xxxxb 23V xxxx0010b 22V 02h SWO/2-0.6V 02h 1.10V 02h --2.2V
0011xxxxb 24V xxxx0011b 23V 03h SWO/2-0.5V 03h 1.15V 03h --2.4V
0100xxxxb 25V xxxx0100b 24V 04h SWO/2-0.4V 04h 1.20V 04h --2.6V
0101xxxxb 26V xxxx0101b 25V 05h SWO/2-0.3V 05h 1.25V 05h --2.8V
0110xxxxb 27V xxxx0110b 26V 06h SWO/2-0.2V 06h 1.30V 06h --3.0V
0111xxxxb 28V xxxx0111b 27V 07h SWO/2-0.1V 07h 1.35V 07h --3.2V
1000xxxxb 29V xxxx1000b 28V 08h SWO/2 08h 1.70V 08h --3.4V
1001xxxxb 30V xxxx1001b 29V 09h SWO/2+0.1 09h 1.75V 09h --3.6V
1010xxxxb 31V xxxx1010b 30V 0Ah SWO/2+0.2 0Ah 1.80V 0Ah --3.8V
1011xxxxb 32V xxxx1011b 31V 0Bh SWO/2+0.3 0Bh 1.85V 0Bh --4.0V
1100xxxxb 33V xxxx1100b 32V 0Ch SWO/2+0.4 0Ch 1.90V 0Ch --4.2V
1101xxxxb 34V xxxx1101b 33V 0Dh SWO/2+0.5 0Dh 1.95V 0Dh --4.4V
1110xxxxb 35V xxxx1110b 34V 0Eh SWO/2+0.6 0Eh 2.00V 0Eh --4.6V
1111xxxxb 36V xxxx1111b 35V 0Fh SWO/2+0.7 0Fh 2.05V 0Fh --4.8V
10h --5.0V
DLY0 DLY1 DLY2 VCC1 11h --5.2V
DAC Address DAC Address DAC Address DAC Address
08h 08h 08h 01h 12h --5.4V
(HEX) (HEX) (HEX) (HEX)
SETTING SETTING SETTING SETTING
DLY1 DLY1 DLY2 VCC1 13h --5.6V
DATA (BIN) DATA (BIN) DATA (BIN) DATA (BIN)
xxxx00xxb 3ms xxxx00xxb 0ms xx00xxxxb 0ms 00h 3.2V 14h --5.8V
xxxx01xxb 8ms xxxx01xxb 5ms xx01xxxxb 5ms 01h 3.3V 15h --6.0V
xxxx10xxb 16ms xxxx10xxb 10ms xx10xxxxb 10ms 02h 3.4V 16h --6.2V
xxxx11xxb 0ms xxxx11xxb 15ms xx11xxxxb 15ms 03h 3.5V 17h --6.4V
18h --6.6V
DLY3 19h --6.8V
DAC Address
08h 1Ah --7.0V
(HEX)
SETTING
DLY3 1Bh --7.2V
DATA (BIN)
00xxxxxxb 0ms 1Ch --7.4V
01xxxxxxb 10ms 1Dh --7.6V
10xxxxxxb 20ms 1Eh --7.8V
11xxxxxxb 30ms 1Fh --8.0V

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38 / 44 October 2017 – Rev.1.0.1
 SM4085

Appendix C
Setting GMA_1 GMA_2 GMA_3 GMA_4
DAC Address
09h 0Ah / 0Bh 0Ch / 0Dh 0Eh
(HEX)
Resolution(RES) (SWO-HVDD)/511 (SWO-HVDD)/511 (SWO-HVDD)/511 (SWO-HVDD)/511
00h VDD-(RES*255)V VDD-(RES*383)V VDD-(RES*511)V VDD-(RES*511)V
01h VDD-(RES*254)V VDD-(RES*382)V VDD-(RES*510)V VDD-(RES*510)V
02h VDD-(RES*253)V VDD-(RES*381)V VDD-(RES*509)V VDD-(RES*509)V
03h VDD-(RES*252)V VDD-(RES*380)V VDD-(RES*508)V VDD-(RES*508)V
04h VDD-(RES*251)V VDD-(RES*379)V VDD-(RES*507)V VDD-(RES*507)V
05h VDD-(RES*250)V VDD-(RES*378)V VDD-(RES*506)V VDD-(RES*506)V
⁞ ⁞ ⁞ ⁞ ⁞
FAh VDD-(RES*5)V VDD-(RES*133)V VDD-(RES*261)V VDD-(RES*261)V
FBh VDD-(RES*4)V VDD-(RES*132)V VDD-(RES*260)V VDD-(RES*260)V
FCh VDD-(RES*3)V VDD-(RES*131)V VDD-(RES*259)V VDD-(RES*259)V
FDh VDD-(RES*2)V VDD-(RES*130)V VDD-(RES*258)V VDD-(RES*258)V
FEh VDD-(RES*1)V VDD-(RES*129)V VDD-(RES*257)V VDD-(RES*257)V
FFh VDD VDD-(RES*128)V VDD-(RES*256)V VDD-(RES*256)V
⁞ - ⁞ ⁞ -
17Bh - VDD-(RES*4)V VDD-(RES*132)V -
17Ch - VDD-(RES*3)V VDD-(RES*131)V -
17Dh - VDD-(RES*2)V VDD-(RES*130)V -
17Eh - VDD-(RES*1)V VDD-(RES*129)V -
17Fh - VDD VDD-(RES*128)V -

Setting GMA_5 GMA_6 GMA_7 GMA_8

DAC Address
0Fh 10h / 11h 12h / 13h 14h
(HEX)
Resolution(RES) HVDD/511 HVDD/511 HVDD/511 HVDD/511
00h HVDD-(RES*255)V HVDD-(RES*383)V HVDD-(RES*511)V HVDD-(RES*511)V
01h HVDD-(RES*254)V HVDD-(RES*382)V HVDD-(RES*510)V HVDD-(RES*510)V
02h HVDD-(RES*253)V HVDD-(RES*381)V HVDD-(RES*509)V HVDD-(RES*509)V
03h HVDD-(RES*252)V HVDD-(RES*380)V HVDD-(RES*508)V HVDD-(RES*508)V
04h HVDD-(RES*251)V HVDD-(RES*379)V HVDD-(RES*507)V HVDD-(RES*507)V
05h HVDD-(RES*250)V HVDD-(RES*378)V HVDD-(RES*506)V HVDD-(RES*506)V
⁞ ⁞ ⁞ ⁞ ⁞
FAh HVDD-(RES*5)V HVDD-(RES*133)V HVDD-(RES*261)V HVDD-(RES*261)V
FBh HVDD-(RES*4)V HVDD-(RES*132)V HVDD-(RES*260)V HVDD-(RES*260)V
FCh HVDD-(RES*3)V HVDD-(RES*131)V HVDD-(RES*259)V HVDD-(RES*259)V
FDh HVDD-(RES*2)V HVDD-(RES*130)V HVDD-(RES*258)V HVDD-(RES*258)V
FEh HVDD-(RES*1)V HVDD-(RES*129)V HVDD-(RES*257)V HVDD-(RES*257)V
FFh HVDD HVDD-(RES*128)V HVDD-(RES*256)V HVDD-(RES*256)V
⁞ - ⁞ ⁞ -
17Bh - HVDD-(RES*4)V HVDD-(RES*132)V -
17Ch - HVDD-(RES*3)V HVDD-(RES*131)V -
17Dh - HVDD-(RES*2)V HVDD-(RES*130)V -
17Eh - HVDD-(RES*1)V HVDD-(RES*129)V -
17Fh - HVDD HVDD-(RES*128)V -

© 2017 Silicon Mitus, Inc. [Link]

October 2017 – Rev.1.0.1 39 / 44
 SM4085

Appendix D
VCOM Operation VCOM Temp.
DAC Address DAC Address
17h 18h
(HEX) (HEX)
SETTING SETTING
Discharge, Temp Comp. VGH/VGL Protection & L/S Option
DATA (BIN) DATA (BIN)
xxx0xxxxb Output Disable xxxxx0xxb L/S Channel 8 - Channel
xxx1xxxxb Discharge Enable xxxxx1xxb Option 10 - Channel
xxxx0000b VCOM-VDD/1023*14 xxxxxx0xb VGH/VGL2 Protection ON
xxxx0001b VCOM-VDD/1023*12 xxxxxx1xb Protection On/Off Protection OFF
xxxx0010b VCOM-VDD/1023*10 xxxxxxx0b L/S A - type
xxxx0011b VCOM-VDD/1023*8 xxxxxxx1b Interface B - type
xxxx0100b VCOM-VDD/1023*6
xxxx0101b VCOM-VDD/1023*4
xxxx0110b VCOM-VDD/1023*2 PVCOM
DAC Address
xxxx0111b Compensated VCOM 15h, 16h
(HEX)
Temperature
SETTING
xxxx1000b VCOM VCOM+VDD/1023*2 PVCOM
DATA (HEX)
xxxx1001b VCOM+VDD/1023*4 00-00h VDD*(120/1023)
xxxx1010b VCOM+VDD/1023*6 00-01h VDD*(121/1023)
xxxx1011b VCOM+VDD/1023*8 00-02h VDD*(123/1023)
xxxx1100b VCOM+VDD/1023*10 00-03h VDD*(124/1023)
xxxx1101b VCOM+VDD/1023*12 00-04h VDD*(125/1023)
xxxx1110b VCOM+VDD/1023*14 00-05h VDD*(126/1023)
xxxx1111b VCOM+VDD/1023*16 ︙ ︙
00-37h VDD*(175/1023)
00-38h VDD*(176/1023)
00-39h VDD*(177/1023)
00-3Ah VDD*(178/1023)
00-3Bh VDD*(179/1023)
00-3Ch VDD*(180/1023)
00-3Dh VDD*(181/1023)
00-3Eh VDD*(182/1023)
00-3Fh VDD*(183/1023)
︙ ︙
01-0Ch VDD*(388/1023)
01-0Dh VDD*(389/1023)
01-0Eh VDD*(390/1023)
01-0Fh VDD*(391/1023)
01-10h VDD*(392/1023)
︙ ︙
01-80h VDD*(504/1023)
01-81h VDD*(505/1023)
01-82h VDD*(506/1023)
01-83h VDD*(507/1023)
01-84h VDD*(508/1023)
01-85h VDD*(509/1023)
01-86h VDD*(510/1023)

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40 / 44 October 2017 – Rev.1.0.1
 SM4085

Package Information
Dimensions are in millimeters unless otherwise noted.

© 2017 Silicon Mitus, Inc. [Link]

October 2017 – Rev.1.0.1 41 / 44
 SM4085

Package Information (Continued)

Dimensions are in millimeters unless otherwise noted.

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Silicon Mitus cannot assume any responsibility for the consequence of use of information furnished nor for any infringement of patents or
other rights of third parties which may result from its use. No circuit patent licenses are implied. Silicon Mitus reserves the right to change
the circuitry and specifications without notice at any time. This publication supersedes and replaces all information previously supplied.
Silicon Mitus products are not authorized for use as critical components in life support devices or systems without the express written
approval of Silicon Mitus.

© 2017 Silicon Mitus, Inc. - Printed in Korea - All Rights Reserved

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October 2017 – Rev.1.0.1 43 / 44
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Revision History
Version Date Page Description

1.0.1 2017.10.30 7 Changes the recommended value of the VGH inductor from 10μH to 22μH.

[Link] © 2017 Silicon Mitus, Inc.

44 / 44 October 2017 – Rev.1.0.1