2024 Third International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE)

Design of Flash ADC with CMOS Logic using

2024 Third International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE) | 979-8-3503-1860-9/24/$31.00 ©2024 IEEE | DOI: 10.1109/ICDCECE60827.2024.10548132

45nm Technology
1st Badarla Sri Pavan 2nd Chetan M H
Department of Electronics and Communication Engineering Department of Electronics and Communication Engineering
Nitte Meenakshi Institute of Technology Nitte Meenakshi Institute of Technology
Bangalore, Karnataka, India Bangalore, Karnataka, India
[Link]@[Link] chetanmhchetan@[Link]

3rd Kartik Pagad 4th S R Shreya

Department of Electronics and Communication Engineering Department of Electronics and Communication Engineering
Nitte Meenakshi Institute of Technology Nitte Meenakshi Institute of Technology
Bangalore, Karnataka, India Bangalore, Karnataka, India
kartikps1947@[Link] srshreya130@[Link]

Abstract—This paper presents the design of a Flash analog-to- time. As a result, Flash ADCs are used in several systems
digital converter (ADC) with 5-bit resolution using complemen- that need high speed and broad bandwidth. The resistor ladder
tary metal-oxide semiconductor (CMOS) logic with 45nm tech- is designed mainly to provide a stable reference voltage for
nology. The methodology comprises of resistive ladder network,
thermometer code generation, binary encoder, and comparator. comparators, yet the value of the resistance is very small.
A two-stage operational amplifier functions as a comparator, Hence, it increases the total power consumption of the ADC
which generates the thermometer code, and the priority encoder due to the resistor ladder network [3]. The Flash ADC with a
translates this code into binary output. The resultant binary two-stage operational amplifier offers high-speed conversion
output is the digital output of the Flash ADC. The primary and enhanced resolution. It leverages the rapid operation
issue in the Flash ADCs was frequently stems, hence the area
and circuit power consumption increases with the increase in of the Flash architecture combined with the precision and
resolution bits. The main goal is to optimize the encoder circuit gain capabilities of the two-stage operational amplifier con-
that enhances the bit count and reduce ADC power consumption. figuration. The methodology focuses on power consumption
To reduce power consumption, the encoder is built using a 2:1 through encoder circuitry, using 2:1 multiplexer, and exploring
multiplexer based on several logics such as transmission gate various logic designs such as pass transistor (PT), transmission
logic, pass transistor logic, and CMOS logic. The results shows
improvement in resolution and reduced power consumption. gate (TG), and CMOS logic [5]. The Performance evaluation
Index Terms—ADC, CMOS, Flash ADC, 2:1 Multiplexer, compares the conversion time, average power consumption
Resistive ladder and the importance of power efficiency in ADC design [8].
This work focuses on the power consumption through encoder
I. I NTRODUCTION circuitry using 2:1 multiplexer with various logic designs.
The advancement in the field of science and technology The performance metrics such as power consumption, area,
has led to a surge in digital signal processing for several and delay are compared [6]. The paper organized as follows.
applications. Signal processing provides several benefits in Section I provides the Introduction. Section II discusses the
most digital domains, including low power consumption, ex- related works. The methodology is described in Section III.
cellent precision, decreased silicon space with design, and pro- The results are provided in Section IV and paper concluded
grammable flexibility. The design process is quicker and more in Section V.
economical. Thus, a system with high speed and small area
must be designed and an analog-to-digital converter (ADC) II. RELATED WORKS
with a much faster speed is necessary [1]. For wireless com- In [1], the authors described the development and applica-
munication and picture processing applications, digital systems tion of a Flash ADC using 45nm technology in LTspice tool
with extended battery life and portability are desirable [2]. with a 3-bit resolution. It uses two-stage operational amplifiers.
Moreover, most of the mixed-signal systems employ ADCs as The ADC architecture includes a resistive ladder network with
front-end components. The design of ADCs that require high seven resistors and six comparators. Variations between neigh-
speed and consume less power need to be concentrated. There boring comparators were minimized by uniformly spreading
are several kinds of ADC designs, such as sigma-delta, flash, reference voltages throughout the ladder network. A variety
successive approximation, etc. The Flash ADCs are the most of encoder designs was implemented including a 2:1 mux-
popular among them because of their parallel design, which based encoder that makes use of PT, TG, and CMOS logics.
allows high speed and limited resolution on the conversion In [4] authors proposed an ADC converter based on flash

979-8-3503-1860-9/24/$31.00 ©2024 IEEE

Authorized licensed use limited to: Zhejiang University. Downloaded on March 19,2025 at [Link] UTC from IEEE Xplore. Restrictions apply.
that uses around 223 µW of power and has a limited output For instance, to implement a 9-bit Flash ADC, 511 compara-
resolution of 3-bits. The encoder uses analog comparator tors are needed, resulting in significant power dissipation and
outputs to get the compressed digital output, which was requiring a considerable die area. Therefore, there is a critical
simulated in Cadence Virtuoso using 180nm technology. In need to minimize power consumption and reduce the footprint
[6], literature explained threshold inverter quantization that of the Flash ADC due to the limitations [9]. It is important that
achieves three-bit quantization by triggering comparators when the resolution of a Flash ADC indicates the total number of
analog voltage exceeds the reference, yielding digital 1s for bits in the output, without necessarily implying high accuracy.
parallel conversions. This method precisely converts analog Hence, while increasing the resolution, the precision of the
signals to digital outputs. In [14], high-speed, low power Flash output enhances. It is achieved at the cost of higher power
ADCs are favored for high frequency applications despite consumption as well as larger die area due to the escalating
modest precision 180nm technology using Cadence tool. The number of comparators. Thus, improving power efficiency and
authors of [15] introduced a power-efficient Flash ADC design minimizing footprint are crucial considerations in the design
with single inverter comparators and multiplexer encoders for and implementation of Flash ADCs [12].
power consumption and latency at 10 M Hz frequency.
B. Resistive Ladder Network
III. PROPOSED METHODOLOGY In this work, we have implemented a 5-bit Flash ADC
A. Flash ADC architecture with a resistive ladder network. Fig. 2 shows the resistive
ladder network, which is to provide constant reference voltages
In this work, firstly, a Flash ADC is designed as shown to the comparators. For an N -bit Flash ADC, the ladder
in Fig. 1. It describes the architecture of ADC. In the im- network requires 2N resistors [4]. In this work, the ladder
plementation of an N-bit Flash ADC, 2N −1 comparators are network serves to distribute the reference voltages evenly
required. Each comparator has two inputs, one for the analog across all the resistors by ensuring the difference between
input signal and the other for the reference voltage signal. the reference voltages of adjacent comparators corresponds
The resistive ladder network consisting of 2N resistors for an to the LSB value. With a reference voltage set to two volts,
N-bit ADC which divides the reference voltage to generate each comparator reference voltage differs by 62.5 mV . Figure
uniformly distributed voltage levels differed by least signif- 3 shows the comparator by applying input signal that is
icant bit (LSB). When the input signal exceeds a particular compared with reference signal. The condition for output is
reference voltage level, the corresponding comparator output as follows [11].
gives a logic high signal; otherwise, produces a logic low Case 1: If Vinput > Vref ; Voutput = Logic High.
signal. This comparison process creates a thermometer code Case 2: If Vinput < Vref ; Voutput = Logic Low.
representation of the analog input signal. Typically, in a 5-bit where Vi is input voltage to the comparator, V0 is the output
Flash ADC implementation, 32 resistors are required for the voltage of the comparator.
resistive ladder network [4]. The output of the comparators
form a thermometer code, that has to be converted into binary
code for further processing. This conversion typically involves
determining the highest reference voltage level exceeded by
the analog input signal, thereby assigning a binary value to
each bit position.
The resolution of a Flash ADC significantly impacts the
output. However, the major drawback is when the resolution
increases, number of comparators requirement also increases.

Fig. 1. Flash ADC architecture. Fig. 2. Resistive Ladder Network

Authorized licensed use limited to: Zhejiang University. Downloaded on March 19,2025 at [Link] UTC from IEEE Xplore. Restrictions apply.
 The term “thermometer code” is used to describe the output
of comparators because, it resembles a thermometer reading,
where the number of 1s increases in proportion to the value,
into the rising mercury level. Several types of encoders can
perform this translation, including ROM encoders, Wallace
tree encoders, multiplexer based encoders, and XOR-based
encoders, each offering distinct advantages and drawbacks
[12]. Among these encoders, the multiplexer based encoder
stands out for its straightforward structural design. Unlike
the Wallace tree encoder, it exhibits a smaller critical path
Fig. 3. Comparator due to its reliance on 2:1 multiplexer. Additionally, the most
significant bit (MSB) in the resulting binary code is set high,
Figure 4 shows a two-stage operational amplifier, which if half of the thermometer code signals logic high, as per the
contains differential stage and common source stage [7]. The fundamental logic employed by the multiplexer based encoder.
inputs are given through M1 transistor and M2 transistor. The In the binary output, the MSB corresponds to a value of
op-amp biasing is possible with M5 and M8 transistors for 2N −1 . To derive subsequent binary outputs, the thermometer
the ensurence that all the transistors are in saturation [9]. The code is further subdivided into two codes. The output of the
transistors M3 and M4 are used to form current mirror and preceding multiplexer stage determines the select line for the
further the current M1 and M2 are subtracted. In case, for subsequent multiplexer stage. This process continues until the
insufficient gain, then the solution is achieved with a common least LSB of the binary output is obtained, culminating in
source amplifier which is formed by transistors M6 and M7.
The comparator in this work is driven by a sinusoidal input
of two volts. The reference voltage of resistive ladder network TABLE I
is compared with the input voltage, and the result will be 5- BIT F LASH ADC
either Logic High or Logic Low. The output of the comparator Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Thermometer code
is obtained by applying the input voltage and the final result 0 0 0 0 0 0000000000000000000000000000000
will be a square waveform as shown in Fig. 5. 0 0 0 0 1 0000000000000000000000000000001
0 0 0 1 0 0000000000000000000000000000011
C. Thermometer to Binary Encoder design
0 0 0 1 1 0000000000000000000000000000111
Table I shows the encoder implementation using 26 numbers 0 0 1 0 0 0000000000000000000000000001111
of 2:1 multiplexer arranged in the following pattern to get 0 0 1 0 1 0000000000000000000000000011111
the encoded binary data [10]. There are various techniques 0 0 1 1 0 0000000000000000000000000111111
available for converting thermometer code to binary code. 0 0 1 1 1 0000000000000000000000001111111
0 1 0 0 0 0000000000000000000000011111111
0 1 0 0 1 0000000000000000000000111111111
0 1 0 1 0 0000000000000000000001111111111
0 1 0 1 1 0000000000000000000011111111111
0 1 1 0 0 0000000000000000000111111111111
0 1 1 0 1 0000000000000000001111111111111
0 1 1 1 0 0000000000000000011111111111111
0 1 1 1 1 0000000000000000111111111111111
1 0 0 0 0 0000000000000001111111111111111
1 0 0 0 1 0000000000000011111111111111111
1 0 0 1 0 0000000000000111111111111111111
Fig. 4. Schematic of two-stage operational amplifier 1 0 0 1 1 0000000000001111111111111111111
1 0 1 0 0 0000000000011111111111111111111
1 0 1 0 1 0000000000111111111111111111111
1 0 1 1 0 0000000001111111111111111111111
1 0 1 1 1 0000000011111111111111111111111
1 1 0 0 0 0000000111111111111111111111111
1 1 0 0 1 0000001111111111111111111111111
1 1 0 1 0 0000011111111111111111111111111
1 1 0 1 1 0000111111111111111111111111111
1 1 1 0 0 0001111111111111111111111111111
1 1 1 0 1 0011111111111111111111111111111
1 1 1 1 0 0111111111111111111111111111111
Fig. 5. Output of comparator 1 1 1 1 1 1111111111111111111111111111111

Authorized licensed use limited to: Zhejiang University. Downloaded on March 19,2025 at [Link] UTC from IEEE Xplore. Restrictions apply.
the completion of the final 2:1 multiplexer stage. By utilizing
the 2:1 multiplexer, an encoder with reduced size and power
consumption is designed, even as the resolution increases [12].

D. 2:1 Multiplexer based Encoder

There are several methods for converting thermometer en-
coded signals to binary code. Among them, the multiplexer
based encoder because of its efficiency. By using 26 multiplex-
ers, the encoder offers a streamlined approach as shown in Fig.
6. From Table I, the truth table reveals a direct equivalence
Fig. 7. Transmission gate logic
between bit B5 and T 16 is a thermometer bit. Moreover, by
leveraging T 16 as a select line for the multiplexer, bit B4
can be derived from T 24 and T 8. The process is extended
to obtain all bits efficiently. By employing multiplexer as an
intermediary for thermometer to binary conversions yields a
circuit with reduced transistor count, thereby enhances the
power efficiency and overall performance. Figure 7 shows the
2:1 multiplexer using TG logic, where the output is controlled
by a switch. In the case of S = 1, the output will be A and for
S = 0, the output is B. Furthermore, a 2:1 multiplexer with
pass transistor logic is shown in Fig 8. Here, we implemented
a multiplexer using two transistors. The logic levels will be
dropped when pass transistors are used, hence a buffer is
introduced to get a stabilized binary 1 and a binay 0. Figure 9
illustrates the CMOS technology to construct a 2:1 multiplexer. Fig. 8. Pass transistor logic
The primary benefit of CMOS logic is that, any Boolean

Fig. 9. CMOS logic

function can be implemented with a pull-up network by using

PMOS transistors, while an NMOS transistor is designed using
pull-down network which produces output between the ground
and power terminals. As the number of transistors increases,
the associated characteristics such as area, power consumption,
and delay also increases [13].
IV. RESULTS AND DISCUSSION
The simulations are executed using Cadence Virtuoso tool
for a 5-bit Flash ADC using CMOS logic with 45 nm
technology. An input signal with a voltage of 2 volts and a
frequency of 1 KHz is applied for transient analysis. Based
on that, the average power has been computed. Figure 10
shows the design of Flash ADC in cadence Virtuoso tool using
45nm technology. It consists of a resistive ladder, comparators,
Fig. 6. Encoder implementation using 2:1 multiplexer and encoder. With the implementation as shown in Fig. 11,

Authorized licensed use limited to: Zhejiang University. Downloaded on March 19,2025 at [Link] UTC from IEEE Xplore. Restrictions apply.
 Fig. 12. Transient analysis for 5-bit Flash ADC using TG logic encoder

Fig. 13. Transient analysis for 5-bit Flash ADC using PT logic encoder

Fig. 10. Implementation of 5-bit Flash ADC using CMOS logic shown in Table II. In terms of area, CMOS Flash ADC requires
high transistor count of 648 compared to other Flash ADCs.
For delay analysis, CMOS Flash ADC is able to achieve lowest
delay of 165.1 ns. These metrics offer insights into the trade-
offs between power, area, and delay while implementing Flash
ADCs. Furthermore, key distinctions between 5-bit and 3-bit
Flash ADCs are highlighted in the Table II and Table III [1].
Although, the power consumption and delay are higher in 5-
bit Flash ADCs due to 25 distinct volatage levels, it provides
higher resolution when compared to 3-bit Flash ADC of 8
levels. Also, the higher area as shown Table II, results in a
increased dynamic range which helps to distinguish smaller
changes in the input voltage.
Fig. 11. 5-bit Flash ADC transient analysis

TABLE II
the simulation results are obtained. As a result, the output is 5- BIT F LASH ADC
obtained for a 5-bit binary transient analysis as shown in Fig.
11. The power consumption in a circuit is decreased by using 5-bit Flash ADC Power Area (Transistor Count) Delay (ns)
CMOS logic design methods. The transient analysis for 5- CMOS Flash ADC 2.736 nW 648 165.1
bit Flash ADC using TG logic encoder waveform is shown in PT Flash ADC 316.9 µW 440 175
Fig. 12. Similarly, the transient analysis for 5-bit Flash ADC
TG Flash ADC 338 µW 548 171
using pass logic encoder is given in Fig. 13. Here, the output
represents the binary data equivalent to the analog input.
The Table II illustrates the performance metrics for three TABLE III
3- BIT F LASH ADC
different types of Flash ADCs such as CMOS, PT, and TG
Flash ADCs. The metrics such as power consumption, area 3-bit Flash ADC [1] Power Area (Transistor Count) Delay (ns)
(measured in transistor count), and delay are evaluated for
CMOS Flash ADC 1.372 nW 448 55
three types of Flash ADCs. Among them, the CMOS Flash
PT Flash ADC 371 µW 363 124.7
ADC exhibits lowest power consumption of 2.736 nW , while
TG Flash ADC 345 µW 390 189
PT and TG Flash ADCs consume significantly more power as

Authorized licensed use limited to: Zhejiang University. Downloaded on March 19,2025 at [Link] UTC from IEEE Xplore. Restrictions apply.
 V. C ONCLUSION [13] S. Kumar and C. Nagesh, “Design of a Two-Step Low-Power and
High-Speed CMOS Flash ADC Architecture,” 2020 24th International
In this research, we have designed a 5-bit Flash ADC with Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, pp.
CMOS logic using 45nm Technology. The simulations have 1-6, 2020.
[14] P. V. Lakshmi, S. Musala and A. Srinivasulu, “Flash ADC’s low power,
been performed with Cadence virtuoso tool. A resistive ladder high speed dynamic comparator,” 2022 IEEE International Women in
network, thermometer code generation, binary encoder, and Engineering (WIE) Conference on Electrical and Computer Engineering
comparator are used to design the Flash ADC. The metrics (WIECON-ECE), Naya Raipur, India, pp. 352-355, 2022.
[15] S. S. Kamate, H. P. Rajani and V. Mallaraddi, “Design and Imple-
such as power, area, and delay are computed for 5-bit Flash mentation of Low Power Flash Analog to Digital Converter,” 2023
ADC. The primary goal is to minimize the power for 5-bit Second International Conference on Electrical, Electronics, Information
Flash ADC through encoder circuitry. Here, a 2:1 multiplexer and Communication Technologies (ICEEICT), Trichirappalli, India, pp.
1-6, 2023.
based encoder have been developed by using several design
logics such as CMOS, TG, and PT logic. Among these logics,
the 5-bit Flash ADC combined with a CMOS 2:1 multiplexer
encoder achieved the lowest power consumption with mini-
mum latency. This improved the Flash ADCs resolution with
lower the average power consumption. Future implentation,
the 5-bit Flash ADC can be optimized by implementing two
step Flash ADC for higher conversion speed. Also, the work
can be further extended using FinFET technology for superior
performance.

R EFERENCES
[1] P. Sowmya, M. Samson and M. J. Mehdi, “Design of Two Stage
Operational Amplifier and Implementation of Flash ADC,” 2021 Third
International Conference on Intelligent Communication Technologies
and Virtual Mobile Networks (ICICV), Tirunelveli, India, 2021, pp. 490-
496.
[2] B. Sri Pavan and V. P. Harigovindan, “Power-Optimized NOMA With
TXOP Tuning-Based Channel Access Scheme for IEEE 802.11ah Dense
IoT Networks,” IEEE Networking Letters, vol. 4, no. 4, pp. 179-183,
Dec. 2022.
[3] L. Rai, P. Kumar, N. Gupta and R. Gupta, “Design of an Ultra-Low
Power CMOS ADC using Threshold Inverter Quantization for Commu-
nication System,” 2022 International Conference for Advancement in
Technology (ICONAT), Goa, India, pp. 1-5, 2022.
[4] Mirza Nemath Ali Baig, Rakesh Ran, “Design and implementation of 3-
bit High-speed Flash ADC for wireless LAN Applications,” IJARCCE,
Vol. 6, 2017.
[5] N. Lotfi, P. Scholz and F. Gerfers, “The Fastest CMOS Single-Channel
5-bit Flash ADC Operating at 18.5 GS/s in 22 nm FD-SOI,” 2023 18th
European Microwave Integrated Circuits Conference (EuMIC), Berlin,
Germany, pp. 121-124, 2023.
[6] A. A. Talukder and M. S. Sarker, “A three-bit threshold inverter quanti-
zation based CMOS Flash ADC,” 2017 4th International Conference on
Advances in Electrical Engineering (ICAEE), Dhaka, Bangladesh, 2017.
[7] Sonu Kumar, Anjali Sharma, “Design of CMOS operational amplifier
in 180nm technology,” International journal of innovative research in
computer and Communication Engineering Vol.5, issue 4, Apr. 2017.
[8] M. K. Adimulam and M. B. Srinivas, “A 12-bit, 1.1-GS/s, Low-Power
Flash ADC,” IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, vol. 30, no. 3, pp. 277-290, March 2022.
[9] L. Raju Thoutam, G. Rajya Vardhini, K. Ramya, M. Neeraj, S. Raviku-
mar and J. Ajayan, “Design of Low Power 2-Bit Flash ADC using High
Performance Dynamic Double Tail Comparator,” 2022 IEEE Interna-
tional Conference on Nanoelectronics, Nanophotonics, Nanomaterials,
Nanobioscience & Nanotechnology (5NANO), Kottayam, India, pp. 1-
5, 2022.
[10] M. P. Ajanya and G. T. Varghese, “Thermometer code to Binary code
Converter for Flash ADC - A Review,” 2018 International Conference
on Control, Power, Communication and Computing Technologies (IC-
CPCCT), Kannur, India, pp. 502-505, 2018.
[11] Neil H.E. Weste, David Harris “CMOS VLSI Design,” Published 11
March 2010, ISBN:978-0-321-54774-3.
[12] G. Tretter, M. Khafaji, D. Fritsche, C. Carta and F. Ellinger, “A 24 GS/s
single-core flash ADC with 3 bit resolution in 28 nm low-power digital
CMOS,” 2015 IEEE Radio Frequency Integrated Circuits Symposium
(RFIC), Phoenix, AZ, USA, pp. 347-350, 2015.

Authorized licensed use limited to: Zhejiang University. Downloaded on March 19,2025 at [Link] UTC from IEEE Xplore. Restrictions apply.