SRI RAMAKRISHNA ENGINEERING COLLEGE

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Vattamalaipalayam, N.G.G.O. Colony Post, Coimbatore – 641 022.

DEPARTMENT OF ROBOTICS & AUTOMATION

ACADEMIC YEAR: 2024-2025

THIRD YEAR – VI SEM

20RA216 INDUSTRIAL IOT FOR AUTOMATION

ACTIVE LEARNING METHOD (ALM)

Case Study: A study on SPI Protocol For IOT

By
PRENESH G (7181210037)
SIDDHARTH B(71812210044)
SMITH V J(71812210045)

Course Coordinator [Link], AP([Link])/RA

 CASE STUDY : SPI Protocol for the IoT

Abstract— The Serial-Peripheral Interface (SPI) protocol is design this SPI so that the testing complexity can be reduced.
one of the important bus protocols for connecting with This system can be fabricated into a single chip. Verilog HDL
peripheral devices form microprocessor. The complexity of the is used for the coding of this system & designed, tested and
circuits has aroused with the enormous advancement of IC evaluated using the ISE 6.0 tool of Xilinx and VeriloggerPro
technology. So, in order to lessen the product failure self- For the design implementation the Xilinx Spartan-2 FPGA
testability in hardware is demanded a lot in recent times. The (XC2S150) .
necessity of self-testability will lead to a solution called Built- The SPI protocol architecture, implementation technique of
in-self-test (BIST). BIST is an effective solution to reduce the the system, circuit schematic and simulation results will be
huge circuit testing cost. This paper represents designing and discussed briefly in the following sections. The system demands
implementation of SPI protocol with BIST capability over of high integration, low bit error rate and low cost can be
FPGA. The need of programming for setting up a network with satisfied by this SPI.
two devices is no longer needed in this proposed system. To
2. SPI PROTOCOL ARCHITECTURE
accomplish compact, stable and reliable data transmission, the
SPI is designed with Verilog HDL language and synthesized In this paper, the SPI protocol implementation uses four
on Spartan 2 FPGA. An EEPROM and FPGA Spartan 2 are logic signals: SCLK, MOSI (Master Output-Slave Input),
used for the communication testing where the FPGA is master MISO (Master Input-Slave Output), SS (Slave Select).SCLK is
and EEPROM is a Slave. the clock, a unidirectional bus, which fed into the slave devices.
MOSI is defined as output from master which is also known as
serial data out. MISO is defined as output from slave which is
1. INTRODUCTION also known as serial data in. SS is an active low signal which is
SPI or Serial-Peripheral Interface is a worldwide accepted used to select the slave devices. A full duplex data transmission
standard communication protocol. SPI protocol was invented is occurred in SPI clock cycle. Fig. 1 shows the data transfer
by Motorola. SPI protocol is considered as one of the very best system of SPI.
among the systems that are connected to a number of devices
and make the communication smooth and fast. SPI as well as
others serial protocols such as I2C and 1-wire for instance, are
well fitted for data communications from integrated circuits for
low or medium data transfer speed to peripherals which are on
chip board .
Several works have been done using VHDL in designing
SPI. A comparison between SPI and I2C Implementation over
FPGA. On that paper, a comparative study of those two
protocols on FPGA platform is presented and the entire design
has been coded in VHDL. For various controlling purposes SPI
is implemented. SPI is presented for motion controller. FPGA
Implementation of SPI of FlexRay Controller.
This paper emphasizes on a new approach of designing SPI
with embedded BIST capability using Field Programmable
Fig. 1. Data Transfer Type of SPI.
Gate Array (FPGA) technology. Testing of a circuit has become
To transfer a data from master device to slave, there are three
increasingly tough as the scale of integration grows. SPI with
types of data formats required. Fig. 2 shows the data format of
the BIST capability provides the specified testability requisites
SPI protocol.
and lowest-price with the highest performance implementation.
Much lesser blocks and modules are used to
 2.1. Control Address
It is 8 bit data format. In the first 0 to 7 bits represent the
control bus. SPIE is interrupt enable signal which enable the
SPI interrupt flag. SPE is the bit for enabling SPI. DORD is
used to determine the data order. If DORD is 0 then LSB will
be transmitted first. MSTR is used to select the master or slave
mode. CPOL & CPHA are clock polarity & clock phase used
for determine the shifted edges of MISO & MOSI data. SPR1
& SPR0 are used to determine the clock rate. Fig. 3. BIST Structure.
2.2. Status Address Random Pattern Generators (RPG): Random Pattern
It is also 8 bit data format. In the 8 to 15 number bits Generator (RPG) generates random patterns which can be
represent the status bus. Here, SPIF is the bit used to determine used for the verification of device like SPI. The RPG is a part
the serial transfer. WCOL is for determine the collision of of the BIST in the verification of the circuits. Many methods
transfer. Bit 10 to 14 is reserved bit. SPI2X is used to double the have been proposed for the BIST equipment design . To
clock speed. produce bytes to test the circuit the method of a random pattern
generator (RPG) is used.
Data values are 8 bit long. In the 16 to 23 number bits represent
the data bus. These are the values which transmit from master This RPG consists of three LFSRs. LFSR 1 is used to generate
to slave and vise-versa. the control address. LFSR 2 produces status address. LFSR 3
gives the data. The generated bytes are used directly in the main
Control 0 1 2 3 4 5 6 7
SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 SPI to obtain better fault coverage. A comparator evaluates the
Status 8 9 10 11 12 13 14 15 response of the SPI with these bytes.
SPIF WCOL - - - - - SPI2X
Data 16 17 18 19 20 21 22 23
MSB - - - - - - LSB
Comparator: This is a comparator which is used to compare
the received and transmitted bit pattern. And then it gives the
Fig. 2. Format of SPI Protocol Bus.
value of error. If the comparator gives bit stream of 101 then
2.3. PROPOSED ARCHITECTURE the device is perfect and running good. If it gives 001 then there
The Proposed structure consists of two modes. One is BIST are some faults occur in the protocol.
mode where the SPI can test itself. Another is normal mode. In 2.4. SPI Structure
normal mode the device works like usual SPI protocol.
Data register is a shift register. Here, as the data goes from
BIST Module master to slave it is Serial Data Out (SDO) for master and Serial
Built-In-Self-Test (BIST) is a design technique where a Data In (SDI) for slave. And when the slave register is full, it
circuit can test itself. This technique can be easily used in starts to transmit data to master. And then SDO and SDI are
various devices like combinational and sequential logic, reversed. Master Clock Generator generates the clock and gives
memories, multipliers, and other embedded logic blocks. it to the slave. The Slave Select Decoder is a decoder controlled
Advanced chip or SOC design is incorporated with large by the control register. This slave select decoder selects the
number of core blocks. This is very much difficult to access slave devices when multiple peripheral devices are needed to be
these chips. So, it is a great challenge to test such embedded connected. Table I demonstrates the operating modes with reset
chips from outside. Some main challenges among them are the and reset_n signal. In the table it is seen that, BIST mode is on
extra testing equipment, cost of testing, level of testing and the when reset pin is set low i.e. 0 & reset_n is 1 and vice versa.
testing speed. All these main challenges can be solved by using
BIST. The main feature of the BIST system is it gives high
speed testing and it can be tested at different test levels.
Moreover, no expensive test equipment is needed. Since, BIST
is far cheaper than conventional system [5], [7].
Fig. 3 shows the structure of the SPI with BIST. The BIST
control signal controls the BIST module. In the BIST module,
there are four sub blocks. They are three random pattern
generators and a comparator.

Fig. 4. SPI Module Architecture.

 TABLE I. OPERATING MODES OF SPI The top level schematic of BIST module is shown. As
described earlier, BIST module consists of three LFSRs and one
reset_n reset BIST Mode NORMAL Mode comparator is depicted.

0 1 OFF ON

1 0 ON OFF

In Fig. 4 the architecture of SPI module is depicted. Here, it

is seen that the master is consists of five main modules. Here,
three registers are described broadly in previous section. The
slave select decoder is used to select the peripheral devices. The
two main modes are shown. It is shown that when reset = 1 and Fig. 6. Pin Diagram of SPI with BIST capability.
reset_n = 0, then normal mode begins and master starts to
communicate with its slave devices. Afterwards, when reset =
0 and reset_n = 1, then the BIST mode is turned on and the
circuit tests itself.

3. SYSTEM SYNTHESIZE & IMPLEMENTATION

Circuit Schematic

Fig. 5. Pin Diagram of SPI.

Fig. 7. Top level schematics of SPI with BIST Module.
TABLE II. Main SPI PIN DESCRIPTION TABLE III. SPI with BIST PIN DESCRIPTION

Pin IN/OUT Description

Pin IN/OUT Description CLK IN Clock generator
CLK IN Clock generator reset_n IN Control Bit for Normal & BIST
reset_n IN Control Bit for Normal & BIST Mode
Mode reset IN Control Bit for Normal & BIST
GO IN Control bit of the SPI Mode
enable IN Enables the Random Pattern
in_data IN Input data byte of the SPI
Generator
in_control IN Input control byte of the SPI GO IN Control bit of the I2C
in_address IN Input status address of the SPI SD_COUNTER OUT CLK pulse counter for BIST Mode
Out_data OUT Output Data byte of Master SPI_SCLK OUT Output pin for I2C CLK for BIST
SD_COUNTER OUT CLK pulse counter for BIST Mode Mode
SPI_SCLK OUT Output pin for SPI CLK SPI_SDAT OUT Output data bus for BIST Mode
SPI_SDAT OUT Output data bus bit_correct OUT Output pin of Comparator for
correct bits
SPI_SDI IN Input data bus
bit_error OUT Output pin of Comparator for
wrong bits
Simulation Results is 10101 then, the signature value should be 101 which mean no
error in the data. Afterwards, when the output stream changed
The timing diagrams are achieved from Testbencher
to 100101, there is an error occur. And the bit_error line goes to
(VeriLogger Pro 6.5). The design is tested in the Xilinx FPGA
001. So, form these two signature values, the error can be easily
where it also gave the correct output. In the timing diagram, the
tested. In this process, the efficiency and bit error rate of the SPI
8 bits of outputs are converted here into 2-digits Hexadecimal
can be self-tested.
numbers.
Table III. COMPARATOR OUTPUT FORMAT
Comparator Signature Value Hexadecimal
1) Simulation Results for BIST Mode
Output Value
a) LFSR 8-bit Random Bit Pattern Generator Bit_Correct 101 5
Bit_Error 001 1
Same type of outputs also come from the LFSR 2 and 3. These
ouputs from LFSRs are directly goes into the main SPI module. 2) Simulation Results NORMAL Mode

Depicts the output of the SPI bus at “NORMAL Mode”. When

the signal “GO” is high, the SD_Counter starts counting. The
Control address, Status Address and Data in hexadecimal are
“14”, “00” and “AA” respectively which are found in the SPI
bus as “00010100”, “00000000” and “10101010” respectively
when the “reset_n” and “SS” are low. By the SPI_SDAT line
it is clearly seen that, the given data are accurately obtained.
SD_Counter values from 3 to A represent the first 8 bits which
are control bits. Then 1 bit is left intentionally blank to reduce
the data collision. SD_counter values from C to 13 & 15 to 1C
are showed status address & data byte respectively.
Fig. 8. LFSR output.
Table IV. RECEIVER OUTPUT FORMAT
b) Comparator Module Output Input Binary Hexadecimal
Type
Control 00010100 14
Byte
Status 00000000 00
Address
Data 10101010 AA

Fig. 9. Comparator Output.

When the control, status and data bits are same as the output
data of SPI module, the bit correct signal form comparator
module is on. Here, the bit correct signature value is 101. In
case of an occurrence of an error in the output stream of SPI,
the bit_error signal is turned on then. The signature value of bit
error signal is set as 001. So, from SPI module, if the output
data

Fig. 10. Normal Mode Output Stream.

The serial data input into the master form slave. When the “SS” of slices is only 9% for main SPI module and it creeps to 13%
line goes high, that means there is no slave is selected. So, in case of SPI with BIST. The usage of input output buffers are
master is now receiving data form the slave. This data comes only 26% & 20% respectively. So that, there are many more
through the SPI_SDI data line. And the output is shown by the feathers can be added with the proposed architecture. In the
out data line. It is seen that the output data line is exactly timing summary, it is seen that the maximum delay for main
same as the SPI_SDI line. SPI module is 7.491ns which is much lesser than conventional
SPIs. In SPI with BIST, the delay is 7.782ns which is also
nominal. Actually, the maximum delay is depended upon the
Gate Delays. So, if the number of gates can be reduced, the
delay will be much smaller. In the proposed design, the logic
delay is 4.038ns and the route delay is 3.744ns. In future, we try
to reduce this logic delay as low as possible.

Table V. DEVICE UTILIZATION SUMMARY

Name Main SPI Module SPI with BIST
Used Blocks Percentag Used Blocks Percenta
es (%) ges (%)
Number of 18 out of 192 9 26 out of 192 13
Slices
Number of 19 out of 384 34 out of 384
Slice Flip (FDRE:7 4 (FDR: 3 8
Fig. 11. SPI When Master Receive Data (SS line goes high) Flops FDSE: 12) FDRE:28
FDSE :3)

B. FPGA Implementation Number of 33 out of 384 8 20 out of 384 5

4 input
Any logical function can be implemented by the Field LUTs
Programmable Gate Array (FPGA) and it should also be noted Number of 24 out of 90 18 out of 90
that FPGA design is more cost-effective than that of ASIC bonded (IBUF :7 26 (IBUF : 4 20
IOBs OBUF : 16 OBUF : 14)
Design. They have lots of advantages over microcontrollers,
OBUFT: 1)
such as greater speed, number of I/O ports and performance. Number of 1 out of 4 25 1 out of 4 25
GCLKs
The proposed design is implemented on Xilinx Spartan-2 Table VI. TIMING SUMMARY FOR MAIN SPI MODULE
FPGA (XC2S150). So here, the master device is Xilinx
Parameters Main SPI Module SPI with BIST
Spartan-2 FPGA. The slave device used here is EEPROM in Seconds Seconds
FPGA. Here, EEPROM means electrically erasable Minimum period 7.491ns 7.782ns
programmable read only memory. EEPROM is a non-volatile Minimum input arrival time 6.981ns 4.722ns
before clock
memory. It is used as a slave device to store small amounts of
Maximum output required 7.913ns 6.959ns
configuration information. time after clock
Maximum delay 7.491ns 7.782ns

4. CONCLUSION
In this paper, an FPGA based implementation of SPI with
BIST capability is presented. Here all the modules are designed
and simulated with Verilog HDL. Then the system is
downloaded in the Xilinx Spartan-2 FPGA (XC2S150). This
SPI is much more flexible, speedy, low cost, and stable with
respect to conventional one. This SPI control bus architecture
can enable the industrial fabrication of chip in a way where only
a pressing of one switch can test itself. So that, it would save
valuable time and cost of testing circuits significantly.
Fig. 12. FPGA Implementation of SPI Bus Protocol.

The Device utilization summary and timing summary are

given in Table V and Table VI respectively. Both the tables are
divided into two parts, Main SPI module and SPI with BIST
capability. From the Table V, it is seen that total number
RTL CLOCK GATING
The RTL clock gating is a technique which is used to control
power dissipated by clock net. In digital synchronous circuits
clock (net) is the main factor for dynamic power dissipation.
RTL clock gating reduces the unwanted switching on the
parts of clock net by disabling the clock [7].
Clock gating works by taking the enable conditions attached
to the registers and uses them to gate the clocks. Hence it is
required that a design must contain these enable conditions in
order to use clock gating. This clock gating process can also
save significant die area as well as dynamic power, since it
removes large numbers of multiplexers and replaces them
with clock gating logic. This clock gating logic is generally in
the form of "Integrated clock gating" (ICG) cells. [8][9].
RTL Clock gating logic can be added into a design in a
variety of ways:

1. RTL coding: Can be coded into the RTL code as

enable conditions that can be automatically RAM is used for storing the received and transmits data
translated into clock gating logic by synthesis tools. for SPI. Clock generator is used to generate the SPI clock
2. Manually inserting into the design by the designers according to the baud rate register and SPI is used for serial
(module level clock gating) by instantiating library communication.
specific ICG (Integrated Clock Gating) cells to gate
the clocks of specific modules or registers. RESULTS AND SIMULATIONS

3. Semi-automatically inserted into the RTL by

automated clock gating tools. [10].

It shows the proposed system overview of SPI- Switch

interface.
The system architecture consists of six blocks. The gated
clock block is used for reducing the dynamic power
consumption of the whole design. The data device selector is
used to select either RAM or Switch at a time for
communication with SPI. Switch is a 4-port device which is
used to program the SPI control register. It consists of 3
registers. Destination address registers gives the information
about the output ports of the switch.
There are 4 output ports of the switch. Last two bits of this
registers decides the output port. Then comes control register
which is used to control the 4-port switch operation and SPI
control register having bits namely CPOL, CPHA, LSBFE
and SPI-enable.

The whole design is synthesized on Lattice Diamond XP2

FPGA families i.e. LFXP2-5E, LFXP2-8E, LFXP2-17E and
LFXP2-30E for the calculation of area, dynamic power, total
dynamic power and power consumption by logic blocks.
The blue blocks are the main blocks i.e. data selector, SPI,
Switch and RAM. The blue lines are the input ports and wires
and orange lines are the output ports.
The Figures 4 shows the performance analysis of the non-
gated architecture on LFXP2-5E.
 Figure 6 Performance analysis of non-gated architecture on LFXP2-17E
device

Figure 4 Performance analysis of non-gated architecture on LFXP2-5E

device

Figure 5, 6 and 7 shows the performance analysis of non-

gated architecture on other XP2 FPGA families.

Figure 7 Performance analysis of non-gated architecture on LFXP2-30 E

device

The performance parameters to be taken under observation

are dynamic power (clock frequency, power supply and logic
blocks) and area (number of LUTs). Similarly the
performance analysis of the non-gated architecture is carried
out on LFXP2-8E, 17E and 30 E.
Figure 5 Performance analysis of non-gated architecture on LFXP2-8E
Table 1 show the area and power calculation of the design on
device different logic families.
Lattice Area(LUTs) Dynamic Total Power
FPGA Power ( Dynamic consumption
XP2 clock power (Logic blocks)
Family frequency) (Power W
mW supply)
mW
LFXP2- 197 4.2 39.9 0.1451
5E
LAXP2- 197 3.7 38.8 0.1482
8E
LAXP2- 197 3.7 39.0 0.1637
17E
LFXP2- 197 3.7 39.2 0.1758
30E

Fig.8 shows the hierarchal view of gated SPI-Switch

interface. The whole design is synthesized on Lattice
Diamond XP2 FPGA families i.e. LFXP2-5E, LFXP2-8E,
LFXP2-17E and LFXP2-30E for the calculation of area,
dynamic power, total dynamic power and power consumption
by logic block.

Figure 9 Performance analysis of gated architecture on LFXP2-5E

Figure 10, 11 and 12 shows the performance analysis of gated

architecture on other XP2 FPGA families.
The performance parameters to be taken under observation
are dynamic power (clock frequency, power supply and logic
blocks) and area (number of LUTs). Similarly the
performance analysis of the gated architecture is carried out
Figure 8 Hierarchal view of gated architetcure
on LFXP2-8E, 17E and 30 E.
In fig.8, blue blocks are the main blocks i.e. Gated clock, SPI,
Switch and RAM. The blue lines are the input ports and wires
and orange lines are the output ports.
The Figures 9 shows the performance analysis of the gated
architecture on LFXP2-5E.
 Figure 12 Performance analysis of gated architecture on LFXP2-30E
Figure 10 Performance analysis of gated architecture on LFXP2-8E
Table 2 shows the area and power calculation of the design
on different logic families.

Lattice Area(LUTs) Dynamic Total Power

FPGA Power ( Dynamic consumption
XP2 clock power (Logic blocks)
Family frequency) (Power W
mW supply)
mW
LFXP2- 179 3.9 30.4 0.1327
5E

LAXP2- 197 3.4 31.1 0.1376

8E

LAXP2- 197 3.4 31.4 0.1531

17E

LFXP2- 179 3.4 31.6 0.1651

30E