IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO.

9, SEPTEMBER 2014 4949

Design and Implementation of a High-Power-Factor

LED Driver With Zero-Voltage Switching-On
Characteristics
Hung-Liang Cheng, Member, IEEE, and Cheng-Wei Lin

Abstract—This paper proposes a novel light-emitting diode obtain smooth dc-link voltage for the following high-frequency
(LED) driver consisting of a buck-boost converter and a buck dc/dc converter. This kind of LED driver inevitably introduces
converter. Each converter adopts a power MOSFET as the ac- highly distorted input current, resulting in a large amount of
tive switch. With no need to use any auxiliary switches or snubber
circuits, both active switches can operate at zero-voltage switching harmonics and a low power factor. In order to prevent distort-
on (ZVS) by freewheeling the inductor current of the converters to ing the ac input source, standards of the harmonic regulation
flow through the intrinsic diodes of the MOSFETS. The buck-boost such as IEC61000–3–2 class C are enacted to limit the input
converter is operated at discontinuous-conduction mode (DCM) current harmonics and to guarantee a power factor of 0.9 at
to perform the function of power-factor correction to ensure al- least. In order to comply with the more stringent regulations
most unity power factor at the input line. The buck converter
steps down the output voltage of the buck-boost converter to drive on current harmonics and to improve the power factor, an addi-
LEDs. It could be designed to operate at either DCM or continuous- tional ac/dc conversion stage is required to cascade in front of
conduction mode. The detailed circuit operations and analysis are the dc/dc converter to perform the function of power-factor cor-
provided. A prototype 60-W LED driver was built and tested. Ex- rection (PFC). It leads to a two-stage approach which includes
perimental results show that the switching losses can be effectively a PFC semistage to shape the input current into a sinusoidal
reduced by operating the active switches at ZVS. The measured
power factor and circuit efficiency are as high as 0.99% and 93%, waveform and a dc/dc semistage to regulate the output volt-
respectively. age [8]–[12]. These two-stage approaches have the advantages
of good performance, fast output dynamic response, and easy
Index Terms—Buck-boost converter, buck converter, light-
emitting diode (LED), power-factor correction (PFC), zero-voltage control. However, they require two power-conversion processes
switching (ZVS). and are usually energy inefficient if the active switches operate
at hard switching. Recently, many single-stage ac/dc converters
have been developed [13]–[22]. These single-stage approaches
I. INTRODUCTION are derived by integrating the PFC converter and the dc/dc con-
verter. By sharing one active switch and the control circuit, the
ITH the advantages of small size, high luminous effi-
W ciency, long life time, fast response, and excellent color
rendering, light-emitting diodes (LEDs) have been widely used
single-stage converters have the advantages of less component
count and are cost-effective solutions.
Among these single-stage and two-stage approaches, the ac-
in many applications. As compared with fluorescent lamps those tive switches usually operate in hard switching, resulting in
require using mercury and may produce pollution, LEDs are high switching losses. The hard-switching operation precludes
environmental friendly devices. In pursuit of energy-saving and the application of higher switching frequency to realize the use
pollution-free light sources, LEDs have gradually replaced flu- of smaller magnetic components and capacitors. In order to im-
orescent lamps and been increasingly and widely used [1]–[7]. prove the circuit efficiency, some soft-switching technologies
For the LED drivers that utilize an ac input source, switching- should be applied to reduce the switching losses of the active
mode ac/dc converters are often adopted, since they have the switches. In the single-stage approaches, both current of the
advantages of high energy-conversion efficiency, high power PFC converter and the dc/dc converter flow through the shared
density, and high control accuracy. Traditionally, an ac/dc con- active switch. It is difficult to make the active switch operate
verter uses a diode-bridge rectifier and a bulky capacitor to at soft switching by creating a current loop for discharging
the energy stored in parasitic capacitance of the active switch.
On the other hand, since the two-stage approaches require two
power-conversion processes, soft-switching operation is even
Manuscript received May 5, 2013; revised July 17, 2013 and September 12, more essential for achieving high circuit efficiency. For reliev-
2013; accepted October 4, 2013. Date of current version April 30, 2014. This
work was supported in part by the National Science Council (NSC) of Taiwan,
ing the switching losses, various circuit using auxiliary switch
Taiwan, under Grant NSC 102-3113-P-214-001 and Grant NSC 102-2221-E- and/or snubber circuits are used [23]–[26]. However, they will
214-027. Recommended for publication by Associate Editor J. M. Alonso. add the circuit complexity and overall cost.
The authors are with the Department of Electrical Engineering, I-Shou
University, Kaohsiung 84001, Taiwan (e-mail: hlcheng@[Link];
To find a better solution, this paper proposes a novel two-
isu10001016M@[Link]). stage LED driver. It consists of a buck-boost converter and a
Color versions of one or more of the figures in this paper are available online buck converter. Both active switches can operate at zero-voltage
at [Link]
Digital Object Identifier 10.1109/TPEL.2013.2285560
switching-on (ZVS) to effectively reduce the switching losses.

0885-8993 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See [Link] standards/publications/rights/[Link] for more information.
4950 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 9, SEPTEMBER 2014

to achieve the PFC function, it should be designed to operate

at discontinuous-conduction mode (DCM). The buck converter
consisting of diodes D6 and DS 2 , an active switch S1 , an in-
ductor Lb , and a capacitor Co . It regulates the output voltage to
drive the LED string and can be designed to operate at either
continuous-conduction mode (CCM) or DCM. Operating a buck
converter at CCM has the advantage of small current ripple but,
it requires using an inductor of higher value than that at DCM
operation. Diode D6 is used to block the reverse current of Lb
and can be removed if the buck converter is designed to operate
at CCM. A small low-pass filter, Lm and Cm , is used to remove
the high-frequency current harmonics at the input line. For dim-
Fig. 1. Two-stage LED driver consisting of a buck-boost converter and a buck
converter.
ming operation, the active switch S3 is placed in series with the
LED string. S3 is controlled by the scheme of low-frequency
pulse-width modulation.
The active switches S1 and S2 are alternately driven by two
gated signals, vGS1 and vGS2 . They are nonoverlapping and
complementary rectangular-wave voltages with a short dead
time at the high switching frequency fs . The dead time is the
time interval when vGS1 and vGS2 are both zero. Neglecting the
short dead time, the duty cycle of vGS1 and vGS2 is 0.5.
For simplifying the circuit analysis, the following assump-
tions are made:
1) all the circuit components are ideal;
2) the capacitances of Cdc and Co are large enough, and
the dc-link voltage Vdc and the output voltage Vo can be
regarded as constant voltage sources.
Fig. 2. Proposed LED driver. The ac line-voltage source is given by
vin (t) = Vm sin (2πfL t) (1)
This paper is organized as follows. Section II shows the deriva-
tion of the proposed circuit topology and the discussion of the where fL and Vm are the frequency and the amplitude of the
circuit operation. Section III describes the detail circuit analysis. line-voltage source, respectively. Its rectified voltage can be
In Section IV, an illustrative design example and experimental expressed as follows:
results of a prototype circuit are presented. Finally, some con- vrec (t) = Vm |sin (2πfL t)| . (2)
clusions are given in Section V.
At steady state, the circuit operation can be divided into six
II. CIRCUIT CONFIGURATION AND OPERATION MODES modes in each high-frequency cycle. For simplifying the circuit
analysis, the low-pass filter and the diode rectifier (D1 −D4 ) is
Fig. 1 shows a two-stage LED driver. The first stage is a buck- represented by the rectified voltage vrec and the LED string is
boost converter to perform the function of PFC, and the second represented by its equivalent resistance RLED . Fig. 3 shows the
stage is a buck converter which steps down the dc-link voltage operation modes, and Fig. 4 illustrates the theoretical waveforms
to drive LEDs. Both active switches of the converters operate in each mode for the case of operating the buck converter at
at hard-switching condition and this results in high switching DCM. The circuit operation is described as follows.
losses. In order to achieve high circuit efficiency, this paper
proposes a novel LED driver, as shown in Fig. 2. The circuit A. Mode I (t0 < t < t1 )
topology is derived by relocating the positions of the semicon-
ductor devices in Fig. 1, and the inductor LP is replaced by a Prior to Mode I, S1 is on to flow the buck current ib . This
taped inductor, T1 . MOSFETs S1 and S2 are the bidirectional mode begins as soon as S1 is turned off. The current ib diverts
switches. Each switch is composed of a transistor and an antipar- from S1 to DS 2 . The voltage across the buck inductor is equal
allel diode. Here, the MOSFET’s intrinsic body diodes DS 1 and to −Vo and ib starts to decrease from a peak value
DS 2 are used as the antiparallel diodes. vb (t) = −Vo (3)
The proposed circuit is mainly composed of a buck-boost
Vo
converter and a buck converter. The buck-boost converter con- ib (t) = ib (t0 ) − (t − t0 ) . (4)
sists of diodes D5 and DS 1 , an active switch S2 , two coupled Lb
inductor Lp1 and Lp2 , and a dc-link capacitor Cdc . It serves At the same time, the voltage across the buck-boost inductor
as the PFC circuit by waveshaping the input current to be Lp1 is equal to the rectified input voltage vrec . Since the buck-
sinusoidal and in phase with the input line voltage. In order boost converter is designed to operate at DCM, the buck-boost
CHENG AND LIN: DESIGN AND IMPLEMENTATION OF A HIGH-POWER-FACTOR LED DRIVER WITH ZERO-VOLTAGE 4951

B. Mode II (t1 < t < t2 )

In this mode, S2 is on and ip1 is higher than ib . There are
two current loops. Parts of ip1 are equal to ib and flows through
D6 , Lb , Co , Lp1 and the line-voltage source, while the rest flows
through S2 , Lp1 and the line-voltage source. The voltage equa-
tions for vb and vp1 are the same as those in Mode I. The current
ib keeps decreasing. On the contrary, ip1 keeps increasing. If
the buck converter operates at DCM, the circuit operation en-
ters Mode III as soon as ib decreases to zero. If it operates at
CCM, the circuit operation enters Mode IV at the instant time
of turning OFF S2 .

C. Mode III (t2 < t < t3 )

The current ib is zero. S2 is kept at on stage and ip1 keeps
increasing. This mode ends at the instant time of turning off S2 ,
and the circuit operation enters Mode IV.

D. Mode IV (t3 < t < t4 )

At the beginning of this mode, ip1 reaches a peak value. In
Fig. 3. Operation modes. (a) Mode I. (b) Mode II. (c) Mode III. (d) Mode IV. order to ensure the buck-boost conversion operation, ip1 should
(e) Mode V. (f) Mode VI. be diverted from S2 and flows through Lp1 , Lp2 , D5 , and DS 1
to charge the dc-link capacitor Cdc when S2 is turned OFF. For
fulfilling this purpose, the voltage across the inductor Lp2 must
be higher than the amplitude of the input voltage to block the
current from the ac line source, i.e.,
 
N2 Vdc
|vp2 | = Vdc = ≥ Vm (7)
N1 + N 2 1 + 1/n
where N1 and N2 are the turn numbers of the coupled inductors,
and n is the turn ratio of N2 to N1 . By this way, the diode-bridge
rectifier is reverse-biased. Currents ip1 and ip2 will be equal
and flow through diode D5 . At the turning-off instant of S2 ,
the magneto-motive force in the coupled inductors should keep
balance in ampere-turns, hence
1 Vm |sin (2πfL t)|
ip1 (t3+ ) = ip1 (t3− ) = (t3 − t0 )
1+n (1 + n) Lp1
(8)
where ip1 (t3 – ) and ip1 (t3+ ) are the currents through Lp1 at the
instants right before and after S2 is turned OFF. As illustrated in
Fig. 4. Theoretical waveforms. Fig. 4, ip1 drops and ip2 rises dramatically at the switching-off
instant. The negative dc-link voltage is imposed on the coupled
current ip1 increases linearly from zero with a rising slope that inductors, and both ip1 and ip2 decrease linearly
is proportional to vrec
vp1 (t) + vp2 (t) = −Vdc (9)
vp1 (t) = vrec (t) (5)
Vm |sin (2πfL t)|
vrec (t) Vm |sin (2πfL t)| ip1 (t) = ip2 (t) = (t3 − t0 )
ip1 (t) = (t − t0 ) = (t − t0 ) . (6) (1 + n) Lp1
Lp1 Lp1
Vdc
In the initial stage of this mode, ib is higher than ip1 . Parts − (t − t3 ) . (10)
(1 + n)2 Lp1
of ib flow through DS 2 , while the rest of ib is equal to ip1 and
flows through Lp1 , diode bridge rectifier and the line-voltage Regarding operation of the buck converter, since DS 1 is on,
source. Since DS 2 is on, the voltage across S2 is clamped at the voltage across Lb is equal to Vdc − Vo and, ib rises linearly:
–0.7 V. After the short dead time, vGS2 becomes a high level.
However, S2 does not conduct current until the rising current vb (t) = Vdc − Vo (11)
ip1 becomes higher than the decreasing current ib and then, the Vdc − Vo
circuit operation enters Mode II. ib (t) = ib (t3 ) + (t − t3 ) . (12)
Lb
4952 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 9, SEPTEMBER 2014

In the initial stage of this mode, ip1 (ip2 ) is higher than ib .

Parts of ip1 flow through DS 1 to charge Cdc , while the rest of
ip1 is equal to ib and flow into the buck converter. Since DS 1 is
on, the voltage across S1 is clamped at –0.7 V. After the short
dead time, vGS1 becomes a high level. However, S1 does not
conduct current until the rising current ib becomes higher than Fig. 5. Conceptual waveform of ip 1 .
the decreasing current ip1 , and then the circuit operation enters
Mode V.
period, i.e.,

E. Mode V (t4 < t < t5 ) t3 − t0 = 0.5Ts (13)

In this mode, S1 is on and ib is higher than ip1 . There are two where Ts is the high-frequency switching period. Fig. 5 shows
current loops. Parts of ib are supplied from the dc-link voltage the conceptual waveform of ip1 . The peak values of ip1 follow
and the rest of ib is equal to ip1 and flow through Lp1 , Lp2 , and a sinusoidal envelope and can be expressed as follows:
D5 . The voltage and current equations for vp1 + vp2 , vb , ip1 , ip2 , |Vm sin (2πfL t)| Ts
and ib are the same as those in Mode IV. Both the currents ip1 ip1,p eak (t) = . (14)
2Lp1
and ip2 keep decreasing. The circuit operation enters Mode IV
when ip1 and ip2 decrease to zero. The rectified current irec is equal to the rising part of ip1
and zero elsewhere. The high-frequency contents of irec can be
F. Mode VI (t5 < t < t6 ) removed by the pass filter (Lm and Cm ). Therefore, the input
current iin is equal to the average of irec over a high-frequency
In this mode, S1 is remained at on stage and ib keeps increas- cycle, as follows:
ing linearly. This mode ends at the time when vGS1 becomes to  Ts
a low level to turn OFF S1 , and the circuit operation returns to 1 Vm T s
iin (t) = irec (t) · d (t) = sin (2πfL t) . (15)
Mode I of the next high-frequency cycle. Ts 0 8Lp1
According to the discussion of the operation mode, by divert- As comparing (1) and (15), it is noticed that the input current is
ing the current in one active switch to the antiparallel diode of a sinusoidal waveform and in phase with the input-line voltage.
the other one is what enables the active switches to achieve ZVS As a result, a high power factor is achieved. The input power can
operation. By this way, the antiparallel diode conducts current be determined by taking an average of its instantaneous value
prior to the transistor in each MOSFET. The voltage across the over one line-frequency cycle, as follows:
transistor is maintained at about –0.7 V when its antiparallel  2π
is on. This small voltage is negligible and the transistor can be 1 Vm2
Pin = vin (t) · iin (t) d (2πfL t) = . (16)
turned ON at zero voltage. It means that the turn-on switching 2π 0 16Lp1 fs
loss is effectively eliminated. Then, the output power can be calculated as follows:
ηVm2
III. CIRCUIT ANALYSIS Po = η · Pin = (17)
16Lp1 fs
Based on the circuit operation described in Section II, the where η represents the circuit conversion efficiency.
two converters in the proposed circuit operate as a buck-boost By substituting (13) into (10), the duration for ip1 to decrease
converter and a buck converter, respectively. Although the an- from the peak value to zero is given by
tiparallel diode of the active switch of one converter serves as
the freewheeling diode of the other converter, the features of the (1 + n) Vm |sin(2πfL t)| Ts
tp,off (t) = . (18)
buck-boost and the buck converter can be retained. Therefore, 2Vdc
the two converters can be analyzed separately. In order to operate the buck-boost converter at DCM,
tp,off (t) must always be less than half of the switching period
A. Buck-Boost Typed Power-Factor Corrector (1 + n) Vm sin(2πfL t)Ts Ts
tp,off (t) = < . (19)
In practice, the frequency of the line-voltage source fL is 2Vdc 2
much lower than the high switching frequency fs of S1 and S2 . From (19), Vdc should be designed to be high enough to
It is reasonable to consider the rectified input voltage vrec as ensure DCM operation over an entire input line-frequency cycle,
a constant over a high-frequency cycle. In the operation from as follows:
Mode I to Mode III, either S2 or DS 2 is on, the rectified voltage
Vdc > (1 + n) Vm . (20)
vrec supplies energy to raise the current ip1 . Since the buck-
boost convert is operated at DCM, ip1 raises from zero at the
B. Buck Converter
beginning of Mode I and reaches a peak value at the end of
Mode III. The rising time of ip1 is the sum of both on times of The on time of the buck converter is the interval from the
S2 and DS 2 , and is equal to half of the high-frequency switching beginning of operation Mode IV to the end of Mode VI. During
CHENG AND LIN: DESIGN AND IMPLEMENTATION OF A HIGH-POWER-FACTOR LED DRIVER WITH ZERO-VOLTAGE 4953

TABLE I
CIRCUIT SPECIFICATIONS

Fig. 6. Boundary curves of dc-link voltage versus transformer turn ratio

(V m = 155 V and V o = 216 V).

this interval, either S1 or DS 1 is on. Hence, the duty ratio of

the buck converter is also 0.5. As mentioned earlier, the buck
converter can designed to operate at either CCM or DCM. If it
is designed to operate at CCM, the inductance Lb needs to be TABLE II
VOLTAGE/CURRENT STRESS IN THE ACTIVE SWITCHES
large enough and meet [27]
 
1 − Db Ts RLED
Lb ≥ Ts RLED = (21)
2 4
where Db represents the duty ratio of the buck converter and
is equal to 0.5. The higher the Lb value, the lower the ripple
current of inductor current ib . If the buck converter is designed
to operate at DCM, ib rises from zero and will reach a peak
value at the end of operation Mode VI. Its peak value is equal
to
(Vdc − Vo ) TS
ib,p eak = . (22)
2Lb
The duration of the interval during which ib decreases from
the peak value to zero is given by TABLE III
CIRCUIT PARAMETERS
(Vdc − Vo ) TS
Tb,off = . (23)
2Vo
As can be seen in Fig. 4, ib is a triangular waveform in each
high-frequency cycle. Its average can be expressed as follows:
(Vdc − Vo )Vdc Ts
ib = . (24)
8Lb Vo
At steady-state operation, the average value of ib is equal to
LED current, as follows:
Vo
ib = . (25)
RLED
Combining (24) and (25), Lb can be calculated as follows:
(Vdc − Vo )Vdc Ts RLED
Lb = . (26) at a high-switching frequency of 50 kHz while the dimming
8Vo2 switch S3 operates at a low-switching frequency of 200 Hz. The
For fulfilling DCM operation, Tb,off as expressed in (23) rated voltage and current of the LED are 3.6 V and 0.28 A, re-
should be shorter than 0.5Ts . This leads to spectively. By the control scheme of low-frequency pulse-width
modulation, dimming operation is obtained by controlling the
Vdc ≤ 2Vo . (27)
duty ratio of the low-frequency switch while the LED forward
voltage is kept constant. For this reason, the LED equivalent
IV. DESIGN EXAMPLE AND EXPERIMENTAL RESULTS resistance can be calculated from the rated voltage and rated
An LED driver for 60 1 W white LEDs is illustrated as a de- current. In this design example, both converters are designed
sign example. Table I lists the circuit specifications. The input to operate at DCM. The design considerations are detailed as
voltage is 110 Vrm s ± 10%. Active switches S1 and S2 operate follows.
4954 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 9, SEPTEMBER 2014

Fig. 7. Control circuit.

Step 1: Determine transformer turn ratio n and dc-link voltage

Vdc . In order to meet the design goals of high-power factor and
ZVS operation of both active switches, the dc-link voltage Vdc
are constrained by (7) and (20). It is noted that Vdc is greater
than two times of the amplitude of the input voltage. The output
voltage of the buck converter is constrained by (27). Therefore,
it is required that the output voltage should be higher than the
amplitude of the input voltage. Using (7), (20), and (27), the
boundary curves of Vdc with respect to the transformer turn
ratio are obtained, as shown in Fig. 6. The color region can meet
the design requirement. It is noted that Vdc should be chosen to
be as low as possible to reduce the voltage stresses on the power
switches. In this design example, the turn ratio n and Vdc are
chosen to be
n = 1, Vdc = 350 V.
Fig. 8. Waveforms of ip 1 (ip 1 : 1 A/div and time: 2 ms/div).

Step 2: Calculate Lp1 and Lp2 . Assuming a circuit efficiency

of 92%, Lp1 and Lp2 are calculated by using (17) conventional buck-boost buck cascade topology. For simplifying
Lp1 = Lp2 = 0.46 mH. the comparison, the transient spikes of the current and voltage
are ignored. In the proposed circuit, either S1 or S2 is on. The
Step 3: Calculate Lb . Using (26), Lb is calculated to be maximum voltage across each switch is Vdc . As soon as turning
Lb = 1.94 mH. off S2 , the current ip2 flows to the antiparallel diode of S1 .
Hence, the maximum current stress on S1 is equal to the peak
Step 4: Determine Lm and Cm . Lm and Cm are used to filter value of ip2 . From Table II, it is noted that the voltage and
out the high-frequency components of the rectified current irec . current stresses on the active switches of the proposed circuit is
By rule of thumb, Lm and Cm are designed as a low-pass filter not significantly increased.
with a natural frequency lower than one-eighth of the switching A prototype circuit was built and tested. Table III lists the
frequency. Lm and Cm are determined to be circuit parameters. Fig. 7 shows the closed-loop control circuit.
For a single LED, a small variation in the forward voltage will
Lm = 2.0 mH, Cm = 0.47 μF.
result in a significant change in the LED current. In this paper,
Table II shows the comparison of voltage and current stresses 60 LEDs are connected in series. It requires more variation in
on the active switches between the proposed circuit and the the output voltage to result in the same amount of change in the
CHENG AND LIN: DESIGN AND IMPLEMENTATION OF A HIGH-POWER-FACTOR LED DRIVER WITH ZERO-VOLTAGE 4955

Fig. 9. Waveforms of v in and iin (v in : 100 V/div, iin : 1 A/div, and time: Fig. 12. Waveforms of ip 1 , ip 2 , and ib (ip 1 , ip 2 , ib : 2 A/div and time:
5 ms/div). 10 μs/div).

Fig. 10. Waveforms of V o and Io (V o : 100 V/div, Io : 0.1 A/div, and time:
5 ms/div).

Fig. 11. Transient response to step changes in line voltage (v in : 100 V/div, Fig. 13. Waveforms of v D S 1 , iS 1 , v D S 2 , and iS 2 at (a) the peak point and
V o : 5 V/div, and time: 50 ms/div). (b) the zero-crossing point of the input-line voltage (v D S 1 , v D S 2 : 200 V/div,
iS 1 , iS 2 : 2 A/div, and time: 5 μs/div).
4956 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 9, SEPTEMBER 2014

TABLE IV
LOSSES IN THE SEMICONDUCTOR COMPONENTS

Fig. 15. Voltage and current waveforms of LED string and the active switches
at duty ratio of 30%. (a) V L E D and Io (V L E D : 100 V/div, Io : 0.1 A/div, and
time: 2 ms/div) and (b) v D S 1 , iS 1 , v D S 2 , and iS 2 (v D S 1 , v D S 2 : 200 V/div,
iS 1 , iS 2 : 1 A/div, and time: 5 μs/div).

Figs. 8 and 9 show the waveforms of the buck-boost-converter

current and the input voltage and current in some line-frequency
cycles. It can be observed that the buck-boost converter operates
at DCM over an entire cycle of the line voltage. It is noted that the
input current is approximately sinusoidal and in phase with the
Fig. 14. Voltage and current waveforms of LED string and the active switches input voltage. The measured power factor is greater than 0.99,
at duty ratio of 70%. (a) V L E D and Io (V L E D : 100 V/div, Io : 0.1 A/div, and
time: 2 ms/div) and (b) v D S 1 , iS 1 , v D S 2 , and iS 2 (v D S 1 , v D S 2 : 200 V/div, and the total harmonic distortion (THD) is 5.2%. It complies
iS 1 , iS 2 : 1 A/div, and time: 5 μs/div). with the standards of IEC 61000–3–2 class C. Fig. 10 shows
the waveforms of the output voltage and output current, which
are well consistent with the design values.
LED current. Besides, the LED current is of pulsed waveform at From (16), the input power can be controlled by the switching
dimming operation. It is difficult and requires sophisticated cir- frequency to achieve a constant output voltage. The output volt-
cuit to precisely detect the peak value of the pulsed current. For age varies from 216.7 to 215.2 V when the input voltage varies
these reasons, the voltage regulation scheme instead of LED cur- from 120 to 100 Vrm s . The value of line regulation is calculated
rent regulation is used. The L6599 is a double-ended controller to be 7.5%. Fig. 11 shows the transient response to step changes
for driving the active switches of the half-bridge topology. Out- in line voltage. Since the buck-boost converter also plays the
put voltage regulation is obtained by modulating the switching role of first regulator to achieve a stable dc-link voltage with
frequency. The feedback signal of the output voltage is trans- low ripple, no significant voltage spike happens in the output
ferred to pin 4 of the L6599 via the phototransistor of the opto- voltage. The measured waveforms of ip1 , ip2 , and ib are shown
coupler PC817 to modulate the switching frequency. in Fig. 12. The experimental results are well in agreement with
CHENG AND LIN: DESIGN AND IMPLEMENTATION OF A HIGH-POWER-FACTOR LED DRIVER WITH ZERO-VOLTAGE 4957

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4958 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 9, SEPTEMBER 2014

Hung-Liang Cheng (M’08) was born in Chunghwa, Cheng-Wei Lin was born in Kaohsiung, Taiwan,
Taiwan, in 1964. He received the B.S., M.S., and in 1988. He received the B.S. and M.S. degrees
Ph.D. degrees in electrical engineering from the Na- in electrical engineering from I-Shou University,
tional Sun Yat-Sen University, Kaohsiung, Taiwan, Kaohsiung, Taiwan, in 2011 and 2013, respectively.
in 1986, 1988, and 2001, respectively. He is currently a Research Assistant with
From 1988 to 2007, he was an Electronic Re- the Department of Electrical Engineering, I-Shou
searcher with the Chung-Shan Institute of Science University. His current research interests include
and Technology, Taoyuan County, Taiwan, where he power electronic converters and their applications on
designed and developed high-power transmitters in lighting.
radar and missile systems. Since February 2007, he
has been with the Department of Electrical Engineer-
ing, I-Shou University, Kaohsiung, where he is currently an Associate Professor.
His current research interests include power-electronic converters and electronic
ballasts/drivers for lighting applications.