Vienna topology based active rectifier:

Modulation and loss calculation

Master of Science Thesis

VISHAL MATHUR

Department of Energy and Environment

Division of Electric Power Engineering
C HALMERS U NIVERSITY OF T ECHNOLOGY
Gothenburg, Sweden 2018
 Master’s thesis 2018:NN

Vienna topology based active rectifier:

Modulation and loss calculation

VISHAL MATHUR

Department of Energy and Environment

Division of Electric Power Engineering
Chalmers University of Technology
Göteborg, Sweden 2018
Vienna topology based active rectifier: Modulation and loss calculation
VISHAL MATHUR

© VISHAL MATHUR, 2018.

Department of Energy and Environment

Division of Electric Power Engineering
Chalmers University of Technology
SE-412 96 Gothenburg
Telephone +46 31 772 1000

Typeset in LATEX
Chalmers Bibliotek, Reproservice
Göteborg, Sweden 2018

iv
Abstract
Due to the increase in the usage of renewable energy sector, the demand for energy
has increased manifolds. With the increasing use of power electronic converter for
processing power, it has become vital to select the topology for any given applica-
tion. Rectifier market is huge because of its application as an active front end. So,
one important aspect in designing is to determine the losses at various levels because
of the efficiency constraint put forwarded by the end users.

In this thesis work an active rectifier using Vienna topology has been simulated
in MATLAB. For modulating the switching pattern for sinusoidal waveform, sine
triangle with third harmonic injection PWM technique is used. It gives a better
voltage utilization as compared to the regular sine triangle PWM. Based on the rat-
ing, the components are selected, and loss calculation is performed and is compared
with a two-level topology. 25 kW input power and 700 V DC link voltage are used
in both cases. Considering only the semiconductor losses, the efficiency at the rated
power is 97.9% for the two level converter and 99.2% for the Vienna rectifer.

Keywords: Vienna rectifier, PWM modulation, Active front end, Third Harmonic
Injection.

vi
Acknowledgements
I humbly acknowledge the help that was extended to me by my Examiner at Chalmers,
Prof. Ola Carlson. Thank you so much for allowing me to do this project work under
your guidance. Special thanks goes to Prof. Torbjörn thiringer for the kind support
given by him every time I needed it.
My heartfelt gratitude to my parents who in-spite of the odds stood by me no matter
what came my way. To my father for guiding me at every step that I took, and
to my mother Dr. Raj Mathur for everything beyond. Special thanks goes to my
sister,brother in law and my sweet niece for their support and kindness.

Vishal Mathur, Göteborg, 2018

viii
x
 Contents

1 Introduction 1
1.1 Problem Background . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Theory 3
2.1 Operation of a two Level converter . . . . . . . . . . . . . . . . . . . 3
2.2 Operation of the VIENNA rectifier . . . . . . . . . . . . . . . . . . . 4
2.3 Modulation techniques for PWM converters . . . . . . . . . . . . . . 7
2.3.1 Sinusoidal PWM . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3.2 PWM with third harmonic injection (THI) . . . . . . . . . . 9
2.4 Loss calculation and component selection . . . . . . . . . . . . . . . . 11
2.4.1 IGBT power losses . . . . . . . . . . . . . . . . . . . . . . . . 11
[Link] Conduction power losses . . . . . . . . . . . . . . . . 11
[Link] Switching power losses . . . . . . . . . . . . . . . . . 12
2.4.2 Diode power losses . . . . . . . . . . . . . . . . . . . . . . . . 13
[Link] Conduction power losses . . . . . . . . . . . . . . . . 13
[Link] Switching power losses . . . . . . . . . . . . . . . . . 13

3 Case-Setup 15
3.1 Loss calculation for a two level converter . . . . . . . . . . . . . . . . 15
3.1.1 Current waveform . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.2 On state loss calculation . . . . . . . . . . . . . . . . . . . . . 17
3.1.3 Switching loss calculation . . . . . . . . . . . . . . . . . . . . 17
3.2 Loss calculation for three level Vienna converter . . . . . . . . . . . . 18
3.2.1 Current waveform . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.2 On state loss calculation . . . . . . . . . . . . . . . . . . . . . 20
3.2.3 Switching loss calculation . . . . . . . . . . . . . . . . . . . . 20

4 Result and Future work 21

4.1 Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1.1 Loss Analysis of a two level converter . . . . . . . . . . . . . . 21
4.1.2 Loss Analysis of the Vienna rectifier . . . . . . . . . . . . . . 23
4.1.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Bibliography 27

xi
Contents

A Appendix I
A.0.1 Analytical equations for currents used in Vienna rectifier for
loss analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
A.0.2 Matlab file for Vienna rectifier . . . . . . . . . . . . . . . . . . I

xii
 1
Introduction

1.1 Problem Background

Power electronic converters depending upon their usage may exhibit characteristics,
which in turn affects the power quality of mains supply in terms of low power factor
and harmonic distortion. Such behaviour imposes a penalty on the users of these
converters by the grid supplier. Using active front end rectifier is a common practice
to overcome this problem. The most common topology in use is a two level active
rectifier, which is relatively simple and robust and therefore its use is widespread.
But, the distorting effect it has on the grid supply is quite significant and somehow
does not provides a solution. It further needs a filter that can limit the current
distortion by capturing the lower harmonics locally. This increases the size of the
components as well as the cost of installation.

To overcome this problem, the use of multilevel converter as active front end (AFE)
is becoming increasingly popular. This reduces the harmonic content of current at
input side, thereby giving it a more sinusoidal shape. Moreover switching at higher
frequency becomes feasible which in turn reduces the size and cost of the components
required, thereby making the converter more compact.

1.2 Previous Work

The usage of active front end rectifiers is not a new notion, but nevertheless an on-
going and rapidly developing field. Extensive work has already been done involving
novel circuits and devices with very interesting results. Many practical aspects are
considered depending upon the constraints that may be relevant for a particular ap-
plication from the user’s end. Vienna topology has been used in power scale ranging
from few kW’s to MW for power system for different scenarios. As it constitutes
the very first step towards the multilevel behaviour as compared to the conventional
two level topology with less switching devices, it becomes an interesting proposition
to carry out its study.

1
1. Introduction

1.3 Purpose
The goal of the work undertaken in this thesis is to implement a model of an active
rectifier based on MATLAB simulation using a three level Vienna topology for de-
termining the semiconductor losses. Thereafter, a comparison is done based on the
loss calculation between the two and three level converters.
The conventional two level rectifier utilizes six switches. The Vienna rectifier uses
three switches and outputs a three level characteristics of phase voltage. It has
a sinusoidal mains current at the input along with low common mode signal and
displays ohmic mains behaviour. By comparison it can be shown that the Vienna
rectifier has got greater advantage in terms of losses over the two level topology.

2
 2
Theory

Three phase rectifiers are commonly used in several applications including drives,
uninterrupted power supplies and various utility interfaces. Since a few decades the
surge in renewable energy sector has increased the interest for research in develop-
ment of power electronic systems. Various topologies exists today depending upon
requirements and applications. As the main concern of this work is with a unidi-
rectional power flow i.e: conversion from AC to DC side, the unidirectional Vienna
topology is chosen.

As described in [1][3][4], a unidirectional three phase/switch/level PWM rectifiers

has the following advantages as compared to a two level conventional rectifier:
*Lower harmonic level of the mains current.
*Lower blocking voltage stress on semiconductor devices.
*Less number of active switches (topology a)
*Higher power density.

However, the controlling complexity is higher compared to a two level topology, as

the capacitive centre point balancing of the output voltage requires a symmetrization
of output voltages, which would be analysed at a later stage.

The chapter herein presents the description of a unidirectional three phase/level/wire

PWM rectifier circuit structure along with its operation. The two different topolo-
gies of the Vienna structures are given along with the rectifier voltage equations.
Secondly, the space vector modulation is explained and the limitation associated
with its operation is considered. The DC link neutral point potential is also dis-
cussed as it has got a direct relevance with the modulation method employed.

2.1 Operation of a two Level converter

Two level converters are widely used in power conversions within a wide range of
power levels. The market domination of such converters have remained strong spe-
cially in the low voltage range of 690 Vrms line to line voltage for IEC and 575 Vrms
line to line for ANSI standard[12]

3
2. Theory

Figure 2.1: Two level converter

As shown in the Figure 2.1, the conventional two level VSC topology consists of
six switches and corresponding six anti parallel diodes attached to each of them. It
functions in all the four quadrants. For explanation consider the first leg connected
to phase A. When the voltage and current are positive the switch S1 conducts
and the current flows to the DC link at the output. When the current is positive
but the voltage is negative i.e because of the PWM action where the reference is
compared with carrier wave, lower diode D2 conducts, as the current cannot change
direction immediately on account of the inductor present at the input. Similarly,
when the current is negative and the voltage is positive, the upper diode D1 conducts,
maintaining the flow of the current. When both voltage and current are negative,
the lower switch S2 conducts. It should be noted that both the upper and lower
switches have complementary switching states.
It can be seen that the voltage stress on the semiconductor switch and diode in
blocking state is equal to the DC link voltage. The voltage that appears across
the switches is from Vdc/2 to -Vdc/2, thereby giving a two level waveform of phase
voltage at the converter side.
The simplicity and ruggedness of this topology has played important role as to its
widespread usage for different applications. It has some drawbacks such as over-
voltages when connected to cables, inferior harmonics spectrum and problem with
higher common mode voltages as comapred to a multilevel topology [12]

2.2 Operation of the VIENNA rectifier

There are different ways of constructing a three level PWM rectifier according to
the literature review[1][2][4][6][7]. The difference can be seen in the switch configu-
ration which basically has a bidirectional nature, but facilitating the same operation
required for rectification. Hence, the analysis presented for the conventional three
switch rectifier holds true irrespective of topology used. Figure 2.2 (a) shows the
structure of the Vienna rectifier having three switches (b) Structure that makes use
of six switch.

4
 2. Theory

Figure 2.2: Vienna topology (a) Conventional three Switch (b) Six Switch

The diodes Dar (1, 2) should be fast recovery diodes operating at switching frequency.
the maximum voltage stress across them is Udc /2. The diodes Da (1, 2) operates at
mains frequency and the voltage across them and the Switch S1, S11 as well as S12
is Udc /2. Despite the high frequency operation of the switching diodes Dar (1, 2) the
active switch is always blocking the voltage. When Switch S1 is in on state, diodes
Da 1 and Da 4 conducts for the positive half cycle, likewise Da 3 and Da 2 conducts
during the negative half cycle. This leads to a higher conduction losses as compared
to the second topology shown in figure 2.1(b) wherein the absence of the diodes on
the right hand side of the switch results in lower conduction and switching losses,
thereby increasing the efficiency. On this account the second topology is preferred.
Vienna rectifier obtains three level phase input characteristics with one active switch
defined by the switching function SW(a,b,c) = (1, 0) where 1 and 0 indicates switch
in ON and OFF state respectively. This combination would be used to denote the
switching instances on phase specific basis. e.g. SW = SWa , SWb , SWc wherein
SWa = 0, SWb = 0, SWc = 1, gives SW = (0 0 1). For analysis purpose, it is
assumed that the three phase system is balanced with no neutral point connected.

5
2. Theory

When phase currents ir(a,b,c) are positive and the switches are in OFF state, the
diodes D(a,b,c)1 and D(ar,br,cr)1 connect the input to the positive bus of the DC link.
Similarly, when the input current is negative the diodes D(a,b,c)2 and D(ar,br,cr)2 con-
nects them to the negative bus of the DC link. When switches S(1,2,3) are on, diodes
Da (1, 4) Db (1, 4) and Dc (1, 4) conduct thereby connecting the phase input to the
DC link neutral point M. Likewise, when the current is negative and switches are in
ON state, Da (2, 3) Db (2, 3) and Dc (2, 3) conduct. This shows that the operation is
dependent on the state of switch as well as the direction of the phase input current.

Figure 2.3: Rectifier input current ia > 0, ib < 0, ic < 0. the arrow mark shows
the direction of input phase and neutral point current

An example of current paths for a particular case of current directions ira > 0, irb <
0, irc < 0 is shown in fig(2.2).This case gives a total of 23 = 8 switching combinations[1].

6
 2. Theory

(1 1 1) and (0 0 0) are two combinations that do not induce a neutral current at

point M. There exists only one zero state given by (1 1 1) as compared to the two
level SVM, where the zero states are given by both (0 0 0) and (1 1 1) as given in
[1]. The neutral point current is given as

iM = swa .ira + swb .irb + swc .irc (2.1)

iC1 = I+ − iload (2.2)

iC2 = iC1 + iM (2.3)

It can be observed that the magnitude of iM is always equal to one of the phase
currents [1].

Figure 2.4: Midpoint neutral current along with the direction of positive and
negative current

2.3 Modulation techniques for PWM converters

There exists various modulation schemes for obtaining a sinusoidal switching pattern
as described in [1][2][6]. A brief explanation about the commonly used modulation
techniques is given in this sub-chapter. However the loss calculation in the upcoming
chapter is analyzed based on third harmonic injection technique (THI).

2.3.1 Sinusoidal PWM

Sinusoidal PWM (SPWM) is a basic method of modulation in which the gate
pulses are generated by comparing the reference signal having fundamental fre-
quency ω0 = 2πf0 with a fixed triangle wave having ωC = 2πfC as carrier frequency
[6]. The three phase reference voltages and currents as shown in Figure 2.4 are given

7
2. Theory

as

vA∗ = V0 sin(ωt) (2.4)

2π
vB∗ = V0 sin(ωt − ) (2.5)
3
4π
vC∗ = V0 sin(ωt − ) (2.6)
3
i∗A = I0 sin(ωt) (2.7)
2π
i∗B = I0 sin(ωt − ) (2.8)
3
4π
i∗C = I0 sin(ωt − ) (2.9)
3
For a two level three phase voltage source converter (VSC) there are two switches
∗
present in each phase arm. When VA,B,C > VCarrier the switch is set in ON state,
∗
which logically is 1, and when VA,B,C < VCarrier the switch is set in OFF state defined
as 0. The gate state of the upper and lower switches in each arm is complementary.
i.e if the upper switch is 1, the lower would be 0. The modulation index is a ratio of
peak phase voltage to peak carrier triangle wave. It can also be expressed in terms
2Vpeak
of the DC output voltage and phase voltage as M = VDC , where Vpeak is the peak
value of the phase voltage.

Figure 2.5: Three phase reference voltages and currents

8
 2. Theory

Figure 2.6: Reference voltages with triangle wave for SPWM for M=1

The wave-forms in Fig(2.5) shows the reference voltages along with a carrier wave,
having modulation index M as one. The range of M for SPWM is from zero to one,
where values lesser than one is known as under-modulation and values exceeding
one is called over-modulation. It must be emphasized that the value of modulation
index is important as in under-modulation the output voltage would be reduced
below the required level needed. On the other hand over modulation may cease the
switching and the corresponding switches remain in ON state within this carrier
time period, resulting in the saturation of the reference voltages. This saturation
leads to reduction in the voltage gain, as the average reference voltage per carrier
cycle cannot be matched with the converter[7].

2.3.2 PWM with third harmonic injection (THI)

The main disadvantage of SPWM is that the DC bus utilization is not optimal as
compared to other modulation techniques available such as space vector modula-
tion (SVPWM). The modulation index could be further increased to 1.15 from 1 by
injecting a third harmonic sequence[2][7]. There are different available techniques
such as Min/Max, where the mean of maximum and minimum values of the volt-
ages is subtracted from the corresponding waveform, thereby improving the voltage
utilization of the DC side. The other way is by adding third harmonic signal (3ω0 )
having one-sixth of the fundamental magnitude, thereby increasing the modulation
index to 1.15.
∗ V0
vA,B,C = V0 sin(ωt ± φ) + sin(3ωt) (2.10)
6
9
2. Theory

Figure 2.7: Reference voltages with third harmonic injection for M=1

Figure 2.8: Reference voltages with third harmonic injection for M=1.15

10
 2. Theory

As shown in Fig(2.6) after addition of the third harmonic sequence, the reference
voltages do not reach the peak of the carrier wave for modulation value of 1. By
increasing M to 1.15 it can be seen from Fig(2.7) that the reference voltages reaches
the peak of the carrier, thereby maximizing the DC link utilization.

2.4 Loss calculation and component selection

Power loss calculation of switching devices in converters is important as it predicts
the system efficiency and provides a reference for thermal management[8]. Two main
type of losses are the conduction and switching losses, which would be analyzed for
IGBT and diodes. Leakage losses are not considered here for the sake of brevity.

2.4.1 IGBT power losses

The IGBT conduction and switching losses are determined from the data sheet of
the device manufacturer the method described in the following section is used for
the respective loss analysis.

[Link] Conduction power losses

Equivalent circuit of an IGBT during on state comprises of two elements connected

in series, a temperature dependent resistor and a DC voltage source as depicted in
the Fig(2.8)

Figure 2.9: Equivalent circuit of an IGBT in on state

(U0 ) and (RI ) are the zero current voltage depicted as (VCEO ) and the on state
resistance respectively at a given temperature that can be obtained from the voltage
characteristics of the IGBT [8]. The instantaneous conduction losses can thus be
given as
PC (t) = UO iC (t) + RI i2C (t) (2.11)

11
2. Theory

Integrating the above equation over one switching time period Tsw gives the average
conduction loss.
1 Z T sw
PC , avg = (U0 ic (t) + RI i2c (t))dt. (2.12)
T sw 0
2
PC , avg = Irms .RI + U0 .Iavg (2.13)

The conduction losses in a PWM converter depends on power factor (φ) as well as
modulation index M. The conduction loss for a single IGBT using PWM (THI) is
explained in[10][11] and can be expressed as

1 π 2 1 M M3
PC,T HI = U0 .Ipeak ( + .[Link]φ) + RI .Ipeak ( + .cosφ − .cos3φ) (2.14)
2π 8 8 3π 15

where M3 is the amplitude of third harmonic and is selected as 1/6 for improving
DC link utilization[10][11].

[Link] Switching power losses

The switching energy losses Eon and Eof f can be determined from the plots given
in the data sheets by the manufacturer. These parameters are proportional to the
current iC and off state voltage Udc across the IGBT [8][9]. The instantaneous value
of the Energy losses are given as

Udc ic
Eon = . .Eon,ref (2.15)
Uref Iref

Udc ic
Eof f = . .Eof f,ref (2.16)
Uref Iref
The average value can be determined by integrating (2.15) and (2.16) over one time
period as
1 Z π Udc ic
Eon,avg = . .Eon,ref .dωt (2.17)
2π 0 Uref Iref
√
2 Udc Irms
Eon = . . .Eon,ref (2.18)
π Uref Iref

1 Z π Udc ic
Eof f,avg = . .Eof f,ref .dωt (2.19)
2π 0 Uref Iref
√
2 Udc Irms
Eof f = . . .Eof f,ref (2.20)
π Uref Iref
The total switching losses can be given as

Psw = (Eon + Eof f ).fsw (2.21)

12
 2. Theory

2.4.2 Diode power losses

[Link] Conduction power losses
The conduction loss calculation of a diode is similar to that of an IGBT, as shown
in Fig(2.9) and is given as
2
PC , avg = Irms .RD + U0 .Iavg (2.22)

Figure 2.10: Equivalent circuit of a diode in on state

Similar to the IGBT conduction losses with third harmonic injection, the loss is
given as [10][11]
1 π 2 1 M M3
PC,T HI = Vf .Ipeak ( − .[Link]φ) + RD .Ipeak ( − .cosφ + .cos3φ) (2.23)
2π 8 8 3π 15

[Link] Switching power losses

The switching losses in a diode is mainly caused by the reverse recovery charge
during the turning off, as the turn on loss is negligible [9]. Err is determined from
the datasheet and the procedure is same as that of Eof f and Eon .
Udc if
Err = . .Err,ref (2.24)
Uref Iref
1 Z π Udc if
Err,avg = . .Err,ref .dωt (2.25)
2π 0 Uref Iref
√
2 Udc Irms
Err = . . .Err,ref (2.26)
π Uref Iref
Many of the data sheets contains the reverse recovery charge and the current, an
empirical equation according to [9] is used to calculate the switching energy.
1
Err = .Qrr .Udc (2.27)
4

13
2. Theory

14
 3
Case-Setup

The parameters for simulation and analytical calculation are given for a particular
case as mentioned.

P owerinput = 25kW
V oltageinput,LL = 400V
V oltageDC = 700V
F requencysupply = 50Hz
F requencysw = 20kHz

For the sake of analysis it is assumed that the phase angle φ between supply voltage
and current is zero i.e no inductor is connected at the converter side and also,
no capacitor was taken into account at the output side either. The modulation
technique employed here is PWM with third harmonic injection (THI).

3.1 Loss calculation for a two level converter

Considering the input voltage of 400 V, and the power rating of 25kW, the current
is calculated for component selection from (3.1)(3.2)(3.3)

Pac = [Link],ph .Irms .cosφ (3.1)

[Link],peak
M= (3.2)
Udc

Irms = 29.3A (3.3)

For component selection the peak value has to be considered which gives Ipeak equals
to 41.5 A. Calculation is done for M= 1.15. The IGBT and diodes would be subjected
to a peak stress of 700V DC with 41.5 A current.

15
3. Case-Setup

Phase-A
300
Ref-A
200
Converter voltage(V)

100

-100

-200

-300

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Time(ms)
Figure 3.1: Two level phase voltage waveform

line to line -AB

600

400
Line voltage(V)

200

-200

-400

-600

8.2 8.25 8.3 8.35 8.4 8.45

Time(ms)
Figure 3.2: Three level line to line voltage waveform

16
 3. Case-Setup

3.1.1 Current waveform

Figure 3.3: Two level diode and switch current waveform

As shown in Fig.(3.3) the chopped current waveform of the 2L-converter. The case
setup is run for one fundamental cycle of 50Hz. The average and RMS values of the
IGBT current are 12.46A and 20.33A respectively. Whereas for diode average and
RMS values are 0.71A and 3.86A respectively.

3.1.2 On state loss calculation

Based on the requirement a 1200 V, 50 A infineon make IKY50N120CH3 IGBT with
anti-parallel diode is selected.

For IGBT,the on state voltage drop VCEO and the on-state resistance rC are taken
for reference value’s of 50 A at 175◦ C. This gives VCEO =0.8V and rC =0.03 Ω from
the slope of the datasheet.

For diode, the forward voltage drop and the onstate resistance are found to be 1.2V
and 15mΩ respectively, as can be calculated from the datasheet.

3.1.3 Switching loss calculation

The parameters needed for calculating the switching losses for an IGBT are the
on and off energies calculated for the base case as taken in the conduction loss
calculation. From the data sheet the values for Eon and Eon are found out to be
4.3 mJ and 4 mJ respectively. The diode reverse recovery charge Qrr is calculated
for the DC voltage of 700 V, and is 8.8 µC. From this, the reverse recovery energy
could be calculated using equation (2.27) and is found to be 1.54 mJ.

17
3. Case-Setup

3.2 Loss calculation for three level Vienna con-

verter

As explained in the theory chapter, the peak voltage stress experienced by the IGBT
and diodes in half leg of the phase is half of the DC link voltage. So, for this case
the voltage stress experienced by the devices would be 350 VDC which is half of
the DC link voltage for the test setup. The peak current remains same at 41.5 A
current. Based on the requirement 600 V infineon make IGBT IKW50N60H3 with
anti parallel diode is selected. For the sake of brevity, the same kind of diode is used
at the grid side as well as for the high switching connected to the DC link. A 600
V 50 A, Infineon make IDW50E60 diode is selected [15]
Fig(3.3) and (3.4) shows the phase voltage and line voltage at the converter side
respectively. The three level characteristics could be seen for phase voltage where
for this particular setup, the levels obtained are +350,0,-350. The line to line voltage
shows a five level characteristic

400

Phase A
300
Ref-A
200
Converter voltage(V)

100

-100

-200

-300

-400
9.5 9.6 9.7 9.8 9.9 10 10.1 10.2 10.3
Time (ms)
Figure 3.4: Three level phase voltage waveform

18
 3. Case-Setup

800

Line to line -AB

600

400
Line voltage(V)

200

-200

-400

-600

-800
0 5 10 15 20
Time (ms)
Figure 3.5: Three level line to line voltage waveform

3.2.1 Current waveform

Figure 3.6: Diode and switch current waveform for Vienna rectifier

Fig.(3.6) shows the current waveform of the 3L-Vienna rectifier for one fundamental
cycle of 50Hz. The average and RMS values of the IGBT current are 1.29A and
4.99A respectively. Whereas for diode Dar1 average and RMS values are 11.88A and

19
3. Case-Setup

20.09A, whereas for Da1 , the average and RMS are 13.18A and 20.7A respectively.
The values are based on simulation. The analytical values obtained from [3][4] are
found to have a good match except the RMS value for the IGBT, which is 3.19A as
compared to 4.99A by simulation [A.0.1]

3.2.2 On state loss calculation

As explained in the case of a two level converter, the two parameters needed for on
state loss calculation are taken from the data-sheet given in the appendix. Zero cur-
rent on state voltage drop and the on-state resistance are chosen for reference value’s
of 50 A at 175◦ C which are 0.9V and 20mΩ respectively for IGBT. For diode, the
forward voltage drop and the on-state resistance are found to be 0.45V and 10mΩ
respectively, as can be calculated from the data-sheet given in reference[13]

3.2.3 Switching loss calculation

The values of EON , EOF F and Qrr found for the reference values of 400 V and 50 A,
are 1.42mJ , 1.13mJ and 8.8 µC respectively. This gives Err to be 0.358 mJ. The
datasheet is as given in reference[14]

20
 4
Result and Future work

4.1 Plots
In this chapter the loss calculation for both the converters are presented and analyzed
for the base case. The results and figures plotted are based on one leg/per phase
due to the symmetrical nature of operation of the other legs.

4.1.1 Loss Analysis of a two level converter

Figure 4.1: Instantaneous conduction losses of IGBT

Simulation was done keeping the value of modulation index M a at 1.15, so as to

optimally utilize the DC link voltage. The instantaneous values of the conduction
losses per phase for the upper and lower IGBT’s, has been depicted in Fig 5.1, the
nomenclature followed for the components is as shown in Fig.2.1. It can be seen
that the peak value for the IGBT loss is 84.5W.

21
4. Result and Future work

Table 4.1: On state loss calculation using matlab model at 20kHz

On state losses in Watts Net loss (Watts)

S1 S2 D1 D2 First leg
22.3 22.3 1.08 1.08 46.76
S3 S4 D3 D4 Second leg
22.3 22.3 1.08 1.08 46.76
S5 S6 D5 D6 Third leg
22.3 22.3 1.08 1.08 46.76
Net conduction losses 140.28 W

Figure 4.2: Instantaneous conduction losses of diodes

The component wise values of the conduction loss taken over once fundamental
cycle i.e average, is given in Table 5.1. Using (2.14) the conduction loss calculated
analytically is given by
1
PC,T = VCEO .Ipeak ( 2π + π8 .[Link]φ) + RI .Ipeak
2 M
( 81 + 3π 1
.cosφ − 90 cos3φ) = 22.2W
The on state loss obtained using Matlab model in table 5.1 gives PC,T HI = 22.3 W.

The analytical onstate loss for a diode is calculated using (2.23) to be

1
PC,D = VF .Ipeak ( 2π − π8 .[Link]φ) + RI .Ipeak
2 M
( 18 − 3π 1
.cosφ + 90 cos3φ) = 1.1W
The on state loss obtained using Matlab model gives PC,D = 1.08W.
This shows a very good match between the analytical as well as simulated loss
behaviour.

22
 4. Result and Future work

Table 4.2: Switching loss calculation using matlab model at 20kHz

Component wise switching

Losses (Watts)
losses breakdown
S1 S2 D1 D2 First leg
53.8 53.8 8.9 8.9 125.4
S3 S4 D3 D4 Second leg
53.8 53.8 8.9 8.9 125.4
S5 S6 D5 D6 Third leg
53.8 53.8 8.9 8.9 125.4
Net switching losses 376.2 W

The average value of the switching losses over one fundamental cycle using the
matlab model of the converter is given in the Table 5.2. For analytical calcula-
tion equations (2.18) and (2.20) are modified, wherein the coefficient’s Ki=1 and
Kv=1.35 are used in the √equation for IGBT
Psw,S = fsw (Eon + Eof f ). π2 .( IIrms
ref
)ki .( UUref
dc kv
) = 53.88W
Similarly, for determining the switching losses of a diode the following equation is
used, having Kid=1 √ and Kvd=0.6
Psw,D = fsw (ERR ). π2 .( IIrms
ref
)kid .( UUref
dc kvd
) = 8.9W

4.1.2 Loss Analysis of the Vienna rectifier

Figure 4.3: Instantaneous conduction losses of diodes

23
4. Result and Future work

The instantaneous diode conduction losses depicted in Fig.4.3 comprises of the high
frequency switching diode Dar1 , having a discretized waveform as well as the contin-
uous conduction of Da1 at half of the fundamental [Link] peak value of the diode
conduction loss is 35.8W. However, loss pattern of Dar1 is chopped and the average
value of the losses are given in the tabulated form. Fig. 4.4 shows the instantaneous
conduction loss of IGBT S11 and S12 . It should be noted that the relative on time
period of the switches is quite small in-spite of the peak onstate loss value being at
75W. This brings down the average value of the losses across the switches over a
fundamental period.

Figure 4.4: Instantaneous conduction losses of IGBT

For the matlab model the instantaneous losses are averaged over the fundamental
cycle, the tabulation of which is given in Table 4.3. Analytically the conduction
losses are determined using the average and root mean square values of the currents
flowing through the components as calculated in the case-setup. The average value
of the conduction losses for components found using (2.13) and (2.22) are

PS = 1.54W
PDar = 9.56W
PDa = 10.23W

On comparing the IGBT conduction loss calculated analytcially with the matlab
model, it can be seen that there is a difference in the values. This is because of the
difference in the RMS current of the IGBT, which is 4.19A found via the equation,
whereas from the simulation the value turns out to be 4.99A.

24
 4. Result and Future work

Table 4.3: On-state loss calculation for Vienna rectifier

Component wise on state loss breakdown Losses (Watts)

S11 S12 Dar1 Dar2 Da1 Da2 First leg
1.71 1.72 9.38 9.38 10.21 10.21 42.62
S21 S22 Dbr1 Dbr2 Db1 Db2 Second leg
1.72 1.72 9.37 9.37 10.21 10.21 42.62
S31 S32 Dcr1 Dcr2 Dc1 Dc2 Third leg
1.72 1.72 9.37 9.37 10.21 10.21 42.62
Net on state losses in Watts 127.86

Table 4.4: Switching loss calculation for Vienna rectifier

Component wise switching loss breakdown Losses (Watts)

S11 S12 Dar1 Dar2 Da1 Da2 First leg
11.22 11.22 1.74 1.74 0 0 25.93
S21 S22 Dbr1 Dbr2 Db1 Db2 Second leg
11.22 11.22 1.74 1.74 0 0 25.93
S31 S32 Dcr1 Dcr2 Dc1 Dc2 Third leg
11.22 11.22 1.74 1.74 0 0 25.93
Net switching losses in Watts 77.80 W

Considering the difference in between the RMS value of the simulated current in the
set-up and the analytical one, it is appropriate to use the later value of 4.99A. Using
(2.18)(2.20) and (2.27) the switching losses are found. On account of the non-linear
characteristics in the datasheet, Ki=1 and Kv=1.35 are included in the equation,
as also considered in the case of two level rectifier. The results obtained thus are
given as

Psw|IGBT = 11.22W
Psw|Dar = 1.74W
Psw|Da = 0W

It can be observed as explained in theory chapter, that the diode Da(1,2) does not have
any switching losses as they operate at fundamental half cycle at instants where the
voltage and current are zero. As shown in Table 4.4 the switching losses simulated
via matlab model has good consistency with the results obtained analytically. In
this case as the equations involved needed the peak value of the supply current i.e
Ipeak =41.4A, no difference in the two results was observed.

4.1.3 Conclusion
For determining the semiconductor efficiency, both type of losses are tabulated for
the sake of ease and comparison as given in Table (4.5) and (4.6).

For the two level converter it is seen that the switching loss of the IGBT is dominant,
whereas the diode conduction losses is negligible. Considering only the semiconduc-

25
4. Result and Future work

Table 4.5: Total loss for two level converter

Two level Rectifier Losses

IGBT Conduction loss 133.8
Diode Conduction loss 6.48
IGBT Switching loss 322.8
Diode Switching loss 53.4
Net loss (Watts) 516.48

Table 4.6: Total loss for Vienna rectifier

Vienna rectifier Losses

IGBT Conduction loss 10.32
Diode Conduction loss 117.54
IGBT Switching loss 67.32
Diode Switching loss 10.44
Net loss (Watts) 205.6

tor losses, the efficiency at the rated power of 25kW is 97.93 %. On the contrary,
in Vienna rectifier although the diode conduction loss is high, at component level,
the switching loss of the IGBT is predominant. The semiconductor loss efficeiency
for vienna rectifier at 25kW is 99.176%. The switching losses increases with increase
in frequency, but the change in the conduction losses would be less comparatively.
This is an important observation and should be considered for proper selection of
the switching frequency.

4.2 Future Work

There are some aspects that needs attention such as design of heat sink. Depending
upon application and purpose, it would be imperative to calculate the harmonics
distortion of currents (THD) at different frequencies. Implementing a control strat-
egy for midpoint voltage is also very important from the operational aspect, that
needs to be addressed.

26
 Bibliography

[1] Viitanen T. (2005) "Space vector modulation of Boost-Type Three phase, three
switch, three level Unidirectional PWM Rectifier-Analysis and implementation"
Thesis for Doctor of Technology, Tampere University of Technology, Finland.
[2] Lipo T.A, Holmes D.G (2003) "Pulse width Modulation for Power Converters:
Principles and Practice" Wiley-IEEE press.
[3] Kolar J.W, Drofenik U, Zach F.C (1996) "Current Handling Capability of the
Neutral Point of Three-Phase /Switch/Level Boost-Type PWM (VIENNA)
Rectifier" IEEE Power Electronics Specialists Conference, 23-27 June 1996,
Baveno, Italy.
[4] Kolar J.W, Drofenik U, Zach F.C (1995) "Space Vector Based Analysis of the
Variation and Control of the Neutral Point Potential of Hysteresis Current Con-
trolled Three-Phase /Switch/Level Rectifier Systems" IEEE Proceedings, Inter-
national Conference on Power Electronics and Drive Systems, 21-24 Feb.1995,
Singapore.
[5] Kolar J.W, Ertl H, Zach F.C (1996) "Design and experimental investigation
of a three-phase high power density high efficiency unity power factor PWM
(VIENNA) rectifier employing a novel integrated power semiconductor mod-
ule" IEEE- Applied Power Electronics Conference and Exposition, Conference
Proceedings, 3-7 March 1996, San Jose, CA, USA.
[6] Haghbin, S. and Thiringer .T (2014) DC bus current harmonics of a three-phase
PWM inverter with the zero sequence injection. In Proceedings. Transportation
Electrification-Conference and Expo (ITEC), pages 1-6, Dearborn, MI.
[7] Ahmet M. Hava, Russel J. Kerkman, Thomas A. Lipo (1998)"Carrier-Based
PWM-VSI Overmodulation Strategies: Analysis, Comparison, and Design"
IEEE Transactions on Power Electronics, VOL. 13, NO. 4, JULY 1998
[8] [Link] (2017) "Modelling and design of inverters using novel power loss cal-
culations and DC-link current/voltage ripple estimation methods and bus bar
analysis" Thesis for Doctor of Philosophy, McMaster University, Hamilton, On-
tario, Canada, Feb. 2017.
[9] Bierhoff, M. H. and Fuchs, F. W. (2004). "Semiconductor losses in voltage
source and current source IGBT converters based on analytical derivation".
In Proceedings, Power Electronics Specialists Conference (PESC), pages 2836-
2842, Aachen, Germany.
[10] L. Mestha and P. Evans. (1989). “Analysis of on-state losses in pwm inverters,”
Electric Power Applications, IEE Proceedings B, vol. 136, no. 4, pp. 189– 195.
[11] Ali Rabiei. (2015) " Efficiency Analysis of Drive-train for an Electrified Vehicle"
PhD thesis, Chalmers University of Technology, Sweden.

27
Bibliography

[12] R. Teichmann, S. Bernet. (2005). "A comparision of three- level converters ver-
sus two level converters for low voltage drives, traction and utility applications"
IEEE Transactions on industrial applications, vol 41, May/June.
[13] Infineon IKW50N60H3, high speed IGBT in trench and field stop technology.
[14] Infineon IDW50E60, emitter controlled diode series.
[15] Infineon IKY50N120CH3, high speed switching third generation IGBT

28
 A
Appendix

A.0.1 Analytical equations for currents used in Vienna rec-

tifier for loss analysis

IT,avg = (1/pi − ma/4) ∗ Ipeak;

IDar,avg = ma/4 ∗ Ipeak;
IDa,avg = 1/pi ∗ Ipeak;

IT,rms = sqrt((1/4) − (2 ∗ ma)/(3 ∗ pi)) ∗ Ipeak;

IDar,rms = sqrt((2 ∗ ma)/(3 ∗ pi)) ∗ Ipeak;
IDa,rms = 1/2 ∗ Ipeak;

A.0.2 Matlab file for Vienna rectifier

I
A.0.2 Matlab file for Vienna rectifier
Tsw=1/20e3;
fsw=20e3;
tstop = 1/50;
tstep = 1e-6;
time = (tstep : tstep : tstop);
Vdc = 700;
A = sqrt(2);
ma=1.15;
Urms_phase=(Vdc/2)*ma/sqrt(2);
%ma=(Uph_peak*2)/Vdc;
Pac = 25e3;
phi=0;
Irms = Pac/(3*Urms_phase)*cos(phi); % phi is zero
Ipeak= sqrt(2)*Irms;
% for conduction losses
VT_IGBT=0.9;
VT_D=0.45;
VT_DF=0.45; % ~ VT_D

Rf_IGBT=0.022;
Rf_D=0.01;
Rf_DF=0.01; % ~ Rf_D

% for switching losses at Iref:

Vref = 400;
Iref = 50;
Esw_IGBT_on = 1.42e-3;
Esw_IGBT_off = 1.13e-3;
Esw_diode = 0.358e-3;

KiD=1;
KvD=0.6;
KiIGBT=1;
KvIGBT=1.35;

% Creation of phase voltages and phase currents :

u1 = A*Urms_phase*sin(100*pi*time);
u2 = A*Urms_phase*sin(100*pi*time - 2*pi/3);
u3 = A*Urms_phase*sin(100*pi*time - 4*pi/3);

i1 = A*Irms*sin(100*pi*time); % considering phase angle as zero/ upf

i2 = A*Irms*sin(100*pi*time - 2*pi/3); % considering phase angle as
zero/ upf
i3 = A*Irms*sin(100*pi*time - 4*pi/3); % considering phase angle as
zero/ upf

% THI having freq 3*fundamental and amlitude 1/6th of fundamental:

u3h = (A*Urms_phase/6)*sin(300*pi*time);

%Creating reference voltages by adding 3rd harmonic injection:

uref1 = u1 + u3h;
uref2 = u2 + u3h;
uref3 = u3 + u3h;

%Generation of a triangle wave:

t_onehalfswitchingperiod = Tsw/tstep/2;
OnePiece = Vdc/2-Vdc*time(1:floor(t_onehalfswitchingperiod))/(Tsw/2);
OneTriangleperiod = [OnePiece,-OnePiece];
NumberOfTrianglePeriods = ceil(tstop/Tsw);

TriangleWave_unadapted=[];
TriangleWave=[];
for j=1:NumberOfTrianglePeriods
TriangleWave_unadapted=[TriangleWave_unadapted,OneTriangleperiod];
end
TriangleWave=TriangleWave_unadapted(1:length(time));

% Generation of double triangle waveform:

UTR1 = 0.5*(TriangleWave)+Vdc/4; % DC positive shift from 0

UTR2 = 0.5*(TriangleWave)-Vdc/4; % DC negative shift from 0
figure(2)
plot(time/10,UTR1,'r',time/10,UTR2,'b',time/10,uref1,'k')

% % Creating instantaneous pole voltages:

u1_inst = zeros(1,length(time));
u1_inst(uref1 > UTR1 & uref1 > UTR2) = 0.5*Vdc; % upper switch is OFF
u1_inst(uref1 < UTR1 & uref1 < UTR2) = -0.5*Vdc;% lower switch is OFF

u2_inst = zeros(1,length(time));
u2_inst(uref2 > UTR1 & uref2 > UTR2) = 0.5*Vdc;
u2_inst(uref2 < UTR1 & uref2 < UTR2) = -0.5*Vdc;

u3_inst = zeros(1,length(time));
u3_inst(uref3 > UTR1 & uref3 > UTR2) = 0.5*Vdc;
u3_inst(uref3 < UTR1 & uref3 < UTR2) = -0.5*Vdc;

figure(3)
plot(time*1000,u1_inst,'b', time*1000,uref1,'r')
xlabel('Time (ms)','FontSize',14)
ylabel(' Converter voltage(V)','FontSize',14)
l = legend('Phase A','Ref-A');
[Link] = 14;

%% Creating line voltages:

u12=u1_inst-u2_inst;
u23=u2_inst-u3_inst;
u31=u3_inst-u1_inst;

figure(4)
plot(time*1000,u12,'b')
xlabel('Time (ms)','FontSize',14)
ylabel(' Line voltage(V)','FontSize',14)
l = legend('Line to line -AB');
[Link] = 14;

%Initialising of current variables :

i_T1U=0*time;
i_T1L=0*time;
i_D1U=0*time;
i_D1L=0*time;
i_D1P=0*time;
i_D1N=0*time;

i_T2U=0*time;
i_T2L=0*time;
i_D2U=0*time;
i_D2L=0*time;
i_D2P=0*time;
i_D2N=0*time;

i_T3U=0*time;
i_T3L=0*time;
i_D3U=0*time;
i_D3L=0*time;
i_D3P=0*time;
i_D3N=0*time;

% leg 1
for count = 1:length(time)
i_inv = i1(count);
u_inv = uref1(count);
x = sign(u1_inst);
y = x(count); % sign:1= +ve*dc/2, sign:0= 0 state, sign:-1 = -
ve*dc/2

if u_inv > 0 % for positive currents

i_D1P(count) = i_inv;
if y==0 % When upper switch is ON, corresponds to sign: 0 state
i_T1U(count)= i_inv; % Current also flows from D1P
else % When upper switch is OFF, coresponds to sign: 1 state
i_D1U(count) = i_inv; % Current also flows from D1P
end

else % for negative currents

i_D1N(count) = i_inv;
 if y==0 % When lower switch is ON, corresponds to sign: 0 state
i_T1L(count) = i_inv; % Current also flows from D1N
else % When lower switch is OFF, coresponds to sign: -1
state
i_D1L(count) = i_inv; % Current also flows from D1N
end
end

% Leg 2
u_inv = uref2(count);
i_inv = i2(count);
x = sign(u2_inst);
y = x(count);
if u_inv > 0
i_D2P(count) = i_inv;
if y==0
i_T2U(count)= i_inv;
else
i_D2U(count) = i_inv;
end
else
i_D2N(count) = i_inv;
if y==0
i_T2L(count) = i_inv;
else
i_D2L(count) = i_inv;
end
end

% Leg 3
u_inv = uref3(count);
i_inv = i3(count);
x = sign(u3_inst);
y = x(count);

if u_inv > 0
i_D3P(count) = i_inv;
if y==0
i_T3U(count)= i_inv;
else
i_D3U(count) = i_inv;
end
else
i_D3N(count) = i_inv;
if y==0
i_T3L(count) = i_inv;
else
i_D3L(count) = i_inv;
end
end
end
%correcting into positive currents
i_T1L= -i_T1L;
i_D1L= -i_D1L;
i_T2L= -i_T2L;
i_D2L= -i_D2L;
i_T3L= -i_T3L;
i_D3L= -i_D3L;
i_D1N= -i_D1N;
i_D2N= -i_D2N;
i_D3N= -i_D3N;

figure(11)
subplot(2,1,1)
plot(time*1000,i_T1U,'r',time*1000,i_D1U,'b',time*1000,i_D1P,'k')
xlabel('Time (ms)','FontSize',14)
ylabel('Current (A)','FontSize',14)
legend('S11','Dar1','Da1')
subplot(2,1,2)
plot(time*1000,i_T1L,'r',time*1000,i_D1L,'b',time*1000,i_D1N,'k')
xlabel('Time (ms)','FontSize',14)
ylabel('Current (A)','FontSize',14)
legend('S12','Dar2','Da2')

% By Simulation:
AverageT1=mean(i_T1U);
AverageD1U=mean(i_D1U);
AverageD1P=mean(i_D1P);

rmsT=sqrt(sum(i_T1U.*i_T1U)/count);
rmsD1U=sqrt(sum(i_D1U.*i_D1U)/count);
rmsD1P=sqrt(sum(i_D1P.*i_D1P)/count);

% By analytical equation from kolar:

I_T_avg=(1/pi-ma/4)*Ipeak;
I_DU_avg= ma/4*Ipeak;
I_DP_avg= 1/pi*Ipeak;

I_T_rms=sqrt((1/4)-(2*ma)/(3*pi))*Ipeak;
I_DU_rms= sqrt((2*ma)/(3*pi))*Ipeak;
I_DP_rms= 1/2*Ipeak;

X = [AverageT1,I_T_avg,AverageD1U,I_DU_avg,AverageD1P,I_DP_avg];
Y= [rmsT,I_T_rms,rmsD1U,I_DU_rms,rmsD1P,I_DP_rms];
% Calculation of ON state losses

p_Onstate_T1U=0*time;
p_Onstate_D1U=0*time;
p_Onstate_T1L=0*time;
p_Onstate_D1L=0*time;
p_On__TD1P=0*time;
p_On__DD1P=0*time;
p_On__TD1N=0*time;
p_On__DD1N=0*time;

p_Onstate_T2U=0*time;
p_Onstate_D2U=0*time;
p_Onstate_T2L=0*time;
p_Onstate_D2L=0*time;
p_On__TD2P=0*time;
p_On__DD2P=0*time;
p_On__TD2N=0*time;
p_On__DD2N=0*time;

p_Onstate_T3U=0*time;
p_Onstate_D3U=0*time;
p_Onstate_T3L=0*time;
p_Onstate_D3L=0*time;
p_On__TD3P=0*time;
p_On__DD3P=0*time;
p_On__TD3N=0*time;
p_On__DD3N=0*time;

for count=1:length(time)

% %leg 1
if i_T1U(count)>0
p_Onstate_T1U(count)=(VT_IGBT +
Rf_IGBT*i_T1U(count))*i_T1U(count);
p_On__TD1P(count)=(VT_D + Rf_D*i_T1U(count))*i_T1U(count);
end
if i_D1U(count)>0
p_Onstate_D1U(count)=(VT_DF + Rf_DF
*i_D1U(count))*i_D1U(count);
p_On__DD1P(count)=(VT_D + Rf_D*i_D1U(count))*i_D1U(count);
end
if i_T1L(count)>0
p_Onstate_T1L(count)=(VT_IGBT +
Rf_IGBT*i_T1L(count))*i_T1L(count);
p_On__TD1N(count)=(VT_D + Rf_D*i_T1L(count))*i_T1L(count);
end
if i_D1L(count)>0
p_Onstate_D1L(count)=(VT_DF + Rf_DF*i_D1L(count))*i_D1L(count);
p_On__DD1N(count)=(VT_D + Rf_D*i_D1L(count))*i_D1L(count);
end

% %leg 2
if i_T2U(count)>0
p_Onstate_T2U(count)=(VT_IGBT +
Rf_IGBT*i_T2U(count))*i_T2U(count);
p_On__TD2P(count)=(VT_D + Rf_D*i_T2U(count))*i_T2U(count);
end
if i_D2U(count)>0
 p_Onstate_D2U(count)=(VT_DF + Rf_DF
*i_D2U(count))*i_D2U(count);
p_On__DD2P(count)=(VT_D + Rf_D*i_D2U(count))*i_D2U(count);
end
if i_T2L(count)>0
p_Onstate_T2L(count)=(VT_IGBT +
Rf_IGBT*i_T2L(count))*i_T2L(count);
p_On__TD2N(count)=(VT_D + Rf_D*i_T2L(count))*i_T2L(count);
end
if i_D2L(count)>0
p_Onstate_D2L(count)=(VT_DF + Rf_DF*i_D2L(count))*i_D2L(count);
p_On__DD2N(count)=(VT_D + Rf_D*i_D2L(count))*i_D2L(count);
end

% %leg 3
if i_T3U(count)>0
p_Onstate_T3U(count)=(VT_IGBT +
Rf_IGBT*i_T3U(count))*i_T3U(count);
p_On__TD3P(count)=(VT_D + Rf_D*i_T3U(count))*i_T3U(count);
end
if i_D3U(count)>0
p_Onstate_D3U(count)=(VT_DF + Rf_DF
*i_D3U(count))*i_D3U(count);
p_On__DD3P(count)=(VT_D + Rf_D*i_D3U(count))*i_D3U(count);
end
if i_T3L(count)>0
p_Onstate_T3L(count)=(VT_IGBT +
Rf_IGBT*i_T3L(count))*i_T3L(count);
p_On__TD3N(count)=(VT_D + Rf_D*i_T3L(count))*i_T3L(count);
end
if i_D3L(count)>0
p_Onstate_D3L(count)=(VT_DF + Rf_DF*i_D3L(count))*i_D3L(count);
p_On__DD3N(count)=(VT_D + Rf_D*i_D3L(count))*i_D3L(count);
end

end

p_Onstate_D1P=(p_On__TD1P + p_On__DD1P);
p_Onstate_D1N=(p_On__TD1N + p_On__DD1N);

p_Onstate_D2P=(p_On__TD2P + p_On__DD2P);
p_Onstate_D2N=(p_On__TD2N + p_On__DD2N);

p_Onstate_D3P=(p_On__TD3P + p_On__DD3P);
p_Onstate_D3N=(p_On__TD3N + p_On__DD3N);

a=mean(p_On__TD1P + p_On__DD1P);
b=mean(p_On__TD1N + p_On__DD1N);

c=mean(p_On__TD2P + p_On__DD2P);
d=mean(p_On__TD2N + p_On__DD2N);
e=mean(p_On__TD3P + p_On__DD3P);
f=mean(p_On__TD3N + p_On__DD3N);

g=[a b c d e f];

figure(5)
plot(time*1000,p_Onstate_D1U,'r',time*1000,p_Onstate_D1P,'k')
xlabel('Time (ms)','FontSize',14)
ylabel('Losses (W)','FontSize',14)
legend('D1U','D1P')
l = legend('Dar1','Da1');
[Link] = 14;
grid on
figure(6)
plot(time*1000,p_Onstate_T1U,'b',time*1000,p_Onstate_T1L,'r')
xlabel('Time (ms)','FontSize',14)
ylabel('Losses (W)','FontSize',14)
legend('S11','S12')
l = legend('S11','S12');
[Link] = 14;
grid on
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%% Average losses of components over once cycle%%%%%
P_Onstate_T1U=mean(p_Onstate_T1U);
P_Onstate_T1L=mean(p_Onstate_T1L);
P_Onstate_D1U=mean(p_Onstate_D1U);
P_Onstate_D1L=mean(p_Onstate_D1L);
p_Onstate_D1P=a;
p_Onstate_D1N=b;

P_Onstate_T2U=mean(p_Onstate_T2U);
P_Onstate_T2L=mean(p_Onstate_T2L);
P_Onstate_D2U=mean(p_Onstate_D2U);
P_Onstate_D2L=mean(p_Onstate_D2L);
p_Onstate_D2P=c;
p_Onstate_D2N=d;

P_Onstate_T3U=mean(p_Onstate_T3U);
P_Onstate_T3L=mean(p_Onstate_T3L);
P_Onstate_D3U=mean(p_Onstate_D3U);
P_Onstate_D3L=mean(p_Onstate_D3L);
p_Onstate_D3P=e;
p_Onstate_D3N=f;

J=[P_Onstate_T1U,P_Onstate_T1L,P_Onstate_D1U,P_Onstate_D1L,a,b];
K=[P_Onstate_T2U,P_Onstate_T2L,P_Onstate_D2U,P_Onstate_D2L,c,d];
L=[P_Onstate_T3U,P_Onstate_T3L,P_Onstate_D3U,P_Onstate_D3L,e,f];
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%
%%%% Calculation of Switching losses:
%%% Finding out the switching instances

% Leg 1 ---------------------------------------------------------------
---
diffT1U=i_T1U(2:length(i_T1U))-i_T1U(1:length(i_T1U)-1);
diffT1L=i_T1L(2:length(i_T1L))-i_T1L(1:length(i_T1L)-1);
[~,TransistorTurnOn1U]=find(diffT1U>1);
[~,TransistorTurnOff1U]=find(diffT1U<-1);
[~,TransistorTurnOn1L]=find(diffT1L>1);
[~,TransistorTurnOff1L]=find(diffT1L<-1);
% Leg 1 positive current
EswOn_T1U_inst=Esw_IGBT_on*i1(TransistorTurnOn1U)/Iref*(Vdc/2/Vref)^KvI
GBT;
EswOn_T1U=sum(EswOn_T1U_inst);

EswOff_T1U_inst=Esw_IGBT_off*i1(TransistorTurnOff1U)/Iref*(Vdc/2/Vref)^
KvIGBT;
EswOff_T1U=sum(EswOff_T1U_inst);

Err_D1U_inst=Esw_diode*(i1(TransistorTurnOn1U))/Iref*(Vdc/2/Vref)^KvD;
Err_D1U=sum(Err_D1U_inst);
% Leg 1 negative current
EswOn_T1L_inst=Esw_IGBT_on*(-
i1(TransistorTurnOn1L))/Iref*(Vdc/2/Vref)^KvIGBT;
EswOn_T1L=sum(EswOn_T1L_inst);

EswOff_T1L_inst=Esw_IGBT_off*(-
i1(TransistorTurnOff1L))/Iref*(Vdc/2/Vref)^KvIGBT;
EswOff_T1L=sum(EswOff_T1L_inst);

Err_D1L_inst=Esw_diode*(-i1(TransistorTurnOn1L))/Iref*(Vdc/2/Vref)^KvD;
Err_D1L=sum(Err_D1L_inst);

% Leg 2 --------------------------------------------------------
diffT2U=i_T2U(2:length(i_T2U))-i_T2U(1:length(i_T2U)-1);
diffT2L=i_T2L(2:length(i_T2L))-i_T2L(1:length(i_T2L)-1);
[~,TransistorTurnOn2U]=find(diffT2U>1);
[~,TransistorTurnOff2U]=find(diffT2U<-1);
[~,TransistorTurnOn2L]=find(diffT2L>1);
[~,TransistorTurnOff2L]=find(diffT2L<-1);
% Leg 2 positive current
EswOn_T2U_inst=Esw_IGBT_on*i2(TransistorTurnOn2U)/Iref*(Vdc/2/Vref)^KvI
GBT;
EswOn_T2U=sum(EswOn_T2U_inst);

EswOff_T2U_inst=Esw_IGBT_off*i2(TransistorTurnOff2U)/Iref*(Vdc/2/Vref)^
KvIGBT;
EswOff_T2U=sum(EswOff_T2U_inst);
Err_D2U_inst=Esw_diode*(i2(TransistorTurnOn2U))/Iref*(Vdc/2/Vref)^KvD;
Err_D2U=sum(Err_D2U_inst);
% Leg 2 negative current
EswOn_T2L_inst=Esw_IGBT_on*(-
i2(TransistorTurnOn2L))/Iref*(Vdc/2/Vref)^KvIGBT;
EswOn_T2L=sum(EswOn_T2L_inst);

EswOff_T2L_inst=Esw_IGBT_off*(-
i2(TransistorTurnOff2L))/Iref*(Vdc/2/Vref)^KvIGBT;
EswOff_T2L=sum(EswOff_T2L_inst);

Err_D2L_inst=Esw_diode*(-i2(TransistorTurnOn2L))/Iref*(Vdc/2/Vref)^KvD;
Err_D2L=sum(Err_D2L_inst);

% Leg 3 ---------------------------------------------------------------
-
diffT3U=i_T3U(2:length(i_T3U))-i_T3U(1:length(i_T3U)-1);
diffT3L=i_T3L(2:length(i_T3L))-i_T3L(1:length(i_T3L)-1);
[~,TransistorTurnOn3U]=find(diffT3U>1);
[~,TransistorTurnOff3U]=find(diffT3U<-1);
[~,TransistorTurnOn3L]=find(diffT3L>1);
[~,TransistorTurnOff3L]=find(diffT3L<-1);
% Leg 3 positive current
EswOn_T3U_inst=Esw_IGBT_on*i3(TransistorTurnOn3U)/Iref*(Vdc/2/Vref)^KvI
GBT;
EswOn_T3U=sum(EswOn_T3U_inst);

EswOff_T3U_inst=Esw_IGBT_off*i3(TransistorTurnOff3U)/Iref*(Vdc/2/Vref)^
KvIGBT;
EswOff_T3U=sum(EswOff_T3U_inst);

Err_D3U_inst=Esw_diode*(i3(TransistorTurnOn3U))/Iref*(Vdc/2/Vref)^KvD;
Err_D3U=sum(Err_D3U_inst);
% Leg 3 negative current
EswOn_T3L_inst=Esw_IGBT_on*(-
i3(TransistorTurnOn3L))/Iref*(Vdc/2/Vref)^KvIGBT;
EswOn_T3L=sum(EswOn_T3L_inst);

EswOff_T3L_inst=Esw_IGBT_off*(-
i3(TransistorTurnOff3L))/Iref*(Vdc/2/Vref)^KvIGBT;
EswOff_T3L=sum(EswOff_T3L_inst);

Err_D3L_inst=Esw_diode*(-i3(TransistorTurnOn3L))/Iref*(Vdc/2/Vref)^KvD;
Err_D3L=sum(Err_D3L_inst);

%% Switching loss coefficient summation

PswOn_T1U=EswOn_T1U/time(length(time));
PswOff_T1U=EswOff_T1U/time(length(time));
PswErr_D1U=Err_D1U/time(length(time));

PswOn_T1L=EswOn_T1L/time(length(time));
PswOff_T1L=EswOff_T1L/time(length(time));
PswErr_D1L=Err_D1L/time(length(time));

PswOn_T2U=EswOn_T2U/time(length(time));
PswOff_T2U=EswOff_T2U/time(length(time));
PswErr_D2U=Err_D2U/time(length(time));

PswOn_T2L=EswOn_T2L/time(length(time));
PswOff_T2L=EswOff_T2L/time(length(time));
PswErr_D2L=Err_D2L/time(length(time));

PswOn_T3U=EswOn_T3U/time(length(time));
PswOff_T3U=EswOff_T3U/time(length(time));
PswErr_D3U=Err_D3U/time(length(time));

PswOn_T3L=EswOn_T3L/time(length(time));
PswOff_T3L=EswOff_T3L/time(length(time));
PswErr_D3L=Err_D3L/time(length(time));

Psw_T1U=PswOn_T1U+PswOff_T1U;
Psw_T1L=PswOn_T1L+PswOff_T1L;
Psw_D1U=PswErr_D1U;
Psw_D1L=PswErr_D1L;
Psw_T2U=PswOn_T2U+PswOff_T2U;
Psw_T2L=PswOn_T2L+PswOff_T2L;
Psw_D2U=PswErr_D2U;
Psw_D2L=PswErr_D2L;
Psw_T3U=PswOn_T3U+PswOff_T3U;
Psw_T3L=PswOn_T3L+PswOff_T3L;
Psw_D3U=PswErr_D3U;
Psw_D3L=PswErr_D3L;