Netlist quality checks

Below are certain checks that, should be fulfilled post-synthesis to ensure netlist
qualifications before it is delivered for physical implementation.

1. No Clocks:

In this check, we ensure that all the required clocks reach the sync points. Some
major reasons for getting no clock violation in design are mentioned below:

Clock definition missing: This is observed when clock creation is missing in the
clock constraint file.
RTL connectivity issue/Tie off: This type of no clock is observed when there is
missing connectivity in between modules in the RTL or having direct tie-offs in
the RTL.

Impact: Ideally, all the registers in the design should be clocked. If no clock issue
is left in the design, then it will report unconstraint endpoints and can cause
optimization issues on such paths.

Solution: To resolve the above-mentioned no clocks violation, we need to get

the corrected RTL (from the designer) and clock constraints files with all the
required clock definitions.

Command: check_timing -include {no_clock}

2. Unconstraint end-points:

This is due to the missing IO constraints, clock definitions, or due to some

exceptions at the sequential cells or ports. Possible reasons are case constant, no
arrival path, or false path.

Impact: If IO constraints are missing in the design, then the external launch time
for the input path or the capture time for the output path will be missed. It can
cause an incomplete timing check. If the path is expected to be false, it could
lead to an incorrect timing check.

Solution: To resolve these problems, we need the correct constraint file (sdc),
which defines all the required clocks used in the design, IO delays on all the
required ports, verified false path, and case constants in design.

Command: check_timing -include {unconstrained_endpoints}

3. Timing:

In this check, the entire design is divided into timing paths. For each timing path,
the delay is calculated and checks violation based on timing constraints (clock
period, clock uncertainty, and setup time). The major reasons for having timing
violations are- levels of logic, incorrect/missing constraints such as clock
relations, clock exceptions, and incorrect uncertainty.

Impact: If a huge timing violation is reported at the synthesis, this violation will
be difficult to fix at later stages (PNR/ECO), which also impacts the power and
area.
Solution: The techniques used to resolve/reduce timing violations are user-
defined path groups with appreciate weightage, by disabling selectively/entirely
multibit banking in design, bound creation, using timing efforts high or
incremental compilation. If we are performing Physical Aware synthesis, it is
expected to have a good macro placement that improves timing violations.

Command: report_timing or report_qor

4. LEC:

This is one of the important checks that validate the correctness of the netlist
concerning the RTL.

It is recommended to perform this check when there is an update in the RTL or

netlist. Generally, in the synthesis LEC, a check is performed between the RTL vs
synthesize netlist and synthesize netlist vs post scan netlist.

General issues due to which the LEC can fail are as follows:

 CSN Missing: The missing CSN (Connect Supply Net) can lead to LEC failure.

 Isolation cell mapping: When there is an issue with UPF constraint, then there
could be a possibility of having different isolation cells, mapped in between
the RTL and synthesize netlist, that may cause LEC failure.

 Undriven Nets: If we have undriven nets in the RTL, the synthesize tool will tie
off these nets causing LEC failure. This can be resolved by getting the RTL
fixed or if the undriven is expected, then you need to use undriven constraints
to pass the LEC.

Constraint used (formality): set_constants <net_name> <0/1>

Impact: If the LEC is not clean then the equivalence is not maintained between
the RTL and netlist which can lead to functionality failure.

EDA Tool: Formality from Synopsys, conformal from Cadence

5. Timing loop:

In the RTL, if in between combo logic, the output is again feed to the same input
of combo logic that forms a logical loop, this loop is called the timing loop. We
can get the timing loops due to RTL connectivity issues in design that, which can
lead to meta-stable data, thus, we should avoid timing loops while netlist
generation.

Impact: The path with timing loops will not have endpoints. If such loops are not
broken then the path will not be correctly timed.

Solution: If we are getting timing loops that are expected to have then in such
case, we need to use the constraint to break such timing loops. If such timing
loops are not expected in design, then we need to get the updated RTL.

Command: check_timing -include {loops}

6. Empty module:

If the RTL module definitions don’t have any logical content such as wire, inputs,
or outputs, then such modules are called empty modules. This check is
performed before compilation.

By default, empty modules are removed during synthesis. If we want to preserve

this empty module, we need to apply constraint (set_dont_touch) on that module
before compilation.
Command: check_design
7. Removed Flop:

If the register is removed during compilation and optimization, then such flop is
reported as removed flops. If the register is either unloaded or constant, then by
default during compilation such flip flop is removed from the design.

If such flip flops are expected in design, then we need to use certain constraints
to preserve this.

Command:
report_unloaded_registers
report_constant_registers

8. Floating pins and multidriven pins:

In the design there might be a possibility that a few of the pins are not connected
to any element present in the design. Such pins are known as floating pins. While
performing optimization, such floating pins cells might get optimized due to
which there could be a breakdown in logic.

Multidriven nets are detected when there is more than one input connected to
the same net from different modules. This is not accepted in design and you need
to fix this issue. It requires RTL correction to resolve this issue.

9. Latches:

The latches are not expected in design and during compilation, the tool gives a
warning if the design infers a latch. Below are a few reasons why a latch is not
preferred in design:

 As latches are level triggers and can change the output at an active level of
the clock.

 The latch output is stable only at an inactive level of the clock cycle, due to
which the entire clock cycle is not utilized for timing check
Design Exchange Format (DEF file): The Design Exchange (DEF) file is
an ASCII representation of physical information of the design. DEF contains
Property definition, Die area, Row definition, Physical cell definition, STD
cell definition, special net, regular nets, port, blockages, module constraints
etc.

Physical Library (LEF): It contains all the physical information about the
cells (Technology and Macro cells) and nets. It also contains the Layer
definitions, Metal capacitance definitions, Macro cell definitions, macro cell
dimensions, Layout of pins, Blockages information, DRC information given
by foundry etc.

Link library

A link library is a collection of cells that are used to describe the function
of mapped cells prior to optimization. The link library is typically used to
provide cells that are not available in the target library, such as RAMs,
ROMs, and macros. The link library can contain cells from any technology
library, but it is typically recommended to use the same technology
library for the target library and the link library.

Target library

the technology library you want to map to during synthesis. Target library is
used for technology mapping. All the combo (AND, NAND, NOT, etc) and the
sequential (SDFF, DFF, etc) are mapped to equivalent gates from the target.
Synthesis is about converting RTL to gates.

Q. Can we do synthesis without giving timing constraints?

Yes, it is possible to do synthesis without giving timing constraints. However,

the resulting design may not meet the timing requirements of the design.
Q. Can we do synthesis without giving timing constraints?

Yes, it is possible to do synthesis without giving timing constraints. However, the

resulting design may not meet the timing requirements of the design.

ISSUE:

1. Syntax Errors

Description: These errors occur when the code written in Hardware

Description Languages (HDLs) like VHDL or Verilog does not conform to
the syntax rules of the language.

Fix: Review the HDL code for typos, missing semicolons, incorrect use of
keywords, and ensure proper module and port definitions.

2. Semantic Errors

Description: These errors arise when the code is syntactically correct but
does not make sense logically (e.g., using signals before they are
defined).

Fix: Check the logic of the design, ensure that all signals are properly
declared and initialized, and validate the intended functionality against
the specifications.

3. Timing Violations

Description: Timing violations occur when the design does not meet the
required setup, hold, or clock- to-output timing constraints.

Fix: Optimize critical paths by:

Adjusting the placement of

components. Changing the clock

speed.
Adding pipeline stages to distribute

logic delays. Using faster

components if feasible.

4. Resource Constraints

Description: This error happens when the design exceeds the available
resources on the target FPGA or ASIC, such as logic cells, memory blocks,
or I/O pins.

Fix:

Optimize the design to reduce resource usage (e.g., through

logic minimization). Use hierarchical design to manage

complexity

Partition the design if possible, or choose a target device with more resources.

5. Connectivity Errors

Description: These errors occur when there are issues with signal
connections, such as unconnected ports or incorrect connections
between modules.

Fix:

Use design rule checks (DRC) to identify

unconnected nets. Carefully review the

interconnections between modules.

Ensure that all ports are correctly connected and accounted for.

6. Functional Errors

Description: These errors occur when the synthesized design does not
produce the expected output for given inputs.

Fix:

Simulate the design using testbenches to verify

functionality. Review the logic to ensure it

matches the intended algorithm.

Use assertions and formal verification tools to catch discrepancies.

7. Optimization Errors

Description: Errors can arise from overly aggressive optimization that alters

the intended functionality. Fix:

Review optimization settings in the synthesis tool.

Disable certain optimizations that may lead to functional changes and re-
synthesize.

8. Tool-Specific Errors

Description: These are errors specific to the synthesis tool being used, such
as licensing issues, bugs, or compatibility problems with the design files.

Fix:

Check the tool documentation for known issues and updates.

Ensure that you are using the correct version of the tool compatible with

your design files. Contact support for assistance with tool-specific

issues.

Real issue

Unresolved reference at elab stage in which module is missing and its logic
definition is also missing :-

Solution :- suppose there is Module say cvp_mme and its missing out design
we can add lib and lef to particular module so unresolved reference
resolved

As if we get unresolved reference then linking is not proper to our design it

fails . As module is not linked to sub module .

Logic of level is high in our design :-

Reason :- As in datapath combinal cell is taking more delay as result setup

is violate when clock reach to endpoint .
So how many number of cells is required in combination cell so that our setup
is not violate. As in synthesis we have to reduce setup violation.

Solution :- Replace lvt cells by hvt cells .

Which cell is taking more delay swap it lower drive strength

Upf cells is missing :- In synthesis some upf cells were

missing we can do Report_lp_ cells

So it report which cell is missing and we inform to upf power team so that
they will update in upf .
Sta :-

Issues seen in sta :-

1. In pre layout unlocked flop I seen in my design. So register is not

getting clock it coming from source but in between it doesn't reach to
particular pin of flop

Solution:- when u trace back through get_chain_selection

Then I found there is exception is applied on that path where

clock is not reaching... May be set_disable_timing or

set_false_path is applied .on that particular path So thats why it

is getting unclocked register

2. Bolna ki unconstrained endpoint I seen bolna if we solved

unclocked then unconstrained endpoint also gone .

Means unconstrained we are getting because proper constraint nhi milta

endpoint pe .

So is liye batata hai unconstrained endpoint.

Divide by 1 circuit create_generate_clock -combinational main use krte hai

Kyuki humko combinational path ke through generate clock dena padta hai
toh agar koi si frequency denge divide by 1 toh woh whi frequency output
tak jayegi through combinational cells

Cross-talk affects both Setup and Hold, just that depends on both the signals
switching direction. Hold may get affected if both switches in the same
direction & Setup gets affected if both switches in the opposite direction