RM0486

Reference manual
STM32N647/657xx Arm®-based 32-bit MCUs

Introduction
This document is addressed to application developers. It provides complete information on
how to use the STM32N647xx and STM32N657xx (referred to as STM32N6x7xx)
microcontrollers memory and peripherals.
For ordering information, mechanical and electrical device characteristics, refer to the
datasheet.

For information on the Arm® Cortex®-M55 core, refer to the corresponding Arm® Technical
Reference Manual available on [Link]
STM32N6x7xx microcontrollers include ST state-of-the-art patented technology.

Related documents
• STM32N647/657xx datasheet (DS14791)
• STM32 Cortex®-M55 MCUs programming manual (PM0273)
• UM3234 “How to proceed with boot ROM on STM32N6 MCUs”
• STM32N6xx MCU errata sheet (ES0621)

January 2025 RM0486 Rev 2 1/4691

[Link] 1
Contents RM0486

Contents

1 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

1.1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
1.2 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
1.3 Register reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
1.4 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
1.5 Availability of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

2 Memory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

2.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
2.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
2.1.2 Bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
2.2 Bus network-on-chip (NoC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
2.2.1 STNoC AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
2.2.2 NPU_NIC network interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
2.2.3 Multi-layer AHB interconnect (AHBM) . . . . . . . . . . . . . . . . . . . . . . . . . 161
2.3 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
2.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
2.3.2 Memory map and register boundary addresses . . . . . . . . . . . . . . . . . 163

3 System security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

3.1 Key security features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
3.2 Secure boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
3.3 Secure provisioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
3.4 Temporal isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
3.5 Resource isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
3.5.1 Trustzone filtering using IDAU/SAU . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
3.5.2 Privileged OS-controlled isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
3.5.3 RIF infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
3.5.4 Multi-tenancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
3.5.5 NPU timeslicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
3.5.6 NPU cache (CACHEAXI) management . . . . . . . . . . . . . . . . . . . . . . . . 187
3.5.7 Memory firewalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
3.5.8 RIF-aware peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

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3.6 Secure storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

3.6.1 Battery backup registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
3.6.2 Secure RAM and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
3.6.3 Fuse secrets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
3.6.4 Hardware key management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
3.6.5 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
3.7 Tamper detection and response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
3.8 Crypto engines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
3.8.1 Accelerators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
3.8.2 Memory cipher engine (MCE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
3.8.3 NPU encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
3.9 Access controlled debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

4 Boot and security control (BSEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
4.2 BSEC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
4.3 BSEC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
4.3.1 BSEC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
4.3.2 BSEC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
4.3.3 BSEC reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
4.3.4 Organization and use of fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
4.3.5 Operations on fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
4.3.6 BSEC read and programming status reporting . . . . . . . . . . . . . . . . . . 205
4.3.7 Lifecycle management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
4.3.8 Epoch registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
4.3.9 BSEC local access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
4.3.10 Temporal isolation in BSEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
4.3.11 BSEC debug and trace control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
4.3.12 Device features control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
4.3.13 Scratch registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
4.3.14 JTAG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
4.3.15 STM32 root hardware unique key (RHUK) . . . . . . . . . . . . . . . . . . . . . 210
4.3.16 BSEC error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
4.3.17 BSEC tamper response mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . 211
4.4 BSEC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
4.5 BSEC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

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4.5.1 BSEC fuse word w value register (BSEC_FVRw) . . . . . . . . . . . . . . . . 212

4.5.2 BSEC sticky programming lock register x (BSEC_SPLOCKx) . . . . . . 213
4.5.3 BSEC sticky write lock register x (BSEC_SWLOCKx) . . . . . . . . . . . . . 213
4.5.4 BSEC sticky reload lock register x (BSEC_SRLOCKx) . . . . . . . . . . . . 214
4.5.5 BSEC OTP valid register x (BSEC_OTPVLDRx) . . . . . . . . . . . . . . . . . 214
4.5.6 BSEC shadowed fuses status register x (BSEC_SFSRx) . . . . . . . . . . 215
4.5.7 BSEC OTP control register (BSEC_OTPCR) . . . . . . . . . . . . . . . . . . . 215
4.5.8 BSEC write data register (BSEC_WDR) . . . . . . . . . . . . . . . . . . . . . . . 216
4.5.9 BSEC scratch register x (BSEC_SCRATCHRx) . . . . . . . . . . . . . . . . . 217
4.5.10 BSEC lock register (BSEC_LOCKR) . . . . . . . . . . . . . . . . . . . . . . . . . . 217
4.5.11 BSEC JTAG input register (BSEC_JTAGINR) . . . . . . . . . . . . . . . . . . . 218
4.5.12 BSEC JTAG output register (BSEC_JTAGOUTR) . . . . . . . . . . . . . . . . 218
4.5.13 BSEC unmap register (BSEC_UNMAPR) . . . . . . . . . . . . . . . . . . . . . . 218
4.5.14 BSEC status register (BSEC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
4.5.15 BSEC OTP status register (BSEC_OTPSR) . . . . . . . . . . . . . . . . . . . . 220
4.5.16 BSEC epoch register (BSEC_EPOCHRx) . . . . . . . . . . . . . . . . . . . . . . 221
4.5.17 BSEC epoch selection control register (BSEC_EPOCHSELCR) . . . . 222
4.5.18 BSEC debug control register (BSEC_DBGCR) . . . . . . . . . . . . . . . . . . 222
4.5.19 BSEC AP unlock (BSEC_AP_UNLOCK) . . . . . . . . . . . . . . . . . . . . . . . 223
4.5.20 BSEC HDPL status register (BSEC_HDPLSR) . . . . . . . . . . . . . . . . . . 224
4.5.21 BSEC HDPL control register (BSEC_HDPLCR) . . . . . . . . . . . . . . . . . 224
4.5.22 BSEC next HDPL control register (BSEC_NEXTHDPLCR) . . . . . . . . 225
4.5.23 BSEC write once scratch register x (BSEC_WOSCRx) . . . . . . . . . . . 225
4.5.24 BSEC hot reset count register (BSEC_HRCR) . . . . . . . . . . . . . . . . . . 226
4.5.25 BSEC warm reset count register (BSEC_WRCR) . . . . . . . . . . . . . . . . 226
4.5.26 BSEC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

5 OTP mapping (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

6 Resource isolation framework security controller (RIFSC) . . . . . . . 246

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
6.2 RIFSC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
6.3 RIFSC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
6.3.1 RIFSC reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
6.3.2 RISUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
6.3.3 RCC security settings for RIF-aware peripherals and RAMs . . . . . . . . 247
6.3.4 RIMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

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6.4 RIFSC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

6.4.1 RIFSC RISC slave configuration register x (RIFSC_RISC_CR) . . . . . 249
6.4.2 RIFSC RISC slave security configuration register x
(RIFSC_RISC_SECCFGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
6.4.3 RIFSC RISFC slave privileged register x
(RIFSC_RISC_PRIVCFGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
6.4.4 RIFSC RISC slave resource configuration lock register x
(RIFSC_RISC_RCFGLOCKRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
6.4.5 RIFSC RIMC master configuration register (RIFSC_RIMC_CR) . . . . . 251
6.4.6 RIFSC RIMC master attribute register x (RIFSC_RIMC_ATTRx) . . . . 252
6.4.7 RIFSC peripheral protection status register 0 (RIFSC_PPSR0) . . . . . 252
6.4.8 RIFSC peripheral protection status register 1 (RIFSC_PPSR1) . . . . . 253
6.4.9 RIFSC peripheral protection status register 2 (RIFSC_PPSR2) . . . . . 253
6.4.10 RIFSC peripheral protection status register 3 (RIFSC_PPSR3) . . . . . 253
6.4.11 RIFSC peripheral protection status register 4 (RIFSC_PPSR4) . . . . . 254
6.4.12 RIFSC peripheral protection status register 5 (RIFSC_PPSR5) . . . . . 254
6.4.13 RIFSC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

7 Resource isolation slave unit for address space

protection (full version) (RISAF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
7.1 RISAF introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
7.2 RISAF main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
7.3 RISAF implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
7.4 RISAF functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
7.4.1 RISAF block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
7.4.2 RISAF internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
7.4.3 RISAF reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
7.4.4 RISAF address space management . . . . . . . . . . . . . . . . . . . . . . . . . . 259
7.4.5 RISAF programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
7.4.6 RISAF runtime modification of region or subregion configuration . . . . 261
7.4.7 Managing illegal accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
7.5 RISAF registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
7.5.1 RISAF configuration register (RISAF_CR) . . . . . . . . . . . . . . . . . . . . . 263
7.5.2 RISAF illegal access status register (RISAF_IASR) . . . . . . . . . . . . . . 263
7.5.3 RISAF illegal access clear register (RISAF_IACR) . . . . . . . . . . . . . . . 264
7.5.4 RISAF illegal access error status register (RISAF_IAESR) . . . . . . . . . 264
7.5.5 RISAF illegal address register (RISAF_IADDR) . . . . . . . . . . . . . . . . . 265
7.5.6 RISAF region x configuration register (RISAF_REGx_CFGR) . . . . . . 265

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7.5.7 RISAF region x start-address register (RISAF_REGx_STARTR) . . . . 266

7.5.8 RISAF region x end-address register (RISAF_REGx_ENDR) . . . . . . . 267
7.5.9 RISAF region x CID configuration register
(RISAF_REGx_CIDCFGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
7.5.10 RISAF region x subregion A configuration register
(RISAF_REGx_ACFGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
7.5.11 RISAF region x subregion A start-address register
(RISAF_REGx_ASTARTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
7.5.12 RISAF region x subregion A end-address register
(RISAF_REGx_AENDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
7.5.13 RISAF region x subregion A nested mode register
(RISAF_REGx_ANESTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
7.5.14 RISAF region x subregion B configuration register
(RISAF_REGx_BCFGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
7.5.15 RISAF region x subregion B start-address register
(RISAF_REGx_BSTARTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
7.5.16 RISAF region x subregion B end-address register
(RISAF_REGx_BENDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
7.5.17 RISAF region x subregion B nested mode register
(RISAF_REGx_BNESTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
7.5.18 RISAF register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

8 Illegal access controller (IAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

8.1 IAC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
8.2 IAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
8.3 IAC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
8.4 IAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
8.4.1 IAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
8.4.2 IAC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
8.4.3 IAC reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
8.4.4 IAC use in RIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
8.4.5 IAC management by trusted application . . . . . . . . . . . . . . . . . . . . . . . 280
8.5 IAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
8.6 IAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
8.6.1 IAC interrupt enable register x (IAC_IERx) . . . . . . . . . . . . . . . . . . . . . 281
8.6.2 IAC interrupt status register x (IAC_ISRx) . . . . . . . . . . . . . . . . . . . . . . 281
8.6.3 IAC interrupt clear register x (IAC_ICRx) . . . . . . . . . . . . . . . . . . . . . . . 282
8.6.4 IAC ILAC input status register x (IAC_IISRx) . . . . . . . . . . . . . . . . . . . 282
8.6.5 IAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

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9 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

9.1 Boot after system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
9.1.1 Flash boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
9.1.2 Serial boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
9.1.3 Development boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
9.2 Boot from a low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

10 SRAM configuration controller (RAMCFG) . . . . . . . . . . . . . . . . . . . . . 286

10.1 RAMCFG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
10.2 RAMCFG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
10.3 RAMCFG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
10.3.1 Internal SRAM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
10.3.2 FLEXRAM control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
10.3.3 ECC (BKPSRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
10.4 RAMCFG low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
10.5 RAMCFG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
10.6 RAMCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
10.6.1 RAMCFG AXISRAM1 control register (RAMCFG_AXISRAM1CR) . . . 293
10.6.2 RAMCFG AXISRAMx interrupt status register
(RAMCFG_AXISRAMxISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
10.6.3 RAMCFG AXISRAMx erase key register
(RAMCFG_AXISRAMxERKEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
10.6.4 RAMCFG AXISRAMx control register (RAMCFG_AXISRAMxCR) . . . 294
10.6.5 RAMCFG AHBSRAMx control register (RAMCFG_AHBSRAMxCR) . 295
10.6.6 RAMCFG AHBSRAMx interrupt status register
(RAMCFG_AHBSRAMxISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
10.6.7 RAMCFG AHBSRAMx erase key register
(RAMCFG_AHBSRAMxERKEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
10.6.8 RAMCFG VENCRAM control register (RAMCFG_VENCRAMCR) . . . 296
10.6.9 RAMCFG VENCRAM interrupt status register
(RAMCFG_VENCRAMISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
10.6.10 RAMCFG VENCRAM erase key register
(RAMCFG_VENCRAMERKEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
10.6.11 RAMCFG BKPSRAM control register (RAMCFG_BKPSRAMCR) . . . 298
10.6.12 RAMCFG BKPSRAM interrupt enable register
(RAMCFG_BKPSRAMIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
10.6.13 RAMCFG BKPSRAM interrupt status register
(RAMCFG_BKPSRAMISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

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10.6.14 RAMCFG BKPSRAM single error address register

(RAMCFG_BKPSRAMESEAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
10.6.15 RAMCFG BKPSRAM double error address register
(RAMCFG_BKPSRAMEDEAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
10.6.16 RAMCFG BKPSRAM interrupt clear register
(RAMCFG_BKPSRAMICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
10.6.17 RAMCFG BKPSRAM ECC key register
(RAMCFG_BKPSRAMECCKEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
10.6.18 RAMCFG BKPSRAM erase key register
(RAMCFG_BKPSRAMERKEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
10.6.19 RAMCFG FLEXRAM control register
(RAMCFG_FLEXRAMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
10.6.20 RAMCFG FLEXRAM interrupt status register
(RAMCFG_FLEXRAMISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
10.6.21 RAMCFG FLEXRAM erase key register
(RAMCFG_FLEXRAMERKEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
10.6.22 RAMCFG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

11 Texture cache (ICACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

11.1 ICACHE introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
11.2 ICACHE main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
11.3 ICACHE implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
11.4 ICACHE functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
11.4.1 ICACHE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
11.4.2 ICACHE reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
11.4.3 ICACHE TAG memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
11.4.4 Direct-mapped ICACHE (1-way cache) . . . . . . . . . . . . . . . . . . . . . . . . 310
11.4.5 ICACHE enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
11.4.6 Cacheable and noncacheable traffic . . . . . . . . . . . . . . . . . . . . . . . . . . 311
11.4.7 Cacheable accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
11.4.8 ICACHE maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
11.4.9 ICACHE performance monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
11.4.10 ICACHE boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
11.5 ICACHE low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
11.6 ICACHE error management and interrupts . . . . . . . . . . . . . . . . . . . . . . 314
11.7 ICACHE registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
11.7.1 ICACHE control register (ICACHE_CR) . . . . . . . . . . . . . . . . . . . . . . . 314
11.7.2 ICACHE status register (ICACHE_SR) . . . . . . . . . . . . . . . . . . . . . . . . 315
11.7.3 ICACHE interrupt enable register (ICACHE_IER) . . . . . . . . . . . . . . . . 316

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11.7.4 ICACHE flag clear register (ICACHE_FCR) . . . . . . . . . . . . . . . . . . . . 316

11.7.5 ICACHE hit monitor register (ICACHE_HMONR) . . . . . . . . . . . . . . . . 317
11.7.6 ICACHE miss monitor register (ICACHE_MMONR) . . . . . . . . . . . . . . 317
11.7.7 ICACHE register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

12 AXI cache (CACHEAXI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

12.1 CACHEAXI introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
12.2 CACHEAXI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
12.3 CACHEAXI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
12.4 CACHEAXI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
12.4.1 CACHEAXI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
12.4.2 CACHEAXI reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
12.4.3 CACHEAXI TAG memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
12.4.4 CACHEAXI enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
12.4.5 Cacheable and noncacheable AXI traffic to slave cache port . . . . . . . 327
12.4.6 Cacheable accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
12.4.7 AXI traffic to master port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
12.4.8 AXI traffic to slave SRAM port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
12.4.9 CACHEAXI security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
12.4.10 CACHEAXI maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
12.4.11 CACHEAXI performance monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . 332
12.4.12 CACHEAXI boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
12.5 CACHEAXI low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
12.6 CACHEAXI error management and interrupts . . . . . . . . . . . . . . . . . . . . 333
12.7 CACHEAXI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
12.7.1 CACHEAXI control register 1 (CACHEAXI_CR1) . . . . . . . . . . . . . . . . 335
12.7.2 CACHEAXI status register (CACHEAXI_SR) . . . . . . . . . . . . . . . . . . . 336
12.7.3 CACHEAXI interrupt enable register (CACHEAXI_IER) . . . . . . . . . . . 337
12.7.4 CACHEAXI flag clear register (CACHEAXI_FCR) . . . . . . . . . . . . . . . . 338
12.7.5 CACHEAXI read-hit monitor register (CACHEAXI_RHMONR) . . . . . . 339
12.7.6 CACHEAXI read-miss monitor register (CACHEAXI_RMMONR) . . . . 339
12.7.7 CACHEAXI read-allocate miss monitor register
(CACHEAXI_RAMMONR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
12.7.8 CACHEAXI eviction monitor register (CACHEAXI_EVIMONR) . . . . . . 340
12.7.9 CACHEAXI write-hit monitor register (CACHEAXI_WHMONR) . . . . . 340
12.7.10 CACHEAXI write-miss monitor register (CACHEAXI_WMMONR) . . . 340

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12.7.11 CACHEAXI write-allocate miss monitor register

(CACHEAXI_WAMMONR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
12.7.12 CACHEAXI write-through monitor register (CACHEAXI_WTMONR) . 341
12.7.13 CACHEAXI control register 2 (CACHEAXI_CR2) . . . . . . . . . . . . . . . . 341
12.7.14 CACHEAXI command range start address register
(CACHEAXI_CMDRSADDRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
12.7.15 CACHEAXI command range end address register
(CACHEAXI_CMDREADDRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
12.7.16 CACHEAXI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

13 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

13.1 PWR introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
13.2 PWR main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
13.3 PWR block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
13.3.1 PWR pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
13.4 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
13.4.1 System supply startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
13.4.2 Core domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
13.4.3 PWR external supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
13.4.4 Backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
13.4.5 Retention domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
13.4.6 Analog supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
13.5 Power supply supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
13.5.1 Power-on reset (POR)/power-down reset (PDR) . . . . . . . . . . . . . . . . . 359
13.5.2 Brownout reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
13.5.3 Vdda18pmu_ok reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
13.5.4 Vddcore_ok reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
13.5.5 VDDCORE monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
13.5.6 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . 362
13.5.7 Peripheral voltage monitoring (PVM) . . . . . . . . . . . . . . . . . . . . . . . . . . 363
13.5.8 Battery voltage thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
13.5.9 Temperature thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
13.6 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
13.6.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
13.6.2 Voltage scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
13.6.3 Power management examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
13.7 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

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13.7.1 Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375

13.7.2 Controlling peripheral clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
13.7.3 Entering low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
13.7.4 Exiting low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
13.7.5 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
13.7.6 Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
13.7.7 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
13.7.8 Power mode output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
13.8 PWR security and privileged protection . . . . . . . . . . . . . . . . . . . . . . . . . 381
13.8.1 Secure/nonsecure access filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
13.8.2 Privileged/unprivileged access filtering . . . . . . . . . . . . . . . . . . . . . . . . 383
13.9 PWR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
13.9.1 PWR control register 1 (PWR_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 383
13.9.2 PWR control register 2 (PWR_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 384
13.9.3 PWR control register 3 (PWR_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . 385
13.9.4 PWR control register 4 (PWR_CR4) . . . . . . . . . . . . . . . . . . . . . . . . . . 385
13.9.5 PWR voltage scaling control register (PWR_VOSCR) . . . . . . . . . . . . 386
13.9.6 PWR backup domain control register 1 (PWR_BDCR1) . . . . . . . . . . . 387
13.9.7 PWR backup domain control register 2 (PWR_BDCR2) . . . . . . . . . . . 388
13.9.8 PWR disable backup protection control register (PWR_DBPCR) . . . . 389
13.9.9 PWR CPU control register (PWR_CPUCR) . . . . . . . . . . . . . . . . . . . . 389
13.9.10 PWR supply voltage monitoring control register 1 (PWR_SVMCR1) . 390
13.9.11 PWR supply voltage monitoring control register 2 (PWR_SVMCR2) . 392
13.9.12 PWR supply voltage monitoring control register 3 (PWR_SVMCR3) . 393
13.9.13 PWR wake-up clear register (PWR_WKUPCR) . . . . . . . . . . . . . . . . . 395
13.9.14 PWR wake-up status register (PWR_WKUPSR) . . . . . . . . . . . . . . . . . 396
13.9.15 PWR wake-up enable and polarity register (PWR_WKUPEPR) . . . . . 397
13.9.16 PWR security configuration register (PWR_SECCFGR) . . . . . . . . . . . 399
13.9.17 PWR privilege configuration register (PWR_PRIVCFGR) . . . . . . . . . . 400
13.9.18 PWR debug control register 1 (PWR_CRCFG1) . . . . . . . . . . . . . . . . . 403
13.9.19 PWR debug control register 2 (PWR_CRCFG2) . . . . . . . . . . . . . . . . . 404
13.9.20 PWR Debug control register 3 (PWR_CRCFG3) . . . . . . . . . . . . . . . . 404
13.9.21 PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

14 Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409

14.1 RCC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
14.2 RCC power domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409

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14.3 RCC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410

14.4 RCC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
14.5 Functional description of RCC reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
14.5.1 Reset from the PWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
14.5.2 System and application resets (sys_rst, nreset_rstn) . . . . . . . . . . . . . 413
14.5.3 NRST reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
14.5.4 Low-power mode security reset (lpwr_rst) . . . . . . . . . . . . . . . . . . . . . . 414
14.5.5 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
14.5.6 CoreSight debug reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
14.5.7 Option-byte loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
14.5.8 Reset of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
14.5.9 Reset pulse control (RPCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
14.5.10 Reset coverage summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
14.5.11 Reset source identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
14.5.12 Power-on and wake-up sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
14.6 Functional description of RCC clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
14.6.1 Clock naming convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
14.6.2 Oscillator description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
14.6.3 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
14.6.4 Clock output generation (MCO1/MCO2) . . . . . . . . . . . . . . . . . . . . . . . 433
14.6.5 PLL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
14.6.6 System clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
14.6.7 Clock generation in Stop and Standby modes . . . . . . . . . . . . . . . . . . . 440
14.6.8 Peripheral clock distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
14.6.9 General clock concept overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
14.6.10 Peripheral allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
14.6.11 Peripheral clock-gating control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
14.6.12 CPU and bus matrix clock-gating control . . . . . . . . . . . . . . . . . . . . . . . 469
14.6.13 Low-power emulation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
14.7 RCC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
14.8 RCC application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
14.8.1 HSE crystal auto-detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
14.8.2 Calibration and clock frequency measurement using TIMx . . . . . . . . . 472
14.8.3 Clock monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
14.8.4 Clock frequency limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
14.9 RCC security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

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14.9.1 Internal register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

14.9.2 Internal register write-protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
14.10 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
14.10.1 RCC control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
14.10.2 RCC status register (RCC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
14.10.3 RCC Stop mode control register (RCC_STOPCR) . . . . . . . . . . . . . . . 479
14.10.4 RCC configuration register 1 (RCC_CFGR1) . . . . . . . . . . . . . . . . . . . 480
14.10.5 RCC configuration register 2 (RCC_CFGR2) . . . . . . . . . . . . . . . . . . . 481
14.10.6 RCC backup domain protection register (RCC_BDCR) . . . . . . . . . . . 483
14.10.7 RCC reset status register for hardware (RCC_HWRSR) . . . . . . . . . . 484
14.10.8 RCC reset register (RCC_RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
14.10.9 RCC LSE configuration register (RCC_LSECFGR) . . . . . . . . . . . . . . 487
14.10.10 RCC MSI configuration register (RCC_MSICFGR) . . . . . . . . . . . . . . . 488
14.10.11 RCC HSI configuration register (RCC_HSICFGR) . . . . . . . . . . . . . . . 489
14.10.12 RCC HSI monitor control register (RCC_HSIMCR) . . . . . . . . . . . . . . . 490
14.10.13 RCC HSI monitor status register (RCC_HSIMSR) . . . . . . . . . . . . . . . 490
14.10.14 RCC HSE configuration register (RCC_HSECFGR) . . . . . . . . . . . . . . 491
14.10.15 RCC PLL1 configuration register 1 (RCC_PLL1CFGR1) . . . . . . . . . . 492
14.10.16 RCC PLL1 configuration register 2 (RCC_PLL1CFGR2) . . . . . . . . . . 493
14.10.17 RCC PLL1 configuration register 3 (RCC_PLL1CFGR3) . . . . . . . . . . 494
14.10.18 RCC PLL2 configuration register 1 (RCC_PLL2CFGR1) . . . . . . . . . . 495
14.10.19 RCC PLL2 configuration register 2 (RCC_PLL2CFGR2) . . . . . . . . . . 496
14.10.20 RCC PLL2 configuration register 3 (RCC_PLL2CFGR3) . . . . . . . . . . 497
14.10.21 RCC PLL3 configuration register 1 (RCC_PLL3CFGR1) . . . . . . . . . . 498
14.10.22 RCC PLL3 configuration register 2 (RCC_PLL3CFGR2) . . . . . . . . . . 499
14.10.23 RCC PLL3 configuration register 3 (RCC_PLL3CFGR3) . . . . . . . . . . 500
14.10.24 RCC PLL4 configuration register 1 (RCC_PLL4CFGR1) . . . . . . . . . . 501
14.10.25 RCC PLL4 configuration register 2 (RCC_PLL4CFGR2) . . . . . . . . . . 502
14.10.26 RCC PLL4 configuration register 3 (RCC_PLL4CFGR3) . . . . . . . . . . 502
14.10.27 RCC IC1 configuration register (RCC_IC1CFGR) . . . . . . . . . . . . . . . . 504
14.10.28 RCC IC2 configuration register (RCC_IC2CFGR) . . . . . . . . . . . . . . . . 505
14.10.29 RCC IC3 configuration register (RCC_IC3CFGR) . . . . . . . . . . . . . . . . 506
14.10.30 RCC IC4 configuration register (RCC_IC4CFGR) . . . . . . . . . . . . . . . . 506
14.10.31 RCC IC5 configuration register (RCC_IC5CFGR) . . . . . . . . . . . . . . . . 507
14.10.32 RCC IC6 configuration register (RCC_IC6CFGR) . . . . . . . . . . . . . . . . 508
14.10.33 RCC IC7 configuration register (RCC_IC7CFGR) . . . . . . . . . . . . . . . . 509
14.10.34 RCC IC8 configuration register (RCC_IC8CFGR) . . . . . . . . . . . . . . . . 509

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14.10.35 RCC IC9 configuration register (RCC_IC9CFGR) . . . . . . . . . . . . . . . . 510

14.10.36 RCC IC10 configuration register (RCC_IC10CFGR) . . . . . . . . . . . . . . 511
14.10.37 RCC IC11 configuration register (RCC_IC11CFGR) . . . . . . . . . . . . . . 511
14.10.38 RCC IC12 configuration register (RCC_IC12CFGR) . . . . . . . . . . . . . . 512
14.10.39 RCC IC13 configuration register (RCC_IC13CFGR) . . . . . . . . . . . . . . 513
14.10.40 RCC IC14 configuration register (RCC_IC14CFGR) . . . . . . . . . . . . . . 514
14.10.41 RCC IC15 configuration register (RCC_IC15CFGR) . . . . . . . . . . . . . . 515
14.10.42 RCC IC16 configuration register (RCC_IC16CFGR) . . . . . . . . . . . . . . 515
14.10.43 RCC IC17 configuration register (RCC_IC17CFGR) . . . . . . . . . . . . . . 516
14.10.44 RCC IC18 configuration register (RCC_IC18CFGR) . . . . . . . . . . . . . . 517
14.10.45 RCC IC19 configuration register (RCC_IC19CFGR) . . . . . . . . . . . . . . 517
14.10.46 RCC IC20 configuration register (RCC_IC20CFGR) . . . . . . . . . . . . . . 518
14.10.47 RCC clock-source interrupt enable register (RCC_CIER) . . . . . . . . . . 519
14.10.48 RCC clock-source interrupt flag register (RCC_CIFR) . . . . . . . . . . . . 520
14.10.49 RCC clock-source interrupt clear register (RCC_CICR) . . . . . . . . . . . 522
14.10.50 RCC clock configuration for independent peripheral register 1
(RCC_CCIPR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
14.10.51 RCC clock configuration for independent peripheral register 2
(RCC_CCIPR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
14.10.52 RCC clock configuration for independent peripheral register 3
(RCC_CCIPR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
14.10.53 RCC clock configuration for independent peripheral register 4
(RCC_CCIPR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
14.10.54 RCC clock configuration for independent peripheral register 5
(RCC_CCIPR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
14.10.55 RCC clock configuration for independent peripheral register 6
(RCC_CCIPR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
14.10.56 RCC clock configuration for independent peripheral register 7
(RCC_CCIPR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
14.10.57 RCC clock configuration for independent peripheral register 8
(RCC_CCIPR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
14.10.58 RCC clock configuration for independent peripheral register 9
(RCC_CCIPR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
14.10.59 RCC clock configuration for independent peripheral register 12
(RCC_CCIPR12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
14.10.60 RCC clock configuration for independent peripheral register 13
(RCC_CCIPR13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
14.10.61 RCC clock configuration for independent peripheral register 14
(RCC_CCIPR14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
14.10.62 RCC miscellaneous configurations reset register
(RCC_MISCRSTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

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14.10.63 RCC embedded memories reset register (RCC_MEMRSTR) . . . . . . . 543

14.10.64 RCC AHB1 reset register (RCC_AHB1RSTR) . . . . . . . . . . . . . . . . . . 545
14.10.65 RCC AHB2 reset register (RCC_AHB2RSTR) . . . . . . . . . . . . . . . . . . 546
14.10.66 RCC AHB3 reset register (RCC_AHB3RSTR) . . . . . . . . . . . . . . . . . . 547
14.10.67 RCC AHB4 reset register (RCC_AHB4RSTR) . . . . . . . . . . . . . . . . . . 548
14.10.68 RCC AHB5 reset register (RCC_AHB5RSTR) . . . . . . . . . . . . . . . . . . 550
14.10.69 RCC APB1L reset register (RCC_APB1LRSTR) . . . . . . . . . . . . . . . . . 553
14.10.70 RCC APB1H reset register (RCC_APB1HRSTR) . . . . . . . . . . . . . . . . 557
14.10.71 RCC APB2 reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . . . . . . 558
14.10.72 RCC APB4L reset register (RCC_APB4LRSTR) . . . . . . . . . . . . . . . . . 560
14.10.73 RCC APB4H reset register (RCC_APB4HRSTR) . . . . . . . . . . . . . . . . 562
14.10.74 RCC APB5 reset register (RCC_APB5RSTR) . . . . . . . . . . . . . . . . . . . 563
14.10.75 RCC IC dividers enable register (RCC_DIVENR) . . . . . . . . . . . . . . . . 564
14.10.76 RCC embedded buses enable register (RCC_BUSENR) . . . . . . . . . . 567
14.10.77 RCC miscellaneous configurations enable register
(RCC_MISCENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
14.10.78 RCC embedded memories enable register (RCC_MEMENR) . . . . . . 570
14.10.79 RCC AHB1 enable register (RCC_AHB1ENR) . . . . . . . . . . . . . . . . . . 572
14.10.80 RCC AHB2 enable register (RCC_AHB2ENR) . . . . . . . . . . . . . . . . . . 572
14.10.81 RCC AHB3 enable register (RCC_AHB3ENR) . . . . . . . . . . . . . . . . . . 573
14.10.82 RCC AHB4 enable register (RCC_AHB4ENR) . . . . . . . . . . . . . . . . . . 574
14.10.83 RCC AHB5 enable register (RCC_AHB5ENR) . . . . . . . . . . . . . . . . . . 577
14.10.84 RCC APB1L enable register (RCC_APB1LENR) . . . . . . . . . . . . . . . . 581
14.10.85 RCC APB1H enable register (RCC_APB1HENR) . . . . . . . . . . . . . . . . 584
14.10.86 RCC APB2 enable register (RCC_APB2ENR) . . . . . . . . . . . . . . . . . . 585
14.10.87 RCC APB3 enable register (RCC_APB3ENR) . . . . . . . . . . . . . . . . . . 588
14.10.88 RCC APB4L enable register (RCC_APB4LENR) . . . . . . . . . . . . . . . . 588
14.10.89 RCC APB4H enable register (RCC_APB4HENR) . . . . . . . . . . . . . . . . 590
14.10.90 RCC APB5 enable register (RCC_APB5ENR) . . . . . . . . . . . . . . . . . . 591
14.10.91 RCC embedded buses sleep enable register (RCC_BUSLPENR) . . . 592
14.10.92 RCC miscellaneous configurations sleep enable register
(RCC_MISCLPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
14.10.93 RCC embedded memories sleep enable register
(RCC_MEMLPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
14.10.94 RCC AHB1 sleep enable register (RCC_AHB1LPENR) . . . . . . . . . . . 596
14.10.95 RCC AHB2 sleep enable register (RCC_AHB2LPENR) . . . . . . . . . . . 596
14.10.96 RCC AHB3 sleep enable register (RCC_AHB3LPENR) . . . . . . . . . . . 597
14.10.97 RCC AHB4 sleep enable register (RCC_AHB4LPENR) . . . . . . . . . . . 598

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14.10.98 RCC AHB5 sleep enable register (RCC_AHB5LPENR) . . . . . . . . . . . 601

14.10.99 RCC APB1L sleep enable register (RCC_APB1LLPENR) . . . . . . . . . 604
14.10.100RCC APB1H sleep enable register (RCC_APB1HLPENR) . . . . . . . . 608
14.10.101RCC APB2 sleep enable register (RCC_APB2LPENR) . . . . . . . . . . . 609
14.10.102RCC APB3 sleep enable register (RCC_APB3LPENR) . . . . . . . . . . . 611
14.10.103RCC APB4L sleep enable register (RCC_APB4LLPENR) . . . . . . . . . 612
14.10.104RCC APB4H sleep enable register (RCC_APB4HLPENR) . . . . . . . . 614
14.10.105RCC APB5 sleep enable register (RCC_APB5LPENR) . . . . . . . . . . . 615
14.10.106RCC reset duration control register (RCC_RDCR) . . . . . . . . . . . . . . . 616
14.10.107RCC oscillator secure configuration register 0 (RCC_SECCFGR0) . . 617
14.10.108RCC oscillator privilege configuration register 0
(RCC_PRIVCFGR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
14.10.109RCC oscillator lock configuration register 0 (RCC_LOCKCFGR0) . . . 618
14.10.110RCC oscillator public configuration register 0 (RCC_PUBCFGR0) . . . 619
14.10.111RCC PLL secure configuration register 1 (RCC_SECCFGR1) . . . . . . 620
14.10.112RCC PLL privilege configuration register 1 (RCC_PRIVCFGR1) . . . . 621
14.10.113RCC PLL lock configuration register 1 (RCC_LOCKCFGR1) . . . . . . . 621
14.10.114RCC PLL public configuration register1 (RCC_PUBCFGR1) . . . . . . . 622
14.10.115RCC divider secure configuration register 2 (RCC_SECCFGR2) . . . . 623
14.10.116RCC divider privilege configuration register 2 (RCC_PRIVCFGR2) . . 625
14.10.117RCC divider lock configuration register 2 (RCC_LOCKCFGR2) . . . . . 627
14.10.118RCC divider public configuration register 2 (RCC_PUBCFGR2) . . . . 630
14.10.119RCC system secure configuration register 3 (RCC_SECCFGR3) . . . 632
14.10.120RCC system privilege configuration register3 (RCC_PRIVCFGR3) . . 633
14.10.121RCC system lock configuration register 3 (RCC_LOCKCFGR3) . . . . 634
14.10.122RCC system public configuration register 3 (RCC_PUBCFGR3) . . . . 635
14.10.123RCC bus secure configuration register 4 (RCC_SECCFGR4) . . . . . . 635
14.10.124RCC bus privilege configuration register 4 (RCC_PRIVCFGR4) . . . . 637
14.10.125RCC bus lock configuration register 4 (RCC_LOCKCFGR4) . . . . . . . 639
14.10.126RCC bus public configuration register 4 (RCC_PUBCFGR4) . . . . . . . 640
14.10.127RCC bus public configuration register 4 (RCC_PUBCFGR5) . . . . . . . 642
14.10.128RCC control set register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . 644
14.10.129RCC Stop mode configuration set register (RCC_STOPCSR) . . . . . . 645
14.10.130RCC miscellaneous reset register (RCC_MISCRSTSR) . . . . . . . . . . 645
14.10.131RCC memory reset register (RCC_MEMRSTSR) . . . . . . . . . . . . . . . . 646
14.10.132RCC AHB1 reset register (RCC_AHB1RSTSR) . . . . . . . . . . . . . . . . . 647
14.10.133RCC AHB2 reset register (RCC_AHB2RSTSR) . . . . . . . . . . . . . . . . . 647

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14.10.134RCC AHB3 reset register (RCC_AHB3RSTSR) . . . . . . . . . . . . . . . . . 648

14.10.135RCC AHB4 reset register (RCC_AHB4RSTSR) . . . . . . . . . . . . . . . . . 649
14.10.136RCC AHB5 reset register (RCC_AHB5RSTSR) . . . . . . . . . . . . . . . . . 650
14.10.137RCC APB1L reset register (RCC_APB1LRSTSR) . . . . . . . . . . . . . . . 651
14.10.138RCC APB1H reset register (RCC_APB1HRSTSR) . . . . . . . . . . . . . . . 653
14.10.139RCC APB2 reset register (RCC_APB2RSTSR) . . . . . . . . . . . . . . . . . 654
14.10.140RCC APB4L reset register (RCC_APB4LRSTSR) . . . . . . . . . . . . . . . 655
14.10.141RCC APB4H reset register (RCC_APB4HRSTSR) . . . . . . . . . . . . . . . 656
14.10.142RCC APB5 reset register (RCC_APB5RSTSR) . . . . . . . . . . . . . . . . . 656
14.10.143RCC divider enable register (RCC_DIVENSR) . . . . . . . . . . . . . . . . . . 657
14.10.144RCC bus enable register (RCC_BUSENSR) . . . . . . . . . . . . . . . . . . . 658
14.10.145RCC miscellaneous enable register (RCC_MISCENSR) . . . . . . . . . . 659
14.10.146RCC memory enable register (RCC_MEMENSR) . . . . . . . . . . . . . . . 660
14.10.147RCC AHB1 enable register (RCC_AHB1ENSR) . . . . . . . . . . . . . . . . . 661
14.10.148RCC AHB2 enable register (RCC_AHB2ENSR) . . . . . . . . . . . . . . . . . 661
14.10.149RCC AHB3 enable register (RCC_AHB3ENSR) . . . . . . . . . . . . . . . . . 662
14.10.150RCC AHB4 enable register (RCC_AHB4ENSR) . . . . . . . . . . . . . . . . . 663
14.10.151RCC AHB5 enable register (RCC_AHB5ENSR) . . . . . . . . . . . . . . . . . 664
14.10.152RCC APB1L enable register (RCC_APB1LENSR) . . . . . . . . . . . . . . . 665
14.10.153RCC APB1H enable register (RCC_APB1HENSR) . . . . . . . . . . . . . . 667
14.10.154RCC APB2 enable register (RCC_APB2ENSR) . . . . . . . . . . . . . . . . . 668
14.10.155RCC APB3 enable register (RCC_APB3ENSR) . . . . . . . . . . . . . . . . . 669
14.10.156RCC APB4L enable register (RCC_APB4LENSR) . . . . . . . . . . . . . . . 669
14.10.157RCC APB4H enable register (RCC_APB4HENSR) . . . . . . . . . . . . . . 671
14.10.158RCC APB5 enable register (RCC_APB5ENSR) . . . . . . . . . . . . . . . . . 671
14.10.159RCC bus sleep enable register (RCC_BUSLPENSR) . . . . . . . . . . . . 672
14.10.160RCC miscellaneous sleep enable register (RCC_MISCLPENSR) . . . 672
14.10.161RCC memory sleep enable register (RCC_MEMLPENSR) . . . . . . . . 673
14.10.162RCC AHB1 sleep enable register (RCC_AHB1LPENSR) . . . . . . . . . . 674
14.10.163RCC AHB2 sleep enable register (RCC_AHB2LPENSR) . . . . . . . . . . 674
14.10.164RCC AHB3 sleep enable register (RCC_AHB3LPENSR) . . . . . . . . . . 675
14.10.165RCC AHB4 sleep enable register (RCC_AHB4LPENSR) . . . . . . . . . . 676
14.10.166RCC AHB5 sleep enable register (RCC_AHB5LPENSR) . . . . . . . . . . 677
14.10.167RCC APB1L sleep enable register (RCC_APB1LLPENSR) . . . . . . . . 678
14.10.168RCC APB1H sleep enable register (RCC_APB1HLPENSR) . . . . . . . 680
14.10.169RCC APB2 sleep enable register (RCC_APB2LPENSR) . . . . . . . . . . 681
14.10.170RCC APB3 sleep enable register (RCC_APB3LPENSR) . . . . . . . . . . 682

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14.10.171RCC APB4L sleep enable register (RCC_APB4LLPENSR) . . . . . . . . 682

14.10.172RCC APB4H sleep enable register (RCC_APB4HLPENSR) . . . . . . . 684
14.10.173RCC APB5 sleep enable register (RCC_APB5LPENSR) . . . . . . . . . . 684
14.10.174RCC oscillator privilege configuration set register 0
(RCC_PRIVCFGSR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
14.10.175RCC oscillator public configuration set register 0
(RCC_PUBCFGSR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
14.10.176RCC PLL privilege configuration set register 1 (RCC_PRIVCFGSR1) 686
14.10.177RCC PLL public configuration set register 1 (RCC_PUBCFGSR1) . . 687
14.10.178RCC divider privilege configuration set register 2
(RCC_PRIVCFGSR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
14.10.179RCC divider public configuration set register 2
(RCC_PUBCFGSR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
14.10.180RCC system privilege configuration set register 3
(RCC_PRIVCFGSR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
14.10.181RCC system public configuration set register 3 (RCC_PUBCFGSR3) 692
14.10.182RCC privilege configuration set register 4 (RCC_PRIVCFGSR4) . . . 693
14.10.183RCC public configuration set register 4 (RCC_PUBCFGSR4) . . . . . . 694
14.10.184RCC public configuration set register 5 (RCC_PUBCFGSR5) . . . . . . 695
14.10.185RCC control clear register (RCC_CCR) . . . . . . . . . . . . . . . . . . . . . . . 697
14.10.186RCC Stop mode configuration clear register (RCC_STOPCCR) . . . . 697
14.10.187RCC miscellaneous reset clear register (RCC_MISCRSTCR) . . . . . . 698
14.10.188RCC memory reset clear register (RCC_MEMRSTCR) . . . . . . . . . . . 699
14.10.189RCC AHB1 reset clear register (RCC_AHB1RSTCR) . . . . . . . . . . . . 700
14.10.190RCC AHB2 reset clear register (RCC_AHB2RSTCR) . . . . . . . . . . . . 700
14.10.191RCC AHB3 reset clear register (RCC_AHB3RSTCR) . . . . . . . . . . . . 701
14.10.192RCC AHB4 reset clear register (RCC_AHB4RSTCR) . . . . . . . . . . . . 701
14.10.193RCC AHB5 reset clear register (RCC_AHB5RSTCR) . . . . . . . . . . . . 702
14.10.194RCC APB1L reset clear register (RCC_APB1LRSTCR) . . . . . . . . . . . 704
14.10.195RCC APB1H reset clear register (RCC_APB1HRSTCR) . . . . . . . . . . 706
14.10.196RCC APB2 reset clear register (RCC_APB2RSTCR) . . . . . . . . . . . . . 706
14.10.197RCC APB4L reset clear register (RCC_APB4LRSTCR) . . . . . . . . . . . 708
14.10.198RCC APB4H reset clear register (RCC_APB4HRSTCR) . . . . . . . . . . 709
14.10.199RCC APB5 reset clear register (RCC_APB5RSTCR) . . . . . . . . . . . . . 709
14.10.200RCC divider enable clear register (RCC_DIVENCR) . . . . . . . . . . . . . 710
14.10.201RCC bus enable clear register (RCC_BUSENCR) . . . . . . . . . . . . . . . 711
14.10.202RCC miscellaneous enable clear register (RCC_MISCENCR) . . . . . . 712
14.10.203RCC memory enable clear register (RCC_MEMENCR) . . . . . . . . . . . 712

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14.10.204RCC AHB1 enable clear register (RCC_AHB1ENCR) . . . . . . . . . . . . 713

14.10.205RCC AHB2 enable clear register (RCC_AHB2ENCR) . . . . . . . . . . . . 714
14.10.206RCC AHB3 enable clear register (RCC_AHB3ENCR) . . . . . . . . . . . . 714
14.10.207RCC AHB4 enable clear register (RCC_AHB4ENCR) . . . . . . . . . . . . 715
14.10.208RCC AHB5 enable clear register (RCC_AHB5ENCR) . . . . . . . . . . . . 716
14.10.209RCC APB1L enable clear register (RCC_APB1LENCR) . . . . . . . . . . 718
14.10.210RCC APB1H enable clear register (RCC_APB1HENCR) . . . . . . . . . . 720
14.10.211RCC APB2 enable clear register (RCC_APB2ENCR) . . . . . . . . . . . . 721
14.10.212RCC APB3 enable clear register (RCC_APB3ENCR) . . . . . . . . . . . . 722
14.10.213RCC APB4L enable clear register (RCC_APB4LENCR) . . . . . . . . . . 722
14.10.214RCC APB4H enable clear register (RCC_APB4HENCR) . . . . . . . . . . 723
14.10.215RCC APB5 enable clear register (RCC_APB5ENCR) . . . . . . . . . . . . 724
14.10.216RCC bus sleep enable clear register (RCC_BUSLPENCR) . . . . . . . . 725
14.10.217RCC miscellaneous sleep enable clear register
(RCC_MISCLPENCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
14.10.218RCC memory sleep enable clear register (RCC_MEMLPENCR) . . . . 726
14.10.219RCC AHB1 sleep enable clear register (RCC_AHB1LPENCR) . . . . . 727
14.10.220RCC AHB2 sleep enable clear register (RCC_AHB2LPENCR) . . . . . 727
14.10.221RCC AHB3 sleep enable clear register (RCC_AHB3LPENCR) . . . . . 728
14.10.222RCC AHB4 sleep enable clear register (RCC_AHB4LPENCR) . . . . . 729
14.10.223RCC AHB5 sleep enable clear register (RCC_AHB5LPENCR) . . . . . 730
14.10.224RCC APB1L sleep enable clear register (RCC_APB1LLPENCR) . . . 732
14.10.225RCC APB1H sleep enable clear register (RCC_APB1HLPENCR) . . . 733
14.10.226RCC APB2 sleep enable clear register (RCC_APB2LPENCR) . . . . . 734
14.10.227RCC APB3 sleep enable clear register (RCC_APB3LPENCR) . . . . . 735
14.10.228RCC APB4L sleep enable clear register (RCC_APB4LLPENCR) . . . 736
14.10.229RCC APB4H sleep enable clear register (RCC_APB4HLPENCR) . . . 737
14.10.230RCC APB5 sleep enable clear register (RCC_APB5LPENCR) . . . . . 737
14.10.231RCC oscillator privilege configuration clear register 0
(RCC_PRIVCFGCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
14.10.232RCC oscillator public configuration clear register 0
(RCC_PUBCFGCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
14.10.233RCC PLL privilege configuration clear register 1
(RCC_PRIVCFGCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
14.10.234RCC PLL public configuration clear register 1 (RCC_PUBCFGCR1) . 740
14.10.235RCC divider privilege configuration clear register 2
(RCC_PRIVCFGCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
14.10.236RCC divider public configuration clear register 2
(RCC_PUBCFGCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742

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14.10.237RCC system privilege configuration clear register 3

(RCC_PRIVCFGCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
14.10.238RCC system public configuration clear register 3
(RCC_PUBCFGCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
14.10.239RCC privilege configuration clear register 4 (RCC_PRIVCFGCR4) . . 746
14.10.240RCC public configuration clear register 4 (RCC_PUBCFGCR4) . . . . 748
14.10.241RCC public configuration clear register 4 (RCC_PUBCFGCR5) . . . . 749
14.10.242RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

15 General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
15.2 GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
15.3 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
15.3.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
15.3.2 I/O pin AF multiplexer and mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
15.3.3 I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
15.3.4 I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
15.3.5 I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
15.3.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
15.3.7 I/O AF input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
15.3.8 External interrupt/wake-up lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
15.3.9 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
15.3.10 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
15.3.11 AF configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
15.3.12 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
15.3.13 Using HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . . . . 788
15.3.14 Using GPIO pins in VSW supply domain . . . . . . . . . . . . . . . . . . . . . . . 788
15.3.15 Advanced I/O configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
15.3.16 I/O pin isolation using TrustZone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
15.3.17 I/O pin isolation using privilege . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
15.4 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
15.4.1 GPIO port x mode register (GPIOx_MODER) (x = A to H, N to Q) . . . 791
15.4.2 GPIO port x output type register (GPIOx_OTYPER)
(x =A to H, N to Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
15.4.3 GPIO port x output speed register (GPIOx_OSPEEDR)
(x =A to H, N to Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
15.4.4 GPIO port x pull-up/pull-down register (GPIOx_PUPDR)
(x= A to H, N to Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792

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15.4.5 GPIO port x input data register (GPIOx_IDR) (x = A to H, N to Q) . . . 793

15.4.6 GPIO port x output data register (GPIOx_ODR) (x = A to H, N to Q) . 793
15.4.7 GPIO port x bit set/reset register (GPIOx_BSRR) (x = A to H, N to Q) 794
15.4.8 GPIO port x configuration lock register (GPIOx_LCKR)
(x = A to H, N to Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
15.4.9 GPIO port x AF low register (GPIOx_AFRL) (x = A to H, N to Q) . . . . 796
15.4.10 GPIO port x AF high register (GPIOx_AFRH) (x = A to H, N to Q) . . . 796
15.4.11 GPIO port x bit reset register (GPIOx_BRR) (x = A to H, N to Q) . . . . 797
15.4.12 GPIO port x secure configuration register (GPIOx_SECCFGR)
(x = A to H, N to Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
15.4.13 GPIO port x privileged configuration register (GPIOx_PRIVCFGR)
(x = A to H, N to Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
15.4.14 GPIO port x resource configuration lock register
(GPIOx_RCFGLOCKR) (x = A to H, N to Q) . . . . . . . . . . . . . . . . . . . . 799
15.4.15 GPIO port x delay low register (GPIOx_DELAYRL)
(x = A to H, N to Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
15.4.16 GPIO port x delay high register (GPIOx_DELAYRH)
(x = A to H, N to Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
15.4.17 GPIO port x advanced configuration low register (GPIOx_ADVCFGRL)
(x = A to H, N to Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
15.4.18 GPIO port x advanced configuration high register (GPIOx_ADVCFGRH)
(x =A to H, N to Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
15.4.19 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803

16 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 806

16.0.1 I/O compensation cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
16.1 SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
16.1.1 SYSCFG boot pin control register (SYSCFG_BOOTCR) . . . . . . . . . . 807
16.1.2 SYSCFG Cortex-M55 control register (SYSCFG_CM55CR) . . . . . . . 808
16.1.3 SYSCFG Cortex-M55 TCM control register
(SYSCFG_CM55TCMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
16.1.4 SYSCFG Cortex-CM55 memory RW margin register
(SYSCFG_CM55RWMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
16.1.5 SYSCFG Cortex-M55 SVTOR control register
(SYSCFG_INITSVTORCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
16.1.6 SYSCFG Cortex-M55 NSVTOR control register
(SYSCFG_INITNSVTORCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
16.1.7 SYSCFG Cortex-M55 reset type control register
(SYSCFG_CM55RSTCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
16.1.8 SYSCFG Cortex-M55 P-AHB write posting control register
(SYSCFG_CM55PAHBWPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811

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16.1.9 SYSCFG VENCRAM control register (SYSCFG_VENCRAMCR) . . . . 812

16.1.10 SYSCFG potential tamper reset register
(SYSCFG_POTTAMPRSTCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
16.1.11 SYSCFG NPUNIC QoS control register
(SYSCFG_NPUNICQOSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
16.1.12 SYSCFG AHB-AXI bridge early write response control
register (SYSCFG_ICNEWRCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
16.1.13 SYSCFG ICN clock gating control register (SYSCFG_ICNCGCR) . . . 814
16.1.14 SYSCFG VDDIOx compensation cell control register
(SYSCFG_VDDIOxCCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
16.1.15 SYSCFG VDDIOx compensation cell status register
(SYSCFG_VDDIOxCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
16.1.16 SYSCFG VDD compensation cell control register
(SYSCFG_VDDCCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
16.1.17 SYSCFG VDD compensation cell status register
(SYSCFG_VDDCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
16.1.18 SYSCFG control timer break register (SYSCFG_CBR) . . . . . . . . . . . 817
16.1.19 SYSCFG DMA CID secure control register (SYSCFG_SEC_AIDCR) . 818
16.1.20 SYSCFG FMC retiming logic control register
(SYSCFG_FMC_RETIMECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
16.1.21 SYSCFG NPU RAM interleaving control register
(SYSCFG_NPU_ICNCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
16.1.22 SYSCFG boot pin status register (SYSCFG_BOOTSR) . . . . . . . . . . . 820
16.1.23 SYSCFG AHB write posting address error register
(SYSCFG_AHBWP_ERROR_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
16.1.24 SYSCFG SMPS observable signals through HDP selection
configuration register (SYSCFG_SMPSHDPCR) . . . . . . . . . . . . . . . . 821
16.1.25 SYSCFG DMA CID nonsecure control register
(SYSCFG_SECPRIV_AIDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
16.1.26 SYSCFG device ID register (SYSCFG_DEVICEID) . . . . . . . . . . . . . . 822
16.1.27 SYSCFG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822

17 Peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
17.2 Connection summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826

18 High-performance direct memory access controller (HPDMA) . . . . 827

18.1 HPDMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
18.2 HPDMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
18.3 HPDMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828

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18.3.1 HPDMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828

18.3.2 HPDMA allowed AXI maximum burst length . . . . . . . . . . . . . . . . . . . . 829
18.3.3 HPDMA in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
18.3.4 HPDMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
18.3.5 HPDMA block requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
18.3.6 HPDMA channels with peripheral early termination . . . . . . . . . . . . . . . 834
18.3.7 HPDMA triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
18.4 HPDMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
18.4.1 HPDMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
18.4.2 HPDMA channel state and direct programming without
any linked-list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
18.4.3 HPDMA channel suspend and resume . . . . . . . . . . . . . . . . . . . . . . . . 840
18.4.4 HPDMA channel abort and restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
18.4.5 HPDMA linked-list data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
18.4.6 Linked-list item transfer execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
18.4.7 HPDMA channel state and linked-list programming
in run-to-completion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
18.4.8 HPDMA channel state and linked-list programming
in link step mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
18.4.9 HPDMA channel state and linked-list programming . . . . . . . . . . . . . . 857
18.4.10 HPDMA FIFO-based transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859
18.4.11 HPDMA transfer request and arbitration . . . . . . . . . . . . . . . . . . . . . . . 875
18.4.12 HPDMA triggered transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
18.4.13 HPDMA circular buffering with linked-list programming . . . . . . . . . . . . 880
18.4.14 HPDMA transfer in peripheral flow-control mode . . . . . . . . . . . . . . . . . 882
18.4.15 HPDMA secure/nonsecure channel . . . . . . . . . . . . . . . . . . . . . . . . . . 883
18.4.16 HPDMA privileged/unprivileged channel . . . . . . . . . . . . . . . . . . . . . . . 884
18.4.17 HPDMA error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
18.5 HPDMA in debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
18.6 HPDMA in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
18.7 HPDMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
18.8 HPDMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
18.8.1 HPDMA secure configuration register (HPDMA_SECCFGR) . . . . . . . 888
18.8.2 HPDMA privileged configuration register (HPDMA_PRIVCFGR) . . . . 889
18.8.3 HPDMA configuration lock register (HPDMA_RCFGLOCKR) . . . . . . . 890
18.8.4 HPDMA nonsecure masked interrupt status register
(HPDMA_MISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
18.8.5 HPDMA secure masked interrupt status register (HPDMA_SMISR) . . 891

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18.8.6 HPDMA channel x linked-list base address register

(HPDMA_CxLBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
18.8.7 HPDMA channel x CID register (HPDMA_CxCIDCFGR) . . . . . . . . . . 892
18.8.8 HPDMA channel x semaphore control register
(HPDMA_CxSEMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
18.8.9 HPDMA channel x flag clear register (HPDMA_CxFCR) . . . . . . . . . . . 896
18.8.10 HPDMA channel x status register (HPDMA_CxSR) . . . . . . . . . . . . . . 897
18.8.11 HPDMA channel x control register (HPDMA_CxCR) . . . . . . . . . . . . . . 898
18.8.12 HPDMA channel x transfer register 1 (HPDMA_CxTR1) . . . . . . . . . . . 901
18.8.13 HPDMA channel x transfer register 2 (HPDMA_CxTR2) . . . . . . . . . . . 905
18.8.14 HPDMA channel x block register 1 (HPDMA_CxBR1) . . . . . . . . . . . . 909
18.8.15 HPDMA channel x alternate block register 1 (HPDMA_CxBR1) . . . . . 910
18.8.16 HPDMA channel x source address register (HPDMA_CxSAR) . . . . . . 913
18.8.17 HPDMA channel x destination address register (HPDMA_CxDAR) . . 915
18.8.18 HPDMA channel x transfer register 3 (HPDMA_CxTR3) . . . . . . . . . . . 917
18.8.19 HPDMA channel x block register 2 (HPDMA_CxBR2) . . . . . . . . . . . . 918
18.8.20 HPDMA channel x linked-list address register (HPDMA_CxLLR) . . . . 919
18.8.21 HPDMA channel x alternate linked-list address register
(HPDMA_CxLLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
18.8.22 HPDMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922

19 General purpose direct memory access controller (GPDMA) . . . . . . 925

19.1 GPDMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925
19.2 GPDMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925
19.3 GPDMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
19.3.1 GPDMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
19.3.2 GPDMA in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
19.3.3 GPDMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
19.3.4 GPDMA block requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
19.3.5 GPDMA channels with peripheral early termination . . . . . . . . . . . . . . 932
19.3.6 GPDMA triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
19.4 GPDMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
19.4.1 GPDMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
19.4.2 GPDMA channel state and direct programming without any linked-list 936
19.4.3 GPDMA channel suspend and resume . . . . . . . . . . . . . . . . . . . . . . . . 937
19.4.4 GPDMA channel abort and restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
19.4.5 GPDMA linked-list data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
19.4.6 Linked-list item transfer execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942

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19.4.7 GPDMA channel state and linked-list programming

in run-to-completion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943
19.4.8 GPDMA channel state and linked-list programming in link step mode 946
19.4.9 GPDMA channel state and linked-list programming . . . . . . . . . . . . . . 953
19.4.10 GPDMA FIFO-based transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
19.4.11 GPDMA transfer request and arbitration . . . . . . . . . . . . . . . . . . . . . . . 962
19.4.12 GPDMA triggered transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966
19.4.13 GPDMA circular buffering with linked-list programming . . . . . . . . . . . . 967
19.4.14 GPDMA transfer in peripheral flow-control mode . . . . . . . . . . . . . . . . 969
19.4.15 GPDMA secure/nonsecure channel . . . . . . . . . . . . . . . . . . . . . . . . . . 970
19.4.16 GPDMA privileged/unprivileged channel . . . . . . . . . . . . . . . . . . . . . . . 971
19.4.17 GPDMA error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971
19.5 GPDMA in debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
19.6 GPDMA in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
19.7 GPDMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
19.8 GPDMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
19.8.1 GPDMA secure configuration register (GPDMA_SECCFGR) . . . . . . . 975
19.8.2 GPDMA privileged configuration register (GPDMA_PRIVCFGR) . . . . 976
19.8.3 GPDMA configuration lock register (GPDMA_RCFGLOCKR) . . . . . . . 976
19.8.4 GPDMA nonsecure masked interrupt status register
(GPDMA_MISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
19.8.5 GPDMA secure masked interrupt status register (GPDMA_SMISR) . . 978
19.8.6 GPDMA channel x linked-list base address register
(GPDMA_CxLBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978
19.8.7 GPDMA channel x flag clear register (GPDMA_CxFCR) . . . . . . . . . . 979
19.8.8 GPDMA channel x status register (GPDMA_CxSR) . . . . . . . . . . . . . . 980
19.8.9 GPDMA channel x control register (GPDMA_CxCR) . . . . . . . . . . . . . 981
19.8.10 GPDMA channel x transfer register 1 (GPDMA_CxTR1) . . . . . . . . . . 983
19.8.11 GPDMA channel x transfer register 2 (GPDMA_CxTR2) . . . . . . . . . . 987
19.8.12 GPDMA channel x block register 1 (GPDMA_CxBR1) . . . . . . . . . . . . 991
19.8.13 GPDMA channel x alternate block register 1 (GPDMA_CxBR1) . . . . . 992
19.8.14 GPDMA channel x source address register (GPDMA_CxSAR) . . . . . 995
19.8.15 GPDMA channel x destination address register (GPDMA_CxDAR) . . 997
19.8.16 GPDMA channel x transfer register 3 (GPDMA_CxTR3) . . . . . . . . . . 998
19.8.17 GPDMA channel x block register 2 (GPDMA_CxBR2) . . . . . . . . . . . . 999
19.8.18 GPDMA channel x linked-list address register (GPDMA_CxLLR) . . . 1000
19.8.19 GPDMA channel x alternate linked-list address register
(GPDMA_CxLLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002

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19.8.20 GPDMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003

20 Neural-ART accelerator™ (NPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005

20.1 NPU introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005
20.2 NPU implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006
20.3 NPU functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
20.3.1 NPU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
20.3.2 NPU pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008
20.3.3 Configuration network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008
20.3.4 Clock/reset manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
20.3.5 Stream link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
20.3.6 Stream switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
20.3.7 Stream engines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
20.3.8 Encryption/Decryption unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010
20.3.9 Decompression unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010
20.3.10 Convolutional accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
20.3.11 Pooling unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
20.3.12 Activation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014
20.3.13 Arithmetic unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
20.3.14 Reconfigurable buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
20.3.15 Epoch controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
20.3.16 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
20.4 Configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
20.4.1 DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
20.4.2 Simple processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
20.4.3 Multiple processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
20.4.4 Conv-Pool-ReLU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
20.4.5 Chained convolutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020
20.4.6 Split convolutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020
20.5 Address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
20.6 System integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022
20.6.1 System considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022
20.6.2 Architecture intent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022

21 Chrom-ART Accelerator controller (DMA2D) . . . . . . . . . . . . . . . . . . 1025

21.1 DMA2D introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025

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21.2 DMA2D main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025

21.3 DMA2D functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
21.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
21.3.2 DMA2D internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
21.3.3 DMA2D control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
21.3.4 DMA2D foreground and background FIFOs . . . . . . . . . . . . . . . . . . . 1028
21.3.5 DMA2D foreground and background PFC . . . . . . . . . . . . . . . . . . . . . 1028
21.3.6 DMA2D foreground and background CLUT interface . . . . . . . . . . . . 1030
21.3.7 DMA2D blender . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
21.3.8 DMA2D output PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
21.3.9 DMA2D output FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
21.3.10 DMA2D output FIFO byte reordering . . . . . . . . . . . . . . . . . . . . . . . . . 1033
21.3.11 DMA2D AXI master port timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
21.3.12 DMA2D transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
21.3.13 DMA2D configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
21.3.14 YCbCr support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
21.3.15 DMA2D transfer control (start, suspend, abort, and completion) . . . . 1039
21.3.16 Watermark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
21.3.17 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
21.3.18 AXI dead time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
21.4 DMA2D interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
21.5 DMA2D registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041
21.5.1 DMA2D control register (DMA2D_CR) . . . . . . . . . . . . . . . . . . . . . . . 1041
21.5.2 DMA2D interrupt status register (DMA2D_ISR) . . . . . . . . . . . . . . . . 1043
21.5.3 DMA2D interrupt flag clear register (DMA2D_IFCR) . . . . . . . . . . . . . 1043
21.5.4 DMA2D foreground memory address register (DMA2D_FGMAR) . . 1044
21.5.5 DMA2D foreground offset register (DMA2D_FGOR) . . . . . . . . . . . . . 1044
21.5.6 DMA2D background memory address register (DMA2D_BGMAR) . 1045
21.5.7 DMA2D background offset register (DMA2D_BGOR) . . . . . . . . . . . . 1045
21.5.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . 1046
21.5.9 DMA2D foreground color register (DMA2D_FGCOLR) . . . . . . . . . . . 1048
21.5.10 DMA2D background PFC control register (DMA2D_BGPFCCR) . . . 1048
21.5.11 DMA2D background color register (DMA2D_BGCOLR) . . . . . . . . . . 1050
21.5.12 DMA2D foreground CLUT memory address register
(DMA2D_FGCMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
21.5.13 DMA2D background CLUT memory address register
(DMA2D_BGCMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051

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21.5.14 DMA2D output PFC control register (DMA2D_OPFCCR) . . . . . . . . . 1051

21.5.15 DMA2D output color register (DMA2D_OCOLR) . . . . . . . . . . . . . . . . 1052
21.5.16 DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . . . . 1053
21.5.17 DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . . . . 1053
21.5.18 DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . . . . 1054
21.5.19 DMA2D output memory address register (DMA2D_OMAR) . . . . . . . 1054
21.5.20 DMA2D output offset register (DMA2D_OOR) . . . . . . . . . . . . . . . . . 1055
21.5.21 DMA2D number of line register (DMA2D_NLR) . . . . . . . . . . . . . . . . 1055
21.5.22 DMA2D line watermark register (DMA2D_LWR) . . . . . . . . . . . . . . . . 1056
21.5.23 DMA2D AXI master timer configuration register (DMA2D_AMTCR) . 1056
21.5.24 DMA2D foreground CLUT (DMA2D_FGCLUTx) . . . . . . . . . . . . . . . . 1057
21.5.25 DMA2D background CLUT (DMA2D_BGCLUTx) . . . . . . . . . . . . . . . 1057
21.5.26 DMA2D register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058

22 Chrom-GRC (GFXMMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060

22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
22.2 GFXMMU main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
22.3 GFXMMU functional and architectural description . . . . . . . . . . . . . . . . 1060
22.3.1 GFXMMU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
22.3.2 GFXMMU internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061
22.3.3 Virtual memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061
22.3.4 Packing and unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
22.3.5 MMU architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
22.4 GFXMMU interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
22.5 GFXMMU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068
22.5.1 GFXMMU configuration register (GFXMMU_CR) . . . . . . . . . . . . . . . 1068
22.5.2 GFXMMU status register (GFXMMU_SR) . . . . . . . . . . . . . . . . . . . . . 1070
22.5.3 GFXMMU flag clear register (GFXMMU_FCR) . . . . . . . . . . . . . . . . . 1070
22.5.4 GFXMMU default value register (GFXMMU_DVR) . . . . . . . . . . . . . . 1071
22.5.5 GFXMMU default alpha register (GFXMMU_DAR) . . . . . . . . . . . . . . 1071
22.5.6 GFXMMU buffer x configuration register (GFXMMU_BxCR) . . . . . . . 1072
22.5.7 GFXMMU LUT entry x low (GFXMMU_LUTxL) . . . . . . . . . . . . . . . . . 1072
22.5.8 GFXMMU LUT entry x high (GFXMMU_LUTxH) . . . . . . . . . . . . . . . . 1073
22.5.9 GFXMMU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073

23 Graphic timer (GFXTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075

23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075

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23.2 GFXTIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075

23.3 GFXTIM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075
23.3.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075
23.3.2 GFXTIM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
23.3.3 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
23.3.4 Example of clock generator configuration . . . . . . . . . . . . . . . . . . . . . 1079
23.3.5 Absolute timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
23.3.6 Relative timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084
23.3.7 Tearing-effect detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
23.3.8 Event generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
23.3.9 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
23.4 GFXTIM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
23.5 GFXTIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
23.5.1 GFXTIM configuration register (GFXTIM_CR) . . . . . . . . . . . . . . . . . 1088
23.5.2 GFXTIM clock generator configuration register (GFXTIM_CGCR) . . 1089
23.5.3 GFXTIM timers configuration register (GFXTIM_TCR) . . . . . . . . . . . 1091
23.5.4 GFXTIM timers disable register (GFXTIM_TDR) . . . . . . . . . . . . . . . . 1092
23.5.5 GFXTIM events control register (GFXTIM_EVCR) . . . . . . . . . . . . . . 1093
23.5.6 GFXTIM events selection register (GFXTIM_EVSR) . . . . . . . . . . . . . 1093
23.5.7 GFXTIM watchdog timer configuration register
(GFXTIM_WDGTCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
23.5.8 GFXTIM interrupt status register (GFXTIM_ISR) . . . . . . . . . . . . . . . 1097
23.5.9 GFXTIM interrupt clear register (GFXTIM_ICR) . . . . . . . . . . . . . . . . 1098
23.5.10 GFXTIM interrupt enable register (GFXTIM_IER) . . . . . . . . . . . . . . . 1100
23.5.11 GFXTIM timers status register (GFXTIM_TSR) . . . . . . . . . . . . . . . . . 1102
23.5.12 GFXTIM line clock counter reload register (GFXTIM_LCCRR) . . . . . 1103
23.5.13 GFXTIM frame clock counter reload register (GFXTIM_FCCRR) . . . 1103
23.5.14 GFXTIM absolute time register (GFXTIM_ATR) . . . . . . . . . . . . . . . . 1103
23.5.15 GFXTIM absolute frame counter register (GFXTIM_AFCR) . . . . . . . 1104
23.5.16 GFXTIM absolute line counter register (GFXTIM_ALCR) . . . . . . . . . 1104
23.5.17 GFXTIM absolute frame counter compare 1 register
(GFXTIM_AFCC1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105
23.5.18 GFXTIM absolute line counter compare 1 register
(GFXTIM_ALCC1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105
23.5.19 GFXTIM absolute line counter compare 2 register
(GFXTIM_ALCC2R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105
23.5.20 GFXTIM relative frame counter 1 register (GFXTIM_RFC1R) . . . . . 1106

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23.5.21 GFXTIM relative frame counter 1 reload register

(GFXTIM_RFC1RR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106
23.5.22 GFXTIM relative frame counter 2 register (GFXTIM_RFC2R) . . . . . 1107
23.5.23 GFXTIM relative frame counter 2 reload register
(GFXTIM_RFC2RR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107
23.5.24 GFXTIM watchdog counter register (GFXTIM_WDGCR) . . . . . . . . . 1107
23.5.25 GFXTIM watchdog reload register (GFXTIM_WDGRR) . . . . . . . . . . 1108
23.5.26 GFXTIM watchdog pre-alarm register (GFXTIM_WDGPAR) . . . . . . . 1108
23.5.27 GFXTIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108

24 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . 1111

24.1 NVIC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111
24.1.1 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111
24.1.2 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111

25 Extended interrupts and event controller (EXTI) . . . . . . . . . . . . . . . 1119

25.1 EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119
25.2 EXTI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1120
25.3 EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1120
25.3.1 EXTI connections between peripherals and CPU . . . . . . . . . . . . . . . 1121
25.3.2 EXTI wake-up interrupt list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
25.4 EXTI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1124
25.4.1 EXTI configurable event input wake-up . . . . . . . . . . . . . . . . . . . . . . . 1124
25.4.2 EXTI direct event input wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
25.4.3 EXTI multiplexer selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
25.5 EXTI functional behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1126
25.6 EXTI event protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1127
25.6.1 EXTI register security protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127
25.6.2 EXTI register privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
25.7 EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1128
25.7.1 EXTI rising trigger selection register (EXTI_RTSR1) . . . . . . . . . . . . . 1128
25.7.2 EXTI falling trigger selection register (EXTI_FTSR1) . . . . . . . . . . . . 1129
25.7.3 EXTI software interrupt event register (EXTI_SWIER1) . . . . . . . . . . 1130
25.7.4 EXTI rising edge pending register (EXTI_RPR1) . . . . . . . . . . . . . . . 1131
25.7.5 EXTI falling edge pending register (EXTI_FPR1) . . . . . . . . . . . . . . . 1131
25.7.6 EXTI security configuration register (EXTI_SECCFGR1) . . . . . . . . . 1132
25.7.7 EXTI privilege configuration register (EXTI_PRIVCFGR1) . . . . . . . . 1132

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25.7.8 EXTI rising trigger selection register (EXTI_RTSR2) . . . . . . . . . . . . . 1133

25.7.9 EXTI falling trigger selection register (EXTI_FTSR2) . . . . . . . . . . . . 1134
25.7.10 EXTI software interrupt event register (EXTI_SWIER2) . . . . . . . . . . 1135
25.7.11 EXTI rising edge pending register (EXTI_RPR2) . . . . . . . . . . . . . . . 1136
25.7.12 EXTI falling edge pending register (EXTI_FPR2) . . . . . . . . . . . . . . . 1137
25.7.13 EXTI security enable register (EXTI_SECCFGR2) . . . . . . . . . . . . . . 1138
25.7.14 EXTI privilege enable register (EXTI_PRIVCFGR2) . . . . . . . . . . . . . 1139
25.7.15 EXTI rising trigger selection register (EXTI_RTSR3) . . . . . . . . . . . . . 1139
25.7.16 EXTI falling trigger selection register (EXTI_FTSR3) . . . . . . . . . . . . 1140
25.7.17 EXTI software interrupt event register (EXTI_SWIER3) . . . . . . . . . . 1141
25.7.18 EXTI rising edge pending register (EXTI_RPR3) . . . . . . . . . . . . . . . 1142
25.7.19 EXTI falling edge pending register (EXTI_FPR3) . . . . . . . . . . . . . . . 1142
25.7.20 EXTI security enable register (EXTI_SECCFGR3) . . . . . . . . . . . . . . 1143
25.7.21 EXTI privilege enable register (EXTI_PRIVCFGR3) . . . . . . . . . . . . . 1144
25.7.22 EXTI external interrupt selection register 1 (EXTI_EXTICR1) . . . . . . 1144
25.7.23 EXTI external interrupt selection register 2 (EXTI_EXTICR2) . . . . . . 1147
25.7.24 EXTI external interrupt selection register 3 (EXTI_EXTICR3) . . . . . . 1150
25.7.25 EXTI external interrupt selection register 4 (EXTI_EXTICR4) . . . . . . 1152
25.7.26 EXTI lock register (EXTI_LOCKR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155
25.7.27 EXTI CPU wake-up with interrupt mask register 1 (EXTI_IMR1) . . . 1155
25.7.28 EXTI CPU wake-up with event mask register 1 (EXTI_EMR1) . . . . . 1156
25.7.29 EXTI CPU wake-up with interrupt mask register 2 (EXTI_IMR2) . . . 1156
25.7.30 EXTI CPU wake-up with event mask register 2 (EXTI_EMR2) . . . . . 1157
25.7.31 EXTI CPU wake-up with interrupt mask register 3 (EXTI_IMR3) . . . 1157
25.7.32 EXTI CPU wake-up with event mask register 3 (EXTI_EMR3) . . . . . 1158
25.7.33 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1160

26 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . 1163

26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1163
26.2 CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1163
26.3 CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1164
26.3.1 CRC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164
26.3.2 CRC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164
26.3.3 CRC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164
26.4 CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1166
26.4.1 CRC data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166
26.4.2 CRC independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . 1166

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26.4.3 CRC control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167

26.4.4 CRC initial value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168
26.4.5 CRC polynomial (CRC_POL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168
26.4.6 CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169

27 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1170

27.1 FMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1170
27.2 FMC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1171
27.3 FMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1172
27.4 FMC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1173
27.5 AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1173
27.6 AXI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1173
27.6.1 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . 1174
27.7 External device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1175
27.7.1 NOR/PSRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1176
27.7.2 NAND flash memory address mapping . . . . . . . . . . . . . . . . . . . . . . . 1176
27.7.3 SDRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177
27.8 NOR flash/PSRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1180
27.8.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182
27.8.2 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . 1184
27.8.3 General timing rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186
27.8.4 NOR flash/PSRAM controller asynchronous transactions . . . . . . . . . 1186
27.8.5 Synchronous transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1205
27.8.6 NOR/PSRAM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210
27.9 NAND flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219
27.9.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220
27.9.2 NAND flash supported memories and transactions . . . . . . . . . . . . . . 1221
27.9.3 Timing diagrams for NAND flash memory . . . . . . . . . . . . . . . . . . . . . 1222
27.9.4 NAND flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223
27.9.5 NAND flash prewait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224
27.9.6 NAND ECC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225
27.9.7 FMC command sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1228
27.9.8 NAND flash controller interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235
27.9.9 NAND flash controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236
27.10 SDRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1260
27.10.1 SDRAM controller main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1260

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27.10.2 SDRAM External memory interface signals . . . . . . . . . . . . . . . . . . . . 1260

27.10.3 SDRAM controller functional description . . . . . . . . . . . . . . . . . . . . . . 1261
27.10.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267
27.10.5 SDRAM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269
27.11 FMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277

28 Extended-SPI interface (XSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282

28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282
28.2 XSPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282
28.3 XSPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1283
28.4 XSPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284
28.4.1 XSPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284
28.4.2 XSPI pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1288
28.4.3 Clock constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289
28.4.4 XSPI interface to memory modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289
28.4.5 XSPI regular-command protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289
28.4.6 XSPI regular-command protocol signal interface . . . . . . . . . . . . . . . 1293
28.4.7 HyperBus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1298
28.4.8 Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303
28.4.9 XSPI operating modes introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1305
28.4.10 XSPI indirect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305
28.4.11 XSPI automatic status-polling mode . . . . . . . . . . . . . . . . . . . . . . . . . 1307
28.4.12 XSPI memory-mapped mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1307
28.4.13 XSPI configuration introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308
28.4.14 XSPI system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308
28.4.15 XSPI device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1309
28.4.16 XSPI regular-command mode configuration . . . . . . . . . . . . . . . . . . . 1311
28.4.17 XSPI HyperBus protocol configuration . . . . . . . . . . . . . . . . . . . . . . . 1314
28.4.18 XSPI error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1314
28.4.19 XSPI high-speed interface and calibration . . . . . . . . . . . . . . . . . . . . . 1315
28.4.20 XSPI BUSY and ABORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1316
28.4.21 XSPI reconfiguration or deactivation . . . . . . . . . . . . . . . . . . . . . . . . . 1316
28.4.22 NCS behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1317
28.4.23 Software control of two external memories . . . . . . . . . . . . . . . . . . . . 1317
28.4.24 Hardware-controlled extended memory support . . . . . . . . . . . . . . . . 1318
28.5 Address alignment and data number . . . . . . . . . . . . . . . . . . . . . . . . . . 1319

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28.6 XSPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1321

28.7 XSPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1321
28.7.1 XSPI control register (XSPI_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1321
28.7.2 XSPI device configuration register 1 (XSPI_DCR1) . . . . . . . . . . . . . 1325
28.7.3 XSPI device configuration register 2 (XSPI_DCR2) . . . . . . . . . . . . . 1326
28.7.4 XSPI device configuration register 3 (XSPI_DCR3) . . . . . . . . . . . . . 1327
28.7.5 XSPI device configuration register 4 (XSPI_DCR4) . . . . . . . . . . . . . 1328
28.7.6 XSPI status register (XSPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1328
28.7.7 XSPI flag clear register (XSPI_FCR) . . . . . . . . . . . . . . . . . . . . . . . . . 1329
28.7.8 XSPI data length register (XSPI_DLR) . . . . . . . . . . . . . . . . . . . . . . . 1330
28.7.9 XSPI address register (XSPI_AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1330
28.7.10 XSPI data register (XSPI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1331
28.7.11 XSPI polling status mask register (XSPI_PSMKR) . . . . . . . . . . . . . . 1332
28.7.12 XSPI polling status match register (XSPI_PSMAR) . . . . . . . . . . . . . 1332
28.7.13 XSPI polling interval register (XSPI_PIR) . . . . . . . . . . . . . . . . . . . . . 1333
28.7.14 XSPI communication configuration register (XSPI_CCR) . . . . . . . . . 1333
28.7.15 XSPI timing configuration register (XSPI_TCR) . . . . . . . . . . . . . . . . 1335
28.7.16 XSPI instruction register (XSPI_IR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1336
28.7.17 XSPI alternate bytes register (XSPI_ABR) . . . . . . . . . . . . . . . . . . . . 1336
28.7.18 XSPI low-power timeout register (XSPI_LPTR) . . . . . . . . . . . . . . . . . 1336
28.7.19 XSPI wrap communication configuration register
(XSPI_WPCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1337
28.7.20 XSPI wrap timing configuration register (XSPI_WPTCR) . . . . . . . . . 1339
28.7.21 XSPI wrap instruction register (XSPI_WPIR) . . . . . . . . . . . . . . . . . . 1340
28.7.22 XSPI wrap alternate byte register (XSPI_WPABR) . . . . . . . . . . . . . . 1340
28.7.23 XSPI write communication configuration register
(XSPI_WCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1340
28.7.24 XSPI write timing configuration register (XSPI_WTCR) . . . . . . . . . . 1342
28.7.25 XSPI write instruction register (XSPI_WIR) . . . . . . . . . . . . . . . . . . . . 1343
28.7.26 XSPI write alternate byte register (XSPI_WABR) . . . . . . . . . . . . . . . 1343
28.7.27 XSPI HyperBus latency configuration register (XSPI_HLCR) . . . . . . 1344
28.7.28 XSPI full-cycle calibration configuration (XSPI_CALFCR) . . . . . . . . . 1344
28.7.29 XSPI DLL master calibration configuration (XSPI_CALMR) . . . . . . . 1345
28.7.30 XSPI DLL slave output calibration configuration
(XSPI_CALSOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346
28.7.31 XSPI DLL slave input calibration configuration (XSPI_CALSIR) . . . . 1347
28.7.32 XSPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1347

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29 XSPI I/O manager (XSPIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351

29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351
29.2 XSPIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351
29.3 XSPIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351
29.4 XSPIM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351
29.4.1 XSPIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351
29.4.2 XSPIM input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1352
29.4.3 XSPIM matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353
29.4.4 XSPIM multiplexed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353
29.5 Use cases description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354
29.5.1 XSPIs direct octal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354
29.5.2 XSPI direct 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355
29.5.3 XSPI dual-octal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356
29.5.4 XSPI swapped mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357
29.5.5 Two XSPIs multiplexed mode to Port 1 accessing two external
memories, and the third XSPI accessing Port 2 . . . . . . . . . . . . . . . . 1358
29.5.6 Two XSPIs multiplexed mode to Port 2 accessing two external
memories and the third XSPI accessing Port 1 . . . . . . . . . . . . . . . . . 1359
29.5.7 XSPI1 and XSPI2 drive a single external memory . . . . . . . . . . . . . . 1360
29.5.8 A single XSPI drives two external memories . . . . . . . . . . . . . . . . . . . 1361
29.6 XSPIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1363
29.6.1 XSPIM control register (XSPIM_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 1363
29.6.2 XSPIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364

30 Secure digital input/output MultiMediaCard interface (SDMMC) . . 1365

30.1 SDMMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365
30.2 SDMMC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365
30.3 SDMMC bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1366
30.4 SDMMC operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368
30.5 SDMMC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1369
30.5.1 SDMMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1369
30.5.2 SDMMC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1369
30.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1370
30.5.4 SDMMC adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1372
30.5.5 SDMMC AHB slave interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394
30.5.6 SDMMC AHB master interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1395

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30.5.7 AHB and SDMMC_CK clock relation . . . . . . . . . . . . . . . . . . . . . . . . . 1398

30.6 Card functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399
30.6.1 SD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399
30.6.2 CMD12 send timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407
30.6.3 Sleep (CMD5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1411
30.6.4 Interrupt mode (Wait-IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412
30.6.5 Boot operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1413
30.6.6 Response R1b handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1416
30.6.7 Reset and card cycle power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1417
30.7 Hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1418
30.7.1 Hardware flow control during data transfer . . . . . . . . . . . . . . . . . . . . 1418
30.7.2 Block gap hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1419
30.8 Ultra-high-speed phase I (UHS-I) voltage switch . . . . . . . . . . . . . . . . . 1420
30.9 SDMMC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1423
30.10 SDMMC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425
30.10.1 SDMMC power control register (SDMMC_POWER) . . . . . . . . . . . . . 1425
30.10.2 SDMMC clock control register (SDMMC_CLKCR) . . . . . . . . . . . . . . 1426
30.10.3 SDMMC argument register (SDMMC_ARGR) . . . . . . . . . . . . . . . . . . 1428
30.10.4 SDMMC command register (SDMMC_CMDR) . . . . . . . . . . . . . . . . . 1428
30.10.5 SDMMC command response register (SDMMC_RESPCMDR) . . . . 1430
30.10.6 SDMMC response x register (SDMMC_RESPxR) . . . . . . . . . . . . . . 1431
30.10.7 SDMMC data timer register (SDMMC_DTIMER) . . . . . . . . . . . . . . . 1431
30.10.8 SDMMC data length register (SDMMC_DLENR) . . . . . . . . . . . . . . . 1432
30.10.9 SDMMC data control register (SDMMC_DCTRL) . . . . . . . . . . . . . . . 1433
30.10.10 SDMMC data counter register (SDMMC_DCNTR) . . . . . . . . . . . . . . 1434
30.10.11 SDMMC status register (SDMMC_STAR) . . . . . . . . . . . . . . . . . . . . . 1435
30.10.12 SDMMC interrupt clear register (SDMMC_ICR) . . . . . . . . . . . . . . . . 1438
30.10.13 SDMMC mask register (SDMMC_MASKR) . . . . . . . . . . . . . . . . . . . . 1440
30.10.14 SDMMC acknowledgment timer register (SDMMC_ACKTIMER) . . . 1443
30.10.15 SDMMC data FIFO threshold register (SDMMC_FIFOTHRR) . . . . . 1443
30.10.16 SDMMC DMA control register (SDMMC_IDMACTRLR) . . . . . . . . . . 1444
30.10.17 SDMMC IDMA buffer size register (SDMMC_IDMABSIZER) . . . . . . 1444
30.10.18 SDMMC IDMA buffer base address register
(SDMMC_IDMABASER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1445
30.10.19 SDMMC IDMA linked list address register (SDMMC_IDMALAR) . . . 1445
30.10.20 SDMMC IDMA linked list memory base register
(SDMMC_IDMABAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1446

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30.10.21 SDMMC data FIFO registers x (SDMMC_FIFORx) . . . . . . . . . . . . . . 1447

30.10.22 SDMMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447

31 Delay block (DLYB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1450

31.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1450
31.2 DLYB main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1450
31.3 DLYB implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1450
31.4 DLYB functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1450
31.4.1 DLYB diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1450
31.4.2 DLYB internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1452
31.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1454
31.4.4 Lock mode procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455
31.4.5 Bypass mode procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455
31.5 DLYB SDMMC registers description . . . . . . . . . . . . . . . . . . . . . . . . . . 1456
31.5.1 Delay block SDMMC DLL configuration (DLYBSD_CFG) . . . . . . . . . 1456
31.5.2 Delay block SDMMC DLL status (DLYBSD_STATUS) . . . . . . . . . . . 1457
31.5.3 DLYB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457

32 Analog-to-digital converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . 1459

32.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1459
32.2 ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1459
32.3 ADC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1461
32.4 ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1462
32.4.1 ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1462
32.4.2 ADC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1463
32.4.3 ADC clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1466
32.4.4 ADC connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1467
32.4.5 Slave AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1469
32.4.6 ADC Deep-power-down mode (DEEPPWD) . . . . . . . . . . . . . . . . . . . 1469
32.4.7 Single-ended and differential input channels . . . . . . . . . . . . . . . . . . . 1469
32.4.8 Calibration (ADCAL, CALADDOS, ADC_CALFACT) . . . . . . . . . . . . . 1470
32.4.9 ADC on-off control (ADEN, ADDIS, ADRDY) . . . . . . . . . . . . . . . . . . . 1472
32.4.10 Constraints when writing the ADC control bits . . . . . . . . . . . . . . . . . . 1473
32.4.11 Channel selection (SQRx, JSQRx) . . . . . . . . . . . . . . . . . . . . . . . . . . 1474
32.4.12 Channel preselection register (ADC_PCSEL) . . . . . . . . . . . . . . . . . . 1474
32.4.13 Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . 1475

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32.4.14 Single conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477

32.4.15 Continuous conversion mode (CONT = 1) . . . . . . . . . . . . . . . . . . . . . 1477
32.4.16 Starting conversions (ADSTART, JADSTART) . . . . . . . . . . . . . . . . . . 1478
32.4.17 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
32.4.18 Stopping an ongoing conversion (ADSTP, JADSTP) . . . . . . . . . . . . . 1480
32.4.19 Conversion on external trigger and trigger polarity
(EXTSEL, EXTEN, JEXTSEL, JEXTEN) . . . . . . . . . . . . . . . . . . . . . . 1481
32.4.20 Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1483
32.4.21 Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . . . . . . . . 1484
32.4.22 Programmable resolution (RES) - fast conversion mode . . . . . . . . . 1486
32.4.23 End of conversion and end of sampling phase
(EOC, JEOC, EOSMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1486
32.4.24 End of conversion sequence (EOS, JEOS) . . . . . . . . . . . . . . . . . . . . 1486
32.4.25 Timing diagram examples (single/continuous modes,
hardware/software triggers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1487
32.4.26 Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
32.4.27 Managing conversions using the MDF . . . . . . . . . . . . . . . . . . . . . . . 1497
32.4.28 Dynamic low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1498
32.4.29 Analog window watchdog (AWD1EN, JAWD1EN,
AWD1SGL, AWD1CH, AWDCH of ADC_AWD2CR and
ADC_AWD3CR, HTR, LTR, AWDFILT) . . . . . . . . . . . . . . . . . . . . . . . 1502
32.4.30 Oversampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
32.4.31 Dual ADC modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1513
32.4.32 VBAT supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1529
32.4.33 Monitoring the internal voltage reference . . . . . . . . . . . . . . . . . . . . . 1529
32.4.34 Monitoring the supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531
32.5 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1531
32.6 ADC registers (for each ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1532
32.6.1 ADC interrupt and status register (ADC_ISR) . . . . . . . . . . . . . . . . . . 1532
32.6.2 ADC interrupt enable register (ADC_IER) . . . . . . . . . . . . . . . . . . . . . 1535
32.6.3 ADC control register (ADC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1537
32.6.4 ADC configuration register (ADC_CFGR1) . . . . . . . . . . . . . . . . . . . . 1540
32.6.5 ADC configuration register 2 (ADC_CFGR2) . . . . . . . . . . . . . . . . . . 1543
32.6.6 ADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . 1546
32.6.7 ADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . 1547
32.6.8 ADC channel preselection register (ADC_PCSEL) . . . . . . . . . . . . . . 1547
32.6.9 ADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . 1548
32.6.10 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . 1549

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32.6.11 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . 1550

32.6.12 ADC regular sequence register 4 (ADC_SQR4) . . . . . . . . . . . . . . . . 1551
32.6.13 ADC regular data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . 1551
32.6.14 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . 1552
32.6.15 ADC offset y configuration register (ADC_OFCFGRy) . . . . . . . . . . . 1553
32.6.16 ADC offset y register (ADC_OFRy) . . . . . . . . . . . . . . . . . . . . . . . . . . 1554
32.6.17 ADC gain compensation register (ADC_GCOMP) . . . . . . . . . . . . . . 1555
32.6.18 ADC injected channel y data register (ADC_JDRy) . . . . . . . . . . . . . . 1556
32.6.19
ADC analog watchdog 2 configuration register (ADC_AWD2CR) 1556
32.6.20 ADC analog watchdog 3 configuration register (ADC_AWD3CR) . . . 1557
32.6.21 ADC analog watchdog 1 lower threshold register (ADC_AWD1LTR) 1557
32.6.22 ADC analog watchdog 1 higher threshold register
(ADC_AWD1HTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1558
32.6.23 ADC analog watchdog 2 lower threshold register (ADC_AWD2LTR) 1558
32.6.24 ADC analog watchdog 2 higher threshold register
(ADC_AWD2HTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1559
32.6.25 ADC analog watchdog 3 lower threshold register (ADC_AWD3LTR) 1559
32.6.26 ADC analog watchdog 3 higher threshold register
(ADC_AWD3HTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1560
32.6.27 ADC differential mode selection register (ADC_DIFSEL) . . . . . . . . . 1560
32.6.28 ADC calibration factors (ADC_CALFACT) . . . . . . . . . . . . . . . . . . . . . 1560
32.6.29 ADC option register (ADC_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1562
32.7 ADC common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1563
32.7.1 ADC common status register (ADCC_CSR) . . . . . . . . . . . . . . . . . . . 1563
32.7.2 ADC common control register (ADCC_CCR) . . . . . . . . . . . . . . . . . . 1564
32.7.3 ADC common regular data register for dual mode
(ADCC_CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566
32.7.4 ADC common regular data register for dual mode
(ADCC_CDR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566
32.8 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1567

33 Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1571

33.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1571
33.2 DTS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1571
33.3 DTS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1572
33.3.1 DTS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1572
33.3.2 DTS pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1572

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33.3.3 DTS reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1573

33.3.4 DTS serial data adapter (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1575
33.3.5 Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1581
33.3.6 Main APB programming routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1582
33.3.7 Temperature sensor configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 1585
33.4 DTS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1587
33.5 DTS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588
33.5.1 DTS PVT common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588
33.5.2 PVT IRQ registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1590
33.5.3 TS common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1594
33.5.4 TS individual registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1601
33.5.5 DTS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1608

34 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . 1613

34.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613
34.2 VREFBUF implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613
34.3 VREFBUF functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613
34.4 VREFBUF trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1614
34.5 VREFBUF power sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1615
34.6 VREFBUF registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1616
34.6.1 VREFBUF control and status register (VREFBUF_CSR) . . . . . . . . . 1616
34.6.2 VREFBUF calibration control register (VREFBUF_CCR) . . . . . . . . . 1617
34.6.3 VREFBUF register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617

35 Multi-function digital filter (MDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1618

35.1 MDF introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1618
35.2 MDF main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1619
35.3 MDF implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1619
35.4 MDF functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1621
35.4.1 MDF block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1621
35.4.2 MDF pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1622
35.4.3 Serial input interfaces (SITF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1623
35.4.4 ADC slave interface (ADCITF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628
35.4.5 Clock generator (CKGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1629
35.4.6 Bitstream matrix (BSMX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631
35.4.7 Short-circuit detectors (SCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632

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35.4.8 Digital filter processing (DFLT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634

35.4.9 Out-of-limit detector (OLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1644
35.4.10 Digital filter acquisition modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647
35.4.11 Start-up sequence examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1657
35.4.12 Break interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1658
35.4.13 Data transfer to memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1659
35.4.14 Autonomous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1664
35.4.15 Register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1665
35.5 MDF low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666
35.6 MDF interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666
35.7 MDF application informations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1668
35.7.1 MDF configuration examples for audio capture . . . . . . . . . . . . . . . . . 1668
35.7.2 Programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669
35.7.3 Connection examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1671
35.7.4 Global frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672
35.7.5 Total MDF gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673
35.8 MDF registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1677
35.8.1 MDF global control register (MDF_GCR) . . . . . . . . . . . . . . . . . . . . . 1678
35.8.2 MDF clock generator control register (MDF_CKGCR) . . . . . . . . . . . 1678
35.8.3 MDF serial interface control register x (MDF_SITFxCR) . . . . . . . . . . 1681
35.8.4 MDF bitstream matrix control register x (MDF_BSMXxCR) . . . . . . . 1682
35.8.5 MDF digital filter control register x (MDF_DFLTxCR) . . . . . . . . . . . . 1683
35.8.6 MDF digital filter configuration register x (MDF_DFLTxCICR) . . . . . . 1685
35.8.7 MDF reshape filter configuration register x (MDF_DFLTxRSFR) . . . 1686
35.8.8 MDF integrator configuration register x (MDF_DFLTxINTR) . . . . . . . 1687
35.8.9 MDF out-of limit detector control register x (MDF_OLDxCR) . . . . . . 1688
35.8.10 MDF OLDx low threshold register x (MDF_OLDxTHLR) . . . . . . . . . . 1690
35.8.11 MDF OLDx high threshold register x (MDF_OLDxTHHR) . . . . . . . . . 1690
35.8.12 MDF delay control register x (MDF_DLYxCR) . . . . . . . . . . . . . . . . . . 1691
35.8.13 MDF short circuit detector control register x (MDF_SCDxCR) . . . . . 1691
35.8.14 MDF DFLT0 interrupt enable register 0 (MDF_DFLT0IER) . . . . . . . . 1692
35.8.15 MDF DFLTx interrupt enable register x (MDF_DFLTxIER) . . . . . . . . 1694
35.8.16 MDF DFLT0 interrupt status register 0 (MDF_DFLT0ISR) . . . . . . . . . 1695
35.8.17 MDF DFLTx interrupt status register x (MDF_DFLTxISR) . . . . . . . . . 1697
35.8.18 MDF offset error compensation control register x (MDF_OECxCR) . 1698
35.8.19 MDF snapshot data register x (MDF_SNPSxDR) . . . . . . . . . . . . . . . 1699
35.8.20 MDF digital filter data register x (MDF_DFLTxDR) . . . . . . . . . . . . . . 1699

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35.8.21 MDF register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700

36 Audio digital filter (ADF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1702

36.1 ADF introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1702
36.2 ADF main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1702
36.3 ADF implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1703
36.4 ADF functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704
36.4.1 ADF block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704
36.4.2 ADF pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704
36.4.3 Serial input interface (SITF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705
36.4.4 ADC slave interface (ADCITF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1709
36.4.5 Clock generator (CKGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710
36.4.6 Bitstream matrix (BSMX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712
36.4.7 Digital filter processing (DFLT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1713
36.4.8 Digital filter acquisition modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1723
36.4.9 Start-up sequence examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1731
36.4.10 Sound activity detection (SAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1732
36.4.11 Data transfer to memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1740
36.4.12 Autonomous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1743
36.4.13 Register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1743
36.5 ADF low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1744
36.6 ADF interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1744
36.7 ADF application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1746
36.7.1 ADF configuration examples for audio capture . . . . . . . . . . . . . . . . . 1746
36.7.2 Programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1747
36.7.3 Connection examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1749
36.7.4 Global frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1750
36.7.5 Total ADF gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1751
36.7.6 How to compute SAD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1754
36.8 ADF registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1758
36.8.1 ADF global control register (ADF_GCR) . . . . . . . . . . . . . . . . . . . . . . 1758
36.8.2 ADF clock generator control register (ADF_CKGCR) . . . . . . . . . . . . 1759
36.8.3 ADF serial interface control register 0 (ADF_SITF0CR) . . . . . . . . . . 1761
36.8.4 ADF bitstream matrix control register 0 (ADF_BSMX0CR) . . . . . . . . 1762
36.8.5 ADF digital filter control register 0 (ADF_DFLT0CR) . . . . . . . . . . . . . 1763
36.8.6 ADF digital filer configuration register 0 (ADF_DFLT0CICR) . . . . . . . 1765

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36.8.7 ADF reshape filter configuration register 0 (ADF_DFLT0RSFR) . . . . 1766

36.8.8 ADF delay control register 0 (ADF_DLY0CR) . . . . . . . . . . . . . . . . . . 1767
36.8.9 ADF DFLT0 interrupt enable register (ADF_DFLT0IER) . . . . . . . . . . 1768
36.8.10 ADF DFLT0 interrupt status register 0 (ADF_DFLT0ISR) . . . . . . . . . 1769
36.8.11 ADF SAD control register (ADF_SADCR) . . . . . . . . . . . . . . . . . . . . . 1770
36.8.12 ADF SAD configuration register (ADF_SADCFGR) . . . . . . . . . . . . . 1772
36.8.13 ADF SAD sound level register (ADF_SADSDLVR) . . . . . . . . . . . . . . 1773
36.8.14 ADF SAD ambient noise level register (ADF_SADANLVR) . . . . . . . . 1774
36.8.15 ADF digital filter data register 0 (ADF_DFLT0DR) . . . . . . . . . . . . . . . 1774
36.8.16 ADF register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1774

37 Camera subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1777

37.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1777
37.2 Camera path main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1777
37.2.1 DCMI path main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1777
37.2.2 DCMIPP path main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1778
37.3 Camera subsystem implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 1779
37.3.1 Hardware settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1779
37.4 Camera subsystem functional description . . . . . . . . . . . . . . . . . . . . . . 1780
37.4.1 Camera subsystem block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 1780
37.4.2 Camera subsystem pins and external signal interface . . . . . . . . . . . 1780
37.4.3 Camera subsystem reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . 1781
37.4.4 Streaming from the camera subsystem to slave peripherals . . . . . . . 1781
37.4.5 Camera subsystem security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1782
37.5 Camera subsystem programmable parameters . . . . . . . . . . . . . . . . . . 1783
37.5.1 Low-resolution parallel camera and DCMI . . . . . . . . . . . . . . . . . . . . . 1784
37.5.2 High-resolution parallel camera and DCMIPP . . . . . . . . . . . . . . . . . . 1784
37.5.3 High-resolution CSI2 camera and DCMIPP . . . . . . . . . . . . . . . . . . . . 1785
37.5.4 Sensors over target resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1786
37.5.5 Sensors over target pixel rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1786
37.5.6 Double sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1786
37.6 Camera subsystem interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1787
37.7 Camera subsystem registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1787

38 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1788

38.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1788

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38.2 DCMI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1788

38.3 DCMI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1788
38.3.1 DCMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1789
38.3.2 DCMI pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1789
38.3.3 DCMI clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1790
38.3.4 DCMI DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1790
38.3.5 DCMI physical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1790
38.3.6 DCMI synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1792
38.3.7 DCMI capture modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1794
38.3.8 DCMI crop feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1795
38.3.9 DCMI JPEG format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1796
38.3.10 DCMI FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1796
38.3.11 DCMI data format description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1797
38.4 DCMI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1799
38.5 DCMI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1799
38.5.1 DCMI control register (DCMI_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1799
38.5.2 DCMI status register (DCMI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1802
38.5.3 DCMI raw interrupt status register (DCMI_RIS) . . . . . . . . . . . . . . . . 1802
38.5.4 DCMI interrupt enable register (DCMI_IER) . . . . . . . . . . . . . . . . . . . 1803
38.5.5 DCMI masked interrupt status register (DCMI_MIS) . . . . . . . . . . . . . 1804
38.5.6 DCMI interrupt clear register (DCMI_ICR) . . . . . . . . . . . . . . . . . . . . . 1805
38.5.7 DCMI embedded synchronization code register (DCMI_ESCR) . . . . 1806
38.5.8 DCMI embedded synchronization unmask register (DCMI_ESUR) . 1806
38.5.9 DCMI crop window start (DCMI_CWSTRT) . . . . . . . . . . . . . . . . . . . . 1807
38.5.10 DCMI crop window size (DCMI_CWSIZE) . . . . . . . . . . . . . . . . . . . . . 1808
38.5.11 DCMI data register (DCMI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1808
38.5.12 DCMI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1809

39 Digital camera interface pixel pipeline (DCMIPP) . . . . . . . . . . . . . . . 1810

39.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1810
39.2 DCMIPP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1813
39.3 DCMIPP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1815
39.3.1 DCMIPP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1815
39.3.2 DCMIPP pads and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . 1816
39.3.3 DCMIPP reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1816
39.3.4 DCMIPP maximum resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1819

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39.3.5 DCMIPP minimum requirements for frame structure . . . . . . . . . . . . . 1820

39.3.6 Description of DCMIPP pixel format support . . . . . . . . . . . . . . . . . . . 1820
39.4 DCMIPP input and flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1821
39.4.1 Parallel input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1822
39.4.2 Interface from CSI-2 host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1825
39.4.3 Input selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1825
39.4.4 Flow selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1826
39.4.5 Frame counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1827
39.4.6 Frame control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1828
39.4.7 Pipe deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1833
39.5 Pipe0 (dump pipe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1834
39.5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1834
39.5.2 Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1835
39.5.3 Crop/statistics selection/suppression . . . . . . . . . . . . . . . . . . . . . . . . . 1835
39.5.4 Header insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1836
39.5.5 Dump counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1837
39.5.6 Double buffer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1838
39.6 Pipe1 (ISP part) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1839
39.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1839
39.6.2 Byte-to-pixel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1839
39.6.3 Statistics removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1840
39.6.4 Bad pixel removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1841
39.6.5 Input decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1842
39.6.6 Black level calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1843
39.6.7 Exposure compensation and white-balance calibration . . . . . . . . . . . 1844
39.6.8 Demosaicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1845
39.6.9 Color conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1847
39.6.10 Contrast enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1850
39.6.11 Statistics extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1851
39.7 Pipe1 (post-processing part) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1856
39.7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1856
39.7.2 Pixel 2D cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1856
39.7.3 Decimation pre-downsize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1857
39.7.4 Downsize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1858
39.7.5 Regions of interest (ROIs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1860
39.7.6 Gamma conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1861
39.7.7 YUV conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1861

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39.7.8 Chroma down-sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1861

39.7.9 Pixel packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1862
39.7.10 Overrun detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1864
39.8 Pipe2 (post-processing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1865
39.8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1865
39.8.2 Pipe1 and Pipe2 sharing image processing functions . . . . . . . . . . . . 1866
39.9 Application use cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1866
39.9.1 Parallel interface camera sensor module . . . . . . . . . . . . . . . . . . . . . 1866
39.9.2 CSI2 camera sensor module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1867
39.9.3 Force data type format from CSI-2 data flow (pixel pipes only) . . . . . 1874
39.10 Pixel format description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1877
39.10.1 Parallel interface formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1877
39.10.2 Pixel pipe formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1879
39.10.3 Dump pipe formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1880
39.10.4 AXI IP-Plug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1882
39.11 Shadow registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1888
39.12 DCMIPP low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1890
39.13 DCMIPP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1891
39.13.1 Free-running DCMIPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1891
39.13.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1891
39.13.3 Event pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1894
39.14 DCMIPP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1895
39.14.1 DCMIPP IP-Plug global register 1 (DCMIPP_IPGR1) . . . . . . . . . . . . 1895
39.14.2 DCMIPP IP-Plug global register 2 (DCMIPP_IPGR2) . . . . . . . . . . . . 1896
39.14.3 DCMIPP IP-Plug global register 3 (DCMIPP_IPGR3) . . . . . . . . . . . . 1896
39.14.4 DCMIPP IP-Plug identification register (DCMIPP_IPGR8) . . . . . . . . 1897
39.14.5 DCMIPP IP-Plug Clientx register 1 (DCMIPP_IPCxR1) . . . . . . . . . . 1897
39.14.6 DCMIPP IP-Plug Clientx register 2 (DCMIPP_IPCxR2) . . . . . . . . . . 1898
39.14.7 DCMIPP IP-Plug Clientx register 3 (DCMIPP_IPCxR3) . . . . . . . . . . 1898
39.14.8 DCMIPP parallel interface control register (DCMIPP_PRCR) . . . . . . 1899
39.14.9 DCMIPP parallel interface embedded synchronization code register
(DCMIPP_PRESCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1900
39.14.10 DCMIPP parallel interface embedded synchronization unmask register
(DCMIPP_PRESUR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1901
39.14.11 DCMIPP parallel interface interrupt enable register
(DCMIPP_PRIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1902
39.14.12 DCMIPP parallel interface status register (DCMIPP_PRSR) . . . . . . . 1902

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39.14.13 DCMIPP parallel interface interrupt clear register

(DCMIPP_PRFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1903
39.14.14 DCMIPP common configuration register (DCMIPP_CMCR) . . . . . . . 1904
39.14.15 DCMIPP common frame counter register (DCMIPP_CMFRCR) . . . . 1905
39.14.16 DCMIPP common interrupt enable register (DCMIPP_CMIER) . . . . 1905
39.14.17 DCMIPP common status register 1 (DCMIPP_CMSR1) . . . . . . . . . . 1906
39.14.18 DCMIPP common status register 2 (DCMIPP_CMSR2) . . . . . . . . . . 1908
39.14.19 DCMIPP common interrupt clear register (DCMIPP_CMFCR) . . . . . 1910
39.14.20 DCMIPP Pipe0 flow selection configuration register
(DCMIPP_P0FSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1912
39.14.21 DCMIPP Pipe0 flow control configuration register
(DCMIPP_P0FCTCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1912
39.14.22 DCMIPP Pipe0 statistic/crop start register (DCMIPP_P0SCSTR) . . . 1913
39.14.23 DCMIPP Pipe0 statistic/crop size register (DCMIPP_P0SCSZR) . . . 1914
39.14.24 DCMIPP Pipe0 dump counter register (DCMIPP_P0DCCNTR) . . . . 1914
39.14.25 DCMIPP Pipe0 dump limit register (DCMIPP_P0DCLMTR) . . . . . . . 1915
39.14.26 DCMIPP Pipe0 pixel packer configuration register
(DCMIPP_P0PPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1915
39.14.27 DCMIPP Pipe0 pixel packer Memory0 address register 1
(DCMIPP_P0PPM0AR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1917
39.14.28 DCMIPP Pipe0 pixel packer Memory0 address register 2
(DCMIPP_P0PPM0AR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1917
39.14.29 DCMIPP Pipe0 status Memory0 address register
(DCMIPP_P0STM0AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1917
39.14.30 DCMIPP Pipe0 interrupt enable register (DCMIPP_P0IER) . . . . . . . 1918
39.14.31 DCMIPP Pipe0 status register (DCMIPP_P0SR) . . . . . . . . . . . . . . . 1919
39.14.32 DCMIPP Pipe0 interrupt clear register (DCMIPP_P0FCR) . . . . . . . . 1920
39.14.33 DCMIPP Pipe0 current flow selection configuration register
(DCMIPP_P0CFSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1920
39.14.34 DCMIPP Pipe0 current flow control configuration register
(DCMIPP_P0CFCTCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1921
39.14.35 DCMIPP Pipe0 current statistic/crop start register
(DCMIPP_P0CSCSTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1922
39.14.36 DCMIPP Pipe0 current statistic/crop size register
(DCMIPP_P0CSCSZR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1922
39.14.37 DCMIPP Pipe0 current pixel packer configuration register
(DCMIPP_P0CPPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1923
39.14.38 DCMIPP Pipe0 current pixel packer Memory0 address register 1
(DCMIPP_P0CPPM0AR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1925
39.14.39 DCMIPP Pipe0 current pixel packer Memory0 address register 2
(DCMIPP_P0CPPM0AR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1925

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39.14.40 DCMIPP Pipe1 flow selection configuration register

(DCMIPP_P1FSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1926
39.14.41 DCMIPP Pipe1 stat removal configuration register
(DCMIPP_P1SRCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1927
39.14.42 DCMIPP Pipe1 bad pixel removal control register
(DCMIPP_P1BPRCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1928
39.14.43 DCMIPP Pipe1 bad pixel removal status register
(DCMIPP_P1BPRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1928
39.14.44 DCMIPP Pipe1 decimation register (DCMIPP_P1DECR) . . . . . . . . . 1929
39.14.45 DCMIPP Pipe1 black level calibration control register
(DCMIPP_P1BLCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1929
39.14.46 DCMIPP Pipe1 exposure control register 1 (DCMIPP_P1EXCR1) . . 1930
39.14.47 DCMIPP Pipe1 exposure control register 2 (DCMIPP_P1EXCR2) . . 1930
39.14.48 DCMIPP Pipe1 statistics1 control register (DCMIPP_P1ST1CR) . . . 1931
39.14.49 DCMIPP Pipe1 statistics 2 control register (DCMIPP_P1ST2CR) . . . 1932
39.14.50 DCMIPP Pipe1 statistics 3 control register (DCMIPP_P1ST3CR) . . . 1933
39.14.51 DCMIPP Pipe1 statistics window start register
(DCMIPP_P1STSTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1934
39.14.52 DCMIPP Pipe1 statistics window size register
(DCMIPP_P1STSZR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1934
39.14.53 DCMIPP Pipe1 statistics 1 status register (DCMIPP_P1ST1SR) . . . 1935
39.14.54 DCMIPP Pipe1 statistics 2 status register (DCMIPP_P1ST2SR) . . . 1936
39.14.55 DCMIPP Pipe1 statistics 3 status register (DCMIPP_P1ST3SR) . . . 1936
39.14.56 DCMIPP Pipe1 demosaicing configuration register
(DCMIPP_P1DMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1936
39.14.57 DCMIPP Pipe1 ColorConv configuration register
(DCMIPP_P1CCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1937
39.14.58 DCMIPP Pipe1 ColorConv red coefficient register 1
(DCMIPP_P1CCRR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1938
39.14.59 DCMIPP Pipe1 ColorConv red coefficient register 2
(DCMIPP_P1CCRR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1938
39.14.60 DCMIPP Pipe1 ColorConv green coefficient register 1
(DCMIPP_P1CCGR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1939
39.14.61 DCMIPP Pipe1 ColorConv green coefficient register 2
(DCMIPP_P1CCGR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1939
39.14.62 DCMIPP Pipex ColorConv blue coefficient register 1
(DCMIPP_P1CCBR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1940
39.14.63 DCMIPP Pipe1 ColorConv blue coefficient register 2
(DCMIPP_P1CCBR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1940
39.14.64 DCMIPP Pipe1 contrast control register 1 (DCMIPP_P1CTCR1) . . . 1941
39.14.65 DCMIPP Pipe1 contrast control register 2 (DCMIPP_P1CTCR2) . . . 1941

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39.14.66 DCMIPP Pipe1 contrast control register 3 (DCMIPP_P1CTCR3) . . . 1942

39.14.67 DCMIPP Pipex flow control configuration register
(DCMIPP_PxFCTCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1942
39.14.68 DCMIPP Pipex crop window start register (DCMIPP_PxCRSTR) . . . 1943
39.14.69 DCMIPP Pipex crop window size register (DCMIPP_PxCRSZR) . . . 1944
39.14.70 DCMIPP Pipex decimation register (DCMIPP_PxDCCR) . . . . . . . . . 1944
39.14.71 DCMIPP Pipex downsize configuration register
(DCMIPP_PxDSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1945
39.14.72 DCMIPP Pipex downsize ratio register (DCMIPP_PxDSRTIOR) . . . 1945
39.14.73 DCMIPP Pipex downsize destination size register
(DCMIPP_PxDSSZR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1946
39.14.74 DCMIPP Pipex common ROI configuration register
(DCMIPP_PxCMRICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1946
39.14.75 DCMIPP Pipe1 ROIx configuration register 1 (DCMIPP_P1RIxCR1) 1948
39.14.76 DCMIPP Pipe1 ROIx configuration register 2 (DCMIPP_P1RIxCR2) 1948
39.14.77 DCMIPP Pipex gamma configuration register (DCMIPP_PxGMCR) . 1949
39.14.78 DCMIPP Pipe1 YUVConv configuration register
(DCMIPP_P1YUVCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1949
39.14.79 DCMIPP Pipe1 YUVConv red coefficient register 1
(DCMIPP_P1YUVRR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1949
39.14.80 DCMIPP Pipe1 YUVConv red coefficient register 2
(DCMIPP_P1YUVRR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1950
39.14.81 DCMIPP Pipe1 YUVConv green coefficient register 1
(DCMIPP_P1YUVGR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1950
39.14.82 DCMIPP Pipe1 YUVConv green coefficient register 2
(DCMIPP_P1YUVGR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1951
39.14.83 DCMIPP Pipe1 YUVConv blue coefficient register 1
(DCMIPP_P1YUVBR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1951
39.14.84 DCMIPP Pipe1 YUV blue coefficient register 2
(DCMIPP_P1YUVBR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1951
39.14.85 DCMIPP Pipe1 pixel packer configuration register
(DCMIPP_P1PPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1952
39.14.86 DCMIPP Pipe1 pixel packer Memory0 address register 1
(DCMIPP_P1PPM0AR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1953
39.14.87 DCMIPP Pipe1 pixel packer Memory0 address register 2
(DCMIPP_P1PPM0AR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1954
39.14.88 DCMIPP Pipex pixel packer Memory0 pitch register
(DCMIPP_PxPPM0PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1954
39.14.89 DCMIPP Pipex status Memory0 address register
(DCMIPP_PxSTM0AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1955
39.14.90 DCMIPP Pipex pixel packer Memory1 address register 1
(DCMIPP_PxPPM1AR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1955

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39.14.91 DCMIPP Pipex pixel packer Memory1 address register 2

(DCMIPP_PxPPM1AR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1955
39.14.92 DCMIPP Pipex pixel packer Memory1 pitch register
(DCMIPP_PxPPM1PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1956
39.14.93 DCMIPP Pipex status Memory1 address register
(DCMIPP_PxSTM1AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1956
39.14.94 DCMIPP Pipex pixel packer memory2 address register 1
(DCMIPP_PxPPM2AR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1957
39.14.95 DCMIPP Pipex pixel packer memory2 address register 2
(DCMIPP_PxPPM2AR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1957
39.14.96 DCMIPP Pipex status Memory2 address register
(DCMIPP_PxSTM2AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1957
39.14.97 DCMIPP Pipe1 interrupt enable register (DCMIPP_P1IER) . . . . . . . 1958
39.14.98 DCMIPP Pipe1 status register (DCMIPP_P1SR) . . . . . . . . . . . . . . . 1959
39.14.99 DCMIPP Pipe1 interrupt clear register (DCMIPP_P1FCR) . . . . . . . . 1960
39.14.100DCMIPP Pipe1 current flow selection configuration register
(DCMIPP_P1CFSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1960
39.14.101DCMIPP Pipe1 current bad pixel removal register
(DCMIPP_P1CBPRCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1961
39.14.102DCMIPP Pipe1 current black level calibration control register
(DCMIPP_P1CBLCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1962
39.14.103DCMIPP Pipe1 current exposure control register 1
(DCMIPP_P1CEXCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1962
39.14.104DCMIPP Pipe1 current exposure control register 2
(DCMIPP_P1CEXCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1963
39.14.105DCMIPP Pipe1 current statistics 1 control register
(DCMIPP_P1CST1CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1964
39.14.106DCMIPP Pipe1 current statistics 2 control register
(DCMIPP_P1CST2CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1965
39.14.107DCMIPP Pipe1 current statistics 3 control register
(DCMIPP_P1CST3CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1966
39.14.108DCMIPP Pipe1 current statistics window start register
(DCMIPP_P1CSTSTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1967
39.14.109DCMIPP Pipe1 current statistics window size register
(DCMIPP_P1CSTSZR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1967
39.14.110DCMIPP Pipe1 current ColorConv configuration register
(DCMIPP_P1CCCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1968
39.14.111DCMIPP Pipe1 current ColorConv red coefficient register 1
(DCMIPP_P1CCCRR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1968
39.14.112DCMIPP Pipe1 current ColorConv red coefficient register 2
(DCMIPP_P1CCCRR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1969
39.14.113DCMIPP Pipe1 current ColorConv green coefficient register 1
(DCMIPP_P1CCCGR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1969

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39.14.114DCMIPP Pipe1 current ColorConv green coefficient register 2

(DCMIPP_P1CCCGR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1970
39.14.115DCMIPP Pipex current ColorConv blue coefficient register 1
(DCMIPP_P1CCCBR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1970
39.14.116DCMIPP Pipe1 current ColorConv blue coefficient register 2
(DCMIPP_P1CCCBR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1971
39.14.117DCMIPP Pipe1 current contrast control register 1
(DCMIPP_P1CCTCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1971
39.14.118DCMIPP Pipe1 current contrast control register 2
(DCMIPP_P1CCTCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1972
39.14.119DCMIPP Pipe1 current contrast control register 3
(DCMIPP_P1CCTCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1972
39.14.120DCMIPP Pipex current flow control configuration register
(DCMIPP_PxCFCTCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1973
39.14.121DCMIPP Pipex current crop window start register
(DCMIPP_PxCCRSTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1974
39.14.122DCMIPP Pipex current crop window size register
(DCMIPP_PxCCRSZR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1974
39.14.123DCMIPP Pipex current decimation register (DCMIPP_PxCDCCR) . 1975
39.14.124DCMIPP Pipex current downsize configuration register
(DCMIPP_PxCDSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1975
39.14.125DCMIPP Pipex current downsize ratio register
(DCMIPP_PxCDSRTIOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1976
39.14.126DCMIPP Pipex current downsize destination size register
(DCMIPP_PxCDSSZR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1976
39.14.127DCMIPP Pipex current common ROI configuration register
(DCMIPP_PxCCMRICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1977
39.14.128DCMIPP Pipe1 current ROIx configuration register 1
(DCMIPP_P1CRIxCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1978
39.14.129DCMIPP Pipe1 current ROIx configuration register 2
(DCMIPP_P1CRIxCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1978
39.14.130DCMIPP Pipe1 current pixel packer configuration register
(DCMIPP_P1CPPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1979
39.14.131DCMIPP Pipe1 current pixel packer Memory0 address register 1
(DCMIPP_P1CPPM0AR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1980
39.14.132DCMIPP Pipe1 current pixel packer Memory0 address register 2
(DCMIPP_P1CPPM0AR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1981
39.14.133DCMIPP Pipex current pixel packer Memory0 pitch register
(DCMIPP_PxCPPM0PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1981
39.14.134DCMIPP Pipex current pixel packer Memory1 address register 1
(DCMIPP_PxCPPM1AR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1981
39.14.135DCMIPP Pipex current pixel packer Memory1 address register 2
(DCMIPP_PxCPPM1AR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1982

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39.14.136DCMIPP Pipex current pixel packer Memory1 pitch register

(DCMIPP_PxCPPM1PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1982
39.14.137DCMIPP Pipex current pixel packer Memory2 address register 1
(DCMIPP_PxCPPM2AR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1983
39.14.138DCMIPP Pipex current pixel packer Memory2 address register 1
(DCMIPP_PxCPPM2AR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1983
39.14.139DCMIPP Pipe2 flow selection configuration register
(DCMIPP_P2FSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1983
39.14.140DCMIPP Pipe2 ROIx configuration register 1 (DCMIPP_P2RIxCR1) 1984
39.14.141DCMIPP Pipe2 ROIx configuration register 2 (DCMIPP_P2RIxCR2) 1985
39.14.142DCMIPP Pipe2 pixel packer configuration register
(DCMIPP_P2PPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1985
39.14.143DCMIPP Pipe2 pixel packer Memory0 address register 1
(DCMIPP_P2PPM0AR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1987
39.14.144DCMIPP Pipe2 pixel packer Memory0 address register 2
(DCMIPP_P2PPM0AR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1987
39.14.145DCMIPP Pipe2 interrupt enable register (DCMIPP_P2IER) . . . . . . . 1987
39.14.146DCMIPP Pipe2 status register (DCMIPP_P2SR) . . . . . . . . . . . . . . . 1988
39.14.147DCMIPP Pipe2 interrupt clear register (DCMIPP_P2FCR) . . . . . . . . 1989
39.14.148DCMIPP Pipe2 current flow selection configuration register
(DCMIPP_P2CFSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1990
39.14.149DCMIPP Pipe2 current ROIx configuration register 1
(DCMIPP_P2CRIxCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1991
39.14.150DCMIPP Pipe2 current ROIx configuration register 2
(DCMIPP_P2CRIxCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1991
39.14.151DCMIPP Pipe2 current pixel packer configuration register
(DCMIPP_P2CPPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1992
39.14.152DCMIPP Pipe2 current pixel packer Memory0 address register 1
(DCMIPP_P2CPPM0AR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1993
39.14.153DCMIPP Pipe2 current pixel packer Memory0 address register 2
(DCMIPP_P2CPPM0AR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1993
39.15 DCMIPP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1994

40 CSI-2 Host (CSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2009

40.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2009
40.2 Standard and references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2009
40.3 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2009
40.4 CSI-2 Host main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2010
40.5 CSI-2 Host functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2010
40.5.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2010

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40.5.2 System level architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2012

40.5.3 CSI-2 Host reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2013
40.5.4 Lane merger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2014
40.5.5 Clock changer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2015
40.5.6 Low-level protocol (LLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2016
40.5.7 CSI-2 Host protocol output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2026
40.6 CSI-2 Host programming guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2026
40.6.1 CSI-2 PHY setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2026
40.6.2 CSI-2 Host controller setup and data reception start . . . . . . . . . . . . . 2027
40.6.3 Data reception stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2028
40.7 CSI-2 Host low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2028
40.8 CSI-2 Host interrupts and errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2028
40.8.1 Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2030
40.8.2 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2032
40.9 CSI-2 Host registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2033
40.9.1 CSI-2 Host control register (CSI_CR) . . . . . . . . . . . . . . . . . . . . . . . . 2033
40.9.2 CSI-2 Host DPHY_RX control register (CSI_PCR) . . . . . . . . . . . . . . 2035
40.9.3 CSI-2 Host virtual channel x configuration register 1
(CSI_VCxCFGR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2036
40.9.4 CSI-2 Host virtual channel x configuration register 2
(CSI_VCxCFGR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2038
40.9.5 CSI-2 Host virtual channel x configuration register 3
(CSI_VCxCFGR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2039
40.9.6 CSI-2 Host virtual channel x configuration register 4
(CSI_VCxCFGR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2040
40.9.7 CSI-2 Host line byte x configuration register (CSI_LBxCFGR) . . . . . 2041
40.9.8 CSI-2 Host timer x configuration register (CSI_TIMxCFGR) . . . . . . . 2042
40.9.9 CSI-2 Host lane merger configuration register (CSI_LMCFGR) . . . . 2042
40.9.10 CSI-2 Host program interrupt register (CSI_PRGITR) . . . . . . . . . . . . 2043
40.9.11 CSI-2 Host watchdog register (CSI_WDR) . . . . . . . . . . . . . . . . . . . . 2047
40.9.12 CSI-2 Host interrupt enable register 0 (CSI_IER0) . . . . . . . . . . . . . . 2047
40.9.13 CSI-2 Host interrupt enable register 1 (CSI_IER1) . . . . . . . . . . . . . . 2050
40.9.14 CSI-2 Host status register 0 (CSI_SR0) . . . . . . . . . . . . . . . . . . . . . . 2052
40.9.15 CSI-2 Host status register 1 (CSI_SR1) . . . . . . . . . . . . . . . . . . . . . . 2054
40.9.16 CSI-2 Host flag clear register 0 (CSI_FCR0) . . . . . . . . . . . . . . . . . . . 2056
40.9.17 CSI-2 Host flag clear register 1 (CSI_FCR1) . . . . . . . . . . . . . . . . . . . 2057
40.9.18 CSI-2 Host short packet data field register (CSI_SPDFR) . . . . . . . . 2058
40.9.19 CSI-2 Host error register 1 (CSI_ERR1) . . . . . . . . . . . . . . . . . . . . . . 2059

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40.9.20 CSI-2 Host error register 2 (CSI_ERR2) . . . . . . . . . . . . . . . . . . . . . . 2060

40.10 CSI PHY registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2060
40.10.1 CSI PHY reset control register (CSI_PRCR) . . . . . . . . . . . . . . . . . . . 2060
40.10.2 CSI PHY mode control register (CSI_PMCR) . . . . . . . . . . . . . . . . . . 2061
40.10.3 CSI PHY frequency control register (CSI_PFCR) . . . . . . . . . . . . . . . 2062
40.10.4 CSI PHY test control register 0 (CSI_PTCR0) . . . . . . . . . . . . . . . . . . 2062
40.10.5 CSI PHY test control register 1 (CSI_PTCR1) . . . . . . . . . . . . . . . . . . 2063
40.10.6 CSI PHY test status register (CSI_PTSR) . . . . . . . . . . . . . . . . . . . . . 2063
40.11 CSI-2 Host and PHY register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2063

41 Parallel synchronous slave interface (PSSI) . . . . . . . . . . . . . . . . . . 2067

41.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2067
41.2 PSSI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2067
41.3 PSSI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2067
41.3.1 PSSI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2068
41.3.2 PSSI pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2068
41.3.3 PSSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2069
41.3.4 PSSI data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2069
41.3.5 PSSI optional control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2071
41.4 PSSI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2074
41.5 PSSI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2075
41.5.1 PSSI control register (PSSI_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2075
41.5.2 PSSI status register (PSSI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2076
41.5.3 PSSI raw interrupt status register (PSSI_RIS) . . . . . . . . . . . . . . . . . 2077
41.5.4 PSSI interrupt enable register (PSSI_IER) . . . . . . . . . . . . . . . . . . . . 2078
41.5.5 PSSI masked interrupt status register (PSSI_MIS) . . . . . . . . . . . . . . 2078
41.5.6 PSSI interrupt clear register (PSSI_ICR) . . . . . . . . . . . . . . . . . . . . . . 2079
41.5.7 PSSI data register (PSSI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2079
41.5.8 PSSI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2080

42 Display subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2081

42.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2081
42.2 Display subsystem main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2081
42.3 Display subsystem implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 2081
42.4 Display subsystem functional description . . . . . . . . . . . . . . . . . . . . . . . 2081
42.4.1 Display subsystem block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 2081

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42.4.2 Display subsystem pins and external signal interface . . . . . . . . . . . . 2082

42.4.3 Display subsystem clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2082
42.4.4 Display subsystem security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2082
42.5 Display subsystem programmable parameters . . . . . . . . . . . . . . . . . . 2085
42.6 Display subsystem interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2086
42.7 Display subsystem registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2086

43 LCD-TFT display controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . . 2087

43.1 LTDC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2087
43.2 LTDC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2087
43.3 LTDC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2088
43.3.1 LTDC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2088
43.3.2 LTDC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2088
43.3.3 LTDC reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2089
43.4 LTDC configuration parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2091
43.4.1 AXI master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2091
43.4.2 Input layer definition and cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . 2092
43.4.3 Input pixel format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2093
43.4.4 YUV planar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2095
43.4.5 YUV-to-RGB color conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2096
43.4.6 Horizontal or vertical mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2097
43.4.7 Default layer color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2098
43.4.8 Color look-up table (CLUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2098
43.4.9 Transparency color keying . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2099
43.4.10 Display composition - windowing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2099
43.4.11 Display composition - blending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2100
43.4.12 Gamma correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2102
43.4.13 YUV output conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2102
43.4.14 Dithering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2103
43.4.15 CRC hashing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2104
43.4.16 Display timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2104
43.4.17 Output interface polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2106
43.4.18 Shadow registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2107
43.4.19 General control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2108
43.4.20 Hardware trigger generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2108
43.4.21 Provision for a secure layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2109

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43.5 LTDC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2110

43.6 LTDC programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2111
43.7 LTDC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2112
43.7.1 LTDC synchronization size configuration register (LTDC_SSCR) . . . 2112
43.7.2 LTDC back porch configuration register (LTDC_BPCR) . . . . . . . . . . 2112
43.7.3 LTDC active width configuration register (LTDC_AWCR) . . . . . . . . . 2113
43.7.4 LTDC total width configuration register (LTDC_TWCR) . . . . . . . . . . . 2114
43.7.5 LTDC global control register (LTDC_GCR) . . . . . . . . . . . . . . . . . . . . 2114
43.7.6 LTDC shadow reload configuration register (LTDC_SRCR) . . . . . . . 2116
43.7.7 LTDC gamma correction configuration register (LTDC_GCCR) . . . . 2116
43.7.8 LTDC background color configuration register (LTDC_BCCR) . . . . . 2117
43.7.9 LTDC interrupt enable register (LTDC_IER) . . . . . . . . . . . . . . . . . . . 2118
43.7.10 LTDC interrupt status register (LTDC_ISR) . . . . . . . . . . . . . . . . . . . . 2119
43.7.11 LTDC interrupt clear register (LTDC_ICR) . . . . . . . . . . . . . . . . . . . . . 2119
43.7.12 LTDC line interrupt position configuration register (LTDC_LIPCR) . . 2120
43.7.13 LTDC current position status register (LTDC_CPSR) . . . . . . . . . . . . 2121
43.7.14 LTDC current display status register (LTDC_CDSR) . . . . . . . . . . . . . 2121
43.7.15 LTDC external display control register (LTDC_EDCR) . . . . . . . . . . . 2122
43.7.16 LTDC interrupt enable register 2 (LTDC_IER2) . . . . . . . . . . . . . . . . . 2122
43.7.17 LTDC interrupt status register 2 (LTDC_ISR2) . . . . . . . . . . . . . . . . . 2123
43.7.18 LTDC interrupt clear register 2 (LTDC_ICR2) . . . . . . . . . . . . . . . . . . 2124
43.7.19 LTDC line interrupt position configuration register 2 (LTDC_LIPCR2) 2125
43.7.20 LTDC expected CRC register (LTDC_ECRCR) . . . . . . . . . . . . . . . . . 2125
43.7.21 LTDC computed CRC register (LTDC_CCRCR) . . . . . . . . . . . . . . . . 2126
43.7.22 LTDC FIFO underrun threshold register (LTDC_FUTR) . . . . . . . . . . 2126
43.7.23 LTDC layer x configuration 0 register (LTDC_LxC0R) . . . . . . . . . . . . 2127
43.7.24 LTDC layer x configuration 1 register (LTDC_LxC1R) . . . . . . . . . . . . 2128
43.7.25 LTDC layer x reload control register (LTDC_LxRCR) . . . . . . . . . . . . 2128
43.7.26 LTDC layer x control register (LTDC_LxCR) . . . . . . . . . . . . . . . . . . . 2129
43.7.27 LTDC layer x window horizontal position configuration register
(LTDC_LxWHPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2130
43.7.28 LTDC layer x window vertical position configuration register
(LTDC_LxWVPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2131
43.7.29 LTDC layer x color keying configuration register
(LTDC_LxCKCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2131
43.7.30 LTDC layer x pixel format configuration register
(LTDC_LxPFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2132

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43.7.31 LTDC layer x constant alpha configuration register

(LTDC_LxCACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2132
43.7.32 LTDC layer x default color configuration register
(LTDC_LxDCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2133
43.7.33 LTDC layer x blending factors configuration register
(LTDC_LxBFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2133
43.7.34 LTDC layer x burst length configuration register
(LTDC_LxBLCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2134
43.7.35 LTDC layer x planar configuration register
(LTDC_LxPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2135
43.7.36 LTDC layer x color frame buffer address register
(LTDC_LxCFBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2136
43.7.37 LTDC layer x color frame buffer length register
(LTDC_LxCFBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2136
43.7.38 LTDC layer x color frame buffer line number register
(LTDC_LxCFBLNR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2137
43.7.39 LTDC layer 1 auxiliary frame buffer address 0 register
(LTDC_L1AFBA0R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2137
43.7.40 LTDC layer 1 auxiliary frame buffer address 1 register
(LTDC_L1AFBA1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2138
43.7.41 LTDC layer 1 auxiliary frame buffer length register
(LTDC_L1AFBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2138
43.7.42 LTDC layer 1 auxiliary frame buffer line number register
(LTDC_L1AFBLNR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2139
43.7.43 LTDC layer x CLUT write register (LTDC_LxCLUTWR) . . . . . . . . . . 2139
43.7.44 LTDC layer x conversion YCbCr RGB 0 register (LTDC_LxCYR0R) . 2140
43.7.45 LTDC layer x conversion YCbCr RGB 1 register (LTDC_LxCYR1R) . 2140
43.7.46 LTDC layer x flexible pixel format 0 register (LTDC_LxFPF0R) . . . . . 2141
43.7.47 LTDC layer x flexible pixel format 1 register (LTDC_LxFPF1R) . . . . . 2141
43.7.48 LTDC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2142

44 Neo-Chrom graphic processor (GPU2D) . . . . . . . . . . . . . . . . . . . . . . 2147

44.1 GPU2D introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2147
44.2 GPU2D main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2147
44.3 GPU2D general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2148
44.3.1 GPU2D block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2148
44.3.2 GPU2D pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2148

45 Video encoder (VENC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2150

45.1 VENC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2150

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45.2 VENC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2150

45.3 VENC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2150
45.4 VENC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2151
45.4.1 VENC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2151
45.4.2 VENC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2151
45.4.3 VENC reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2152
45.4.4 VENC pre-processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2152
45.4.5 VENC H264 encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2152
45.4.6 VENC JPEG encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2153
45.4.7 VENC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2153
45.4.8 VENC security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2154
45.4.9 VENC power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2154
45.4.10 VENCRAM power-on sequence for AXI access . . . . . . . . . . . . . . . . 2155
45.5 VENC low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2155
45.6 VENC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2155
45.7 VENC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2155
45.7.1 VENC ID register (VENC_SWREG0) . . . . . . . . . . . . . . . . . . . . . . . . 2155
45.7.2 VENC interrupt register (VENC_SWREG1) . . . . . . . . . . . . . . . . . . . . 2156
45.7.3 VENC bus interface configuration register (VENC_SWREG2) . . . . . 2156
45.7.4 VENC device configuration register (VENC_SWREG3) . . . . . . . . . . 2156
45.7.5 VENC base address for output stream data register
(VENC_SWREG5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2157
45.7.6 VENC base address for output control data register
(VENC_SWREG6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2157
45.7.7 VENC base address for reference luma register
(VENC_SWREG7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2157
45.7.8 VENC base address for reference chroma register
(VENC_SWREG8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2158
45.7.9 VENC base address for reconstructed luma register
(VENC_SWREG9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2158
45.7.10 VENC base address for reconstructed chroma register
(VENC_SWREG10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2158
45.7.11 VENC base address for input picture luma register
(VENC_SWREG11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2159
45.7.12 VENC base address for input picture cb register
(VENC_SWREG12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2159
45.7.13 VENC base address for input picture cr register
(VENC_SWREG13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2159
45.7.14 VENC encoder control register 0 (VENC_SWREG14) . . . . . . . . . . . 2160

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45.7.15 VENC encoder control register 1 (VENC_SWREG15) . . . . . . . . . . . 2160

45.7.16 VENC encoder control register 2 (VENC_SWREG16) . . . . . . . . . . . 2160
45.7.17 VENC encoder control register 3 (VENC_SWREG17) . . . . . . . . . . . 2161
45.7.18 VENC encoder control register 4 (VENC_SWREG18) . . . . . . . . . . . 2161
45.7.19 VENC encoder control register 5 (VENC_SWREG19) . . . . . . . . . . . 2161
45.7.20 VENC encoder control register 6 (VENC_SWREG20) . . . . . . . . . . . 2162
45.7.21 VENC encoder control register 7 (VENC_SWREG21) . . . . . . . . . . . 2162
45.7.22 VENC stream header remainder MSB bits register
(VENC_SWREG22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2162
45.7.23 VENC stream header remainder LSB bits register
(VENC_SWREG23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2163
45.7.24 VENC stream buffer limit/output stream size register
(VENC_SWREG24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2163
45.7.25 VENC encoder control register 8 (VENC_SWREG25) . . . . . . . . . . . 2163
45.7.26 VENC intra-slice bitmap
register (VENC_SWREG26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2164
45.7.27 VENC encoder control register 9 (VENC_SWREG27) . . . . . . . . . . . 2164
45.7.28 VENC encoder control register 10 (VENC_SWREG28) . . . . . . . . . . 2164
45.7.29 VENC encoder control register 11 (VENC_SWREG29) . . . . . . . . . . 2165
45.7.30 VENC encoder control register 12 (VENC_SWREG30) . . . . . . . . . . 2165
45.7.31 VENC encoder control register 13 (VENC_SWREG31) . . . . . . . . . . 2165
45.7.32 VENC encoder control register 14 (VENC_SWREG32) . . . . . . . . . . 2166
45.7.33 VENC encoder control register 15 (VENC_SWREG33) . . . . . . . . . . 2166
45.7.34 VENC encoder control register 16 (VENC_SWREG34) . . . . . . . . . . 2166
45.7.35 VENC H.264 checkpoint word error 5-6/encoder control register 17
(VENC_SWREG35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2167
45.7.36 VENC H.264 checkpoint delta QP 1-8/encoder control register 18
(VENC_SWREG36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2167
45.7.37 VENC encoder control register 19, stream start offset
(VENC_SWREG37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2167
45.7.38 VENC macroblock count output register (VENC_SWREG38) . . . . . . 2168
45.7.39 VENC base address for next pic luminance register
(VENC_SWREG39) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2168
45.7.40 VENC stabilization mode control register (VENC_SWREG40) . . . . . 2168
45.7.41 VENC stabilization motion sum div8 output register
(VENC_SWREG41) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2169
45.7.42 VENC stabilization GMV output, matrix 1, up-left position
output register (VENC_SWREG42) . . . . . . . . . . . . . . . . . . . . . . . . . . 2169
45.7.43 VENC stabilization GMV output, matrix 2, up position
output register (VENC_SWREG43) . . . . . . . . . . . . . . . . . . . . . . . . . . 2169

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45.7.44 VENC stabilization matrix 3, up-right position

output register (VENC_SWREG44) . . . . . . . . . . . . . . . . . . . . . . . . . . 2170
45.7.45 VENC stabilization matrix 4, left position
output register (VENC_SWREG45) . . . . . . . . . . . . . . . . . . . . . . . . . . 2170
45.7.46 VENC stabilization matrix 5, GMV position
output register (VENC_SWREG46) . . . . . . . . . . . . . . . . . . . . . . . . . . 2170
45.7.47 VENC stabilization matrix 6, right position
output register (VENC_SWREG47) . . . . . . . . . . . . . . . . . . . . . . . . . . 2171
45.7.48 VENC stabilization matrix 7, down-left position
output register (VENC_SWREG48) . . . . . . . . . . . . . . . . . . . . . . . . . . 2171
45.7.49 VENC stabilization matrix 8, down position
output register (VENC_SWREG49) . . . . . . . . . . . . . . . . . . . . . . . . . . 2171
45.7.50 VENC stabilization matrix 9, down-right position
output register (VENC_SWREG50) . . . . . . . . . . . . . . . . . . . . . . . . . . 2172
45.7.51 VENC base address for cabac context tables H264
register (VENC_SWREG51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2172
45.7.52 VENC base address for MV output writing
register (VENC_SWREG52) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2172
45.7.53 VENC RGB to YUV conversion coefficient A - B
register (VENC_SWREG53) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2173
45.7.54 VENC RGB to YUV conversion coefficient C - E
register (VENC_SWREG54) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2173
45.7.55 VENC RGB to YUV conversion coefficient F, RGB mask
MSB bit position register (VENC_SWREG55) . . . . . . . . . . . . . . . . . . 2173
45.7.56 VENC intra area register (VENC_SWREG56) . . . . . . . . . . . . . . . . . . 2174
45.7.57 VENC CIR intra mb position register (VENC_SWREG57) . . . . . . . . 2174
45.7.58 VENC intra slice bitmap for slices 0..31/base address for
1st DCT partition register (VENC_SWREG58) . . . . . . . . . . . . . . . . . 2174
45.7.59 VENC intra slice bitmap for slices 32..63/base address for
2nd DCT partition register (VENC_SWREG59) . . . . . . . . . . . . . . . . . 2175
45.7.60 VENC 1st ROI area register (VENC_SWREG60) . . . . . . . . . . . . . . . 2175
45.7.61 VENC 2nd ROI area register (VENC_SWREG61) . . . . . . . . . . . . . . 2175
45.7.62 VENC ROI area delta QP, MV register (VENC_SWREG62) . . . . . . . 2176
45.7.63 VENC synthesis configuration register encoder 0
register (VENC_SWREG63) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2176
45.7.64 VENC JPEG luma quantization 1/intra 16x16 mode 0-1
penalty register (VENC_SWREG64) . . . . . . . . . . . . . . . . . . . . . . . . . 2176
45.7.65 VENC JPEG luma quantization 2/intra 16x16 mode 2-3
penalty register (VENC_SWREG65) . . . . . . . . . . . . . . . . . . . . . . . . . 2177
45.7.66 VENC JPEG luma quantization 3/intra 4x4 mode 0-1
penalty register (VENC_SWREG66) . . . . . . . . . . . . . . . . . . . . . . . . . 2177
45.7.67 VENC JPEG luma quantization 4/intra 4x4 mode 2-3
penalty register (VENC_SWREG67) . . . . . . . . . . . . . . . . . . . . . . . . . 2177

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45.7.68 VENC JPEG luma quantization 5/intra 4x4 mode 4-5

penalty register (VENC_SWREG68) . . . . . . . . . . . . . . . . . . . . . . . . . 2178
45.7.69 VENC JPEG luma quantization 6/intra 4x4 mode 6-7
penalty register (VENC_SWREG69) . . . . . . . . . . . . . . . . . . . . . . . . . 2178
45.7.70 VENC JPEG luma quantization 7/intra 4x4 mode 8-9
penalty register (VENC_SWREG70) . . . . . . . . . . . . . . . . . . . . . . . . . 2178
45.7.71 VENC JPEG luma quantization 8/base address for
segmentation map register (VENC_SWREG71) . . . . . . . . . . . . . . . . 2179
45.7.72 VENC JPEG luma quantization 9/segment1
parameter register (VENC_SWREG72) . . . . . . . . . . . . . . . . . . . . . . 2179
45.7.73 VENC JPEG luma quantization 10/segment1
parameter register (VENC_SWREG73) . . . . . . . . . . . . . . . . . . . . . . 2179
45.7.74 VENC JPEG luma quantization 11/segment1
parameter register (VENC_SWREG74) . . . . . . . . . . . . . . . . . . . . . . 2180
45.7.75 VENC JPEG luma quantization 12/segment1
parameter register (VENC_SWREG75) . . . . . . . . . . . . . . . . . . . . . . 2180
45.7.76 VENC JPEG luma quantization 13/segment1
parameter register (VENC_SWREG76) . . . . . . . . . . . . . . . . . . . . . . 2180
45.7.77 VENC JPEG luma quantization 14/segment1
parameter register (VENC_SWREG77) . . . . . . . . . . . . . . . . . . . . . . 2181
45.7.78 VENC JPEG luma quantization 15/segment1
parameter register (VENC_SWREG78) . . . . . . . . . . . . . . . . . . . . . . 2181
45.7.79 VENC JPEG luma quantization 16/segment2
parameter register (VENC_SWREG79) . . . . . . . . . . . . . . . . . . . . . . 2181
45.7.80 VENC JPEG chroma quantization 1/segment2
parameter register (VENC_SWREG80) . . . . . . . . . . . . . . . . . . . . . . 2182
45.7.81 VENC JPEG chroma quantization 2/segment2
parameter register (VENC_SWREG81) . . . . . . . . . . . . . . . . . . . . . . 2182
45.7.82 VENC JPEG chroma quantization 3/segment2
parameter register (VENC_SWREG82) . . . . . . . . . . . . . . . . . . . . . . 2182
45.7.83 VENC JPEG chroma quantization 4/segment2
parameter register (VENC_SWREG83) . . . . . . . . . . . . . . . . . . . . . . 2183
45.7.84 VENC JPEG chroma quantization 5/segment2
parameter register (VENC_SWREG84) . . . . . . . . . . . . . . . . . . . . . . 2183
45.7.85 VENC JPEG chroma quantization 6/segment2
parameter register (VENC_SWREG85) . . . . . . . . . . . . . . . . . . . . . . 2183
45.7.86 VENC JPEG chroma quantization 7/segment2
parameter register (VENC_SWREG86) . . . . . . . . . . . . . . . . . . . . . . 2184
45.7.87 VENC JPEG chroma quantization 8/segment2
parameter register (VENC_SWREG87) . . . . . . . . . . . . . . . . . . . . . . 2184
45.7.88 VENC JPEG chroma quantization 9/segment3
parameter register (VENC_SWREG88) . . . . . . . . . . . . . . . . . . . . . . 2184

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45.7.89 VENC JPEG chroma quantization 10/segment3

parameter register (VENC_SWREG89) . . . . . . . . . . . . . . . . . . . . . . 2185
45.7.90 VENC JPEG chroma quantization 11/segment3
parameter register (VENC_SWREG90) . . . . . . . . . . . . . . . . . . . . . . 2185
45.7.91 VENC JPEG chroma quantization 12/segment3
parameter register (VENC_SWREG91) . . . . . . . . . . . . . . . . . . . . . . 2185
45.7.92 VENC JPEG chroma quantization 13/segment3
parameter register (VENC_SWREG92) . . . . . . . . . . . . . . . . . . . . . . 2186
45.7.93 VENC JPEG chroma quantization 14/segment3
parameter register (VENC_SWREG93) . . . . . . . . . . . . . . . . . . . . . . 2186
45.7.94 VENC JPEG chroma quantization 15/segment3
parameter register (VENC_SWREG94) . . . . . . . . . . . . . . . . . . . . . . 2186
45.7.95 VENC JPEG chroma quantization 16/segment3
parameter register (VENC_SWREG95) . . . . . . . . . . . . . . . . . . . . . . 2187
45.7.96 VENC DMV 4p/1p penalty values 0-3 register (VENC_SWREG96) . 2187
45.7.97 VENC DMV 4p/1p penalty values 4-7 register (VENC_SWREG97) . 2187
45.7.98 VENC DMV 4p/1p penalty values register (VENC_SWREGx) . . . . . 2188
45.7.99 VENC DMV 4p/1p penalty values 124-127
register (VENC_SWREG127) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2188
45.7.100 VENC DMV qpel penalty values 0-3
register (VENC_SWREG128) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2188
45.7.101 VENC DMV qpel penalty values 4-7
register (VENC_SWREG129) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2189
45.7.102 VENC DMV qpel penalty values register (VENC_SWREGx) . . . . . . 2189
45.7.103 VENC DMV qpel penalty values 124-127 register
(VENC_SWREG159) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2189
45.7.104 VENC base address for output of down-scaled encoder image
in YUYV [Link] format register (VENC_SWREG231) . . . . . . . . . . . . . 2190
45.7.105 VENC scaling control register (VENC_SWREGx) . . . . . . . . . . . . . . . 2190
45.7.106 VENC squared error output calculated for 13x13 pixels
per macroblock register (VENC_SWREG236) . . . . . . . . . . . . . . . . . 2190
45.7.107 VENC MAD 2 control and output register (VENC_SWREG237) . . . . 2191
45.7.108 VENC MAD 3 control and output register (VENC_SWREG238) . . . . 2191
45.7.109 VENC segment 1: intra 16x16 mode 0-2 penalty
register (VENC_SWREG256) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2191
45.7.110 VENC segment 1: intra 16x16 mode 3, intra 4x4 0-1
penalty register (VENC_SWREG257) . . . . . . . . . . . . . . . . . . . . . . . . 2192
45.7.111 VENC segment 1: intra 4x4 mode 2-4 penalty
register (VENC_SWREG258) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2192
45.7.112 VENC segment 1: intra 4x4 mode 5-7 penalty
register (VENC_SWREG259) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2192

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45.7.113 VENC segment 1: intra 4x4 mode 8-9 penalty, previous

mode favor for H.264 register (VENC_SWREG260) . . . . . . . . . . . . . 2193
45.7.114 VENC segment 1: bit cost of inter type, intra 16x16 mode
favor register (VENC_SWREG261) . . . . . . . . . . . . . . . . . . . . . . . . . . 2193
45.7.115 VENC segment 1: inter MB mode favor, skip mode penalty,
penalty value for 2nd reference frame register (VENC_SWREG262) 2193
45.7.116 VENC segment 1: penalty value register (VENC_SWREGx) . . . . . . 2194
45.7.117 VENC segment 1: deadzone rate multiplier for plane 0-1
register (VENC_SWREG265) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2194
45.7.118 VENC segment 1: deadzone rate multiplier for plane 2-3
register (VENC_SWREG266) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2194
45.7.119 VENC segment 1: deadzone rate for macroblock skip token 0-1,
dmv penalty coefficient register (VENC_SWREG267) . . . . . . . . . . . 2195
45.7.120 VENC segment 2: intra 16x16 mode 0-2 penalty
register (VENC_SWREG268) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2195
45.7.121 VENC segment 2: intra 16x16 mode 3 penalty, intra 4x4 mode 0-1
penalty register (VENC_SWREG269) . . . . . . . . . . . . . . . . . . . . . . . . 2195
45.7.122 VENC segment 2: intra 4x4 mode 2-4 penalty
register (VENC_SWREG270) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2196
45.7.123 VENC segment 2: intra 4x4 mode 5-7 penalty
register (VENC_SWREG271) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2196
45.7.124 VENC segment 2: intra 4x4 mode 8-9 penalty, intra 4x4 previous
mode favor for H.264 register (VENC_SWREG272) . . . . . . . . . . . . . 2196
45.7.125 VENC segment 2: bit cost of inter type, intra 16x16
mode favor register (VENC_SWREG273) . . . . . . . . . . . . . . . . . . . . . 2197
45.7.126 VENC segment 2: inter MB mode favor, skip mode penalty,
penalty value register (VENC_SWREG274) . . . . . . . . . . . . . . . . . . . 2197
45.7.127 VENC segment 2: penalty value register (VENC_SWREGx) . . . . . . 2197
45.7.128 VENC segment 2: deadzone rate multiplier for plane 0-1
register (VENC_SWREG277) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2198
45.7.129 VENC segment 2: deadzone rate multiplier for plane 2-3
register (VENC_SWREG278) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2198
45.7.130 VENC segment 2: deadzone rate for macroblock skip token 0-1,
dmv penalty coefficient register (VENC_SWREG279) . . . . . . . . . . . 2198
45.7.131 VENC segment 3: intra 16x16 mode 0-2 penalty
register (VENC_SWREG280) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2199
45.7.132 VENC segment 3: intra 16x16 mode 3 penalty, intra 4x4 mode 0-1
penalty register (VENC_SWREG281) . . . . . . . . . . . . . . . . . . . . . . . . 2199
45.7.133 VENC segment 3: intra 4x4 mode 2-4 penalty
register (VENC_SWREG282) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2199
45.7.134 VENC segment 3: intra 4x4 mode 5-7 penalty
register (VENC_SWREG283) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2200

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45.7.135 VENC segment 3: intra 4x4 mode 8-9 penalty, intra 4x4
previous mode favor for H.264 register (VENC_SWREG284) . . . . . 2200
45.7.136 VENC segment 3: bit cost of inter type, intra 16x16
mode favor register (VENC_SWREG285) . . . . . . . . . . . . . . . . . . . . . 2200
45.7.137 VENC segment 3: inter MB mode favor in intra/inter selection,
inter MB mode favor, penalty value for second reference frame
register (VENC_SWREG286) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2201
45.7.138 VENC segment 3: penalty value register (VENC_SWREGx) . . . . . . 2201
45.7.139 VENC segment 3: deadzone rate multiplier for plane 0-1
register (VENC_SWREG289) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2201
45.7.140 VENC segment 3: deadzone rate multiplier for plane 2-3
register (VENC_SWREG290) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2202
45.7.141 VENC segment 3: deadzone rate for macroblock skip token 0-1,
dmv penalty coefficient register (VENC_SWREG291) . . . . . . . . . . . 2202
45.7.142 VENC Mb boost register (VENC_SWREG294) . . . . . . . . . . . . . . . . . 2202
45.7.143 VENC variance control, Pskop conding mode
register (VENC_SWREG295) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2203
45.7.144 VENC synthesis configuration register encoder 1
read only register (VENC_SWREG296) . . . . . . . . . . . . . . . . . . . . . . 2203
45.7.145 VENC MBRC control register (VENC_SWREG297) . . . . . . . . . . . . . 2203
45.7.146 VENC segment 4: intra 4x4 previous mode favor, intra 16x16
mode favor, penalty value for second reference frame
register (VENC_SWREG298) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2204
45.7.147 VENC segment 4: skip mode penalty, inter MB mode favor
register (VENC_SWREG299) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2204
45.7.148 VENC segment 4: penalty value register (VENC_SWREGx) . . . . . . 2204
45.7.149 VENC segment 5: intra 4x4 previous mode favor, intra 16x16 mode
favor, penalty value for second reference frame
register (VENC_SWREG302) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2205
45.7.150 VENC segment 5: skip mode penalty, inter MB mode favor
register (VENC_SWREG303) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2205
45.7.151 VENC segment 5: penalty value register (VENC_SWREGx) . . . . . . 2205
45.7.152 VENC segment 6: intra 4x4 previous mode favor, intra 16x16 mode
favor, penalty value for second reference frame
register (VENC_SWREG306) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2206
45.7.153 VENC segment 6: skip mode penalty, inter MB mode favor
register (VENC_SWREG307) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2206
45.7.154 VENC segment 6: penalty value register (VENC_SWREGx) . . . . . . 2206
45.7.155 VENC segment 7: intra 4x4 previous mode favor, intra 16x16 mode
favor, penalty value for second reference frame
register (VENC_SWREG310) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2207
45.7.156 VENC segment 7: skip mode penalty, inter MB mode favor
register (VENC_SWREG311) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2207

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45.7.157 VENC segment 7: penalty value register (VENC_SWREGx) . . . . . . 2207

45.7.158 VENC segment 8: intra 4x4 previous mode favor, intra 16x16 mode
favor, penalty value for second reference frame
register (VENC_SWREG314) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2208
45.7.159 VENC segment 8: skip mode penalty, inter MB mode favor
register (VENC_SWREG315) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2208
45.7.160 VENC segment 8: penalty value register (VENC_SWREGx) . . . . . . 2208
45.7.161 VENC segment 9: intra 4x4 previous mode favor, intra 16x16 mode
favor, penalty value for second reference frame
register (VENC_SWREG318) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2209
45.7.162 VENC segment 9: skip mode penalty, inter MB mode favor
register (VENC_SWREG319) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2209
45.7.163 VENC segment 9: penalty value register (VENC_SWREGx) . . . . . . 2209
45.7.164 VENC segment 10: intra 4x4 previous mode favor, intra 16x16 mode
favor, penalty value for second reference frame
register (VENC_SWREG322) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2210
45.7.165 VENC segment 10: skip mode penalty, inter MB mode favor
register (VENC_SWREG323) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2210
45.7.166 VENC segment 10: penalty value register (VENC_SWREGx) . . . . . 2210
45.7.167 VENC segment 11: intra 4x4 previous mode favor, intra 16x16 mode
favor, penalty value for second reference frame
register (VENC_SWREG326) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2211
45.7.168 VENC segment 11: skip mode penalty, inter MB mode favor
register (VENC_SWREG327) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2211
45.7.169 VENC segment 11: penalty value register (VENC_SWREGx) . . . . . 2211
45.7.170 VENC segment 12: intra 4x4 previous mode favor, intra 16x16 mode
favor, penalty value for second reference frame register
(VENC_SWREG330) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2212
45.7.171 VENC segment 12: skip mode penalty, inter MB mode favor
register (VENC_SWREG331) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2212
45.7.172 VENC segment 12: penalty value register (VENC_SWREGx) . . . . . 2212
45.7.173 VENC segment 13: intra 4x4 previous mode favor, intra 16x16 mode
favor, penalty value for second reference frame
register (VENC_SWREG334) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2213
45.7.174 VENC segment 13: skip mode penalty, inter MB mode favor
register (VENC_SWREG335) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2213
45.7.175 VENC segment 13: penalty value register (VENC_SWREGx) . . . . . 2213
45.7.176 VENC segment 14: intra 4x4 previous mode favor, intra 16x16 mode
favor, penalty value for second reference frame
register (VENC_SWREG338) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2214
45.7.177 VENC segment 14: skip mode penalty, inter MB mode favor
register (VENC_SWREG339) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2214
45.7.178 VENC segment 14: penalty value register (VENC_SWREGx) . . . . . 2214

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45.7.179 VENC segment 15: intra 4x4 previous mode favor, intra 16x16 mode
favor, penalty value for second reference frame
register (VENC_SWREG342) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2215
45.7.180 VENC segment 15: skip mode penalty, inter MB mode favor
register (VENC_SWREG343) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2215
45.7.181 VENC segment 15: penalty value register (VENC_SWREGx) . . . . . 2215
45.7.182 VENC segment 16: intra 4x4 previous mode favor, intra 16x16 mode
favor, penalty value for second reference frame
register (VENC_SWREG346) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2216
45.7.183 VENC segment 16: skip mode penalty, inter MB mode
favor register (VENC_SWREG347) . . . . . . . . . . . . . . . . . . . . . . . . . . 2216
45.7.184 VENC segment 16: penalty value register (VENC_SWREGx) . . . . . 2216
45.7.185 VENC segment 17: intra 4x4 previous mode favor, intra 16x16 mode
favor, penalty value for second reference frame register
(VENC_SWREG350) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2217
45.7.186 VENC segment 17: skip mode penalty, inter MB mode
favor register (VENC_SWREG351) . . . . . . . . . . . . . . . . . . . . . . . . . . 2217
45.7.187 VENC segment 17: penalty value register (VENC_SWREGx) . . . . . 2217
45.7.188 VENC segment 18: intra 4x4 previous mode favor, intra 16x16
mode favor, penalty value for second reference frame register
(VENC_SWREG354) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2218
45.7.189 VENC segment 18: skip mode penalty, inter MB mode
favor register (VENC_SWREG355) . . . . . . . . . . . . . . . . . . . . . . . . . . 2218
45.7.190 VENC segment 18: penalty value register (VENC_SWREGx) . . . . . 2218
45.7.191 VENC segment 19: intra 4x4 previous mode favor, intra 16x16
mode favor, penalty value for second reference frame register
(VENC_SWREG358) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2219
45.7.192 VENC segment 19: skip mode penalty, inter MB mode
favor register (VENC_SWREG359) . . . . . . . . . . . . . . . . . . . . . . . . . . 2219
45.7.193 VENC segment 19: penalty value register (VENC_SWREGx) . . . . . 2219
45.7.194 VENC segment 20: intra 4x4 previous mode favor, intra 16x16
mode favor, penalty value for second reference frame register
(VENC_SWREG362) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2220
45.7.195 VENC segment 20: skip mode penalty, inter MB mode
favor register (VENC_SWREG363) . . . . . . . . . . . . . . . . . . . . . . . . . . 2220
45.7.196 VENC segment 20: penalty value register (VENC_SWREGx) . . . . . 2220
45.7.197 VENC segment 21: intra 4x4 previous mode favor, intra 16x16
mode favor, penalty value for second reference frame register
(VENC_SWREG366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2221
45.7.198 VENC segment 21: skip mode penalty, inter MB mode
favor register (VENC_SWREG367) . . . . . . . . . . . . . . . . . . . . . . . . . . 2221
45.7.199 VENC segment 21: penalty value register (VENC_SWREGx) . . . . . 2221

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45.7.200 VENC segment 22: intra 4x4 previous mode favor, intra 16x16
mode favor, penalty value for second reference frame
register (VENC_SWREG370) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2222
45.7.201 VENC segment 22: skip mode penalty, inter MB mode
favor register (VENC_SWREG371) . . . . . . . . . . . . . . . . . . . . . . . . . . 2222
45.7.202 VENC segment 22: penalty value register (VENC_SWREGx) . . . . . 2222
45.7.203 VENC segment 23: intra 4x4 previous mode favor, intra 16x16
mode favor, penalty value for second reference frame
register (VENC_SWREG374) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2223
45.7.204 VENC segment 23: skip mode penalty, inter MB mode
favor register (VENC_SWREG375) . . . . . . . . . . . . . . . . . . . . . . . . . . 2223
45.7.205 VENC segment 23: penalty value register (VENC_SWREGx) . . . . . 2223
45.7.206 VENC segment 24: intra 4x4 previous mode favor, intra 16x16
mode favor, penalty value for second reference frame
register (VENC_SWREG378) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2224
45.7.207 VENC segment 24: skip mode penalty, inter MB mode
favor register (VENC_SWREG379) . . . . . . . . . . . . . . . . . . . . . . . . . . 2224
45.7.208 VENC segment 24: penalty value register (VENC_SWREGx) . . . . . 2224
45.7.209 VENC segment 25: intra 4x4 previous mode favor, intra 16x16
mode favor, penalty value for second reference frame
register (VENC_SWREG382) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2225
45.7.210 VENC segment 25: skip mode penalty, inter MB mode
favor register (VENC_SWREG383) . . . . . . . . . . . . . . . . . . . . . . . . . . 2225
45.7.211 VENC segment 25: penalty value register (VENC_SWREGx) . . . . . 2225
45.7.212 VENC segment 26: intra 4x4 previous mode favor, intra 16x16
mode favor, penalty value for second reference frame
register (VENC_SWREG386) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2226
45.7.213 VENC segment 26: skip mode penalty, inter MB mode
favor register (VENC_SWREG387) . . . . . . . . . . . . . . . . . . . . . . . . . . 2226
45.7.214 VENC segment 26: penalty value register (VENC_SWREGx) . . . . . 2226
45.7.215 VENC segment 27: intra 4x4 previous mode favor, intra 16x16
mode favor, penalty value for second reference frame
register (VENC_SWREG390) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2227
45.7.216 VENC segment 27: skip mode penalty, inter MB mode
favor register (VENC_SWREG391) . . . . . . . . . . . . . . . . . . . . . . . . . . 2227
45.7.217 VENC segment 27: penalty value register (VENC_SWREGx) . . . . . 2227
45.7.218 VENC segment 28: intra 4x4 previous mode favor, intra 16x16
mode favor, penalty value for second reference frame
register (VENC_SWREG394) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2228
45.7.219 VENC segment 28: skip mode penalty, inter MB mode
favor register (VENC_SWREG395) . . . . . . . . . . . . . . . . . . . . . . . . . . 2228
45.7.220 VENC segment 28: penalty value register (VENC_SWREGx) . . . . . 2228

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45.7.221 VENC segment 29: intra 4x4 previous mode favor, intra 16x16
mode favor, penalty value for second reference frame
register (VENC_SWREG398) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2229
45.7.222 VENC segment 29: skip mode penalty, inter MB mode
favor register (VENC_SWREG399) . . . . . . . . . . . . . . . . . . . . . . . . . . 2229
45.7.223 VENC segment 29: penalty value register (VENC_SWREGx) . . . . . 2229
45.7.224 VENC segment 30: intra 4x4 previous mode favor, intra 16x16
mode favor, penalty value for second reference frame
register (VENC_SWREG402) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2230
45.7.225 VENC segment 30: skip mode penalty, inter MB mode
favor register (VENC_SWREG403) . . . . . . . . . . . . . . . . . . . . . . . . . . 2230
45.7.226 VENC segment 30: penalty value register (VENC_SWREGx) . . . . . 2230
45.7.227 VENC segment 31: intra 4x4 previous mode favor, intra 16x16 mode
favor, penalty value for second reference frame
register (VENC_SWREG406) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2231
45.7.228 VENC segment 31: skip mode penalty, inter MB mode favor
register (VENC_SWREG407) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2231
45.7.229 VENC segment 31: penalty value register (VENC_SWREGx) . . . . . 2231
45.7.230 VENC MBRC control, QP, offset, enable
register (VENC_SWREG410) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2232
45.7.231 VENC gain of MB QP delta. 8.8 format register
(VENC_SWREG411) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2232
45.7.232 VENC average of MB complexity register (VENC_SWREG412) . . . 2232
45.7.233 VENC reference compression control
register (VENC_SWREG413) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2233
45.7.234 VENC base address for reference luma register
(VENC_SWREG414) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2233
45.7.235 VENC base address for reference chroma register
(VENC_SWREG415) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2233
45.7.236 VENC base address for reconstructed luma register
(VENC_SWREG416) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2234
45.7.237 VENC base address for reconstructed chroma register
(VENC_SWREG417) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2234
45.7.238 VENC base address for second reference luma register
(VENC_SWREG418) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2234
45.7.239 VENC base address for second reference chroma register
(VENC_SWREG419) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2235
45.7.240 VENC limit of chroma RFC buffer register
(VENC_SWREG420) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2235
45.7.241 VENC reorder control register (VENC_SWREG421) . . . . . . . . . . . . 2235
45.7.242 VENC AXI read ID register (VENC_SWREG422) . . . . . . . . . . . . . . . 2236
45.7.243 VENC base address MSB for reference luma compression table
register (VENC_SWREG423) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2236

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45.7.244 VENC base address MSB for reference chroma compression table
register (VENC_SWREG424) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2236
45.7.245 VENC base address MSB for reconstructed luma compression
table register (VENC_SWREG425) . . . . . . . . . . . . . . . . . . . . . . . . . . 2237
45.7.246 VENC base address for reconstructed chroma compression
table register (VENC_SWREG426) . . . . . . . . . . . . . . . . . . . . . . . . . . 2237
45.7.247 VENC base address MSB for second reference luma compression
table register (VENC_SWREG427) . . . . . . . . . . . . . . . . . . . . . . . . . . 2237
45.7.248 VENC base address MSB for second reference chroma compression
table register (VENC_SWREG428) . . . . . . . . . . . . . . . . . . . . . . . . . . 2238
45.7.249 VENC high 32 bits of base address for output stream
data register (VENC_SWREG429) . . . . . . . . . . . . . . . . . . . . . . . . . . 2238
45.7.250 VENC high 32 bits of base address for output control
data register (VENC_SWREG430) . . . . . . . . . . . . . . . . . . . . . . . . . . 2238
45.7.251 VENC high 32 bits of base address for reference luma
register (VENC_SWREG431) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2239
45.7.252 VENC high 32 bits of base address for reference chroma
register (VENC_SWREG432) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2239
45.7.253 VENC high 32 bits of base address for reconstructed luma
register (VENC_SWREG433) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2239
45.7.254 VENC high 32 bits of base address for reconstructed chroma
register (VENC_SWREG434) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2240
45.7.255 VENC high 32 bits of base address for input picture luma
register (VENC_SWREG435) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2240
45.7.256 VENC high 32 bits of base address for input picture cb register
(VENC_SWREG436) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2240
45.7.257 VENC high 32 bits of base address for input picture cr
register (VENC_SWREG437) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2241
45.7.258 VENC high 32 bits of base address for second reference
luma register (VENC_SWREG438) . . . . . . . . . . . . . . . . . . . . . . . . . . 2241
45.7.259 VENC high 32 bits of base address for second reference
chroma register (VENC_SWREG439) . . . . . . . . . . . . . . . . . . . . . . . . 2241
45.7.260 VENC high 32 bits of H264 secondary ref pic base
register (VENC_SWREGx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2242
45.7.261 VENC high 32 bits of base address for next pic luminance
register (VENC_SWREG442) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2242
45.7.262 VENC high 32 bits of base address for cabac context tables H264
register (VENC_SWREG443) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2242
45.7.263 VENC high 32 bits of base address for MV output writing
register (VENC_SWREG444) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2243
45.7.264 VENC high 32 bits of base address for output of down-scaled
encoder image in YUYV [Link] format register (VENC_SWREG449) 2243
45.7.265 VENC low-latency control register (VENC_SWREG497) . . . . . . . . . 2243

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45.7.266 VENC encoder line buffer offset

register (VENC_SWREG498) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2244
45.7.267 VENC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2244

46 JPEG codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2258

46.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2258
46.2 JPEG codec main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2258
46.3 JPEG codec block functional description . . . . . . . . . . . . . . . . . . . . . . . 2259
46.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2259
46.3.2 JPEG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2259
46.3.3 JPEG decoding procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2260
46.3.4 JPEG encoding procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2262
46.4 JPEG codec interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2265
46.5 JPEG codec registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2265
46.5.1 JPEG codec control register (JPEG_CONFR0) . . . . . . . . . . . . . . . . 2265
46.5.2 JPEG codec configuration register 1 (JPEG_CONFR1) . . . . . . . . . . 2266
46.5.3 JPEG codec configuration register 2 (JPEG_CONFR2) . . . . . . . . . . 2267
46.5.4 JPEG codec configuration register 3 (JPEG_CONFR3) . . . . . . . . . . 2267
46.5.5 JPEG codec configuration register x (JPEG_CONFRx) . . . . . . . . . . 2268
46.5.6 JPEG control register (JPEG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2269
46.5.7 JPEG status register (JPEG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2270
46.5.8 JPEG clear flag register (JPEG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . 2271
46.5.9 JPEG data input register (JPEG_DIR) . . . . . . . . . . . . . . . . . . . . . . . . 2272
46.5.10 JPEG data output register (JPEG_DOR) . . . . . . . . . . . . . . . . . . . . . . 2272
46.5.11 JPEG quantization memory x (JPEG_QMEMx_y) . . . . . . . . . . . . . . . 2273
46.5.12 JPEG Huffman min (JPEG_HUFFMINx_y) . . . . . . . . . . . . . . . . . . . . 2273
46.5.13 JPEG Huffman min x (JPEG_HUFFMINx_y) . . . . . . . . . . . . . . . . . . . 2274
46.5.14 JPEG Huffman base (JPEG_HUFFBASEx) . . . . . . . . . . . . . . . . . . . 2274
46.5.15 JPEG Huffman symbol (JPEG_HUFFSYMBx) . . . . . . . . . . . . . . . . . 2275
46.5.16 JPEG DHT memory (JPEG_DHTMEMx) . . . . . . . . . . . . . . . . . . . . . . 2276
46.5.17 JPEG Huffman encoder ACx (JPEG_HUFFENC_ACx_y) . . . . . . . . . 2276
46.5.18 JPEG Huffman encoder DCx (JPEG_HUFFENC_DCx_y) . . . . . . . . 2277
46.5.19 JPEG codec register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2278

47 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . 2280

47.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2280
47.2 RNG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2280

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47.3 RNG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2281

47.3.1 RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2281
47.3.2 RNG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2281
47.3.3 Random number generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2281
47.3.4 RNG initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2284
47.3.5 RNG operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2285
47.3.6 RNG clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2287
47.3.7 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2287
47.3.8 RNG low-power use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2288
47.4 RNG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2289
47.5 RNG processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2289
47.6 RNG entropy source validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2290
47.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2290
47.6.2 Validation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2290
47.7 RNG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2291
47.7.1 RNG control register (RNG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2291
47.7.2 RNG status register (RNG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2293
47.7.3 RNG data register (RNG_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2294
47.7.4 RNG noise source control register (RNG_NSCR) . . . . . . . . . . . . . . . 2295
47.7.5 RNG health test control register (RNG_HTCR) . . . . . . . . . . . . . . . . . 2296
47.7.6 RNG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2296

48 Secure AES coprocessor (SAES) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2297

48.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2297
48.2 SAES main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2297
48.3 SAES implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2298
48.4 SAES functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2298
48.4.1 SAES block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2298
48.4.2 SAES internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2299
48.4.3 SAES reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2300
48.4.4 SAES symmetric cipher implementation . . . . . . . . . . . . . . . . . . . . . . 2300
48.4.5 SAES encryption or decryption typical usage . . . . . . . . . . . . . . . . . . 2301
48.4.6 SAES authenticated encryption, decryption, and cipher-based
message authentication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2303
48.4.7 SAES ciphertext stealing and data padding . . . . . . . . . . . . . . . . . . . 2304
48.4.8 SAES suspend and resume operations . . . . . . . . . . . . . . . . . . . . . . . 2304

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48.4.9 SAES basic chaining modes (ECB, CBC) . . . . . . . . . . . . . . . . . . . . . 2305

48.4.10 SAES counter (CTR) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2309
48.4.11 SAES Galois/counter mode (GCM) . . . . . . . . . . . . . . . . . . . . . . . . . . 2311
48.4.12 SAES Galois message authentication code (GMAC) . . . . . . . . . . . . 2315
48.4.13 SAES counter with CBC-MAC (CCM) . . . . . . . . . . . . . . . . . . . . . . . . 2317
48.4.14 SAES operation with wrapped keys . . . . . . . . . . . . . . . . . . . . . . . . . . 2322
48.4.15 SAES operation with shared keys . . . . . . . . . . . . . . . . . . . . . . . . . . . 2326
48.4.16 SAES data registers and data swapping . . . . . . . . . . . . . . . . . . . . . . 2327
48.4.17 SAES key registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2330
48.4.18 SAES initialization vector registers . . . . . . . . . . . . . . . . . . . . . . . . . . 2331
48.4.19 SAES error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2332
48.5 SAES interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2334
48.6 SAES DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2334
48.7 SAES processing latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2335
48.8 SAES registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2337
48.8.1 SAES control register (SAES_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 2337
48.8.2 SAES status register (SAES_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2340
48.8.3 SAES data input register (SAES_DINR) . . . . . . . . . . . . . . . . . . . . . . 2341
48.8.4 SAES data output register (SAES_DOUTR) . . . . . . . . . . . . . . . . . . . 2342
48.8.5 SAES key register 0 (SAES_KEYR0) . . . . . . . . . . . . . . . . . . . . . . . . 2342
48.8.6 SAES key register 1 (SAES_KEYR1) . . . . . . . . . . . . . . . . . . . . . . . . 2343
48.8.7 SAES key register 2 (SAES_KEYR2) . . . . . . . . . . . . . . . . . . . . . . . . 2343
48.8.8 SAES key register 3 (SAES_KEYR3) . . . . . . . . . . . . . . . . . . . . . . . . 2343
48.8.9 SAES initialization vector register 0 (SAES_IVR0) . . . . . . . . . . . . . . 2344
48.8.10 SAES initialization vector register 1 (SAES_IVR1) . . . . . . . . . . . . . . 2344
48.8.11 SAES initialization vector register 2 (SAES_IVR2) . . . . . . . . . . . . . . 2344
48.8.12 SAES initialization vector register 3 (SAES_IVR3) . . . . . . . . . . . . . . 2345
48.8.13 SAES key register 4 (SAES_KEYR4) . . . . . . . . . . . . . . . . . . . . . . . . 2345
48.8.14 SAES key register 5 (SAES_KEYR5) . . . . . . . . . . . . . . . . . . . . . . . . 2345
48.8.15 SAES key register 6 (SAES_KEYR6) . . . . . . . . . . . . . . . . . . . . . . . . 2346
48.8.16 SAES key register 7 (SAES_KEYR7) . . . . . . . . . . . . . . . . . . . . . . . . 2346
48.8.17 SAES suspend registers (SAES_SUSPRx) . . . . . . . . . . . . . . . . . . . . 2346
48.8.18 SAES interrupt enable register (SAES_IER) . . . . . . . . . . . . . . . . . . . 2347
48.8.19 SAES interrupt status register (SAES_ISR) . . . . . . . . . . . . . . . . . . . 2348
48.8.20 SAES interrupt clear register (SAES_ICR) . . . . . . . . . . . . . . . . . . . . 2349
48.8.21 SAES register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2350

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49 Cryptographic processor (CRYP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2352

49.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2352
49.2 CRYP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2352
49.3 CRYP implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2353
49.4 CRYP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2354
49.4.1 CRYP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2354
49.4.2 CRYP internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2355
49.4.3 CRYP reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2355
49.4.4 CRYP symmetric cipher implementation . . . . . . . . . . . . . . . . . . . . . . 2355
49.4.5 CRYP encryption/ decryption typical usage . . . . . . . . . . . . . . . . . . . . 2356
49.4.6 CRYP authenticated encryption, decryption, and cipher-based
message authentication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2359
49.4.7 CRYP ciphertext stealing and data padding . . . . . . . . . . . . . . . . . . . 2359
49.4.8 CRYP suspend and resume operations . . . . . . . . . . . . . . . . . . . . . . . 2360
49.4.9 CRYP basic chaining modes (ECB, CBC) . . . . . . . . . . . . . . . . . . . . . 2360
49.4.10 CRYP counter mode (CTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2365
49.4.11 CRYP AES Galois/counter mode (GCM) . . . . . . . . . . . . . . . . . . . . . . 2367
49.4.12 CRYP AES Galois message authentication code (GMAC) . . . . . . . . 2373
49.4.13 CRYP AES Counter with CBC-MAC (CCM) . . . . . . . . . . . . . . . . . . . 2374
49.4.14 AES key sharing with secure AES co-processor . . . . . . . . . . . . . . . . 2379
49.4.15 CRYP data registers and data swapping . . . . . . . . . . . . . . . . . . . . . . 2380
49.4.16 CRYP key registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2383
49.4.17 CRYP initialization vector registers . . . . . . . . . . . . . . . . . . . . . . . . . . 2383
49.4.18 CRYP error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2384
49.5 CRYP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2384
49.6 CRYP DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2385
49.7 CRYP processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2386
49.8 CRYP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2387
49.8.1 CRYP control register (CRYP_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 2387
49.8.2 CRYP status register (CRYP_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2389
49.8.3 CRYP data input register (CRYP_DINR) . . . . . . . . . . . . . . . . . . . . . . 2391
49.8.4 CRYP data output register (CRYP_DOUTR) . . . . . . . . . . . . . . . . . . . 2391
49.8.5 CRYP DMA control register (CRYP_DMACR) . . . . . . . . . . . . . . . . . . 2392
49.8.6 CRYP interrupt mask set/clear register (CRYP_IMSCR) . . . . . . . . . . 2392
49.8.7 CRYP raw interrupt status register (CRYP_RISR) . . . . . . . . . . . . . . 2393
49.8.8 CRYP masked interrupt status register (CRYP_MISR) . . . . . . . . . . . 2393

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49.8.9 CRYP key register 0L (CRYP_K0LR) . . . . . . . . . . . . . . . . . . . . . . . . 2394

49.8.10 CRYP key register 0R (CRYP_K0RR) . . . . . . . . . . . . . . . . . . . . . . . . 2395
49.8.11 CRYP key register 1L (CRYP_K1LR) . . . . . . . . . . . . . . . . . . . . . . . . 2395
49.8.12 CRYP key register 1R (CRYP_K1RR) . . . . . . . . . . . . . . . . . . . . . . . . 2395
49.8.13 CRYP key register 2L (CRYP_K2LR) . . . . . . . . . . . . . . . . . . . . . . . . 2396
49.8.14 CRYP key register 2R (CRYP_K2RR) . . . . . . . . . . . . . . . . . . . . . . . . 2396
49.8.15 CRYP key register 3L (CRYP_K3LR) . . . . . . . . . . . . . . . . . . . . . . . . 2397
49.8.16 CRYP key register 3R (CRYP_K3RR) . . . . . . . . . . . . . . . . . . . . . . . . 2397
49.8.17 CRYP initialization vector register 0L (CRYP_IV0LR) . . . . . . . . . . . . 2397
49.8.18 CRYP initialization vector register 0R (CRYP_IV0RR) . . . . . . . . . . . 2398
49.8.19 CRYP initialization vector register 1L (CRYP_IV1LR) . . . . . . . . . . . . 2398
49.8.20 CRYP initialization vector register 1R (CRYP_IV1RR) . . . . . . . . . . . 2399
49.8.21 CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) 2399
49.8.22 CRYP context swap GCM registers (CRYP_CSGCMxR) . . . . . . . . . 2400
49.8.23 CRYP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2400

50 Hash processor (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2402

50.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2402
50.2 HASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2402
50.3 HASH implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2403
50.4 HASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2403
50.4.1 HASH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2403
50.4.2 HASH internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2403
50.4.3 About secure hash algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2404
50.4.4 Message data feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2404
50.4.5 Message digest computing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2405
50.4.6 Message padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2407
50.4.7 HMAC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2408
50.4.8 HASH suspend/resume operations . . . . . . . . . . . . . . . . . . . . . . . . . . 2410
50.4.9 HASH DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2412
50.4.10 HASH error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2413
50.4.11 HASH processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2413
50.5 HASH interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2414
50.6 HASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2414
50.6.1 HASH control register (HASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 2414
50.6.2 HASH data input register (HASH_DIN) . . . . . . . . . . . . . . . . . . . . . . . 2416

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50.6.3 HASH start register (HASH_STR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2417

50.6.4 HASH digest registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2418
50.6.5 HASH interrupt enable register (HASH_IMR) . . . . . . . . . . . . . . . . . . 2420
50.6.6 HASH status register (HASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2420
50.6.7 HASH context swap registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2421
50.6.8 HASH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2422

51 Memory cipher engine (MCE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2424

51.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2424
51.2 MCE main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2424
51.3 MCE implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2425
51.4 MCE functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2425
51.4.1 MCE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2425
51.4.2 MCE internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2425
51.4.3 MCE programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2426
51.4.4 MCE reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2427
51.4.5 MCE block cipher encryption mode . . . . . . . . . . . . . . . . . . . . . . . . . . 2427
51.4.6 MCE stream cipher encryption mode . . . . . . . . . . . . . . . . . . . . . . . . 2429
51.4.7 MCE AXI traffic management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2430
51.4.8 MCE encryption disable options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2430
51.4.9 MCE error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2431
51.5 MCE interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2431
51.6 MCE registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2432
51.6.1 MCE configuration register (MCE_CR) . . . . . . . . . . . . . . . . . . . . . . . 2432
51.6.2 MCE status register (MCE_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2433
51.6.3 MCE illegal access status register (MCE_IASR) . . . . . . . . . . . . . . . . 2434
51.6.4 MCE illegal access clear register (MCE_IACR) . . . . . . . . . . . . . . . . . 2434
51.6.5 MCE illegal access interrupt enable register (MCE_IAIER) . . . . . . . . 2434
51.6.6 MCE illegal address register (MCE_IADDR) . . . . . . . . . . . . . . . . . . . 2435
51.6.7 MCE region x configuration register (MCE_REGCRx) . . . . . . . . . . . 2435
51.6.8 MCE start address for region x register
(MCE_SADDRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2437
51.6.9 MCE end address for region x register
(MCE_EADDRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2437
51.6.10 .MCE master key x (MCE_MKEYRx) . . . . . . . . . . . . . . . . . . . . . . . . 2438
51.6.11 MCE fast master key x (MCE_FMKEYRx) . . . . . . . . . . . . . . . . . . . . 2438
51.6.12 MCE cipher context z configuration register (MCE_CCzCFGR) . . . . 2439

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51.6.13 MCE cipher context z nonce register 0 (MCE_CCzNR0) . . . . . . . . . 2440

51.6.14 MCE cipher context z nonce register 1 (MCE_CCzNR1) . . . . . . . . . 2441
51.6.15 MCE cipher context z key register 0 (MCE_CCzKEYR0) . . . . . . . . . 2441
51.6.16 MCE cipher context z key register 1 (MCE_CCzKEYR1) . . . . . . . . . 2442
51.6.17 MCE cipher context z key register 2 (MCE_CCzKEYR2) . . . . . . . . . 2442
51.6.18 MCE cipher context z key register 3 (MCE_CCzKEYR3) . . . . . . . . . 2442
51.6.19 MCE register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2443

52 Public key accelerator (PKA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2445

52.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2445
52.2 PKA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2445
52.3 PKA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2446
52.3.1 PKA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2446
52.3.2 PKA internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2446
52.3.3 PKA reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2446
52.3.4 PKA public key acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2447
52.3.5 Typical applications for PKA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2449
52.3.6 PKA procedure to perform an operation . . . . . . . . . . . . . . . . . . . . . . 2451
52.3.7 PKA error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2452
52.4 PKA operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2453
52.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2453
52.4.2 Montgomery parameter computation . . . . . . . . . . . . . . . . . . . . . . . . . 2454
52.4.3 Modular addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2454
52.4.4 Modular subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2455
52.4.5 Modular and Montgomery multiplication . . . . . . . . . . . . . . . . . . . . . . 2455
52.4.6 Modular exponentiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2456
52.4.7 Modular inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2458
52.4.8 Modular reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2458
52.4.9 Arithmetic addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2459
52.4.10 Arithmetic subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2459
52.4.11 Arithmetic multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2460
52.4.12 Arithmetic comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2460
52.4.13 RSA CRT exponentiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2460
52.4.14 Point on elliptic curve Fp check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2461
52.4.15 ECC Fp scalar multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2462
52.4.16 ECDSA sign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2463
52.4.17 ECDSA verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2465

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52.4.18 ECC complete addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2466

52.4.19 ECC double base ladder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2466
52.4.20 ECC projective to affine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2467
52.5 Example of configurations and processing times . . . . . . . . . . . . . . . . . 2468
52.5.1 Supported elliptic curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2468
52.5.2 Computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2470
52.6 PKA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2472
52.7 PKA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2473
52.7.1 PKA control register (PKA_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2473
52.7.2 PKA status register (PKA_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2475
52.7.3 PKA clear flag register (PKA_CLRFR) . . . . . . . . . . . . . . . . . . . . . . . . 2476
52.7.4 PKA RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2476
52.7.5 PKA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2477

53 Advanced-control timers (TIM1/TIM8) . . . . . . . . . . . . . . . . . . . . . . . . 2478

53.1 TIM1/TIM8 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2478
53.2 TIM1/TIM8 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2478
53.3 TIM1/TIM8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2479
53.3.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2479
53.3.2 TIM1/TIM8 pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . 2480
53.3.3 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2484
53.3.4 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2486
53.3.5 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2498
53.3.6 External trigger input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2499
53.3.7 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2500
53.3.8 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2504
53.3.9 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2506
53.3.10 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2507
53.3.11 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2508
53.3.12 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2509
53.3.13 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2510
53.3.14 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2518
53.3.15 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2519
53.3.16 Combined 3-phase PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2520
53.3.17 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . 2521
53.3.18 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2524

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53.3.19 Bidirectional break inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2530

53.3.20 Clearing the tim_ocxref signal on an external event . . . . . . . . . . . . . 2531
53.3.21 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2532
53.3.22 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2533
53.3.23 Retriggerable One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2535
53.3.24 Pulse on compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2536
53.3.25 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2538
53.3.26 Direction bit output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2555
53.3.27 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2556
53.3.28 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2556
53.3.29 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2556
53.3.30 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2558
53.3.31 ADC triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2563
53.3.32 ADC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2563
53.3.33 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2564
53.3.34 TIM1/TIM8 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2565
53.3.35 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2565
53.4 TIM1/TIM8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2566
53.5 TIM1/TIM8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2566
53.6 TIM1/TIM8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2567
53.6.1 TIMx control register 1 (TIMx_CR1)(x = 1, 8) . . . . . . . . . . . . . . . . . . 2567
53.6.2 TIMx control register 2 (TIMx_CR2)(x = 1, 8) . . . . . . . . . . . . . . . . . . 2568
53.6.3 TIMx slave mode control register (TIMx_SMCR)(x = 1, 8) . . . . . . . . 2572
53.6.4 TIMx DMA/interrupt enable register (TIMx_DIER)(x = 1, 8) . . . . . . . . 2576
53.6.5 TIMx status register (TIMx_SR)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . 2577
53.6.6 TIMx event generation register (TIMx_EGR)(x = 1, 8) . . . . . . . . . . . . 2580
53.6.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)
(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2581
53.6.8 TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2583
53.6.9 TIMx capture/compare mode register 2 (TIMx_CCMR2)
(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2586
53.6.10 TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2587
53.6.11 TIMx capture/compare enable register (TIMx_CCER)(x = 1, 8) . . . . 2590
53.6.12 TIMx counter (TIMx_CNT)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . 2594
53.6.13 TIMx prescaler (TIMx_PSC)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . 2594
53.6.14 TIMx autoreload register (TIMx_ARR)(x = 1, 8) . . . . . . . . . . . . . . . . . 2595

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53.6.15 TIMx repetition counter register (TIMx_RCR)(x = 1, 8) . . . . . . . . . . . 2595

53.6.16 TIMx capture/compare register 1 (TIMx_CCR1)(x = 1, 8) . . . . . . . . . 2596
53.6.17 TIMx capture/compare register 2 (TIMx_CCR2)(x = 1, 8) . . . . . . . . . 2596
53.6.18 TIMx capture/compare register 3 (TIMx_CCR3)(x = 1, 8) . . . . . . . . . 2597
53.6.19 TIMx capture/compare register 4 (TIMx_CCR4)(x = 1, 8) . . . . . . . . . 2598
53.6.20 TIMx break and dead-time register (TIMx_BDTR)(x = 1, 8) . . . . . . . 2599
53.6.21 TIMx capture/compare register 5 (TIMx_CCR5)(x = 1, 8) . . . . . . . . . 2603
53.6.22 TIMx capture/compare register 6 (TIMx_CCR6)(x = 1, 8) . . . . . . . . . 2604
53.6.23 TIMx capture/compare mode register 3 (TIMx_CCMR3)
(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2605
53.6.24 TIMx timer deadtime register 2 (TIMx_DTR2)(x = 1, 8) . . . . . . . . . . . 2606
53.6.25 TIMx timer encoder control register (TIMx_ECR)(x = 1, 8) . . . . . . . . 2607
53.6.26 TIMx timer input selection register (TIMx_TISEL)(x = 1, 8) . . . . . . . . 2608
53.6.27 TIMx alternate function option register 1 (TIMx_AF1)(x = 1, 8) . . . . . 2609
53.6.28 TIMx alternate function register 2 (TIMx_AF2)(x = 1, 8) . . . . . . . . . . 2612
53.6.29 TIMx DMA control register (TIMx_DCR)(x = 1, 8) . . . . . . . . . . . . . . . 2614
53.6.30 TIMx DMA address for full transfer (TIMx_DMAR)(x = 1, 8) . . . . . . . 2616
53.6.31 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2616

54 General-purpose timers (TIM2/TIM3/TIM4/TIM5) . . . . . . . . . . . . . . . . 2619

54.1 TIM2/TIM3/TIM4/TIM5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 2619
54.2 TIM2/TIM3/TIM4/TIM5 main features . . . . . . . . . . . . . . . . . . . . . . . . . . 2619
54.3 TIM2/TIM3/TIM4/TIM5 implementation . . . . . . . . . . . . . . . . . . . . . . . . 2620
54.4 TIM2/TIM3/TIM4/TIM5 functional description . . . . . . . . . . . . . . . . . . . . 2621
54.4.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2621
54.4.2 TIM2/TIM3/TIM4/TIM5 pins and internal signals . . . . . . . . . . . . . . . . 2622
54.4.3 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2625
54.4.4 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2627
54.4.5 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2639
54.4.6 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2643
54.4.7 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2645
54.4.8 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2646
54.4.9 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2647
54.4.10 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2647
54.4.11 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2649
54.4.12 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2657
54.4.13 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2658

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54.4.14 Clearing the tim_ocxref signal on an external event . . . . . . . . . . . . . 2659

54.4.15 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2661
54.4.16 Retriggerable one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2662
54.4.17 Pulse on compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2663
54.4.18 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2665
54.4.19 Direction bit output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2683
54.4.20 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2684
54.4.21 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2684
54.4.22 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . 2684
54.4.23 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2688
54.4.24 ADC triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2693
54.4.25 ADC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2695
54.4.26 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2695
54.4.27 TIM2/TIM3/TIM4/TIM5 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . 2696
54.4.28 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2697
54.4.29 TIM2/TIM3/TIM4/TIM5 low-power modes . . . . . . . . . . . . . . . . . . . . . 2697
54.4.30 TIM2/TIM3/TIM4/TIM5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2698
54.5 TIM2/TIM3/TIM4/TIM5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2699
54.5.1 TIMx control register 1 (TIMx_CR1)(x = 2 to 5) . . . . . . . . . . . . . . . . . 2699
54.5.2 TIMx control register 2 (TIMx_CR2)(x = 2 to 5) . . . . . . . . . . . . . . . . . 2700
54.5.3 TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5) . . . . . . . 2702
54.5.4 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5) . . . . . . 2706
54.5.5 TIMx status register (TIMx_SR)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . 2707
54.5.6 TIMx event generation register (TIMx_EGR)(x = 2 to 5) . . . . . . . . . . 2709
54.5.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5) . 2710
54.5.8 TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2712
54.5.9 TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 5) . 2714
54.5.10 TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2715
54.5.11 TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 5) . . . 2718
54.5.12 TIMx counter (TIMx_CNT)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . 2720
54.5.13 TIMx prescaler (TIMx_PSC)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . 2720
54.5.14 TIMx autoreload register (TIMx_ARR)(x = 2 to 5) . . . . . . . . . . . . . . . 2721
54.5.15 TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 5) . . . . . . . 2721
54.5.16 TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 5) . . . . . . . 2722
54.5.17 TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 5) . . . . . . . 2723

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54.5.18 TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 5) . . . . . . . 2724

54.5.19 TIMx timer encoder control register (TIMx_ECR)(x = 2 to 5) . . . . . . . 2725
54.5.20 TIMx timer input selection register (TIMx_TISEL)(x = 2 to 5) . . . . . . 2726
54.5.21 TIMx alternate function register 1 (TIMx_AF1)(x = 2 to 5) . . . . . . . . . 2727
54.5.22 TIMx alternate function register 2 (TIMx_AF2)(x = 2 to 5) . . . . . . . . . 2728
54.5.23 TIMx DMA control register (TIMx_DCR)(x = 2 to 5) . . . . . . . . . . . . . . 2729
54.5.24 TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5) . . . . . . 2730
54.5.25 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2731

55 Basic timers (TIM6/TIM7/TIM18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2734

55.1 TIM6/TIM7/TIM18 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2734
55.2 TIM6/TIM7/TIM18 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2734
55.3 TIM6/TIM7/TIM18 functional description . . . . . . . . . . . . . . . . . . . . . . . 2734
55.3.1 TIM6/TIM7/TIM18 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2734
55.3.2 TIM6/TIM7/TIM18 internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 2735
55.3.3 TIM6/TIM7/TIM18 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2735
55.3.4 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2736
55.3.5 Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2738
55.3.6 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2744
55.3.7 ADC triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2745
55.3.8 ADC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2745
55.3.9 TIM6/TIM7/TIM18 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2746
55.3.10 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2746
55.3.11 TIM6/TIM7/TIM18 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . 2746
55.3.12 TIM6/TIM7/TIM18 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2746
55.4 TIM6/TIM7/TIM18 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2747
55.4.1 TIMx control register 1 (TIMx_CR1)(x = 6, 7, 18) . . . . . . . . . . . . . . . 2747
55.4.2 TIMx control register 2 (TIMx_CR2)(x = 6, 7, 18) . . . . . . . . . . . . . . . 2749
55.4.3 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6, 7, 18) . . . . 2749
55.4.4 TIMx status register (TIMx_SR)(x = 6, 7, 18) . . . . . . . . . . . . . . . . . . . 2751
55.4.5 TIMx event generation register (TIMx_EGR)(x = 6, 7, 18) . . . . . . . . . 2751
55.4.6 TIMx counter (TIMx_CNT)(x = 6, 7, 18) . . . . . . . . . . . . . . . . . . . . . . . 2751
55.4.7 TIMx prescaler (TIMx_PSC)(x = 6, 7, 18) . . . . . . . . . . . . . . . . . . . . . 2752
55.4.8 TIMx autoreload register (TIMx_ARR)(x = 6, 7, 18) . . . . . . . . . . . . . . 2752
55.4.9 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2753

56 General-purpose timers (TIM9/TIM10/TIM11/TIM12/TIM13/TIM14) . 2754

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56.1 TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 introduction . . . . . . . . . . . . . 2754

56.2 TIM9/TIM12 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2754
56.3 TIM10/TIM11/TIM13/TIM14 main features . . . . . . . . . . . . . . . . . . . . . . 2755
56.4 TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 functional description . . . . . . 2756
56.4.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2756
56.4.2 TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 pins and internal signals . . 2757
56.4.3 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2759
56.4.4 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2761
56.4.5 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2764
56.4.6 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2766
56.4.7 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2768
56.4.8 PWM input mode (TIM9/TIM12 only) . . . . . . . . . . . . . . . . . . . . . . . . . 2769
56.4.9 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2770
56.4.10 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2771
56.4.11 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2772
56.4.12 Combined PWM mode (TIM9/TIM12 only) . . . . . . . . . . . . . . . . . . . . 2777
56.4.13 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2778
56.4.14 Retriggerable one pulse mode (TIM9/TIM12 only) . . . . . . . . . . . . . . 2780
56.4.15 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2781
56.4.16 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2781
56.4.17 TIM9/TIM12 external trigger synchronization . . . . . . . . . . . . . . . . . . 2781
56.4.18 Slave mode – combined reset + trigger mode . . . . . . . . . . . . . . . . . . 2784
56.4.19 Slave mode – combined reset + gated mode . . . . . . . . . . . . . . . . . . 2784
56.4.20 Timer synchronization (TIM9/TIM12 only) . . . . . . . . . . . . . . . . . . . . . 2784
56.4.21 Using timer output as trigger for other timers
(TIM10/TIM11/TIM13/TIM14 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2784
56.4.22 ADC triggers (TIM9/TIM12 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2784
56.4.23 ADC synchronization (TIM9/TIM12 only) . . . . . . . . . . . . . . . . . . . . . . 2785
56.4.24 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2786
56.5 TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 low-power modes . . . . . . . . 2786
56.6 TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 interrupts . . . . . . . . . . . . . . . 2786
56.7 TIM9/TIM12 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2786
56.7.1 TIMx control register 1 (TIMx_CR1)(x = 9, 12) . . . . . . . . . . . . . . . . . 2787
56.7.2 TIM12 control register 2 (TIMx_CR2)(x = 9, 12) . . . . . . . . . . . . . . . . 2788
56.7.3 TIMx slave mode control register (TIMx_SMCR)(x = 9, 12) . . . . . . . 2789
56.7.4 TIMx interrupt enable register (TIMx_DIER)(x = 9, 12) . . . . . . . . . . . 2791
56.7.5 TIMx status register (TIMx_SR)(x = 9, 12) . . . . . . . . . . . . . . . . . . . . . 2792

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56.7.6 TIMx event generation register (TIMx_EGR)(x = 9, 12) . . . . . . . . . . . 2793

56.7.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 9, 12) . 2794
56.7.8 TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 9, 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2795
56.7.9 TIMx capture/compare enable register (TIMx_CCER)(x = 9, 12) . . . 2798
56.7.10 TIMx counter (TIMx_CNT)(x = 9, 12) . . . . . . . . . . . . . . . . . . . . . . . . . 2799
56.7.11 TIMx prescaler (TIMx_PSC)(x = 9, 12) . . . . . . . . . . . . . . . . . . . . . . . 2800
56.7.12 TIMx autoreload register (TIMx_ARR)(x = 9, 12) . . . . . . . . . . . . . . . . 2800
56.7.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 9, 12) . . . . . . . . 2801
56.7.14 TIMx capture/compare register 2 (TIMx_CCR2)(x = 9, 12) . . . . . . . . 2801
56.7.15 TIMx timer input selection register (TIMx_TISEL)(x = 9, 12) . . . . . . . 2802
56.7.16 TIM9/TIM12 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2803
56.8 TIM10/TIM11/TIM13/TIM14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . 2805
56.8.1 TIMx control register 1 (TIMx_CR1)(x = 10, 11, 13, 14) . . . . . . . . . . 2805
56.8.2 TIMx interrupt enable register (TIMx_DIER)(x = 10, 11, 13, 14) . . . . 2806
56.8.3 TIMx status register (TIMx_SR)(x = 10, 11, 13, 14) . . . . . . . . . . . . . . 2806
56.8.4 TIMx event generation register (TIMx_EGR)(x = 10, 11, 13, 14) . . . . 2807
56.8.5 TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 10, 11, 13, 14) . . . . . . . . . . . . . . . . . . . . . . . . . . 2808
56.8.6 TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 10, 11, 13, 14) . . . . . . . . . . . . . . . . . . . . . . . . . . 2809
56.8.7 TIMx capture/compare enable register
(TIMx_CCER)(x = 10, 11, 13, 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2811
56.8.8 TIMx counter (TIMx_CNT)(x = 10, 11, 13, 14) . . . . . . . . . . . . . . . . . . 2812
56.8.9 TIMx prescaler (TIMx_PSC)(x = 10, 11, 13, 14) . . . . . . . . . . . . . . . . 2813
56.8.10 TIMx autoreload register (TIMx_ARR)(x = 10, 11, 13, 14) . . . . . . . . . 2813
56.8.11 TIMx capture/compare register 1 (TIMx_CCR1)(x = 10, 11, 13, 14) . 2814
56.8.12 TIMx timer input selection register (TIMx_TISEL)(x = 10, 11, 13, 14) 2814
56.8.13 TIM10/TIM11/TIM13/TIM14 register map . . . . . . . . . . . . . . . . . . . . . 2815

57 General purpose timers (TIM15/TIM16/TIM17) . . . . . . . . . . . . . . . . . 2817

57.1 TIM15/TIM16/TIM17 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2817
57.2 TIM15 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2817
57.3 TIM16/TIM17 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2818
57.4 TIM15/TIM16/TIM17 functional description . . . . . . . . . . . . . . . . . . . . . 2819
57.4.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2819
57.4.2 TIM15/TIM16/TIM17 pins and internal signals . . . . . . . . . . . . . . . . . . 2820
57.4.3 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2823

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57.4.4 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2825

57.4.5 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2829
57.4.6 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2830
57.4.7 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2832
57.4.8 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2834
57.4.9 PWM input mode (only for TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2836
57.4.10 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2837
57.4.11 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2837
57.4.12 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2839
57.4.13 Combined PWM mode (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . . . 2844
57.4.14 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . 2845
57.4.15 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2848
57.4.16 Bidirectional break input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2852
57.4.17 Clearing the tim_ocxref signal on an external event . . . . . . . . . . . . . 2853
57.4.18 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2854
57.4.19 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2856
57.4.20 Retriggerable one pulse mode (TIM15 only) . . . . . . . . . . . . . . . . . . . 2857
57.4.21 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2858
57.4.22 Timer input XOR function (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . 2858
57.4.23 External trigger synchronization (TIM15 only) . . . . . . . . . . . . . . . . . . 2858
57.4.24 Slave mode – combined reset + trigger mode (TIM15 only) . . . . . . . 2861
57.4.25 Slave mode – combined reset + gated mode (TIM15 only) . . . . . . . . 2861
57.4.26 Timer synchronization (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . . . . 2862
57.4.27 Using timer output as trigger for other timers (TIM16/TIM17 only) . . 2862
57.4.28 ADC triggers (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2862
57.4.29 ADC synchronization (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . . . . 2863
57.4.30 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2863
57.4.31 TIM15/TIM16/TIM17 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . 2864
57.4.32 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2865
57.5 TIM15/TIM16/TIM17 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . 2865
57.6 TIM15/TIM16/TIM17 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2865
57.7 TIM15 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2867
57.7.1 TIM15 control register 1 (TIM15_CR1) . . . . . . . . . . . . . . . . . . . . . . . 2867
57.7.2 TIM15 control register 2 (TIM15_CR2) . . . . . . . . . . . . . . . . . . . . . . . 2868
57.7.3 TIM15 slave mode control register (TIM15_SMCR) . . . . . . . . . . . . . 2871
57.7.4 TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . . . . . . . . . 2873
57.7.5 TIM15 status register (TIM15_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . 2874

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57.7.6 TIM15 event generation register (TIM15_EGR) . . . . . . . . . . . . . . . . 2876

57.7.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . . . . 2877
57.7.8 TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2879
57.7.9 TIM15 capture/compare enable register (TIM15_CCER) . . . . . . . . . 2881
57.7.10 TIM15 counter (TIM15_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2884
57.7.11 TIM15 prescaler (TIM15_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2884
57.7.12 TIM15 autoreload register (TIM15_ARR) . . . . . . . . . . . . . . . . . . . . . 2885
57.7.13 TIM15 repetition counter register (TIM15_RCR) . . . . . . . . . . . . . . . . 2885
57.7.14 TIM15 capture/compare register 1 (TIM15_CCR1) . . . . . . . . . . . . . . 2886
57.7.15 TIM15 capture/compare register 2 (TIM15_CCR2) . . . . . . . . . . . . . . 2887
57.7.16 TIM15 break and dead-time register (TIM15_BDTR) . . . . . . . . . . . . 2887
57.7.17 TIM15 timer deadtime register 2 (TIM15_DTR2) . . . . . . . . . . . . . . . . 2890
57.7.18 TIM15 input selection register (TIM15_TISEL) . . . . . . . . . . . . . . . . . 2891
57.7.19 TIM15 alternate function register 1 (TIM15_AF1) . . . . . . . . . . . . . . . 2892
57.7.20 TIM15 alternate function register 2 (TIM15_AF2) . . . . . . . . . . . . . . . 2894
57.7.21 TIM15 DMA control register (TIM15_DCR) . . . . . . . . . . . . . . . . . . . . 2895
57.7.22 TIM15 DMA address for full transfer (TIM15_DMAR) . . . . . . . . . . . . 2896
57.7.23 TIM15 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2896
57.8 TIM16/TIM17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2899
57.8.1 TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . . . . . . . . . . . . 2899
57.8.2 TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . . . . . . . . . . . . 2900
57.8.3 TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . 2901
57.8.4 TIMx status register (TIMx_SR)(x = 16 to 17) . . . . . . . . . . . . . . . . . . 2902
57.8.5 TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . . . . . 2903
57.8.6 TIMx capture/compare mode register 1 (TIMx_CCMR1)
(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2904
57.8.7 TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2905
57.8.8 TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . 2907
57.8.9 TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . 2910
57.8.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . 2910
57.8.11 TIMx auto-reautoreload register (TIMx_ARR)(x = 16 to 17) . . . . . . . 2911
57.8.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . . . . . 2911
57.8.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . . 2912
57.8.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . 2913
57.8.15 TIMx timer deadtime register 2 (TIMx_DTR2)(x = 16 to 17) . . . . . . . 2916
57.8.16 TIMx input selection register (TIMx_TISEL)(x = 16 to 17) . . . . . . . . . 2917

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57.8.17 TIMx alternate function register 1 (TIMx_AF1)(x = 16 to 17) . . . . . . . 2917

57.8.18 TIMx alternate function register 2 (TIMx_AF2)(x = 16 to 17) . . . . . . . 2920
57.8.19 TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . . . . . . . . . 2920
57.8.20 TIM16/TIM17 DMA address for full transfer
(TIMx_DMAR)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2921
57.8.21 TIM16/TIM17 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2923

58 Low-power timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2925

58.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2925
58.2 LPTIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2925
58.3 LPTIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2926
58.4 LPTIM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2927
58.4.1 LPTIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2927
58.4.2 LPTIM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2928
58.4.3 LPTIM input and trigger mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 2930
58.4.4 LPTIM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2931
58.4.5 Glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2932
58.4.6 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2933
58.4.7 Trigger multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2933
58.4.8 Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2934
58.4.9 Timeout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2936
58.4.10 Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2936
58.4.11 Register update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2937
58.4.12 Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2938
58.4.13 Timer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2938
58.4.14 Timer counter reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2939
58.4.15 Encoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2939
58.4.16 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2941
58.4.17 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2942
58.4.18 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2943
58.4.19 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2945
58.4.20 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2947
58.4.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2948
58.5 LPTIM low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2948
58.6 LPTIM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2948
58.7 LPTIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2949
58.7.1 LPTIMx interrupt and status register (LPTIMx_ISR)(x = 4 to 5) . . . . . 2950

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58.7.2 LPTIMx interrupt and status register [alternate] (LPTIMx_ISR)

(x = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2951
58.7.3 LPTIMx interrupt and status register [alternate] (LPTIMx_ISR)
(x = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2953
58.7.4 LPTIMx interrupt clear register (LPTIMx_ICR)(x = 4 to 5) . . . . . . . . . 2955
58.7.5 LPTIMx interrupt clear register [alternate] (LPTIMx_ICR)
(x = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2956
58.7.6 LPTIMx interrupt clear register [alternate] (LPTIMx_ICR)
(x = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2957
58.7.7 LPTIMx interrupt enable register (LPTIMx_DIER)(x = 4 to 5) . . . . . . 2958
58.7.8 LPTIMx interrupt enable register [alternate] (LPTIMx_DIER)
(x = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2960
58.7.9 LPTIMx interrupt enable register [alternate] (LPTIMx_DIER)
(x = 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2961
58.7.10 LPTIM configuration register (LPTIM_CFGR) . . . . . . . . . . . . . . . . . . 2963
58.7.11 LPTIM control register (LPTIM_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 2966
58.7.12 LPTIM compare register 1 (LPTIM_CCR1) . . . . . . . . . . . . . . . . . . . . 2967
58.7.13 LPTIM autoreload register (LPTIM_ARR) . . . . . . . . . . . . . . . . . . . . . 2968
58.7.14 LPTIM counter register (LPTIM_CNT) . . . . . . . . . . . . . . . . . . . . . . . . 2968
58.7.15 LPTIM configuration register 2 (LPTIM_CFGR2) . . . . . . . . . . . . . . . 2969
58.7.16 LPTIM repetition register (LPTIM_RCR) . . . . . . . . . . . . . . . . . . . . . . 2970
58.7.17 LPTIM capture/compare mode register 1 (LPTIM_CCMR1) . . . . . . . 2970
58.7.18 LPTIM compare register 2 (LPTIM_CCR2) . . . . . . . . . . . . . . . . . . . . 2973
58.7.19 LPTIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2973

59 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2976

59.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2976
59.2 IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2976
59.3 IWDG implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2976
59.4 IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2977
59.4.1 IWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2977
59.4.2 IWDG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2978
59.4.3 Software and hardware watchdog modes . . . . . . . . . . . . . . . . . . . . . 2978
59.4.4 Window option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2979
59.4.5 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2982
59.4.6 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2982
59.5 IWDG low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2983
59.6 IWDG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2983

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59.7 IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2985

59.7.1 IWDG key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2986
59.7.2 IWDG prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . 2986
59.7.3 IWDG reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . 2987
59.7.4 IWDG status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2987
59.7.5 IWDG window register (IWDG_WINR) . . . . . . . . . . . . . . . . . . . . . . . 2989
59.7.6 IWDG early wake-up interrupt register (IWDG_EWCR) . . . . . . . . . . 2989
59.7.7 IWDG interrupt clear register (IWDG_ICR) . . . . . . . . . . . . . . . . . . . . 2990
59.7.8 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2991

60 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . 2992

60.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2992
60.2 WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2992
60.3 WWDG implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2992
60.4 WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2993
60.4.1 WWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2993
60.4.2 WWDG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2993
60.4.3 Enabling the watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2994
60.4.4 Controlling the down-counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2994
60.4.5 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . 2994
60.4.6 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2995
60.5 WWDG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2996
60.6 WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2996
60.6.1 WWDG control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . 2996
60.6.2 WWDG configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . 2997
60.6.3 WWDG status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . 2998
60.6.4 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2998

61 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2999

61.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2999
61.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2999
61.3 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000
61.3.1 RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000
61.3.2 RTC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3002
61.3.3 GPIOs controlled by the RTC and TAMP . . . . . . . . . . . . . . . . . . . . . . 3003
61.3.4 RTC secure protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3006

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61.3.5 RTC privilege protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3007

61.3.6 Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3008
61.3.7 Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3009
61.3.8 Calendar ultra-low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3010
61.3.9 Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3010
61.3.10 Periodic auto-wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3010
61.3.11 RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 3011
61.3.12 Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3014
61.3.13 Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3015
61.3.14 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3015
61.3.15 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3016
61.3.16 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3017
61.3.17 Timestamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3019
61.3.18 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3019
61.3.19 Tamper and alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3020
61.4 RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3020
61.5 RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3021
61.6 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3022
61.6.1 RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3023
61.6.2 RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3024
61.6.3 RTC subsecond register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . 3025
61.6.4 RTC initialization control and status register (RTC_ICSR) . . . . . . . . 3026
61.6.5 RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . 3028
61.6.6 RTC wake-up timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . 3029
61.6.7 RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3029
61.6.8 RTC privilege mode control register (RTC_PRIVCFGR) . . . . . . . . . . 3033
61.6.9 RTC secure configuration register (RTC_SECCFGR) . . . . . . . . . . . . 3035
61.6.10 RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . 3036
61.6.11 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . 3037
61.6.12 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . 3038
61.6.13 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . 3039
61.6.14 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . 3040
61.6.15 RTC timestamp subsecond register (RTC_TSSSR) . . . . . . . . . . . . . 3041
61.6.16 RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . 3041
61.6.17 RTC alarm A subsecond register (RTC_ALRMASSR) . . . . . . . . . . . . 3043
61.6.18 RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . 3044
61.6.19 RTC alarm B subsecond register (RTC_ALRMBSSR) . . . . . . . . . . . 3045

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61.6.20 RTC status register (RTC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3046

61.6.21 RTC nonsecure masked interrupt status register (RTC_MISR) . . . . . 3047
61.6.22 RTC secure masked interrupt status register (RTC_SMISR) . . . . . . 3048
61.6.23 RTC status clear register (RTC_SCR) . . . . . . . . . . . . . . . . . . . . . . . . 3049
61.6.24 RTC alarm A binary mode register (RTC_ALRABINR) . . . . . . . . . . . 3050
61.6.25 RTC alarm B binary mode register (RTC_ALRBBINR) . . . . . . . . . . . 3051
61.6.26 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3052

62 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . 3054

62.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3054
62.2 TAMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3055
62.3 TAMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3056
62.3.1 TAMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3056
62.3.2 TAMP pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3057
62.3.3 GPIOs controlled by the RTC and TAMP . . . . . . . . . . . . . . . . . . . . . . 3059
62.3.4 TAMP register write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3059
62.3.5 TAMP secure protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3059
62.3.6 Backup registers protection zones . . . . . . . . . . . . . . . . . . . . . . . . . . . 3060
62.3.7 TAMP privilege protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 3060
62.3.8 Boot hardware key (BHK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3061
62.3.9 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3061
62.3.10 TAMP backup registers and other device secrets erase . . . . . . . . . . 3062
62.3.11 Tamper detection configuration and initialization . . . . . . . . . . . . . . . . 3063
62.4 TAMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3070
62.5 TAMP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3071
62.6 TAMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3071
62.6.1 TAMP control register 1 (TAMP_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 3071
62.6.2 TAMP control register 2 (TAMP_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 3073
62.6.3 TAMP control register 3 (TAMP_CR3) . . . . . . . . . . . . . . . . . . . . . . . . 3076
62.6.4 TAMP filter control register (TAMP_FLTCR) . . . . . . . . . . . . . . . . . . . 3077
62.6.5 TAMP active tamper control register 1 (TAMP_ATCR1) . . . . . . . . . . 3078
62.6.6 TAMP active tamper seed register (TAMP_ATSEEDR) . . . . . . . . . . . 3080
62.6.7 TAMP active tamper output register (TAMP_ATOR) . . . . . . . . . . . . . 3081
62.6.8 TAMP active tamper control register 2 (TAMP_ATCR2) . . . . . . . . . . 3082
62.6.9 TAMP secure configuration register (TAMP_SECCFGR) . . . . . . . . . 3085
62.6.10 TAMP privilege configuration register (TAMP_PRIVCFGR) . . . . . . . 3086

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62.6.11 TAMP interrupt enable register (TAMP_IER) . . . . . . . . . . . . . . . . . . . 3087

62.6.12 TAMP status register (TAMP_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3089
62.6.13 TAMP nonsecure masked interrupt status register (TAMP_MISR) . . 3091
62.6.14 TAMP secure masked interrupt status register (TAMP_SMISR) . . . . 3093
62.6.15 TAMP status clear register (TAMP_SCR) . . . . . . . . . . . . . . . . . . . . . 3094
62.6.16 TAMP monotonic counter 1 register (TAMP_COUNT1R) . . . . . . . . . 3096
62.6.17 TAMP option register (TAMP_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3096
62.6.18 TAMP resources protection configuration register (TAMP_RPCFGR) 3097
62.6.19 TAMP backup x register (TAMP_BKPxR) . . . . . . . . . . . . . . . . . . . . . 3098
62.6.20 TAMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3099

63 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . 3101

63.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3101
63.2 I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3101
63.3 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3102
63.4 I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3102
63.4.1 I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3103
63.4.2 I2C pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3103
63.4.3 I2C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3104
63.4.4 I2C mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3104
63.4.5 I2C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3105
63.4.6 I2C reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3109
63.4.7 I2C data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3110
63.4.8 I2C target mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3112
63.4.9 I2C controller mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3121
63.4.10 I2C_TIMINGR register configuration examples . . . . . . . . . . . . . . . . . 3132
63.4.11 SMBus specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3134
63.4.12 SMBus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3136
63.4.13 SMBus I2C_TIMEOUTR register configuration examples . . . . . . . . . 3138
63.4.14 SMBus target mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3139
63.4.15 SMBus controller mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3142
63.4.16 Wake-up from Stop mode on address match . . . . . . . . . . . . . . . . . . 3145
63.4.17 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3146
63.5 I2C in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3148
63.6 I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3148
63.7 I2C DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3149

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63.7.1 Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3149

63.7.2 Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3149
63.8 I2C debug modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3150
63.9 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3150
63.9.1 I2C control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3150
63.9.2 I2C control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3153
63.9.3 I2C own address 1 register (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . 3155
63.9.4 I2C own address 2 register (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . 3155
63.9.5 I2C timing register (I2C_TIMINGR) . . . . . . . . . . . . . . . . . . . . . . . . . . 3156
63.9.6 I2C timeout register (I2C_TIMEOUTR) . . . . . . . . . . . . . . . . . . . . . . . 3157
63.9.7 I2C interrupt and status register (I2C_ISR) . . . . . . . . . . . . . . . . . . . . 3158
63.9.8 I2C interrupt clear register (I2C_ICR) . . . . . . . . . . . . . . . . . . . . . . . . 3161
63.9.9 I2C PEC register (I2C_PECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3162
63.9.10 I2C receive data register (I2C_RXDR) . . . . . . . . . . . . . . . . . . . . . . . 3162
63.9.11 I2C transmit data register (I2C_TXDR) . . . . . . . . . . . . . . . . . . . . . . . 3163
63.9.12 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3164

64 Improved inter-integrated circuit (I3C) . . . . . . . . . . . . . . . . . . . . . . . 3165

64.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3165
64.2 I3C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3165
64.3 I3C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3167
64.3.1 I3C instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3167
64.3.2 I3C wake-up from low-power mode(s) . . . . . . . . . . . . . . . . . . . . . . . . 3167
64.3.3 I3C FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3167
64.3.4 I3C triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3167
64.3.5 I3C interrupt(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3167
64.3.6 I3C MIPI® support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3168
64.4 I3C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3169
64.5 I3C pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3169
64.6 I3C reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3170
64.6.1 I3C reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3170
64.6.2 I3C clocks and requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3170
64.7 I3C peripheral state and programming . . . . . . . . . . . . . . . . . . . . . . . . . 3172
64.7.1 I3C peripheral state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3172
64.7.2 I3C controller state and programming sequence . . . . . . . . . . . . . . . . 3172
64.7.3 I3C target state and programming sequence . . . . . . . . . . . . . . . . . . 3177

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64.8 I3C registers and programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3181

64.8.1 I3C register set, as controller/target . . . . . . . . . . . . . . . . . . . . . . . . . . 3181
64.8.2 I3C registers and fields use versus peripheral state, as controller . . 3182
64.8.3 I3C registers and fields usage versus peripheral state, as target . . . 3185
64.9 I3C bus transfers and programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 3187
64.9.1 I3C command set (CCCs), as controller/target . . . . . . . . . . . . . . . . . 3187
64.9.2 I3C broadcast/direct CCC transfer (except ENTDAA, RSTACT),
as controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3191
64.9.3 I3C broadcast ENTDAA CCC transfer, as controller . . . . . . . . . . . . . 3193
64.9.4 I3C broadcast/direct RSTACT CCC transfer, as controller . . . . . . . . 3193
64.9.5 I3C broadcast/direct CCC transfer
(except ENTDAA, DEFTGTS, DEFGRPA), as target . . . . . . . . . . . . 3195
64.9.6 I3C broadcast ENTDAA CCC transfer, as target . . . . . . . . . . . . . . . . 3197
64.9.7 I3C broadcast DEFTGTS CCC transfer, as target . . . . . . . . . . . . . . . 3198
64.9.8 I3C broadcast DEFGRPA CCC transfer, as target . . . . . . . . . . . . . . . 3199
64.9.9 I3C direct GETSTATUS CCC response, as target . . . . . . . . . . . . . . . 3200
64.9.10 I3C private read/write transfer, as controller . . . . . . . . . . . . . . . . . . . 3201
64.9.11 I3C private read/write transfer, as target . . . . . . . . . . . . . . . . . . . . . . 3202
64.9.12 Legacy I2C read/write transfer, as controller . . . . . . . . . . . . . . . . . . . 3203
64.9.13 I3C IBI transfer, as controller/target . . . . . . . . . . . . . . . . . . . . . . . . . . 3204
64.9.14 I3C hot-join request transfer, as controller/target . . . . . . . . . . . . . . . . 3206
64.9.15 I3C controller-role request transfer, as controller/target . . . . . . . . . . 3207
64.10 I3C FIFOs management, as controller . . . . . . . . . . . . . . . . . . . . . . . . . 3208
64.10.1 C-FIFO management, as controller . . . . . . . . . . . . . . . . . . . . . . . . . . 3208
64.10.2 TX-FIFO management, as controller . . . . . . . . . . . . . . . . . . . . . . . . . 3209
64.10.3 RX-FIFO management, as controller . . . . . . . . . . . . . . . . . . . . . . . . . 3212
64.10.4 S-FIFO management, as controller . . . . . . . . . . . . . . . . . . . . . . . . . . 3214
64.11 I3C FIFOs management, as target . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3216
64.11.1 RX-FIFO management, as target . . . . . . . . . . . . . . . . . . . . . . . . . . . 3216
64.11.2 TX-FIFO management, as target . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3217
64.12 I3C error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3220
64.12.1 Controller error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3220
64.12.2 Target error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3222
64.13 I3C wake-up from low-power mode(s) . . . . . . . . . . . . . . . . . . . . . . . . . 3223
64.13.1 Wake-up from Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3223
64.14 I3C in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3226
64.15 I3C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3227

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64.16 I3C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3228

64.16.1 I3C message control register (I3C_CR) . . . . . . . . . . . . . . . . . . . . . . . 3228
64.16.2 I3C message control register [alternate] (I3C_CR) . . . . . . . . . . . . . . 3230
64.16.3 I3C configuration register (I3C_CFGR) . . . . . . . . . . . . . . . . . . . . . . . 3232
64.16.4 I3C receive data byte register (I3C_RDR) . . . . . . . . . . . . . . . . . . . . . 3237
64.16.5 I3C receive data word register (I3C_RDWR) . . . . . . . . . . . . . . . . . . . 3237
64.16.6 I3C transmit data byte register (I3C_TDR) . . . . . . . . . . . . . . . . . . . . 3238
64.16.7 I3C transmit data word register (I3C_TDWR) . . . . . . . . . . . . . . . . . . 3239
64.16.8 I3C IBI payload data register (I3C_IBIDR) . . . . . . . . . . . . . . . . . . . . . 3241
64.16.9 I3C target transmit configuration register (I3C_TGTTDR) . . . . . . . . . 3242
64.16.10 I3C status register (I3C_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3243
64.16.11 I3C status error register (I3C_SER) . . . . . . . . . . . . . . . . . . . . . . . . . . 3244
64.16.12 I3C received message register (I3C_RMR) . . . . . . . . . . . . . . . . . . . . 3246
64.16.13 I3C event register (I3C_EVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3247
64.16.14 I3C interrupt enable register (I3C_IER) . . . . . . . . . . . . . . . . . . . . . . . 3251
64.16.15 I3C clear event register (I3C_CEVR) . . . . . . . . . . . . . . . . . . . . . . . . . 3253
64.16.16 I3C own device characteristics register (I3C_DEVR0) . . . . . . . . . . . 3255
64.16.17 I3C device x characteristics register (I3C_DEVRx) . . . . . . . . . . . . . . 3257
64.16.18 I3C maximum read length register (I3C_MAXRLR) . . . . . . . . . . . . . . 3259
64.16.19 I3C maximum write length register (I3C_MAXWLR) . . . . . . . . . . . . . 3260
64.16.20 I3C timing register 0 (I3C_TIMINGR0) . . . . . . . . . . . . . . . . . . . . . . . 3261
64.16.21 I3C timing register 1 (I3C_TIMINGR1) . . . . . . . . . . . . . . . . . . . . . . . 3262
64.16.22 I3C timing register 2 (I3C_TIMINGR2) . . . . . . . . . . . . . . . . . . . . . . . 3264
64.16.23 I3C bus characteristics register (I3C_BCR) . . . . . . . . . . . . . . . . . . . . 3265
64.16.24 I3C device characteristics register (I3C_DCR) . . . . . . . . . . . . . . . . . 3266
64.16.25 I3C get capability register (I3C_GETCAPR) . . . . . . . . . . . . . . . . . . . 3267
64.16.26 I3C controller-role capability register (I3C_CRCAPR) . . . . . . . . . . . . 3268
64.16.27 I3C get max data speed register (I3C_GETMXDSR) . . . . . . . . . . . . 3269
64.16.28 I3C extended provisioned ID register (I3C_EPIDR) . . . . . . . . . . . . . 3271
64.16.29 I3C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3272

65 Universal synchronous/asynchronous receiver

transmitter (USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3275
65.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3275
65.2 USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3275
65.3 USART extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3276
65.4 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3276

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65.5 USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3278

65.5.1 USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3278
65.5.2 USART pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3278
65.5.3 USART clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3280
65.5.4 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3280
65.5.5 USART FIFOs and thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3283
65.5.6 USART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3283
65.5.7 USART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3286
65.5.8 USART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3293
65.5.9 Tolerance of the USART receiver to clock deviation . . . . . . . . . . . . . 3295
65.5.10 USART auto baud rate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3296
65.5.11 USART multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . 3298
65.5.12 USART Modbus communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3300
65.5.13 USART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3301
65.5.14 USART LIN (local interconnection network) mode . . . . . . . . . . . . . . 3302
65.5.15 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3304
65.5.16 USART single-wire half-duplex communication . . . . . . . . . . . . . . . . . 3308
65.5.17 USART receiver timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3308
65.5.18 USART smartcard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3309
65.5.19 USART IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3313
65.5.20 Continuous communication using USART and DMA . . . . . . . . . . . . . 3316
65.5.21 RS232 hardware flow control and RS485 driver enable . . . . . . . . . . 3318
65.5.22 USART low-power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3321
65.6 USART in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3324
65.7 USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3324
65.8 USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3327
65.8.1 USART control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . 3327
65.8.2 USART control register 1 [alternate] (USART_CR1) . . . . . . . . . . . . . 3331
65.8.3 USART control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . 3334
65.8.4 USART control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . 3338
65.8.5 USART control register 3 [alternate] (USART_CR3) . . . . . . . . . . . . . 3342
65.8.6 USART baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . 3346
65.8.7 USART guard time and prescaler register (USART_GTPR) . . . . . . . 3346
65.8.8 USART receiver timeout register (USART_RTOR) . . . . . . . . . . . . . . 3347
65.8.9 USART request register (USART_RQR) . . . . . . . . . . . . . . . . . . . . . . 3348
65.8.10 USART interrupt and status register (USART_ISR) . . . . . . . . . . . . . 3349
65.8.11 USART interrupt and status register [alternate] (USART_ISR) . . . . . 3355

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65.8.12 USART interrupt flag clear register (USART_ICR) . . . . . . . . . . . . . . 3360

65.8.13 USART receive data register (USART_RDR) . . . . . . . . . . . . . . . . . . 3361
65.8.14 USART transmit data register (USART_TDR) . . . . . . . . . . . . . . . . . . 3362
65.8.15 USART prescaler register (USART_PRESC) . . . . . . . . . . . . . . . . . . 3362
65.8.16 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3363

66 Low-power universal asynchronous receiver

transmitter (LPUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3365
66.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3365
66.2 LPUART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3365
66.3 LPUART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3366
66.4 LPUART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3368
66.4.1 LPUART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3368
66.4.2 LPUART pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 3369
66.4.3 LPUART clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3370
66.4.4 LPUART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3370
66.4.5 LPUART FIFOs and thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3372
66.4.6 LPUART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3372
66.4.7 LPUART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3376
66.4.8 LPUART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3380
66.4.9 Tolerance of the LPUART receiver to clock deviation . . . . . . . . . . . . 3381
66.4.10 LPUART multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . 3382
66.4.11 LPUART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3384
66.4.12 LPUART single-wire half-duplex communication . . . . . . . . . . . . . . . . 3385
66.4.13 Continuous communication using DMA and LPUART . . . . . . . . . . . . 3385
66.4.14 RS232 hardware flow control and RS485 driver enable . . . . . . . . . . 3388
66.4.15 LPUART low-power management . . . . . . . . . . . . . . . . . . . . . . . . . . . 3390
66.5 LPUART in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3393
66.6 LPUART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3394
66.7 LPUART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3395
66.7.1 LPUART control register 1 (LPUART_CR1) . . . . . . . . . . . . . . . . . . . 3395
66.7.2 LPUART control register 1 [alternate] (LPUART_CR1) . . . . . . . . . . . 3398
66.7.3 LPUART control register 2 (LPUART_CR2) . . . . . . . . . . . . . . . . . . . 3401
66.7.4 LPUART control register 3 (LPUART_CR3) . . . . . . . . . . . . . . . . . . . 3403
66.7.5 LPUART control register 3 [alternate] (LPUART_CR3) . . . . . . . . . . . 3406
66.7.6 LPUART baud rate register (LPUART_BRR) . . . . . . . . . . . . . . . . . . 3408

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66.7.7 LPUART request register (LPUART_RQR) . . . . . . . . . . . . . . . . . . . . 3408

66.7.8 LPUART interrupt and status register (LPUART_ISR) . . . . . . . . . . . 3409
66.7.9 LPUART interrupt and status register [alternate] (LPUART_ISR) . . . 3414
66.7.10 LPUART interrupt flag clear register (LPUART_ICR) . . . . . . . . . . . . 3417
66.7.11 LPUART receive data register (LPUART_RDR) . . . . . . . . . . . . . . . . 3418
66.7.12 LPUART transmit data register (LPUART_TDR) . . . . . . . . . . . . . . . . 3418
66.7.13 LPUART prescaler register (LPUART_PRESC) . . . . . . . . . . . . . . . . 3419
66.7.14 LPUART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3420

67 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3422

67.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3422
67.2 SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3422
67.3 SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3423
67.4 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3424
67.4.1 SPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3424
67.4.2 SPI pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3425
67.4.3 SPI communication general aspects . . . . . . . . . . . . . . . . . . . . . . . . . 3426
67.4.4 Communications between one master and one slave . . . . . . . . . . . . 3426
67.4.5 Standard multislave communication . . . . . . . . . . . . . . . . . . . . . . . . . 3429
67.4.6 Multimaster communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3432
67.4.7 Slave select (SS) pin management . . . . . . . . . . . . . . . . . . . . . . . . . . 3432
67.4.8 Ready pin (RDY) management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3436
67.4.9 Communication formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3436
67.4.10 Configuring the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3438
67.4.11 Enabling the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3439
67.4.12 SPI data transmission and reception procedures . . . . . . . . . . . . . . . 3440
67.4.13 Disabling the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3444
67.4.14 Communication using DMA (direct memory addressing) . . . . . . . . . . 3445
67.5 SPI specific modes and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3447
67.5.1 TI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3447
67.5.2 SPI error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3447
67.5.3 CRC computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3451
67.6 SPI in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3452
67.7 SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3452
67.8 I2S main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3454
67.9 I2S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3454

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67.9.1 I2S general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3454

67.9.2 Pin sharing with SPI function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3455
67.9.3 Bitfields usable in I2S/PCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 3455
67.9.4 Slave and master modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3456
67.9.5 Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3456
67.9.6 Additional serial interface flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . 3462
67.9.7 Startup sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3464
67.9.8 Stop sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3466
67.9.9 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3467
67.9.10 Internal FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3469
67.9.11 FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3470
67.9.12 Handling of underrun situation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3470
67.9.13 Handling of overrun situation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3471
67.9.14 Frame error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3472
67.9.15 DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3474
67.9.16 Programing examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3474
67.10 I2S interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3476
67.11 SPI/I2S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3477
67.11.1 SPI/I2S control register 1 (SPI_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 3477
67.11.2 SPI/I2S control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 3479
67.11.3 SPI/I2S configuration register 1 (SPI_CFG1) . . . . . . . . . . . . . . . . . . 3479
67.11.4 SPI/I2S configuration register 2 (SPI_CFG2) . . . . . . . . . . . . . . . . . . 3482
67.11.5 SPI/I2S interrupt enable register (SPI_IER) . . . . . . . . . . . . . . . . . . . 3484
67.11.6 SPI/I2S status register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3485
67.11.7 SPI/I2S interrupt/status flags clear register (SPI_IFCR) . . . . . . . . . . 3488
67.11.8 SPI/I2S transmit data register (SPI_TXDR) . . . . . . . . . . . . . . . . . . . . 3489
67.11.9 SPI/I2S receive data register (SPI_RXDR) . . . . . . . . . . . . . . . . . . . . 3489
67.11.10 SPI/I2S polynomial register (SPI_CRCPOLY) . . . . . . . . . . . . . . . . . . 3490
67.11.11 SPI/I2S transmitter CRC register (SPI_TXCRC) . . . . . . . . . . . . . . . . 3490
67.11.12 SPI/I2S receiver CRC register (SPI_RXCRC) . . . . . . . . . . . . . . . . . . 3491
67.11.13 SPI/I2S underrun data register (SPI_UDRDR) . . . . . . . . . . . . . . . . . 3492
67.11.14 SPI/I2S configuration register (SPI_I2SCFGR) . . . . . . . . . . . . . . . . . 3492
67.11.15 SPI/I2S register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3494

68 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3496

68.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3496
68.2 SAI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3496

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68.3 SAI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3497

68.4 SAI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3498
68.4.1 SAI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3498
68.4.2 SAI pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3499
68.4.3 Main SAI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3500
68.4.4 SAI synchronization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3501
68.4.5 Audio data size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3502
68.4.6 Frame synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3502
68.4.7 Slot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3505
68.4.8 SAI clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3507
68.4.9 Internal FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3510
68.4.10 PDM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3512
68.4.11 AC’97 link controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3520
68.4.12 SPDIF output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3522
68.4.13 Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3525
68.4.14 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3529
68.4.15 Disabling the SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3532
68.4.16 SAI DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3532
68.5 SAI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3533
68.6 SAI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3535
68.6.1 SAI global configuration register (SAI_GCR) . . . . . . . . . . . . . . . . . . . 3535
68.6.2 SAI configuration register 1 (SAI_ACR1) . . . . . . . . . . . . . . . . . . . . . . 3535
68.6.3 SAI configuration register 2 (SAI_ACR2) . . . . . . . . . . . . . . . . . . . . . . 3538
68.6.4 SAI frame configuration register (SAI_AFRCR) . . . . . . . . . . . . . . . . . 3540
68.6.5 SAI slot register (SAI_ASLOTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3541
68.6.6 SAI interrupt mask register (SAI_AIM) . . . . . . . . . . . . . . . . . . . . . . . . 3542
68.6.7 SAI status register (SAI_ASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3543
68.6.8 SAI clear flag register (SAI_ACLRFR) . . . . . . . . . . . . . . . . . . . . . . . . 3545
68.6.9 SAI data register (SAI_ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3546
68.6.10 SAI configuration register 1 (SAI_BCR1) . . . . . . . . . . . . . . . . . . . . . . 3547
68.6.11 SAI configuration register 2 (SAI_BCR2) . . . . . . . . . . . . . . . . . . . . . . 3549
68.6.12 SAI frame configuration register (SAI_BFRCR) . . . . . . . . . . . . . . . . . 3551
68.6.13 SAI slot register (SAI_BSLOTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3552
68.6.14 SAI interrupt mask register (SAI_BIM) . . . . . . . . . . . . . . . . . . . . . . . . 3553
68.6.15 SAI status register (SAI_BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3555
68.6.16 SAI clear flag register (SAI_BCLRFR) . . . . . . . . . . . . . . . . . . . . . . . . 3557
68.6.17 SAI data register (SAI_BDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3558

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68.6.18 SAI PDM control register (SAI_PDMCR) . . . . . . . . . . . . . . . . . . . . . . 3558

68.6.19 SAI PDM delay register (SAI_PDMDLY) . . . . . . . . . . . . . . . . . . . . . . 3559
68.6.20 SAI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3561

69 SPDIF receiver interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 3563

69.1 SPDIFRX interface introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3563
69.2 SPDIFRX main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3563
69.3 SPDIFRX functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3563
69.3.1 SPDIFRX pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . 3564
69.3.2 S/PDIF protocol (IEC-60958) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3565
69.3.3 SPDIFRX decoder (SPDIFRX_DC) . . . . . . . . . . . . . . . . . . . . . . . . . . 3567
69.3.4 SPDIFRX tolerance to clock deviation . . . . . . . . . . . . . . . . . . . . . . . . 3571
69.3.5 SPDIFRX synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3571
69.3.6 SPDIFRX handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3573
69.3.7 Data reception management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3575
69.3.8 Dedicated control flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3577
69.3.9 Reception errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3578
69.3.10 Clocking strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3580
69.3.11 Symbol clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3580
69.3.12 DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3582
69.3.13 Interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3583
69.3.14 Register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3584
69.4 Programming procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3584
69.4.1 Initialization phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3585
69.4.2 Handling of interrupts coming from SPDIFRX . . . . . . . . . . . . . . . . . . 3586
69.4.3 Handling of interrupts coming from DMA . . . . . . . . . . . . . . . . . . . . . . 3586
69.5 SPDIFRX interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3587
69.5.1 SPDIFRX control register (SPDIFRX_CR) . . . . . . . . . . . . . . . . . . . . 3587
69.5.2 SPDIFRX interrupt mask register (SPDIFRX_IMR) . . . . . . . . . . . . . . 3589
69.5.3 SPDIFRX status register (SPDIFRX_SR) . . . . . . . . . . . . . . . . . . . . . 3590
69.5.4 SPDIFRX interrupt flag clear register (SPDIFRX_IFCR) . . . . . . . . . . 3592
69.5.5 SPDIFRX data input register (SPDIFRX_FMT0_DR) . . . . . . . . . . . . 3593
69.5.6 SPDIFRX data input register (SPDIFRX_FMT1_DR) . . . . . . . . . . . . 3593
69.5.7 SPDIFRX data input register (SPDIFRX_FMT2_DR) . . . . . . . . . . . . 3594
69.5.8 SPDIFRX channel status register (SPDIFRX_CSR) . . . . . . . . . . . . . 3595
69.5.9 SPDIFRX debug information register (SPDIFRX_DIR) . . . . . . . . . . . 3595
69.5.10 SPDIFRX interface register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3596

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70 Management data input/output (MDIOS) . . . . . . . . . . . . . . . . . . . . . . 3597

70.1 MDIOS introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3597
70.2 MDIOS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3597
70.3 MDIOS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3598
70.3.1 MDIOS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3598
70.3.2 MDIOS pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3598
70.3.3 MDIOS protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3598
70.3.4 MDIOS enabling and disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3599
70.3.5 MDIOS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3600
70.3.6 MDIOS APB frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3601
70.3.7 Write/read flags and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3601
70.3.8 MDIOS error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3602
70.3.9 MDIOS in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3603
70.3.10 MDIOS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3603
70.4 MDIOS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3603
70.4.1 MDIOS configuration register (MDIOS_CR) . . . . . . . . . . . . . . . . . . . 3603
70.4.2 MDIOS write flag register (MDIOS_WRFR) . . . . . . . . . . . . . . . . . . . . 3604
70.4.3 MDIOS clear write flag register (MDIOS_CWRFR) . . . . . . . . . . . . . . 3605
70.4.4 MDIOS read flag register (MDIOS_RDFR) . . . . . . . . . . . . . . . . . . . . 3605
70.4.5 MDIOS clear read flag register (MDIOS_CRDFR) . . . . . . . . . . . . . . 3606
70.4.6 MDIOS status register (MDIOS_SR) . . . . . . . . . . . . . . . . . . . . . . . . . 3606
70.4.7 MDIOS clear flag register (MDIOS_CLRFR) . . . . . . . . . . . . . . . . . . . 3607
70.4.8 MDIOS input data register x (MDIOS_DINRx) . . . . . . . . . . . . . . . . . . 3607
70.4.9 MDIOS output data register x (MDIOS_DOUTRx) . . . . . . . . . . . . . . 3608
70.4.10 MDIOS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3608

71 Controller area network with flexible data rate (FDCAN) . . . . . . . . 3610

71.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3610
71.2 FDCAN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3613
71.3 FDCAN implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3613
71.4 FDCAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3614
71.4.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3615
71.4.2 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3624
71.4.3 Message RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3624
71.4.4 FIFO acknowledge handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3636
71.4.5 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3637

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71.4.6 Clock calibration on CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3638

71.4.7 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3642
71.4.8 TTCAN operations (FDCAN1 only) . . . . . . . . . . . . . . . . . . . . . . . . . . 3643
71.4.9 TTCAN configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3644
71.4.10 Message scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3646
71.4.11 TTCAN gap control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3653
71.4.12 Stop watch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3654
71.4.13 Local time, cycle time, global time,
and external clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . 3654
71.4.14 TTCAN error level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3657
71.4.15 TTCAN message handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3658
71.4.16 TTCAN interrupt and error handling . . . . . . . . . . . . . . . . . . . . . . . . . 3661
71.4.17 Level 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3662
71.4.18 Synchronization to external time schedule . . . . . . . . . . . . . . . . . . . . 3664
71.4.19 FDCAN Rx buffer and FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . 3665
71.4.20 FDCAN Tx buffer element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3667
71.4.21 FDCAN Tx event FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3669
71.4.22 FDCAN standard message ID filter element . . . . . . . . . . . . . . . . . . . 3670
71.4.23 FDCAN extended message ID filter element . . . . . . . . . . . . . . . . . . . 3672
71.4.24 FDCAN trigger memory element . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3673
71.5 FDCAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3675
71.5.1 FDCAN core release register (FDCAN_CREL) . . . . . . . . . . . . . . . . . 3675
71.5.2 FDCAN Endian register (FDCAN_ENDN) . . . . . . . . . . . . . . . . . . . . . 3675
71.5.3 FDCAN data bit timing and prescaler register (FDCAN_DBTP) . . . . 3675
71.5.4 FDCAN test register (FDCAN_TEST) . . . . . . . . . . . . . . . . . . . . . . . . 3676
71.5.5 FDCAN RAM watchdog register (FDCAN_RWD) . . . . . . . . . . . . . . . 3677
71.5.6 FDCAN CC control register (FDCAN_CCCR) . . . . . . . . . . . . . . . . . . 3678
71.5.7 FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) . 3680
71.5.8 FDCAN timestamp counter configuration register (FDCAN_TSCC) . 3681
71.5.9 FDCAN timestamp counter value register (FDCAN_TSCV) . . . . . . . 3681
71.5.10 FDCAN timeout counter configuration register (FDCAN_TOCC) . . . 3682
71.5.11 FDCAN timeout counter value register (FDCAN_TOCV) . . . . . . . . . 3683
71.5.12 FDCAN error counter register (FDCAN_ECR) . . . . . . . . . . . . . . . . . 3683
71.5.13 FDCAN protocol status register (FDCAN_PSR) . . . . . . . . . . . . . . . . 3684
71.5.14 FDCAN transmitter delay compensation register (FDCAN_TDCR) . . 3686
71.5.15 FDCAN interrupt register (FDCAN_IR) . . . . . . . . . . . . . . . . . . . . . . . 3686
71.5.16 FDCAN interrupt enable register (FDCAN_IE) . . . . . . . . . . . . . . . . . 3689

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71.5.17 FDCAN interrupt line select register (FDCAN_ILS) . . . . . . . . . . . . . . 3691

71.5.18 FDCAN interrupt line enable register (FDCAN_ILE) . . . . . . . . . . . . . 3692
71.5.19 FDCAN global filter configuration register (FDCAN_GFC) . . . . . . . . 3693
71.5.20 FDCAN standard ID filter configuration register (FDCAN_SIDFC) . . 3694
71.5.21 FDCAN extended ID filter configuration register (FDCAN_XIDFC) . . 3694
71.5.22 FDCAN extended ID and mask register (FDCAN_XIDAM) . . . . . . . . 3695
71.5.23 FDCAN high priority message status register (FDCAN_HPMS) . . . . 3696
71.5.24 FDCAN new data 1 register (FDCAN_NDAT1) . . . . . . . . . . . . . . . . . 3696
71.5.25 FDCAN new data 2 register (FDCAN_NDAT2) . . . . . . . . . . . . . . . . . 3697
71.5.26 FDCAN Rx FIFO 0 configuration register (FDCAN_RXF0C) . . . . . . . 3697
71.5.27 FDCAN Rx FIFO 0 status register (FDCAN_RXF0S) . . . . . . . . . . . . 3698
71.5.28 FDCAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A) . . . . . . 3699
71.5.29 FDCAN Rx buffer configuration register (FDCAN_RXBC) . . . . . . . . . 3699
71.5.30 FDCAN Rx FIFO 1 configuration register (FDCAN_RXF1C) . . . . . . . 3700
71.5.31 FDCAN Rx FIFO 1 status register (FDCAN_RXF1S) . . . . . . . . . . . . 3701
71.5.32 FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A) . . . . . . 3702
71.5.33 FDCAN Rx buffer element size configuration register
(FDCAN_RXESC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3702
71.5.34 FDCAN Tx buffer configuration register (FDCAN_TXBC) . . . . . . . . . 3703
71.5.35 FDCAN Tx FIFO/queue status register (FDCAN_TXFQS) . . . . . . . . 3704
71.5.36 FDCAN Tx buffer element size configuration register
(FDCAN_TXESC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3705
71.5.37 FDCAN Tx buffer request pending register (FDCAN_TXBRP) . . . . . 3705
71.5.38 FDCAN Tx buffer add request register (FDCAN_TXBAR) . . . . . . . . . 3706
71.5.39 FDCAN Tx buffer cancellation request register (FDCAN_TXBCR) . . 3707
71.5.40 FDCAN Tx buffer transmission occurred register (FDCAN_TXBTO) 3707
71.5.41 FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF) . . 3708
71.5.42 FDCAN Tx buffer transmission interrupt enable register
(FDCAN_TXBTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3708
71.5.43 FDCAN Tx buffer cancellation finished interrupt enable register
(FDCAN_TXBCIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3709
71.5.44 FDCAN Tx event FIFO configuration register (FDCAN_TXEFC) . . . 3709
71.5.45 FDCAN Tx event FIFO status register (FDCAN_TXEFS) . . . . . . . . . 3710
71.5.46 FDCAN Tx event FIFO acknowledge register (FDCAN_TXEFA) . . . 3711
71.5.47 FDCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3711
71.6 TTCAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3715
71.6.1 FDCAN TT trigger memory configuration register
(FDCAN_TTTMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3715

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71.6.2 FDCAN TT reference message configuration register

(FDCAN_TTRMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3715
71.6.3 FDCAN TT operation configuration register (FDCAN_TTOCF) . . . . . 3716
71.6.4 FDCAN TT matrix limits register (FDCAN_TTMLM) . . . . . . . . . . . . . 3718
71.6.5 FDCAN TUR configuration register (FDCAN_TURCF) . . . . . . . . . . . 3719
71.6.6 FDCAN TT operation control register (FDCAN_TTOCN) . . . . . . . . . 3720
71.6.7 FDCAN TT global time preset register (FDCAN_TTGTP) . . . . . . . . . 3722
71.6.8 FDCAN TT time mark register (FDCAN_TTTMK) . . . . . . . . . . . . . . . 3722
71.6.9 FDCAN TT interrupt register (FDCAN_TTIR) . . . . . . . . . . . . . . . . . . 3723
71.6.10 FDCAN TT interrupt enable register (FDCAN_TTIE) . . . . . . . . . . . . . 3725
71.6.11 FDCAN TT interrupt line select register (FDCAN_TTILS) . . . . . . . . . 3727
71.6.12 FDCAN TT operation status register (FDCAN_TTOST) . . . . . . . . . . 3728
71.6.13 FDCAN TUR numerator actual register (FDCAN_TURNA) . . . . . . . . 3730
71.6.14 FDCAN TT local and global time register (FDCAN_TTLGT) . . . . . . . 3731
71.6.15 FDCAN TT cycle time and count register (FDCAN_TTCTC) . . . . . . . 3731
71.6.16 FDCAN TT capture time register (FDCAN_TTCPT) . . . . . . . . . . . . . 3732
71.6.17 FDCAN TT cycle sync mark register (FDCAN_TTCSM) . . . . . . . . . . 3732
71.6.18 FDCAN TT trigger select register (FDCAN_TTTS) . . . . . . . . . . . . . . 3733
71.6.19 FDCAN TT register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3733
71.7 CCU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3735
71.7.1 Clock calibration unit core release register (FDCAN_CCU_CREL) . . 3735
71.7.2 Calibration configuration register (FDCAN_CCU_CCFG) . . . . . . . . . 3735
71.7.3 Calibration status register (FDCAN_CCU_CSTAT) . . . . . . . . . . . . . . 3737
71.7.4 Calibration watchdog register (FDCAN_CCU_CWD) . . . . . . . . . . . . 3737
71.7.5 Clock calibration unit interrupt register (FDCAN_CCU_IR) . . . . . . . . 3738
71.7.6 Clock calibration unit interrupt enable register (FDCAN_CCU_IE) . . 3739
71.7.7 CCU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3739

72 USB subsystem (USBSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3741

72.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3741
72.2 USB2 OTG high-speed Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3741
72.2.1 USB2 OTG high-speed Port 1 main features . . . . . . . . . . . . . . . . . . 3741
72.2.2 USB2 OTG high-speed Port 1 functional description . . . . . . . . . . . . 3742
72.2.3 USB2 OTG high-speed Port 1 interrupts . . . . . . . . . . . . . . . . . . . . . . 3744
72.2.4 Battery charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3744
72.2.5 ID management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3745
72.2.6 VBUS detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3745

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72.3 USB2 OTG high-speed Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3745

72.3.1 USB2 OTG high-speed Port 2 main features . . . . . . . . . . . . . . . . . . 3745
72.3.2 USB2 OTG high-speed Port 2 functional description . . . . . . . . . . . . 3746
72.3.3 USB2 OTG high-speed Port 2 interrupts . . . . . . . . . . . . . . . . . . . . . . 3748
72.3.4 Battery charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3748
72.3.5 ID management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3748
72.3.6 VBUS management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3748
72.4 USB Type-C and power delivery interface . . . . . . . . . . . . . . . . . . . . . . 3749
72.4.1 USB Type-C and power delivery interface main features . . . . . . . . . 3749
72.4.2 USB Type-C and power delivery interface implementation . . . . . . . . 3749
72.4.3 USB Type-C and power delivery interface functional description . . . 3751
72.4.4 USB Type-C and power delivery interrupts . . . . . . . . . . . . . . . . . . . . 3752
72.5 Debug signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3753

73 USB on-the-go high-speed (OTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3754

73.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3754
73.2 OTG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3755
73.2.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3755
73.2.2 Host-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3756
73.2.3 Peripheral-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3756
73.3 OTG implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3756
73.4 OTG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3757
73.4.1 OTG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3757
73.4.2 OTG pin and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3757
73.4.3 OTG core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3758
73.4.4 OTG detections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3758
73.4.5 High-speed OTG PHY connected to OTG . . . . . . . . . . . . . . . . . . . . . 3758
73.4.6 Battery charging detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3758
73.5 OTG dual role device (DRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3759
73.5.1 ID line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3759
73.6 OTG as a USB peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3759
73.6.1 Peripheral states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3760
73.6.2 Peripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3761
73.7 OTG as a USB host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3763
73.7.1 USB host states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3764
73.7.2 Host channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3765

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73.7.3 Host scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3766

73.8 OTG SOF trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3767
73.8.1 Host SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3768
73.8.2 Peripheral SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3768
73.9 OTG low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3768
73.10 OTG Dynamic update of the OTG_HFIR register . . . . . . . . . . . . . . . . 3769
73.11 OTG data FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3770
73.11.1 Peripheral FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3770
73.11.2 Host FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3771
73.11.3 FIFO RAM allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3773
73.12 OTG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3774
73.13 OTG control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3776
73.13.1 CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3776
73.14 OTG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3781
73.14.1 OTG control and status register (OTG_GOTGCTL) . . . . . . . . . . . . . 3781
73.14.2 OTG interrupt register (OTG_GOTGINT) . . . . . . . . . . . . . . . . . . . . . 3783
73.14.3 OTG AHB configuration register (OTG_GAHBCFG) . . . . . . . . . . . . . 3784
73.14.4 OTG USB configuration register (OTG_GUSBCFG) . . . . . . . . . . . . . 3785
73.14.5 OTG reset register (OTG_GRSTCTL) . . . . . . . . . . . . . . . . . . . . . . . . 3787
73.14.6 OTG core interrupt register [alternate] (OTG_GINTSTS) . . . . . . . . . 3790
73.14.7 OTG core interrupt register [alternate] (OTG_GINTSTS) . . . . . . . . . 3794
73.14.8 OTG interrupt mask register [alternate] (OTG_GINTMSK) . . . . . . . . 3799
73.14.9 OTG interrupt mask register [alternate] (OTG_GINTMSK) . . . . . . . . 3800
73.14.10 OTG receive status debug read register [alternate]
(OTG_GRXSTSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3802
73.14.11 OTG receive status debug read register [alternate]
(OTG_GRXSTSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3803
73.14.12 OTG status read and pop registers (OTG_GRXSTSP) . . . . . . . . . . . 3804
73.14.13 OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . 3805
73.14.14 OTG receive FIFO size register (OTG_GRXFSIZ) . . . . . . . . . . . . . . 3806
73.14.15 OTG host non-periodic transmit FIFO size register [alternate]
(OTG_HNPTXFSIZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3807
73.14.16 Endpoint 0 transmit FIFO size [alternate] (OTG_DIEPTXF0) . . . . . . 3807
73.14.17 OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3808
73.14.18 OTG general core configuration register (OTG_GCCFG) . . . . . . . . . 3809
73.14.19 OTG core ID register (OTG_CID) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3810

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73.14.20 OTG core LPM configuration register (OTG_GLPMCFG) . . . . . . . . . 3811

73.14.21 OTG host periodic transmit FIFO size register
(OTG_HPTXFSIZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3815
73.14.22 OTG device IN endpoint transmit FIFO x size register
(OTG_DIEPTXFx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3815
73.14.23 Host-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3815
73.14.24 OTG host configuration register (OTG_HCFG) . . . . . . . . . . . . . . . . . 3816
73.14.25 OTG host frame interval register (OTG_HFIR) . . . . . . . . . . . . . . . . . 3816
73.14.26 OTG host frame number/frame time remaining register
(OTG_HFNUM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3817
73.14.27 OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3818
73.14.28 OTG host all channels interrupt register (OTG_HAINT) . . . . . . . . . . 3819
73.14.29 OTG host all channels interrupt mask register
(OTG_HAINTMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3819
73.14.30 OTG host port control and status register (OTG_HPRT) . . . . . . . . . . 3820
73.14.31 OTG host channel x characteristics register (OTG_HCCHARx) . . . . 3822
73.14.32 OTG host channel x split control register (OTG_HCSPLTx) . . . . . . . 3823
73.14.33 OTG host channel x interrupt register (OTG_HCINTx) . . . . . . . . . . . 3824
73.14.34 OTG host channel x interrupt mask register (OTG_HCINTMSKx) . . 3825
73.14.35 OTG host channel x transfer size register (OTG_HCTSIZx) . . . . . . . 3826
73.14.36 OTG host channel x DMA address register(OTG_HCDMAx) . . . . . . 3827
73.14.37 Device-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3827
73.14.38 OTG device configuration register (OTG_DCFG) . . . . . . . . . . . . . . . 3827
73.14.39 OTG device control register (OTG_DCTL) . . . . . . . . . . . . . . . . . . . . 3829
73.14.40 OTG device status register (OTG_DSTS) . . . . . . . . . . . . . . . . . . . . . 3831
73.14.41 OTG device IN endpoint common interrupt mask register
(OTG_DIEPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3832
73.14.42 OTG device OUT endpoint common interrupt mask register
(OTG_DOEPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3833
73.14.43 OTG device all endpoints interrupt register (OTG_DAINT) . . . . . . . . 3834
73.14.44 OTG all endpoints interrupt mask register
(OTG_DAINTMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3835
73.14.45 OTG device threshold control register (OTG_DTHRCTL) . . . . . . . . . 3835
73.14.46 OTG device IN endpoint FIFO empty interrupt mask register
(OTG_DIEPEMPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3836
73.14.47 OTG device IN endpoint x control register [alternate]
(OTG_DIEPCTLx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3837
73.14.48 OTG device IN endpoint x control register [alternate]
(OTG_DIEPCTLx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3839

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73.14.49 OTG device IN endpoint x interrupt register (OTG_DIEPINTx) . . . . . 3841

73.14.50 OTG device IN endpoint 0 transfer size register
(OTG_DIEPTSIZ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3842
73.14.51 OTG device IN endpoint x DMA address register
(OTG_DIEPDMAx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3843
73.14.52 OTG device IN endpoint transmit FIFO status register
(OTG_DTXFSTSx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3843
73.14.53 OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) . 3844
73.14.54 OTG device control OUT endpoint 0 control register
(OTG_DOEPCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3844
73.14.55 OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) . . 3846
73.14.56 OTG device OUT endpoint 0 transfer size register
(OTG_DOEPTSIZ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3848
73.14.57 OTG device OUT endpoint x DMA address register
(OTG_DOEPDMAx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3849
73.14.58 OTG device OUT endpoint x control register [alternate]
(OTG_DOEPCTLx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3849
73.14.59 OTG device OUT endpoint x control register [alternate]
(OTG_DOEPCTLx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3851
73.14.60 OTG device OUT endpoint x transfer size register
(OTG_DOEPTSIZx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3853
73.14.61 OTG power and clock gating control register (OTG_PCGCCTL) . . . 3854
73.14.62 OTG power and clock gating control register 1 (OTG_PCGCCTL1) . 3855
73.14.63 OTG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3856
73.15 OTG programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3863
73.15.1 Core initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3863
73.15.2 Host initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3864
73.15.3 Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3865
73.15.4 DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3865
73.15.5 Host programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3865
73.15.6 Device programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3898
73.15.7 Worst case response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3918
73.15.8 OTG programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3920

74 USB HS PHY controller (USBPHYC) . . . . . . . . . . . . . . . . . . . . . . . . . 3921

74.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3921
74.2 USBPHYC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3921
74.3 USBPHYC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3921
74.4 USBPHYC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3921

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74.4.1 USBPHYC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3921

74.4.2 USBPHYC reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3921
74.4.3 USBPHYC programmable parameters . . . . . . . . . . . . . . . . . . . . . . . 3922
74.4.4 USBPHYC trimming of electrical parameters . . . . . . . . . . . . . . . . . . 3922
74.5 USBPHYC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3922
74.5.1 USBPHYC control register (USBPHYC_CR) . . . . . . . . . . . . . . . . . . . 3922
74.5.2 USBPHYC trimming 1 register (USBPHYC_TRIM1CR) . . . . . . . . . . 3924
74.5.3 USBPHYC trimming 2 register (USBPHYC_TRIM2CR) . . . . . . . . . . 3928
74.5.4 USBPHYC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3929

75 USB Type-C®/USB Power Delivery interface (UCPD) . . . . . . . . . . . . 3930

75.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3930
75.2 UCPD main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3930
75.3 UCPD implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3931
75.4 UCPD functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3931
75.4.1 UCPD block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3932
75.4.2 UCPD reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3933
75.4.3 Physical layer protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3933
75.4.4 UCPD BMC transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3940
75.4.5 UCPD BMC receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3941
75.4.6 UCPD Type-C pull-ups (Rp) and pull-downs (Rd) . . . . . . . . . . . . . . . 3943
75.4.7 UCPD Type-C voltage monitoring and de-bouncing . . . . . . . . . . . . . 3943
75.4.8 UCPD fast role swap (FRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3944
75.4.9 UCPD DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3944
75.4.10 Wake-up from Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3944
75.5 UCPD programming sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3944
75.5.1 Initialization phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3944
75.5.2 Type-C state machine handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3945
75.5.3 USB PD transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3946
75.5.4 USB PD receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3947
75.6 UCPD low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3948
75.7 UCPD interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3949
75.8 UCPD registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3950
75.8.1 UCPD configuration register 1 (UCPD_CFGR1) . . . . . . . . . . . . . . . . 3950
75.8.2 UCPD configuration register 2 (UCPD_CFGR2) . . . . . . . . . . . . . . . . 3952
75.8.3 UCPD control register (UCPD_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 3952

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75.8.4 UCPD interrupt mask register (UCPD_IMR) . . . . . . . . . . . . . . . . . . . 3955

75.8.5 UCPD status register (UCPD_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . 3956
75.8.6 UCPD interrupt clear register (UCPD_ICR) . . . . . . . . . . . . . . . . . . . . 3959
75.8.7 UCPD Tx ordered set type register (UCPD_TX_ORDSETR) . . . . . . 3960
75.8.8 UCPD Tx payload size register (UCPD_TX_PAYSZR) . . . . . . . . . . . 3960
75.8.9 UCPD Tx data register (UCPD_TXDR) . . . . . . . . . . . . . . . . . . . . . . . 3961
75.8.10 UCPD Rx ordered set register (UCPD_RX_ORDSETR) . . . . . . . . . . 3961
75.8.11 UCPD Rx payload size register (UCPD_RX_PAYSZR) . . . . . . . . . . . 3962
75.8.12 UCPD receive data register (UCPD_RXDR) . . . . . . . . . . . . . . . . . . . 3962
75.8.13 UCPD Rx ordered set extension register 1
(UCPD_RX_ORDEXTR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3963
75.8.14 UCPD Rx ordered set extension register 2
(UCPD_RX_ORDEXTR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3963
75.8.15 UCPD register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3964

76 Ethernet (ETH): gigabit media access control

(GMAC) with DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3966
76.1 Ethernet introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3966
76.2 Ethernet main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3966
76.2.1 Standard compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3966
76.2.2 MAC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3966
76.2.3 Transaction layer (MTL) features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3968
76.2.4 DMA block features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3969
76.2.5 Bus interface features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3970
76.2.6 Audio and video features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3971
76.2.7 Time sensitive networking features . . . . . . . . . . . . . . . . . . . . . . . . . . 3971
76.2.8 Generic queuing features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3971
76.3 Ethernet pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3971
76.4 Ethernet architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3973
76.4.1 DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3974
76.4.2 MTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3981
76.4.3 MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3981
76.4.4 Multiple channels and queues support . . . . . . . . . . . . . . . . . . . . . . . 3986
76.5 Ethernet functional description: MAC . . . . . . . . . . . . . . . . . . . . . . . . . . 3998
76.5.1 Double VLAN processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3998
76.5.2 Source address and VLAN insertion, replacement, or deletion . . . . . 3999
76.5.3 Queue/channel-based VLAN tag insertion on Tx . . . . . . . . . . . . . . . 4000

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76.5.4 Packet filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4001

76.5.5 IEEE 1588 timestamp support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4013
76.5.6 Time sensitive networking (TSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4039
76.5.7 Checksum offload engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4068
76.5.8 TCP segmentation offload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4074
76.5.9 IPv4 ARP offload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4080
76.5.10 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4081
76.5.11 Flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4082
76.5.12 MAC management counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4085
76.5.13 Interrupts generated by the MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4087
76.5.14 MAC and MMC register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 4087
76.6 Ethernet functional description: PHY interfaces . . . . . . . . . . . . . . . . . . 4088
76.6.1 Station management agent (SMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 4088
76.6.2 Media independent interface (MII) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4095
76.6.3 Reduced media independent interface (RMII) . . . . . . . . . . . . . . . . . . 4096
76.6.4 Reduced gigabit media independent interface (RGMII) . . . . . . . . . . . 4099
76.7 Ethernet low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4102
76.7.1 Low-power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4102
76.7.2 Energy Efficient Ethernet (EEE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4108
76.8 Ethernet interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4114
76.8.1 DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4114
76.8.2 MTL interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4116
76.8.3 MAC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4116
76.9 Ethernet programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4117
76.9.1 DMA initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4117
76.9.2 MTL initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4118
76.9.3 MAC initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4119
76.9.4 Performing normal receive and transmit operation . . . . . . . . . . . . . . 4119
76.9.5 Stopping and starting transmission . . . . . . . . . . . . . . . . . . . . . . . . . . 4120
76.9.6 Programming guidelines for switching to new descriptor list
in RxDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4121
76.9.7 Programming guidelines for switching the AXI clock frequency . . . . 4121
76.9.8 Programming guidelines for multichannel multiqueue operation . . . . 4121
76.9.9 Programming guidelines for GMII link state transitions . . . . . . . . . . . 4124
76.9.10 Programming guidelines for IEEE 1588 timestamping . . . . . . . . . . . 4125
76.9.11 Programming guidelines for PTP offload feature . . . . . . . . . . . . . . . . 4126
76.9.12 Programming guidelines for AV feature . . . . . . . . . . . . . . . . . . . . . . . 4130

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76.9.13 Programming guidelines for Energy Efficient Ethernet (EEE) . . . . . . 4132

76.9.14 Programming guidelines for flexible pulse-per-second (PPS) output 4133
76.9.15 Programming guidelines for IEEE 1588 auxiliary snapshot . . . . . . . . 4136
76.9.16 Programming guidelines for TSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4136
76.9.17 Programming guidelines to perform VLAN filtering on the receiver . . 4137
76.9.18 Programming guidelines for extended VLAN filtering
and routing on reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4138
76.9.19 Programming sequence for queue/channel-
based VLAN inclusion register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4138
76.9.20 Programming guidelines for EST . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4139
76.9.21 Programming the launch time in time-based scheduling . . . . . . . . . . 4141
76.9.22 Enabling the frame preemption function . . . . . . . . . . . . . . . . . . . . . . 4141
76.10 Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4142
76.10.1 Descriptor overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4142
76.10.2 Descriptor structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4142
76.10.3 Transmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4146
76.10.4 Receive descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4159
76.10.5 Enhanced descriptor for time-based scheduling . . . . . . . . . . . . . . . . 4172
76.11 Ethernet registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4176
76.11.1 Ethernet register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4176
76.11.2 Ethernet DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4176
76.11.3 Ethernet MTL registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4207
76.11.4 Ethernet MAC and MMC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 4240

77 Hardware debug port (HDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4368

77.1 HDP introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4368
77.2 HDP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4368
77.3 HDP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4370
77.4 HDP register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4370
77.4.1 HDP control register (HDP_CTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . 4370
77.4.2 HDP multiplexer control register (HDP_MUX) . . . . . . . . . . . . . . . . . . 4371
77.4.3 HDP read back value register (HDP_VAL) . . . . . . . . . . . . . . . . . . . . 4371
77.4.4 HDP general-purpose output set register (HDP_GPOSET) . . . . . . . 4371
77.4.5 HDP general purpose output clear register (HDP_GPOCLR) . . . . . . 4372
77.4.6 HDP general purpose output value register (HDP_GPOVAL) . . . . . . 4372
77.4.7 HDP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4372

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78 Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4374

78.1 DBG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4374
78.2 DBG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4375
78.3 DBG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4377
78.4 DBG pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4377
78.5 DBG power, clock, and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4378
78.5.1 DBG power domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4378
78.5.2 DBG clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4378
78.5.3 Debug reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4379
78.6 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4379
78.6.1 BSEC control over debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4380
78.6.2 Authentication signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4380
78.7 Debug authentication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4381
78.7.1 Main characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4381
78.7.2 Debug authentication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4381
78.8 Chip-level TAP controller (CLTAPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4382
78.9 Serial-wire and JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . 4382
78.9.1 JTAG debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4383
78.9.2 SWD debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4386
78.9.3 Debug port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4388
78.10 Access ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4396
78.10.1 AP0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4398
78.10.2 AP1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4401
78.10.3 AP2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4405
78.10.4 ROM tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4410
78.10.5 System/MCU ROM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4412
78.11 Cortex-M55 debug features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4417
78.11.1 Processor ROM table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4417
78.11.2 Processor ROM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4419
78.11.3 Data watchpoint and trace unit (DWT) . . . . . . . . . . . . . . . . . . . . . . . . 4423
78.11.4 Cortex-M55 DWT registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4424
78.11.5 Cortex-M55 performance monitoring unit (PMU) . . . . . . . . . . . . . . . . 4438
78.11.6 Cortex-M55 PMU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4439
78.11.7 Instrumentation trace macrocell (ITM) . . . . . . . . . . . . . . . . . . . . . . . . 4452
78.11.8 Cortex-M55 ITM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4453
78.11.9 Breakpoint Unit (BPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4461

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78.11.10 Cortex-M55 BPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4461

78.11.11 Embedded Trace Macrocell (ETM) . . . . . . . . . . . . . . . . . . . . . . . . . . 4468
78.11.12 Cortex-M55 ETM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4468
78.11.13 Cross trigger interface (CTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4495
78.12 Trace and debug subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4495
78.12.1 Trace subsystem ROM table registers . . . . . . . . . . . . . . . . . . . . . . . . 4498
78.12.2 Global timestamp generator (TSGEN) . . . . . . . . . . . . . . . . . . . . . . . . 4502
78.12.3 TSGEN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4503
78.12.4 Cross trigger interface (CTI) and matrix (CTM) . . . . . . . . . . . . . . . . . 4510
78.12.5 CTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4514
78.12.6 Trace funnel (CSTF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4529
78.12.7 Trace funnel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4529
78.12.8 Embedded trace FIFO (ETF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4539
78.12.9 Embedded trace FIFO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4540
78.12.10 Embedded trace router (ETR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4558
78.12.11 ETR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4562
78.12.12 Trace port interface unit (TPIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4582
78.12.13 TPIU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4583
78.12.14 Trace replicator (REP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4599
78.12.15 Trace replicator registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4599
78.12.16 Serial-wire output (SWO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4609
78.12.17 SWO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4610
78.12.18 System trace macrocell (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4620
78.12.19 STM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4623
78.12.20 Microcontroller debug unit (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . 4649
78.12.21 DBGMCU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4650
78.13 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4661

79 Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4662

79.1 Unique device ID register (96 bits) (UID) . . . . . . . . . . . . . . . . . . . . . . . 4662
79.2 Device part number (RPN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4663
79.3 Package data register (PKG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4664
79.4 Device version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4664
79.5 Boot ROM version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4665

80 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4666

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81 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4667

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List of tables

Table 1. Memory map based on IDAU mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 2. Memory map and peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . 167
Table 3. Peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 4. Aliasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 5. Nonsecure peripheral functions that can be connected to secure I/Os . . . . . . . . . . . . . . 190
Table 6. Internal tampers in TAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 7. Effect of low-power modes on TAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 8. Accelerated cryptographic operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 9. BSEC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 10. BSEC initial status reporting structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 11. BSEC ad-hoc error/status reporting structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 12. BSEC states definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 13. Current HDPL coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 14. BSEC Next HDPL register usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 15. BSEC debug register legal values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 16. BSEC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 17. OTP mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 18. OTP fuse description (lower OTP region) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 19. OTP fuse description (mid OTP region) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 20. RISUP indexes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 21. RISC indexes purely for RCC security control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Table 22. RIMU resource assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Table 23. RIFSC register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Table 24. RISAF resource assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Table 25. RISAF internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Table 26. RISAF subregion security setup matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 27. RISAF register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 28. Peripheral indexes in IAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 29. IAC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Table 30. IAC interrupt request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Table 31. IAC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Table 32. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Table 33. Internal SRAM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Table 34. Hardware-erase conditions for internal SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Table 35. FLEXRAM supported configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Table 36. FLEXMEM versus retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Table 37. Effect of low-power modes on RAMCFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 38. RAMCFG interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 39. RAMCFG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Table 40. ICACHE features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Table 41. TAG memory dimensioning parameters
for n-way set associative operating mode (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Table 42. TAG memory dimensioning parameters for direct-mapped cache mode . . . . . . . . . . . . . 310
Table 43. ICACHE cacheability for AHB transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Table 44. ICACHE interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Table 45. ICACHE register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Table 46. CACHEAXI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Table 47. TAG memory dimensioning parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

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Table 48. CACHEAXI supported AXI 4-bit memory/cache attribute . . . . . . . . . . . . . . . . . . . . . . . . . 327

Table 49. CACHEAXI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Table 50. CACHEAXI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Table 51. PWR input/output signals connected to package pins or balls . . . . . . . . . . . . . . . . . . . . . 347
Table 52. PWR internal input/output signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Table 53. Wake-up source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Table 54. Supply configuration control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Table 55. Operating mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Table 56. Functionalities depending on system operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Table 57. Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Table 58. Stop mode SVOS high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Table 59. Stop mode SVOS low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Table 60. Standby and Stop flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Table 61. Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Table 62. Power mode output states versus MCU power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Table 63. PWR register security overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Table 64. PWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Table 65. RCC input/output signals connected to package pins or balls . . . . . . . . . . . . . . . . . . . . . 410
Table 66. RCC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Table 67. Reset coverage summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Table 68. Reset source identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Table 69. Oscillator states versus system modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Table 70. Clock output selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Table 71. STOPWUCK description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Table 72. HSISTOPEN and MSISTOPEN behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Table 73. Peripheral clock distribution summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
Table 74. SDMMC interface clock constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
Table 75. Peripheral clock enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
Table 76. Interrupt sources and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
Table 77. Maximum peripheral clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
Table 78. RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
Table 79. Port x bit configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
Table 80. Secure AF between peripherals and allocated I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
Table 81. GPIO secured bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
Table 82. GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
Table 83. SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
Table 84. Connectivity matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
Table 85. Implementation of HPDMA1 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
Table 86. HPDMA1 in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
Table 87. Programmed HPDMA1 request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
Table 88. Programmed HPDMA1 request as a block request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
Table 89. HPDMA1 channel with peripheral early termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
Table 90. Programmed HPDMA1 request with peripheral early termination . . . . . . . . . . . . . . . . . . 834
Table 91. Programmed HPDMA1 trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
Table 92. Programmed HPDMA source/destination burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859
Table 93. Programmed data handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864
Table 94. Effect of low-power modes on HPDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
Table 95. HPDMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
Table 96. HPDMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
Table 97. GPDMA1 channel implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
Table 98. GPDMA1 wake-up in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
Table 99. Programmed GPDMA1 request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927

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Table 100. Programmed GPDMA1 request as a block request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932

Table 101. GPDMA1 channel with peripheral early termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
Table 102. Programmed GPDMA1 request with peripheral early termination . . . . . . . . . . . . . . . . . . 932
Table 103. Programmed GPDMA1 trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
Table 104. Programmed GPDMA source/destination burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
Table 105. Programmed data handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960
Table 106. Effect of low-power modes on GPDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
Table 107. GPDMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
Table 108. GPDMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
Table 109. Neural-ART 14 NPU configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006
Table 110. Neural-ART 14 NPU signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008
Table 111. Activation functions example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014
Table 112. Neural-ART 14 functional units memory base addresses. . . . . . . . . . . . . . . . . . . . . . . . 1021
Table 113. DMA2D internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
Table 114. DMA2D trigger interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
Table 115. Supported color mode in input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
Table 116. Data order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
Table 117. Alpha mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
Table 118. Supported CLUT color mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
Table 119. CLUT data order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
Table 120. Supported color mode in output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
Table 121. Data order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
Table 122. Standard data order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
Table 123. Output FIFO byte reordering steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
Table 124. MCU order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
Table 125. DMA2D interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
Table 126. DMA2D register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
Table 127. GFXMMU internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061
Table 128. GFXMMU interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
Table 129. GFXMMU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
Table 130. GFXTIM input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
Table 131. GFXTIM internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
Table 132. GFXTIM trigger interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
Table 133. Graphic timer interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
Table 134. GFXTIM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108
Table 135. STM32N6x7xx vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111
Table 136. EXTI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120
Table 137. EXTI signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120
Table 138. EVG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
Table 139. EXTI line connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
Table 140. EXTI event input configurations and register control . . . . . . . . . . . . . . . . . . . . . . . . . . . 1124
Table 141. Masking functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126
Table 142. Register protection overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127
Table 143. EXTI register map sections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
Table 144. EXTI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1160
Table 145. CRC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164
Table 146. CRC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169
Table 147. FMC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171
Table 148. FMC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173
Table 149. FMC memory regions (default mapping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175
Table 150. FMC memory region remap using BMAP[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175
Table 151. NOR/PSRAM subregion selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1176

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Table 152. NOR/PSRAM External memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1176

Table 153. NAND access memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1176
Table 154. SDRAM device selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177
Table 155. SDRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177
Table 156. SDRAM address mapping with 8-bit data bus width. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178
Table 157. SDRAM address mapping with 16-bit data bus width. . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
Table 158. SDRAM address mapping with 32-bit data bus width. . . . . . . . . . . . . . . . . . . . . . . . . . . 1179
Table 159. Programmable NOR/PSRAM access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1181
Table 160. Non-multiplexed I/O NOR flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182
Table 161. 16-bit multiplexed I/O NOR flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182
Table 162. Non-multiplexed I/Os PSRAM/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183
Table 163. 16-bit multiplexed I/O PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183
Table 164. NOR flash/PSRAM: Example of supported memories and transactions . . . . . . . . . . . . 1184
Table 165. FMC_BCRx bitfields (mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1188
Table 166. FMC_BTRx bitfields (mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1188
Table 167. FMC_BCRx bitfields (mode A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1190
Table 168. FMC_BTRx bitfields (mode A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191
Table 169. FMC_BWTRx bitfields (mode A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191
Table 170. FMC_BCRx bitfields (mode 2/B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193
Table 171. FMC_BTRx bitfields (mode 2/B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
Table 172. FMC_BWTRx bitfields (mode 2/B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
Table 173. FMC_BCRx bitfields (mode C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196
Table 174. FMC_BTRx bitfields (mode C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196
Table 175. FMC_BWTRx bitfields (mode C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197
Table 176. FMC_BCRx bitfields (mode D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198
Table 177. FMC_BTRx bitfields (mode D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199
Table 178. FMC_BWTRx bitfields (mode D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199
Table 179. FMC_BCRx bitfields (muxed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
Table 180. FMC_BTRx bitfields (muxed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1202
Table 181. FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . . . . . . . . . . . . . . . . . . 1207
Table 182. FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . . . . . . . . . . . . . . . . . . 1208
Table 183. FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . . . . . . . . . . . . . . . . . . 1209
Table 184. FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . . . . . . . . . . . . . . . . . . 1210
Table 185. Programmable NAND flash access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220
Table 186. 8-bit NAND flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220
Table 187. 16-bit NAND flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1221
Table 188. Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1221
Table 189. Number of ECC parity bytes per sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226
Table 190. FMC NAND controller Interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235
Table 191. HPR relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1241
Table 192. ECC result relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242
Table 193. SDRAM signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1260
Table 194. FMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277
Table 195. XSPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1283
Table 196. XSPI input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1288
Table 197. XSPI internal signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1288
Table 198. Command/address phase description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299
Table 199. OctaRAM command address bit assignment
(based on 64 Mb OctaRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1311
Table 200. Address alignment cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1319
Table 201. XSPI interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1321
Table 202. XSPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1347

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Table 203. XSPIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351

Table 204. XSPIM input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1352
Table 205. Use cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1354
Table 206. XSPIM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364
Table 207. SDMMC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365
Table 208. SDMMC operation modes SD and SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368
Table 209. SDMMC operation modes e•MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368
Table 210. SDMMC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1369
Table 211. SDMMC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1370
Table 212. SDMMC Command and data phase selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371
Table 213. Command token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1377
Table 214. Short response with CRC token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1378
Table 215. Short response without CRC token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1378
Table 216. Long response with CRC token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1378
Table 217. Specific Commands overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1379
Table 218. Command path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1380
Table 219. Command path error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1380
Table 220. Data token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388
Table 221. Data path status flags and clear bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388
Table 222. Data path error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1390
Table 223. Data FIFO access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1391
Table 224. Transmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1392
Table 225. Receive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394
Table 226. AHB and SDMMC_CK clock frequency relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1398
Table 227. SDIO special operation control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399
Table 228. 4-bit mode Start, interrupt, and CRC-status Signaling detection . . . . . . . . . . . . . . . . . . 1403
Table 229. CMD12 use cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1408
Table 230. Data block gap hardware flow control behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1420
Table 231. Hardware flow control selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1420
Table 232. SDMMC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424
Table 233. Response type and SDMMC_RESPxR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1431
Table 234. SDMMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447
Table 235. STM32N6x7xx features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1450
Table 236. DLYB functional signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1452
Table 237. DLYB interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1453
Table 238. DLYB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457
Table 239. ADC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1461
Table 240. ADC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1463
Table 241. ADC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1463
Table 242. ADC1/2 interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1463
Table 243. Configuring the trigger polarity for regular external triggers . . . . . . . . . . . . . . . . . . . . . . 1481
Table 244. Configuring the trigger polarity for injected external triggers . . . . . . . . . . . . . . . . . . . . . 1482
Table 245. TSAR timings depending on resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1486
Table 246. Offset computation versus data resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490
Table 247. 12-bit data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492
Table 248. Numerical examples for 32-bit or 16-bit format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1493
Table 249. Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1503
Table 250. Analog watchdog 1, 2, 3 comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504
Table 251. Maximum output results versus N and M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1508
Table 252. Oversampler operating mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1512
Table 253. DELAY bits versus ADC resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1518
Table 254. ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1532

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RM0486 List of tables

Table 255. ADC register map and reset values for each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1567
Table 256. ADC register map and reset values (master and slave ADC
common registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1570
Table 257. DTS internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1572
Table 258. DTS interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1573
Table 259. SDA slave registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1578
Table 260. SDA TS control register (SDATS_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1578
Table 261. SDA TS configuration register (SDATS_CFGR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1579
Table 262. SDA TS data register (SDATS_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1580
Table 263. SDA TS timer register (SDATS_TIMERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1581
Table 264. Output resolution configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1586
Table 265. DTS interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1587
Table 266. DTS register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588
Table 267. PVT common register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1608
Table 268. PVT IRQ register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1608
Table 269. DTS TSC clock synthesizer register map and reset values . . . . . . . . . . . . . . . . . . . . . . 1609
Table 270. DTS TS individual register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1611
Table 271. VREFBUF typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613
Table 272. VREF buffer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1614
Table 273. VREFBUF register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617
Table 274. MDF features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1619
Table 275. MDF external pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1622
Table 276. MDF internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1622
Table 277. MDF trigger connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1622
Table 278. MDF break connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1623
Table 279. Control of the common clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1630
Table 280. Clock constraints with respect to the incoming stream . . . . . . . . . . . . . . . . . . . . . . . . . . 1631
Table 281. Data size according to CIC order and CIC decimation values . . . . . . . . . . . . . . . . . . . . 1638
Table 282. Maximum decimation ratio versus order and input data size . . . . . . . . . . . . . . . . . . . . . 1639
Table 283. Possible gain values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640
Table 284. Recommended maximum gain values versus CIC decimation ratios. . . . . . . . . . . . . . . 1642
Table 285. Most common microphone settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1642
Table 286. HPF 3 dB cut-off frequencies examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1644
Table 287. Register protection summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1665
Table 288. Effect of low-power modes on MDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666
Table 289. MDF interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1668
Table 290. Examples of MDF settings for microphone capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669
Table 291. Programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669
Table 292. Output signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1676
Table 293. MDF register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700
Table 294. ADF features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1703
Table 295. ADF external pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704
Table 296. ADF internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704
Table 297. ADF trigger connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705
Table 298. Control of the common clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1711
Table 299. Clock constraints with respect to the incoming stream . . . . . . . . . . . . . . . . . . . . . . . . . . 1712
Table 300. Data size according to CIC order and CIC decimation values . . . . . . . . . . . . . . . . . . . . 1717
Table 301. Possible gain values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1718
Table 302. Recommended maximum gain values
versus CIC decimation ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1720
Table 303. Most common microphone settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1721
Table 304. HPF 3 dB cut-off frequency examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1723

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Table 305. ANSLP values versus FRSIZE and sampling rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1736
Table 306. Threshold values according SNTHR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1737
Table 307. Register protection summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1743
Table 308. Effect of low-power modes on ADF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1744
Table 309. ADF interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1745
Table 310. Examples of ADF settings for microphone capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1746
Table 311. Programming sequence (CIC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1747
Table 312. Programming sequence (CIC5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1748
Table 313. Output signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1753
Table 314. ADF register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1774
Table 315. Camera subsystem RIF peripheral ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1783
Table 316. DCMI input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1789
Table 317. DCMI internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1789
Table 318. Positioning of captured data bytes in 32-bit words (8-bit width) . . . . . . . . . . . . . . . . . . . 1791
Table 319. Positioning of captured data bytes in 32-bit words (10-bit width) . . . . . . . . . . . . . . . . . . 1791
Table 320. Positioning of captured data bytes in 32-bit words (12-bit width) . . . . . . . . . . . . . . . . . . 1791
Table 321. Positioning of captured data bytes in 32-bit words (14-bit width) . . . . . . . . . . . . . . . . . . 1792
Table 322. Data storage in monochrome progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . 1797
Table 323. Data storage in RGB progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1798
Table 324. Data storage in YCbCr progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1798
Table 325. Data storage in YCbCr progressive video format - Y extraction mode . . . . . . . . . . . . . . 1798
Table 326. DCMI interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1799
Table 327. DCMI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1809
Table 328. Available pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1810
Table 329. Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1811
Table 330. DCMIPP input/output pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1816
Table 331. DCMIPP input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1816
Table 332. DCMIPP clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1816
Table 333. DCMIPP resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1817
Table 334. Parallel interface maximum resolution (80 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1818
Table 335. Supported pixel formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1820
Table 336. DCMIPP_PRCR bit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1824
Table 337. DCMIPP_PRESCR and DCMIPP_PRESUR bit function . . . . . . . . . . . . . . . . . . . . . . . . 1825
Table 338. DCMIPP_PxFCTCR bit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1832
Table 339. DCMIPP_P0PPCR bit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1835
Table 340. DCMIPP_P0DCCNTR and DCMIPP_P0DCLMTR bit function. . . . . . . . . . . . . . . . . . . . 1838
Table 341. DCMIPP_P1SRCR bit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1841
Table 342. DCMIPP_P1BPRCR and DCMIPP_P1BPRSR bit function . . . . . . . . . . . . . . . . . . . . . . 1841
Table 343. DCMIPP_P1DECR bit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1843
Table 344. DCMIPP_P1BLCCR bit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1843
Table 345. DCMIPP_P1EXCR1 and DCMIPP_P1EXCR2 bit function. . . . . . . . . . . . . . . . . . . . . . . 1844
Table 346. DCMIPP_P1DMCR bit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1846
Table 347. DCMIPP_PxCCyy (yy = R0, R1, G0, G1, B0, B1) bit function . . . . . . . . . . . . . . . . . . . . 1847
Table 348. Color conversion: examples of coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1848
Table 349. DCMIPP_P1CTCR1,2,3 bit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1850
Table 350. DCMIPP_P1STyCR (y = 1, 2, 3), DCMIPP_P1STySR (y = 1, 2, 3),
DCMIPP_P1STSTR and DCMIPP_P1STSZR bit function . . . . . . . . . . . . . . . . . . . . . . . 1852
Table 351. Statistics extraction: collected data vs. modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1853
Table 352. DCMIPP_PxCRSTR and DCMIPP_PxCRSZR bit function . . . . . . . . . . . . . . . . . . . . . . 1857
Table 353. DCMIPP_PxDCCR bit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1858
Table 354. DCMIPP_PxDSCR, DCMIPP_PxDSRTIOR, DCMIPP_PxDSSZR. . . . . . . . . . . . . . . . . 1859
Table 355. DCMIPP_PxPPCR bit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1862

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RM0486 List of tables

Table 356. Parallel interface input pixel formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1877

Table 357. Correspondence between index and DCMIPP_PRCR register values. . . . . . . . . . . . . . 1878
Table 358. Parallel interface input pixel formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1879
Table 359. Pixel pipe output pixel format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1879
Table 360. Dump pipe OUTPUT pixel formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1881
Table 361. Shadow and physical registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1888
Table 362. DCMIPP low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1890
Table 363. DCMIPP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1893
Table 364. Event connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1894
Table 365. DCMIPP registers organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1895
Table 366. DCMIPP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1994
Table 367. Glossary of terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2009
Table 368. Effect of low-power modes on CSI-2 Host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 2028
Table 369. List of errors detected by the CSI-2 Host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2028
Table 370. List of events that trigger an interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2029
Table 371. CSI-2 Host and PHY register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 2063
Table 372. PSSI input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2069
Table 373. PSSI internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2069
Table 374. Positioning of captured data bytes in 32-bit words (8-bit width) . . . . . . . . . . . . . . . . . . . 2070
Table 375. Positioning of captured data bytes in 32-bit words (16-bit width) . . . . . . . . . . . . . . . . . . 2071
Table 376. PSSI interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2074
Table 377. PSSI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2080
Table 378. Display subsystem RIF peripheral ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2085
Table 379. LTDC pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2088
Table 380. LTDC trigger interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2089
Table 381. Clock domain for each register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2089
Table 382. LTDC register access and updated durations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2091
Table 383. Pixel data mapping versus color format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2094
Table 384. LTDC hardware triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2109
Table 385. LTDC interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2111
Table 386. LTDC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2142
Table 387. GPU2D internal input/output signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2148
Table 388. GPU2D trigger connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2149
Table 389. VENC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2244
Table 390. JPEG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2259
Table 391. JPEG trigger connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2260
Table 392. JPEG codec interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2265
Table 393. JPEG codec register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2278
Table 394. RNG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2281
Table 395. RNG interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2289
Table 396. RNG initialization times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2290
Table 397. RNG configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2290
Table 398. Configuration selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2291
Table 399. RNG register map and reset map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2296
Table 400. CRYP versus SAES features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2298
Table 401. SAES internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2299
Table 402. SAES approved symmetric key functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2300
Table 403. Counter mode initialization vector definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2310
Table 404. Initialization of IV registers in GCM mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2313
Table 405. GCM last block definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2313
Table 406. Initialization of IV registers in CCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2319
Table 407. AES data swapping example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2328

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Table 408. Key endianness in SAES_KEYRx registers (128/256-bit keys) . . . . . . . . . . . . . . . . . . . 2330

Table 409. IVI bitfield spread over SAES_IVRx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2332
Table 410. SAES interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2334
Table 411. Processing latency for ECB, CBC and CTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2335
Table 412. Processing latency for GCM and CCM (in SAES kernel clock cycles) . . . . . . . . . . . . . . 2335
Table 413. SAES register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2350
Table 414. CRYP versus SAES features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2353
Table 415. CRYP internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2355
Table 416. CRYP approved AES symmetric key functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2355
Table 417. Counter mode initialization vector definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2366
Table 418. GCM mode IVI registers initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2369
Table 419. GCM last block definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2369
Table 420. CCM mode IVI registers initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2376
Table 421. AES data swapping example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2381
Table 422. Key endianness in CRYP_KxR/LR registers (128/192/256-bit keys) . . . . . . . . . . . . . . . 2383
Table 423. Initialization vector endianness in CRYP_IVxR registers (AES) . . . . . . . . . . . . . . . . . . . 2383
Table 424. CRYP interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2385
Table 425. Processing latency for ECB, CBC and CTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2386
Table 426. Processing latency for GCM and CCM (in clock cycles). . . . . . . . . . . . . . . . . . . . . . . . . 2387
Table 427. CRYP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2400
Table 428. HASH internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2403
Table 429. Information on supported hash algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2404
Table 430. Hash processor outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2407
Table 431. Processing time (in clock cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2413
Table 432. HASH interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2414
Table 433. HASH1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2422
Table 434. MCE internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2425
Table 435. MCE block cipher latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2429
Table 436. MCE stream cipher latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2430
Table 437. MCE interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2431
Table 438. MCE register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2443
Table 439. Internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2446
Table 440. PKA integer arithmetic functions list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2447
Table 441. PKA prime field (Fp) elliptic curve functions list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2448
Table 442. Montgomery parameter computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2454
Table 443. Modular addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2455
Table 444. Modular subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2455
Table 445. Montgomery multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2456
Table 446. Modular exponentiation (normal mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2457
Table 447. Modular exponentiation (fast mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2457
Table 448. Modular exponentiation (protected mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2458
Table 449. Modular inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2458
Table 450. Modular reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2459
Table 451. Arithmetic addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2459
Table 452. Arithmetic subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2459
Table 453. Arithmetic multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2460
Table 454. Arithmetic comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2460
Table 455. CRT exponentiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2461
Table 456. Point on elliptic curve Fp check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2462
Table 457. ECC Fp scalar multiplication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2462
Table 458. ECDSA sign - Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2464
Table 459. ECDSA sign - Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2464

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Table 460. Extended ECDSA sign - Extra outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2465

Table 461. ECDSA verification - Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2465
Table 462. ECDSA verification - Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2466
Table 463. ECC complete addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2466
Table 464. ECC double base ladder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2467
Table 465. ECC projective to affine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2468
Table 466. Family of supported curves for ECC operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2469
Table 467. Modular exponentiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2470
Table 468. ECC scalar multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2470
Table 469. ECDSA signature average computation time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2471
Table 470. ECDSA verification average computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2471
Table 471. ECC double base ladder average computation times . . . . . . . . . . . . . . . . . . . . . . . . . . 2471
Table 472. ECC projective to affine average computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . 2471
Table 473. ECC complete addition average computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2471
Table 474. Point on elliptic curve Fp check average computation times . . . . . . . . . . . . . . . . . . . . . 2471
Table 475. Montgomery parameters average computation times. . . . . . . . . . . . . . . . . . . . . . . . . . . 2472
Table 476. PKA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2472
Table 477. PKA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2477
Table 478. TIM input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2480
Table 479. TIM internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2480
Table 480. Interconnect to the tim_ti1 input multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2481
Table 481. Interconnect to the tim_ti2 input multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2481
Table 482. Interconnect to the tim_ti3 input multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2482
Table 483. Interconnect to the tim_ti4 input multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2482
Table 484. Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2482
Table 485. Interconnect to the tim_etr input multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2483
Table 486. Timer break interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2483
Table 487. Timer break2 interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2483
Table 488. System break interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2483
Table 489. CCR and ARR register change dithering pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2516
Table 490. CCR register change dithering pattern in center-aligned PWM mode . . . . . . . . . . . . . . 2517
Table 491. Behavior of timer outputs versus tim_brk/tim_brk2 inputs . . . . . . . . . . . . . . . . . . . . . . . 2529
Table 492. Break protection disarming conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2531
Table 493. Counting direction versus encoder signals (CC1P = CC2P = 0) . . . . . . . . . . . . . . . . . . 2539
Table 494. Counting direction versus encoder signals and polarity settings . . . . . . . . . . . . . . . . . . 2543
Table 495. DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2565
Table 496. Effect of low-power modes on TIM1/TIM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2566
Table 497. Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2566
Table 498. Output control bits for complementary tim_ocx and tim_ocxn channels
with break feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2593
Table 499. TIMx register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2616
Table 500. STM32N6x7xx general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2620
Table 501. TIM input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2622
Table 502. TIM internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2622
Table 503. Interconnect to the tim_ti1 input multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2623
Table 504. Interconnect to the tim_ti2 input multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2623
Table 505. Interconnect to the tim_ti3 input multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2623
Table 506. Interconnect to the tim_ti4 input multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2624
Table 507. TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2624
Table 508. Interconnect to the tim_etr input multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2624
Table 509. CCR and ARR register change dithering pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2656
Table 510. CCR register change dithering pattern in center-aligned PWM mode . . . . . . . . . . . . . . 2657

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List of tables RM0486

Table 511. Counting direction versus encoder signals(CC1P = CC2P = 0) . . . . . . . . . . . . . . . . . . . 2666

Table 512. Counting direction versus encoder signals and polarity settings . . . . . . . . . . . . . . . . . . 2671
Table 513. DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2697
Table 514. Effect of low-power modes on TIM2/TIM3/TIM4/TIM5 . . . . . . . . . . . . . . . . . . . . . . . . . . 2697
Table 515. Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2698
Table 516. Output control bit for standard tim_ocx channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2719
Table 517. TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 2731
Table 518. TIM internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2735
Table 519. TIMx_ARR register change dithering pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2744
Table 520. DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2746
Table 521. Effect of low-power modes on TIM6/TIM7/TIM18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2746
Table 522. Interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2746
Table 523. TIMx register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2753
Table 524. TIM input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2757
Table 525. TIM internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2757
Table 526. Interconnect to the tim_ti1 input multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2758
Table 527. Interconnect to the tim_ti2 input multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2758
Table 528. TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2758
Table 529. CCR and ARR register change dithering pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2776
Table 530. Effect of low-power modes on TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 . . . . . . . . . . . . 2786
Table 531. Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2786
Table 532. Output control bit for standard tim_ocx channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2799
Table 533. TIMx register map and reset values (x = 9, 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2803
Table 534. Output control bit for standard tim_ocx channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2812
Table 535. TIM10/TIM11/TIM13/TIM14 register map and reset values . . . . . . . . . . . . . . . . . . . . . . 2815
Table 536. TIM input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2820
Table 537. TIM internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2821
Table 538. Interconnect to the tim_ti1 input multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2822
Table 539. Interconnect to the tim_ti2 input multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2822
Table 540. TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2822
Table 541. Timer break interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2823
Table 542. System break interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2823
Table 543. CCR and ARR register change dithering pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2843
Table 544. Break protection disarming conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2852
Table 545. DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2865
Table 546. Effect of low-power modes on TIM15/TIM16/TIM17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2865
Table 547. Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2866
Table 548. Output control bits for complementary tim_ocx and tim_ocxn channels with break
feature (TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2883
Table 549. TIM15 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2896
Table 550. Output control bits for complementary tim_oc1 and tim_oc1n channels with break
feature (TIM16/TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2909
Table 551. TIM16/TIM17 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2923
Table 552. STM32N6x7xx LPTIM features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2926
Table 553. LPTIM1/2/3 input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2928
Table 554. LPTIM4/5 input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2928
Table 555. LPTIM1/2/3 internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2929
Table 556. LPTIM4/5 internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2929
Table 557. LPTIM1/2/3/4/5 external trigger connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2930
Table 558. LPTIM1/2/3 input 1 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2930
Table 559. LPTIM1/2/3 input 2 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2930
Table 560. LPTIM1/2/3 input capture 1 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2930

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Table 561. LPTIM1 input capture 2 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2931

Table 562. LPTIM2 input capture 2 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2931
Table 563. LPTIM3 input capture 2 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2931
Table 564. Prescaler division ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2933
Table 565. Encoder counting scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2940
Table 566. Input capture Glitch filter latency (in counter step unit). . . . . . . . . . . . . . . . . . . . . . . . . . 2944
Table 567. Effect of low-power modes on the LPTIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2948
Table 568. Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2949
Table 569. LPTIM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2973
Table 570. IWDG features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2976
Table 571. IWDG delays versus actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2977
Table 572. IWDG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2978
Table 573. Effect of low power modes on IWDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2983
Table 574. IWDG interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2985
Table 575. IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2991
Table 576. WWDG features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2992
Table 577. WWDG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2993
Table 578. WWDG interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2996
Table 579. WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2998
Table 580. RTC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3002
Table 581. RTC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3002
Table 582. RTC interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3003
Table 583. RTC pin PC13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3003
Table 584. RTC_OUT mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3005
Table 585. Effect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3020
Table 586. RTC pins functionality over modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3021
Table 587. Nonsecure interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3021
Table 588. Secure interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3022
Table 589. RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3052
Table 590. TAMP input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3057
Table 591. TAMP internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3057
Table 592. TAMP interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3058
Table 593. Device resource x tamper protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3063
Table 594. Active tamper output change period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3066
Table 595. Minimum ATPER value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3068
Table 596. Active tamper filtered pulse duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3069
Table 597. Effect of low-power modes on TAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3070
Table 598. TAMP pins functionality over modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3070
Table 599. Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3071
Table 600. TAMP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3099
Table 601. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3102
Table 602. I2C input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3103
Table 603. I2C internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3104
Table 604. Comparison of analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3106
Table 605. I²C-bus and SMBus specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . 3108
Table 606. I2C configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3112
Table 607. I²C-bus and SMBus specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3123
Table 608. Timing settings for fI2CCLK of 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3133
Table 609. Timing settings for fI2CCLK of 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3133
Table 610. SMBus timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3135
Table 611. SMBus with PEC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3137
Table 612. TIMEOUTA[11:0] for maximum tTIMEOUT of 25 ms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3138

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Table 613. TIMEOUTB[11:0] for maximum tLOW:SEXT and tLOW:MEXT of 8 ms . . . . . . . . . . . . . . . . 3138

Table 614. TIMEOUTA[11:0] for maximum tIDLE of 50 µs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3138
Table 615. Effect of low-power modes to I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3148
Table 616. I2C interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3148
Table 617. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3164
Table 618. I3C instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3167
Table 619. I3C wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3167
Table 620. I3C FIFOs implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3167
Table 621. I3C interrupt(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3167
Table 622. I3C peripheral controller/target features versus MIPI v1.1 . . . . . . . . . . . . . . . . . . . . . . . 3168
Table 623. I3C input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3169
Table 624. I3C internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3169
Table 625. I3C register usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3181
Table 626. I3C registers/fields usage versus controller state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3182
Table 627. I3C registers/fields usage versus target state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3185
Table 628. List of supported I3C CCCs, as controller/target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3188
Table 629. I3C controller error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3220
Table 630. I3C target error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3222
Table 631. Effect of low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3226
Table 632. I3C interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3227
Table 633. I3C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3272
Table 634. Instance implementation on STM32N6x7xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3276
Table 635. USART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3277
Table 636. USART/UART input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3279
Table 637. USART internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3280
Table 638. Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3292
Table 639. Tolerance of the USART receiver when BRR [3:0] = 0000. . . . . . . . . . . . . . . . . . . . . . . 3296
Table 640. Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . . . . . . . . . 3296
Table 641. USART frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3301
Table 642. Effect of low-power modes on the USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3324
Table 643. USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3325
Table 644. USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3363
Table 645. Instance implementation on STM32N6x7xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3366
Table 646. USART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3366
Table 647. LPUART input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3369
Table 648. LPUART internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3369
Table 649. Error calculation for programmed baud rates at lpuart_ker_ck_pres= 32.768 kHz . . . . 3380
Table 650. Tolerance of the LPUART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3381
Table 652. Effect of low-power modes on the LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3393
Table 653. LPUART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3394
Table 654. LPUART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3420
Table 655. SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3423
Table 656. SPI/I2S input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3425
Table 657. SPI internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3426
Table 658. Effect of low-power modes on the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3452
Table 659. SPI wake-up and interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3453
Table 660. Bitfields usable in PCM/I2S mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3455
Table 661. WS and CK level before SPI/I2S is enabled when AFCNTR = 1 . . . . . . . . . . . . . . . . . . 3464
Table 662. Serial data line swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3464
Table 663. CLKGEN programming examples for usual I2S frequencies . . . . . . . . . . . . . . . . . . . . . 3468
Table 664. I2S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3477
Table 665. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3494

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Table 666. SAI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3497

Table 667. SAI internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3499
Table 668. SAI input/output pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3499
Table 669. External synchronization selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3502
Table 670. MCLK_x activation conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3507
Table 671. Clock generator programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3510
Table 672. SAI_A configuration for TDM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3517
Table 673. TDM frame configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3519
Table 674. SOPD pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3523
Table 675. Parity bit calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3523
Table 676. Audio sampling frequency versus symbol rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3524
Table 677. SAI interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3533
Table 678. SAI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3561
Table 679. SPDIFRX internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3564
Table 680. SPDIFRX pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3564
Table 681. Transition sequence for preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3570
Table 682. Minimum spdifrx_ker_ck frequency versus audio sampling rate . . . . . . . . . . . . . . . . . . 3580
Table 683. Conditions of spdifrx_symb_ck generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3581
Table 684. Bit field property versus SPDIFRX state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3584
Table 685. SPDIFRX interface register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3596
Table 686. MDIOS input/output signals connected to package pins or balls . . . . . . . . . . . . . . . . . . 3598
Table 687. MDIOS internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3598
Table 688. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3603
Table 689. MDIOS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3608
Table 690. CAN subsystem I/O signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3610
Table 691. CAN subsystem I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3611
Table 692. CAN triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3611
Table 693. Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3613
Table 694. DLC coding in FDCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3618
Table 695. Example of filter configuration for Rx buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3631
Table 696. Example of filter configuration for Debug messages . . . . . . . . . . . . . . . . . . . . . . . . . . . 3632
Table 697. Possible configurations for frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3632
Table 698. Tx buffer/FIFO - Queue element size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3633
Table 699. First byte of level 1 reference message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3643
Table 700. First four bytes of level 2 reference message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3644
Table 701. First four bytes of level 0 reference message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3644
Table 702. TUR configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3645
Table 703. System matrix, Node A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3650
Table 704. Trigger list, Node A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3651
Table 705. Number of data bytes transmitted with a reference message. . . . . . . . . . . . . . . . . . . . . 3658
Table 706. Rx buffer and FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3665
Table 707. Rx buffer and FIFO element description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3665
Table 708. Tx buffer and FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3667
Table 709. Tx buffer element description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3667
Table 710. Tx Event FIFO element. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3669
Table 711. Tx Event FIFO element description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3669
Table 712. Standard message ID filter element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3670
Table 713. Standard message ID filter element field description . . . . . . . . . . . . . . . . . . . . . . . . . . . 3671
Table 714. Extended message ID filter element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3672
Table 715. Extended message ID filter element field description . . . . . . . . . . . . . . . . . . . . . . . . . . . 3672
Table 716. Trigger memory element. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3673
Table 717. Trigger memory element description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3673

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Table 718. FDCAN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3711

Table 719. FDCAN TT register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3733
Table 720. CCU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3739
Table 721. USB2 OTG high-speed Port 1 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3742
Table 722. USB2 OTG high-speed Port 1 internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3743
Table 723. USB2 OTG high-speed Port 1 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3744
Table 724. USB2 OTG high-speed Port 1 wake-up events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3744
Table 725. USB2 OTG high-speed Port 2 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3746
Table 726. USB2 OTG high-speed Port 2 internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3746
Table 727. USB2 OTG high-speed Port 2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3748
Table 728. USB2 OTG high-speed Port 2 wake-up events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3748
Table 729. USB Type-C and power delivery pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3751
Table 730. USB Type-C and power delivery internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3751
Table 731. USB Type-C and power delivery interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3752
Table 732. USB Type-C and power delivery events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3752
Table 733. OTG speeds supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3754
Table 734. OTG implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3756
Table 735. OTG input/output pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3757
Table 736. OTG input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3758
Table 737. Compatibility of STM32 low power modes with the OTG . . . . . . . . . . . . . . . . . . . . . . . . 3768
Table 738. Core global control and status registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3776
Table 739. Host-mode control and status registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3777
Table 740. Device-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3778
Table 741. Data FIFO (DFIFO) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3780
Table 742. Power and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 3781
Table 743. TRDT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3787
Table 744. Minimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3830
Table 745. OTG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3856
Table 746. USBPHYC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3921
Table 747. USBPHYC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3929
Table 748. UCPD implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3931
Table 749. UCPD signals on pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3932
Table 750. UCPD internal signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3932
Table 751. 4b5b symbol encoding table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3934
Table 752. Ordered sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3936
Table 753. Validation of ordered sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3936
Table 754. Data size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3936
Table 755. Coding for ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx . . . . . . . 3945
Table 756. Type-C sequence (source: 3A); cable/sink connected (Rd on CC1; Ra on CC2) . . . . . 3946
Table 757. Effect of low power modes on the UCPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3948
Table 758. UCPD interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3949
Table 759. UCPD register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3964
Table 760. Ethernet peripheral pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3971
Table 761. Ethernet internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3972
Table 762. Fixed priority scheme for DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3986
Table 763. Routing DA/SA failed packets to Rx queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3990
Table 764. Routing DA/SA pass but VLAN filter fail packets to Rx queue . . . . . . . . . . . . . . . . . . . . 3991
Table 765. Priority routing of filter pass packets when OMCBCQ = 0 . . . . . . . . . . . . . . . . . . . . . . . 3991
Table 766. Priority routing of filter pass packets when OMCBCQ = 1 . . . . . . . . . . . . . . . . . . . . . . . 3991
Table 767. Weight for DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3994
Table 768. Example of credit value per transmit cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3995
Table 769. Double VLAN processing features in Tx path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3998

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Table 770. Double VLAN processing in Rx path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3999

Table 771. VLAN insertion or replacement based on VLTI bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4000
Table 772. Destination address filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4004
Table 773. Source address filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4005
Table 774. VLAN match status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4006
Table 775. OTS and ITS bit values with at least one perfect filter enabled . . . . . . . . . . . . . . . . . . . 4009
Table 776. OTS and ITS bit values with only VLAN Hash filter enabled . . . . . . . . . . . . . . . . . . . . . 4010
Table 777. Rx Queue routing table for Unicast-tagged packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4011
Table 778. Ordinary clock: PTP messages for snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4014
Table 779. End-to-end transparent clock: PTP messages for snapshot . . . . . . . . . . . . . . . . . . . . . 4015
Table 780. Peer-to-peer transparent clock: PTP messages for snapshot . . . . . . . . . . . . . . . . . . . . 4016
Table 781. Egress and ingress latency for PHY interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4020
Table 782. Minimum PTP clock frequency example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4020
Table 783. Message format defined in IEEE 1588-2008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4021
Table 784. Message format defined in IEEE 1588-2008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4022
Table 785. IPv6-UDP PTP packet fields required for control and status . . . . . . . . . . . . . . . . . . . . . 4023
Table 786. Ethernet PTP packet fields required for control and status . . . . . . . . . . . . . . . . . . . . . . 4024
Table 787. Timestamp Snapshot Dependency on ETH_MACTSCR bits . . . . . . . . . . . . . . . . . . . . . 4025
Table 788. PTP message generation criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4031
Table 789. Common PTP message header fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4033
Table 790. MAC Transmit PTP mode and one-step timestamping operation. . . . . . . . . . . . . . . . . . 4036
Table 791. External memory used for holding the two gate-control lists . . . . . . . . . . . . . . . . . . . . . 4041
Table 792. GCL and associated registers - BTR and CTR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4045
Table 793. GCL and associated registers - BTR and CTR, execution time > CycleTime . . . . . . . . 4046
Table 794. GCL and Associated Registers - BTR and CTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4048
Table 795. Extending to New List By Truncating the Current List . . . . . . . . . . . . . . . . . . . . . . . . . . 4049
Table 796. Switching to New List By Extending the Current List . . . . . . . . . . . . . . . . . . . . . . . . . . . 4050
Table 797. Gate Control List When FPE is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4052
Table 798. Gate Control List When FPE is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4052
Table 799. Valid SMD Values of mPacket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4055
Table 800. Valid frag_count values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4055
Table 801. Current and Previous SMD Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4056
Table 802. Current and previous SMD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4056
Table 803. Preemption Control Values on MRI Interface for Various Frame Types. . . . . . . . . . . . . 4060
Table 804. MMC Counters and Associated Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4061
Table 805. Transmit checksum offload engine functions for different packet types . . . . . . . . . . . . . 4070
Table 806. Receive checksum offload engine functions for different packet types . . . . . . . . . . . . . 4073
Table 807. TSO: TCP and IP header fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4077
Table 808. Pause packet fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4082
Table 809. Tx MAC flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4083
Table 810. Rx MAC flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4084
Table 811. Size of the maximum receive packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4086
Table 812. MCD clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4089
Table 813. MDIO Clause 45 frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4090
Table 814. MDIO Clause 22 frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4091
Table 815. Remote wake-up packet filter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4104
Table 816. Description of the remote wake-up filter fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4105
Table 817. Remote wake-up packet and PMT interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . 4106
Table 818. Transfer complete interrupt behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4115
Table 819. TDES0 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4146
Table 820. TDES1 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4147
Table 821. TDES2 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4147

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Table 822. TDES3 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4148

Table 823. TDES0 normal descriptor (write-back format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4151
Table 824. TDES1 normal descriptor (write-back format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4151
Table 825. TDES2 normal descriptor (write-back format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4152
Table 826. TDES3 normal descriptor (write-back format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4152
Table 827. TDES0 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4156
Table 828. TDES1 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4156
Table 829. TDES2 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4157
Table 830. TDES3 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4157
Table 831. RDES0 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4160
Table 832. RDES1 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4160
Table 833. RDES2 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4160
Table 834. RDES3 normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4161
Table 835. RDES0 normal descriptor (write-back format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4162
Table 836. RDES1 normal descriptor (write-back format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4163
Table 837. RDES2 normal descriptor (write-back format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4165
Table 838. RDES3 normal descriptor (write-back format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4167
Table 839. RDES0 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4170
Table 840. RDES1 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4171
Table 841. RDES2 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4171
Table 842. RDES3 context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4171
Table 843. Enhanced normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4172
Table 844. ETH_DMA common register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4202
Table 845. ETH_DMA_CH0 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4203
Table 846. ETH_DMA_CH1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4205
Table 847. ETH_MTL register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4235
Table 848. Giant Packet Status based on S2KP and JE Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4244
Table 849. Packet Length based on the CST and ACS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4244
Table 850. Ethernet MAC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4354
Table 851. Muxing of HDP signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4368
Table 852. HDP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4372
Table 853. SWJ-DP pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4377
Table 854. Trace port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4377
Table 855. Serial-wire trace port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4377
Table 856. Trigger pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4378
Table 857. Authentication signal initial states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4381
Table 858. JTAG-DP data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4385
Table 859. Packet request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4386
Table 860. ACK response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4387
Table 861. Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4387
Table 862. Debug port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4388
Table 863. Debug port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4395
Table 864. AP1-2 authentication behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4397
Table 865. AP0 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4401
Table 866. AP1 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4405
Table 867. AP2 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4410
Table 868. System ROM table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4411
Table 869. MCU ROM table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4411
Table 870. System ROM table register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4416
Table 871. Processor ROM table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4417
Table 872. Processor ROM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4422
Table 873. DWT register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4435

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Table 874. PMU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4450

Table 875. ITM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4460
Table 876. BPU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4467
Table 877. ETM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4492
Table 878. Trace subsystem ROM table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4496
Table 879. Trace subsystem ROM table register map and reset values . . . . . . . . . . . . . . . . . . . . . 4502
Table 880. TSGEN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4509
Table 881. Trace and debug subsystem CTI_0 inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4512
Table 882. Trace and debug subsystem CTI_0 outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4512
Table 883. Trace and debug subsystem CTI_1 inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4512
Table 884. Trace and debug subsystem CTI_1 outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4513
Table 885. Cortex-M55 CTI inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4513
Table 886. Cortex-M55 CTI outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4513
Table 887. CTI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4527
Table 888. CSTF register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4537
Table 889. ETF register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4556
Table 890. ETR scatter-gather page format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4561
Table 891. ETR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4580
Table 892. TPIU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4597
Table 893. ETR replicator allocation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4599
Table 894. Replicator register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4608
Table 895. SWO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4618
Table 896. STM extended stimulus port memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4620
Table 897. STM trace packet ID mapping to AXI masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4621
Table 898. Hardware event mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4622
Table 899. STM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4645
Table 900. DBGMCU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4658
Table 901. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4667

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List of figures

Figure 1. Interconnect top view - STM32N6x7 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 2. Key management principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 3. BSEC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 4. BSEC fuse mapping overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 5. RISAF block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 6. RISAF region programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Figure 7. RISAF region on-the-fly resizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 8. IAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Figure 9. FLEXMEM versus retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Figure 10. ICACHE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Figure 11. ICACHE TAG and data memories functional view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Figure 12. CACHEAXI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Figure 13. CACHEAXI TAG and data memories functional view . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Figure 14. Power control block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Figure 15. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Figure 16. System supply configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Figure 17. Device startup (VCORE supplied directly from SMPS step-down converter) . . . . . . . . . . 352
Figure 18. Device startup (VCORE supplied from an external regulator) . . . . . . . . . . . . . . . . . . . . . 353
Figure 19. Backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Figure 20. Retention domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Figure 21. POR/PDR waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Figure 22. BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Figure 23. Vdda18pmu_ok reset threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Figure 24. Vddcore_ok reset thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Figure 25. VDDCORE monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Figure 26. PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Figure 27. V08CAP thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
Figure 28. Temperature thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Figure 29. VCORE voltage scaling versus system power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Figure 30. Dynamic voltage scaling in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Figure 31. Dynamic voltage scaling behavior in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Figure 32. Dynamic Voltage Scaling from Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Figure 33. RCC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Figure 34. Simplified reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Figure 35. NRST reset pulse control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Figure 36. Boot sequences versus system states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Figure 37. Top-level clock tree. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Figure 38. HSE clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Figure 39. HSE clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Figure 40. LSE clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Figure 41. HSI calibration flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Figure 42. MSI calibration flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Figure 43. PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Figure 44. Spread spectrum modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
Figure 45. Core and bus clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Figure 46. Key signals controlling low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Figure 47. Clock distribution for the NPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
Figure 48. Clock distribution for PSSI, CSI, and DCMIPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

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Figure 49. Clock distribution for GPU, ICACHE, and GFXMMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
Figure 50. Clock distribution for LTDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
Figure 51. Clock distribution for VENC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
Figure 52. Clock distribution for OTG1, OTG2, and UCPD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Figure 53. Clock distribution for ETH1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
Figure 54. Clock management for ETH1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
Figure 55. Clock distribution for MDIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
Figure 56. Clock distribution for FMC and MCE4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
Figure 57. Clock distribution for XSPIs and MCE1/2/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
Figure 58. Clock distribution for SDMMCx and companions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
Figure 59. Clock distribution for ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
Figure 60. Clock distribution for RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
Figure 61. Clock distribution for IWDG and WWDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Figure 62. Clock distribution for trace and debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Figure 63. Kernel clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Figure 64. Enable logic details for peripheral kernel clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
Figure 65. Basic structure of an I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
Figure 66. Input floating/pull-up/pull-down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
Figure 67. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
Figure 68. AF configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
Figure 69. Programmable analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
Figure 70. I/O compensation cell control overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
Figure 71. HPDMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
Figure 72. HPDMA channel direct programming without linked-list (HPDMA_CxLLR = 0) . . . . . . . . 840
Figure 73. HPDMA channel suspend and resume sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
Figure 74. HPDMA channel abort and restart sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
Figure 75. Static linked-list data structure (all Uxx = 1) of a linear addressing channel x . . . . . . . . . 843
Figure 76. Static linked-list data structure (all Uxx = 1) of a 2D addressing channel x . . . . . . . . . . . 844
Figure 77. HPDMA dynamic linked-list data structure of linear addressing channel x. . . . . . . . . . . . 845
Figure 78. HPDMA dynamic linked-list data structure of a 2D addressing channel x . . . . . . . . . . . . 845
Figure 79. HPDMA channel execution and linked-list programming
in run-to-completion mode (HPDMA_CxCR.LSM = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
Figure 80. Inserting a LLIn with an auxiliary HPDMA channel y . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
Figure 81. HPDMA channel execution and linked-list programming
in link step mode (HPDMA_CxCR.LSM = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
Figure 82. Building LLIn+1: HPDMA dynamic linked-lists in link step mode . . . . . . . . . . . . . . . . . . . 853
Figure 83. Replace with a new LLIn’ in register file in link step mode . . . . . . . . . . . . . . . . . . . . . . . . 854
Figure 84. Replace with a new LLIn’ and LLIn+1’ in memory in link step mode (option 1) . . . . . . . . 855
Figure 85. Replace with a new LLIn’ and LLIn+1’ in memory in link step mode (option 2) . . . . . . . . 856
Figure 86. HPDMA channel execution and linked-list programming . . . . . . . . . . . . . . . . . . . . . . . . . 858
Figure 87. Programmed 2D addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861
Figure 88. HPDMA arbitration policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
Figure 89. Trigger hit, memorization and overrun waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
Figure 90. HPDMA circular buffer programming: update of the memory start address
with a linear addressing channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
Figure 91. Shared HPDMA channel with circular buffering: update of the memory
start address with a linear addressing channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
Figure 92. GPDMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
Figure 93. GPDMA channel direct programming without linked-list (GPDMA_CxLLR = 0) . . . . . . . . 937
Figure 94. GPDMA channel suspend and resume sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
Figure 95. GPDMA channel abort and restart sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
Figure 96. Static linked-list data structure (all Uxx = 1)

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of a linear addressing channel x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940

Figure 97. Static linked-list data structure (all Uxx = 1)
of a 2D addressing channel x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
Figure 98. GPDMA dynamic linked-list data structure
of a linear addressing channel x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
Figure 99. GPDMA dynamic linked-list data structure
of a 2D addressing channel x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
Figure 100. GPDMA channel execution and linked-list programming
in run-to-completion mode (GPDMA_CxCR.LSM = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
Figure 101. Inserting a LLIn with an auxiliary GPDMA channel y . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
Figure 102. GPDMA channel execution and linked-list programming
in link step mode (GPDMA_CxCR.LSM = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948
Figure 103. Building LLIn+1: GPDMA dynamic linked-lists in link step mode . . . . . . . . . . . . . . . . . . . 949
Figure 104. Replace with a new LLIn’ in register file in link step mode . . . . . . . . . . . . . . . . . . . . . . . . 950
Figure 105. Replace with a new LLIn’ and LLIn+1’ in memory in link step mode (option 1) . . . . . . . . 951
Figure 106. Replace with a new LLIn’ and LLIn+1’ in memory in link step mode (option 2) . . . . . . . . 952
Figure 107. GPDMA channel execution and linked-list programming . . . . . . . . . . . . . . . . . . . . . . . . . 954
Figure 108. Programmed 2D addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
Figure 109. GPDMA arbitration policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
Figure 110. Trigger hit, memorization, and overrun waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
Figure 111. GPDMA circular buffer programming: update of the memory start address
with a linear addressing channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
Figure 112. Shared GPDMA channel with circular buffering: update of the memory
start address with a linear addressing channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
Figure 113. Stream processing engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005
Figure 114. Chaining of processing units. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006
Figure 115. Neural-ART 14 NPU accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
Figure 116. Stream engines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010
Figure 117. Two dimensional lossy compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
Figure 118. Decompression unit (DECUN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
Figure 119. Convolutional accelerator (CONVACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
Figure 120. Example of pooling operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
Figure 121. Pooling unit (POOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
Figure 122. Activation unit (ACTIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014
Figure 123. Arithmetic unit (ARITH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
Figure 124. Memory to memory transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
Figure 125. Simple processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
Figure 126. Multiple processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
Figure 127. Classical Conv-Pool-ReLU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
Figure 128. Chained convolutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020
Figure 129. Split convolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020
Figure 130. Neural-ART 14 integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
Figure 131. DMA2D block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
Figure 132. Intel 8080 16-bit mode (RGB565) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
Figure 133. Intel 8080 18/24-bit mode (RGB888) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
Figure 134. GFXMMU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
Figure 135. Virtual buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
Figure 136. Virtual buffer and physical buffer memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
Figure 137. MMU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
Figure 138. Block validation/comparator implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066
Figure 139. GFXTIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
Figure 140. Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078

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Figure 141. Waveforms in standalone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080

Figure 142. Active counters and signals in standalone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080
Figure 143. Waveforms with external HSYNC and VSYNC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080
Figure 144. Waveforms with external HSYNC only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
Figure 145. Active counters and signals with external HSYNC only . . . . . . . . . . . . . . . . . . . . . . . . . 1081
Figure 146. Waveforms with external VSYNC only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
Figure 147. Active counters with external VSYNC only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
Figure 148. Prescaling when external VSYNC only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
Figure 149. Waveforms with external CSYNC only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
Figure 150. Active counters and signals with external CSYNC only . . . . . . . . . . . . . . . . . . . . . . . . . 1083
Figure 151. Prescaling when external CSYNC only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
Figure 152. Tearing-effect configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
Figure 153. Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
Figure 154. EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120
Figure 155. Configurable event trigger logic CPU wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1124
Figure 156. EXTI direct events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
Figure 157. EXTI mux GPIO selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126
Figure 158. CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164
Figure 159. FMC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172
Figure 160. Mode 1 read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187
Figure 161. Mode 1 write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187
Figure 162. Mode A read access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1189
Figure 163. Mode A write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1190
Figure 164. Mode 2 and mode B read access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192
Figure 165. Mode 2 write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192
Figure 166. Mode B write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193
Figure 167. Mode C read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195
Figure 168. Mode C write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195
Figure 169. Mode D read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197
Figure 170. Mode D write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198
Figure 171. Muxed read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200
Figure 172. Muxed write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
Figure 173. Asynchronous wait during a read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204
Figure 174. Asynchronous wait during a write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . 1204
Figure 175. Wait configuration waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1206
Figure 176. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . . . . . . . 1207
Figure 177. Synchronous multiplexed write mode waveforms - PSRAM (CRAM). . . . . . . . . . . . . . . 1209
Figure 178. NAND flash controller waveforms for common memory access. . . . . . . . . . . . . . . . . . . 1222
Figure 179. NAND flash controller waveforms for TCLR and TAR timings . . . . . . . . . . . . . . . . . . . . 1223
Figure 180. Access to NAND flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224
Figure 181. NAND flash page (2 Kbytes) layout with BCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1228
Figure 182. Example of 2 Kbyte page program sequence with 4-bit BCH. . . . . . . . . . . . . . . . . . . . . 1230
Figure 183. Chained-page read command timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232
Figure 184. Example of 2-Kbyte page read sequence with 4-bit BCH. . . . . . . . . . . . . . . . . . . . . . . . 1233
Figure 185. SDRAM burst write waveforms
(AXI 4-word transfer, no page boundary crossing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262
Figure 186. SDRAM burst read waveforms
(AXI 4-word transfer, no page boundary crossing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263
Figure 187. SDRAM burst read crossing a row boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264
Figure 188. SDRAM burst write crossing a row boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265
Figure 189. Read followed by write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265
Figure 190. Write followed by read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266

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Figure 191. SDRAM Self-refresh waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267

Figure 192. Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268
Figure 193. Power-down with Auto-refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269
Figure 194. XSPI block diagram for 16-bit configuration(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284
Figure 195. XSPI block diagram for dual-octal configuration(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1285
Figure 196. XSPI block diagram for octal configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286
Figure 197. XSPI block diagram in quad configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287
Figure 198. XSPI block diagram for dual-quad configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1288
Figure 199. SDR read command in 16-bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1290
Figure 200. DTR read in octal-SPI mode with DQS (Macronix mode) example . . . . . . . . . . . . . . . . 1293
Figure 201. SDR write command in octal-SPI mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295
Figure 202. DTR write in octal-SPI mode (Macronix mode) example . . . . . . . . . . . . . . . . . . . . . . . . 1296
Figure 203. Example of HyperBus read operation (8-bit data mode) . . . . . . . . . . . . . . . . . . . . . . . . 1298
Figure 204. HyperBus write operation with initial latency (8-bit data mode) . . . . . . . . . . . . . . . . . . . 1300
Figure 205. HyperBus read operation with additional latency (8-bit data mode) . . . . . . . . . . . . . . . . 1300
Figure 206. HyperBus write operation with additional latency (8-bit data mode) . . . . . . . . . . . . . . . . 1301
Figure 207. HyperBus write operation with no latency (register write). . . . . . . . . . . . . . . . . . . . . . . . 1301
Figure 208. HyperBus read operation page crossing with latency (8-bit data mode) . . . . . . . . . . . . 1302
Figure 209. HyperBus write operation with initial latency (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . 1303
Figure 210. D0/D1 data ordering in octal-SPI DTR mode (Micron) - Read access . . . . . . . . . . . . . . 1310
Figure 211. OctaRAM read operation with reverse data ordering D1/D0 . . . . . . . . . . . . . . . . . . . . . 1310
Figure 212. NCS when CKMODE = 0 (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1317
Figure 213. Example of software control of two external memories . . . . . . . . . . . . . . . . . . . . . . . . . 1318
Figure 214. Example of hardware-controlled extended memory support . . . . . . . . . . . . . . . . . . . . . 1319
Figure 215. XSPIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1352
Figure 216. XSPI direct octal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355
Figure 217. XSPI direct 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356
Figure 218. XSPI dual-octal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357
Figure 219. XSPI swapped (octal) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1358
Figure 220. XSPI multiplexed mode to Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1359
Figure 221. XSPI multiplexed (octal and dual-octal) mode to Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . 1360
Figure 222. XSPI1 and XSPI2 drive a single external memory (octal mode). . . . . . . . . . . . . . . . . . . 1361
Figure 223. Single XSPI driving two external memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1362
Figure 224. SDMMC “no response” and “no data” operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1366
Figure 225. SDMMC (multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1366
Figure 226. SDMMC (multiple) block write operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1367
Figure 227. SDMMC (sequential) stream read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1367
Figure 228. SDMMC (sequential) stream write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1367
Figure 229. SDMMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1369
Figure 230. SDMMC Command and data phase relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371
Figure 231. Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1373
Figure 232. Command/response path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1374
Figure 233. Command path state machine (CPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375
Figure 234. Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1381
Figure 235. DDR mode data packet clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1382
Figure 236. DDR mode CRC status / boot acknowledgment clocking. . . . . . . . . . . . . . . . . . . . . . . . 1382
Figure 237. Data path state machine (DPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1383
Figure 238. CLKMUX unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394
Figure 239. Linked list structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1397
Figure 240. Asynchronous interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400
Figure 241. Synchronous interrupt period data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1401
Figure 242. Synchronous interrupt period data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1401

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Figure 243. Asynchronous interrupt period data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402

Figure 244. Asynchronous interrupt period data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1403
Figure 245. Clock stop with SDMMC_CK for DS, HS, SDR12, SDR25. . . . . . . . . . . . . . . . . . . . . . . 1406
Figure 246. Clock stop with SDMMC_CK for DDR50, SDR50, SDR104 . . . . . . . . . . . . . . . . . . . . . . 1406
Figure 247. Read Wait with SDMMC_CK < 50 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407
Figure 248. Read Wait with SDMMC_CK > 50 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407
Figure 249. CMD12 stream timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1410
Figure 250. CMD5 Sleep Awake procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412
Figure 251. Normal boot mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1414
Figure 252. Alternative boot mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1415
Figure 253. Command response R1b busy signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1416
Figure 254. SDMMC state control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1417
Figure 255. Card cycle power / power up diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1418
Figure 256. Read block gap hardware flow timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1419
Figure 257. CMD11 signal voltage switch sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1421
Figure 258. Voltage switch transceiver typical application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1423
Figure 259. DLYB block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1451
Figure 260. ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1462
Figure 261. ADC clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1466
Figure 262. ADC1 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1467
Figure 263. ADC2 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1468
Figure 264. Enabling/disabling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1473
Figure 265. Bulb mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1476
Figure 266. Analog-to-digital conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
Figure 267. Stopping ongoing regular conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1480
Figure 268. Stopping ongoing regular and injected conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1481
Figure 269. Triggers shared between ADC master and slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482
Figure 270. Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1484
Figure 271. Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1487
Figure 272. Continuous conversion of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . 1487
Figure 273. Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . 1488
Figure 274. Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . 1488
Figure 275. Right alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490
Figure 276. Right alignment (offset enabled, signed value). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1491
Figure 277. Left alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1491
Figure 278. Left alignment (offset enabled, signed value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492
Figure 279. Example of overrun (OVRMOD = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495
Figure 280. Example of overrun (OVRMOD = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495
Figure 281. AUTODLY = 1, regular conversion in continuous mode, software trigger . . . . . . . . . . . 1499
Figure 282. AUTODLY = 1, regular hardware conversions interrupted by injected conversions
(DISCEN = 0; JDISCEN = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500
Figure 283. AUTODLY = 1, regular hardware conversions interrupted by injected conversions. . . . . . . .
(DISCEN = 1, JDISCEN = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501
Figure 284. AUTODLY = 1, regular continuous conversions interrupted by injected conversions . . 1501
Figure 285. AUTODLY = 1 in autoinjection mode (JAUTO = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502
Figure 286. Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502
Figure 287. ADC_AWDy_OUT signal generation (on all regular channels). . . . . . . . . . . . . . . . . . . . 1505
Figure 288. ADC_AWDy_OUT signal generation (AWDy flag not cleared by software) . . . . . . . . . . 1505
Figure 289. ADC_AWDy_OUT signal generation (on a single regular channel) . . . . . . . . . . . . . . . . 1506
Figure 290. ADC_AWDy_OUT signal generation (on all injected channels) . . . . . . . . . . . . . . . . . . . 1506
Figure 291. 12-bit result oversampling with 10-bit right shift and rounding . . . . . . . . . . . . . . . . . . . . 1507
Figure 292. Triggered regular oversampling mode (TROVS bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . 1509

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Figure 293. Regular oversampling modes (4x ratio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510

Figure 294. Regular and injected oversampling modes used simultaneously . . . . . . . . . . . . . . . . . . 1511
Figure 295. Triggered regular oversampling with injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1511
Figure 296. Oversampling in autoinjection mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1512
Figure 297. Dual ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1514
Figure 298. Injected simultaneous mode on four channels: Dual ADC mode . . . . . . . . . . . . . . . . . . 1515
Figure 299. Regular simultaneous mode on 16 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . 1517
Figure 300. Interleaved mode on 1 channel in continuous conversion mode:
Dual ADC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1519
Figure 301. Interleaved mode on 1 channel in single conversion mode:
Dual ADC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1519
Figure 302. Interleaved conversion with injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1520
Figure 303. Alternate trigger: injected group of each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1521
Figure 304. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . . . . . . . . 1522
Figure 305. Alternate + regular simultaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1523
Figure 306. Case of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 1523
Figure 307. Interleaved single channel CH0 with injected sequence CH11, CH12 . . . . . . . . . . . . . . 1524
Figure 308. Two interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1524
Figure 309. Two interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1524
Figure 310. DMA Requests in regular simultaneous mode when DAMDF[1:0]=0b00 . . . . . . . . . . . . 1525
Figure 311. DMA requests in interleaved mode when DAMDF = 0b10 . . . . . . . . . . . . . . . . . . . . . . . 1526
Figure 312. VBAT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1529
Figure 313. VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1530
Figure 314. DTS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1572
Figure 315. Serial data adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1575
Figure 316. SDA data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1576
Figure 317. Falling alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1581
Figure 318. Rising alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1582
Figure 319. VREFBUF block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613
Figure 320. MDF block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1621
Figure 321. SITFx overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1624
Figure 322. SPI timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1625
Figure 323. Manchester timing example (SITFMOD = 11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1627
Figure 324. CKGEN overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1630
Figure 325. BSMX overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632
Figure 326. SCD functional view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
Figure 327. SCD timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
Figure 328. DFLT overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1635
Figure 329. Programmable delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636
Figure 330. CIC3 and CIC5 frequency response with decimation ratio = 32 . . . . . . . . . . . . . . . . . . . 1638
Figure 331. Reshape filter frequency response normalized (FRS / 2 = 1). . . . . . . . . . . . . . . . . . . . . 1643
Figure 332. Out-of-limit detector thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1646
Figure 333. Trigger logic for DFLT and CKGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648
Figure 334. Asynchronous continuous mode (ACQMOD[2:0] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 1649
Figure 335. Asynchronous single-shot mode (ACQMOD[2:0] = 001) . . . . . . . . . . . . . . . . . . . . . . . . 1650
Figure 336. Synchronous continuous mode (ACQMOD[2:0] = 010) . . . . . . . . . . . . . . . . . . . . . . . . . 1651
Figure 337. Synchronous single-shot mode (ACQMOD[2:0] = 011) . . . . . . . . . . . . . . . . . . . . . . . . . 1652
Figure 338. Window continuous mode (ACQMOD[2:0] = 100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1653
Figure 339. Snapshot mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655
Figure 340. Discard function example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1656

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Figure 341. Start sequence with DFLTEN, in continuous mode, audio configuration . . . . . . . . . . . . 1657
Figure 342. Start sequence with trigger input, in continuous mode, motor configuration . . . . . . . . . 1658
Figure 343. Break interface simplified view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1659
Figure 344. MDF_DFLTxDR data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1659
Figure 345. Data re-synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1660
Figure 346. Data transfer in interleaved-transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1661
Figure 347. Data path for interleaved- and independent-transfer modes . . . . . . . . . . . . . . . . . . . . . 1663
Figure 348. Example of overflow and transfer to memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1664
Figure 349. MDF interrupt interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1667
Figure 350. Sensor connection examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672
Figure 351. Global frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673
Figure 352. Detailed frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673
Figure 353. Simplified DFLT view with gain information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1676
Figure 354. ADF block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704
Figure 355. SITF overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1706
Figure 356. SPI timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1707
Figure 357. Manchester timing example (SITFMOD = 11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1708
Figure 358. CKGEN overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1711
Figure 359. BSMX overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1713
Figure 360. DFLT overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1714
Figure 361. Programmable delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1715
Figure 362. CIC4 and CIC5 frequency response with decimation ratio = 32 or 16 . . . . . . . . . . . . . . 1716
Figure 363. Reshape filter frequency response normalized (FRS / 2 = 1). . . . . . . . . . . . . . . . . . . . . 1722
Figure 364. Trigger logic for DFLT and CKGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1724
Figure 365. Asynchronous continuous mode (ACQMOD[2:0] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 1725
Figure 366. Asynchronous single-shot mode (ACQMOD[2:0] = 001) . . . . . . . . . . . . . . . . . . . . . . . . 1726
Figure 367. Synchronous continuous mode (ACQMOD[2:0] = 010) . . . . . . . . . . . . . . . . . . . . . . . . . 1727
Figure 368. Synchronous single-shot mode (ACQMOD[2:0] = 011) . . . . . . . . . . . . . . . . . . . . . . . . . 1728
Figure 369. Window continuous mode (ACQMOD[2:0] = 100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1729
Figure 370. Discard function example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1731
Figure 371. Start sequence with DFLTEN, in continuous mode, audio configuration . . . . . . . . . . . . 1731
Figure 372. SAD block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1732
Figure 373. SAD flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1734
Figure 374. SAD timing diagram example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1740
Figure 375. ADF_DFLTxDR data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1740
Figure 376. Data re-synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1741
Figure 377. Example of overflow and transfer to memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1742
Figure 378. ADF interrupt interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1745
Figure 379. Sensor connection examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1750
Figure 380. Global frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1750
Figure 381. Detailed frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1751
Figure 382. Simplified DFLT view with gain information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1753
Figure 383. SAD example working with SADMOD = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1756
Figure 384. SAD example working with SADMOD = 1x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1758
Figure 385. Camera subsystem block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1780
Figure 386. Camera subsystem clock diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1781
Figure 387. DCMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1789
Figure 388. DCMI signal waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1790
Figure 389. Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1792
Figure 390. Frame capture waveforms in snapshot mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1794
Figure 391. Frame capture waveforms in continuous grab mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 1795
Figure 392. Coordinates and size of the window after cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1795

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Figure 393. Data capture waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1796

Figure 394. Pixel raster scan order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1797
Figure 395. DCMIPP overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1811
Figure 396. DCMIPP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1815
Figure 397. VC flow processed by one pipe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1830
Figure 398. Two exclusive VC flows processed by one reconfigured pipe . . . . . . . . . . . . . . . . . . . . 1830
Figure 399. Two overlapping VC flows processed by two pipes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1831
Figure 400. Snapshot (CPTMODE = 1) and Continuous (CPTMODE = 0) capture modes. . . . . . . . 1832
Figure 401. Pipe0 (dump) architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1834
Figure 402. Pipe1 ISP architecture view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1839
Figure 403. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1856
Figure 404. Downsize with coverage filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1859
Figure 405. Example with two ROIs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1860
Figure 406. Pipe2 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1865
Figure 407. Use case: Pipe0 (statistics), Pipe1 (pixels). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1867
Figure 408. Statistics and RGB data for single virtual channel data flow . . . . . . . . . . . . . . . . . . . . . 1868
Figure 409. Three pipes within a single virtual channel in CSI2 mode . . . . . . . . . . . . . . . . . . . . . . . 1868
Figure 410. Handling interleaved packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1869
Figure 411. Handling interleaved packets across two pixel pipes . . . . . . . . . . . . . . . . . . . . . . . . . . . 1869
Figure 412. Interlaced video (based on single pixel pipe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1870
Figure 413. Interlaced video (based on two pixel pipes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1870
Figure 414. 3D sensors (top-bottom) processed by two pixel pipes . . . . . . . . . . . . . . . . . . . . . . . . . 1875
Figure 415. CSI-2 Host block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2011
Figure 416. CSI-2 Host architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2012
Figure 417. CSI-2 Host clock domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2014
Figure 418. Lane merger input and output (one data lane) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2015
Figure 419. Lane merger input and output (two data lanes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2015
Figure 420. Data lane mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2015
Figure 421. Low-level protocol overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2016
Figure 422. CSI2- long-packet structure for a D-PHY physical layer . . . . . . . . . . . . . . . . . . . . . . . . . 2017
Figure 423. Short-packet structure based on D-PHY physical layer . . . . . . . . . . . . . . . . . . . . . . . . . 2017
Figure 424. DATA ID structure in short or long packet format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2018
Figure 425. Data interleaving using data type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2019
Figure 426. Data interleaving using virtual channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2020
Figure 427. RAW6 (BPP6) input and output format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2021
Figure 428. Raw7 (BPP7) input and output format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2022
Figure 429. Raw8 (BPP8) input and output format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2023
Figure 430. Raw 10 (BPP10) input and output format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2023
Figure 431. Raw12 (BPP12) input/output format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2024
Figure 432. Raw14 (BPP14) input format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2025
Figure 433. Raw16 (BPP16) input/output format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2026
Figure 434. PSSI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2068
Figure 435. Top-level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2068
Figure 436. Data enable in receive mode waveform diagram (CKPOL=0) . . . . . . . . . . . . . . . . . . . . 2072
Figure 437. Data enable waveform diagram in transmit mode (CKPOL=0). . . . . . . . . . . . . . . . . . . . 2072
Figure 438. Ready in receive mode waveform diagram (CKPOL=0). . . . . . . . . . . . . . . . . . . . . . . . . 2073
Figure 439. Bidirectional PSSI_DE/PSSI_RDY waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2074
Figure 440. Bidirectional PSSI_DE/PSSI_RDY connection diagram . . . . . . . . . . . . . . . . . . . . . . . . 2074
Figure 441. Display subsystem block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2082
Figure 442. Display subsystem clock diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2082
Figure 443. LTDC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2088
Figure 444. Layer window programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2100

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Figure 445. Blending two layers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2101

Figure 446. LTDC synchronous timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2105
Figure 447. GPU2D block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2148
Figure 448. VENC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2151
Figure 449. JPEG codec block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2259
Figure 450. RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2281
Figure 451. NIST SP800-90B entropy source model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2282
Figure 452. RNG initialization overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2285
Figure 453. SAES block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2299
Figure 454. Encryption/ decryption typical usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2301
Figure 455. Typical operation with authentication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2303
Figure 456. Example of suspend mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2304
Figure 457. ECB encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2305
Figure 458. ECB decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2305
Figure 459. CBC encryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2306
Figure 460. CBC decryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2306
Figure 461. Message construction in CTR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2309
Figure 462. CTR encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2310
Figure 463. Message construction in GCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2311
Figure 464. GCM authenticated encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2313
Figure 465. Message construction in GMAC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2316
Figure 466. GMAC authentication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2316
Figure 467. Message construction in CCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2317
Figure 468. CCM mode authenticated encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2319
Figure 469. Operation with wrapped keys for SAES in ECB and CBC modes . . . . . . . . . . . . . . . . . 2322
Figure 470. Operation with wrapped keys for SAES in CTR mode . . . . . . . . . . . . . . . . . . . . . . . . . . 2325
Figure 471. Usage of Shared-key mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2326
Figure 472. 128-bit block construction according to the data type. . . . . . . . . . . . . . . . . . . . . . . . . . . 2329
Figure 473. Key protection mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2331
Figure 474. CRYP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2354
Figure 475. Encryption/ decryption typical usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2356
Figure 476. Typical operation with authentication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2359
Figure 477. Example of suspend mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2360
Figure 478. ECB encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2361
Figure 479. ECB decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2361
Figure 480. CBC encryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2362
Figure 481. CBC decryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2362
Figure 482. Message construction in CTR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2365
Figure 483. CTR encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2366
Figure 484. Message construction in GCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2368
Figure 485. GCM authenticated encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2369
Figure 486. Message construction in GMAC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2373
Figure 487. GMAC authentication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2373
Figure 488. Message construction in CCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2374
Figure 489. CCM mode authenticated encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2376
Figure 490. 128-bit block construction according to the data type. . . . . . . . . . . . . . . . . . . . . . . . . . . 2382
Figure 491. HASH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2403
Figure 492. Message data swapping feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2405
Figure 493. HASH suspend/resume mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2411
Figure 494. MCE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2425
Figure 495. MCE region programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2426
Figure 496. MCE implementation of block ciphers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2428

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Figure 497. MCE implementation of stream cipher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2429

Figure 498. PKA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2446
Figure 499. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2479
Figure 500. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 2485
Figure 501. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 2485
Figure 502. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2487
Figure 503. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2487
Figure 504. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2488
Figure 505. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2488
Figure 506. Counter timing diagram, update event when ARPE = 0
(TIMx_ARR not preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2489
Figure 507. Counter timing diagram, update event when ARPE = 1
(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2490
Figure 508. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2491
Figure 509. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2492
Figure 510. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2492
Figure 511. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2493
Figure 512. Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . 2493
Figure 513. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . 2495
Figure 514. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2495
Figure 515. Counter timing diagram, internal clock divided by 4, TIMx_ARR = 0x36 . . . . . . . . . . . . 2496
Figure 516. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2496
Figure 517. Counter timing diagram, update event with ARPE = 1 (counter underflow) . . . . . . . . . . 2497
Figure 518. Counter timing diagram, Update event with ARPE = 1 (counter overflow) . . . . . . . . . . . 2498
Figure 519. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . 2499
Figure 521. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 2501
Figure 522. tim_ti2 external clock connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2501
Figure 523. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2502
Figure 524. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2503
Figure 525. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2504
Figure 526. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 2504
Figure 527. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2505
Figure 528. Output stage of capture/compare channel (channel 1, idem ch. 2, 3 and 4) . . . . . . . . . 2505
Figure 529. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . . . . . . . . . . . . . 2506
Figure 530. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2508
Figure 531. Output compare mode, toggle on tim_oc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2510
Figure 532. Edge-aligned PWM waveforms (ARR = 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2511
Figure 533. Center-aligned PWM waveforms (ARR = 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2512
Figure 534. Dithering principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2513
Figure 535. Data format and register coding in dithering mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2514
Figure 536. PWM resolution vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2515
Figure 537. PWM dithering pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2516
Figure 538. Dithering effect on duty cycle in center-aligned PWM mode . . . . . . . . . . . . . . . . . . . . . 2517
Figure 539. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . 2519
Figure 540. Combined PWM mode on channel 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2520
Figure 541. 3-phase combined PWM signals with multiple trigger pulses per period . . . . . . . . . . . . 2521
Figure 542. Complementary output with symmetrical dead-time insertion . . . . . . . . . . . . . . . . . . . . 2522
Figure 543. Asymmetrical deadtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2523
Figure 544. Dead-time waveforms with delay greater than the negative pulse . . . . . . . . . . . . . . . . . 2523
Figure 545. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . 2523
Figure 546. Break and Break2 circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2526
Figure 547. Various output behavior in response to a break event on tim_brk (OSSI = 1) . . . . . . . . 2528

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Figure 548. PWM output state following tim_brk and tim_brk2 assertion (OSSI = 1) . . . . . . . . . . . . 2529
Figure 549. PWM output state following tim_brk assertion (OSSI = 0) . . . . . . . . . . . . . . . . . . . . . . . 2530
Figure 550. Output redirection (tim_brk2 request not represented) . . . . . . . . . . . . . . . . . . . . . . . . . . 2531
Figure 551. Clearing TIMx tim_ocxref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2532
Figure 552. 6-step generation, COM example (OSSR = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2533
Figure 553. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2534
Figure 554. Retriggerable one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2536
Figure 555. Pulse generator circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2536
Figure 556. Pulse generation on compare event, for edge-aligned and encoder modes . . . . . . . . . 2537
Figure 557. Extended pulsewidth in case of concurrent triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2538
Figure 558. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . 2540
Figure 559. Example of encoder interface mode with tim_ti1fp1 polarity inverted. . . . . . . . . . . . . . . 2540
Figure 560. Quadrature encoder counting modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2541
Figure 561. Direction plus clock encoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2542
Figure 562. Directional clock encoder mode (CC1P = CC2P = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2542
Figure 563. Directional clock encoder mode (CC1P = CC2P = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2543
Figure 564. Index gating options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2544
Figure 565. Jittered Index signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2544
Figure 566. Index generation for IPOS[1:0] = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2545
Figure 567. Counter reading with index gated on channel A (IPOS[1:0] = 11) . . . . . . . . . . . . . . . . . 2545
Figure 568. Counter reading with index ungated (IPOS[1:0] = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . 2546
Figure 569. Counter reading with index gated on channel A and B. . . . . . . . . . . . . . . . . . . . . . . . . . 2546
Figure 570. Encoder mode behavior in case of narrow index pulse (IPOS[1:0] = 11) . . . . . . . . . . . . 2547
Figure 571. Counter reset Narrow index pulse (closer view, ARR = 0x07) . . . . . . . . . . . . . . . . . . . . 2548
Figure 572. Index behavior in x1 and x2 mode (IPOS[1:0] = 01). . . . . . . . . . . . . . . . . . . . . . . . . . . . 2549
Figure 573. Directional index sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2549
Figure 574. Counter reset as function of FIDX bit setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2550
Figure 575. Index blanking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2550
Figure 576. Index behavior in clock + direction mode, IPOS[0] = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 2551
Figure 577. Index behavior in directional clock mode, IPOS[0] = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 2551
Figure 578. State diagram for quadrature encoded signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2552
Figure 579. Up-counting encoder error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2553
Figure 580. Down-counting encode error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2554
Figure 581. Encoder mode change with preload transferred on update (SMSPS = 0) . . . . . . . . . . . 2555
Figure 582. Measuring time interval between edges on three signals . . . . . . . . . . . . . . . . . . . . . . . . 2556
Figure 583. Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2558
Figure 584. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2559
Figure 585. Control circuit in Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2560
Figure 586. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2561
Figure 587. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . 2562
Figure 588. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2621
Figure 589. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 2626
Figure 590. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 2627
Figure 591. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2628
Figure 592. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2628
Figure 593. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2629
Figure 594. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2629
Figure 595. Counter timing diagram, Update event when ARPE = 0 (TIMx_ARR not preloaded). . . 2630
Figure 596. Counter timing diagram, Update event when ARPE = 1 (TIMx_ARR preloaded). . . . . . 2631
Figure 597. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2632
Figure 598. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2633
Figure 599. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2633

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Figure 600. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2634

Figure 601. Counter timing diagram, Update event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2634
Figure 602. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . 2636
Figure 603. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2636
Figure 604. Counter timing diagram, internal clock divided by 4, TIMx_ARR = 0x36 . . . . . . . . . . . . 2637
Figure 605. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2637
Figure 606. Counter timing diagram, Update event with ARPE = 1 (counter underflow). . . . . . . . . . 2638
Figure 607. Counter timing diagram, Update event with ARPE = 1 (counter overflow) . . . . . . . . . . . 2639
Figure 608. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 2640
Figure 609. tim_ti2 external clock connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2640
Figure 610. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2641
Figure 611. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2642
Figure 612. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2643
Figure 613. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 2643
Figure 614. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2644
Figure 615. Output stage of capture/compare channel (channel 1, idem ch.2, 3 and 4) . . . . . . . . . . 2644
Figure 616. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2647
Figure 617. Output compare mode, toggle on tim_oc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2649
Figure 618. Edge-aligned PWM waveforms (ARR = 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2650
Figure 619. Center-aligned PWM waveforms (ARR = 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2651
Figure 620. Dithering principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2652
Figure 621. Data format and register coding in dithering mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2653
Figure 622. PWM resolution vs frequency (16-bit mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2654
Figure 623. PWM resolution vs frequency (32-bit mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2654
Figure 624. PWM dithering pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2655
Figure 625. Dithering effect on duty cycle in center-aligned PWM mode . . . . . . . . . . . . . . . . . . . . . 2656
Figure 626. Generation of two phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . 2658
Figure 627. Combined PWM mode on channels 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2659
Figure 628. OCREF_CLR input selection multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2660
Figure 629. Clearing TIMx tim_ocxref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2660
Figure 630. Example of One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2661
Figure 631. Retriggerable one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2663
Figure 632. Pulse generator circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2664
Figure 633. Pulse generation on compare event, for edge-aligned and encoder modes . . . . . . . . . 2664
Figure 634. Extended pulse width in case of concurrent triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . 2665
Figure 635. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . 2667
Figure 636. Example of encoder interface mode with tim_ti1fp1 polarity inverted . . . . . . . . . . . . . . 2667
Figure 637. Quadrature encoder counting modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2668
Figure 638. Direction plus clock encoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2669
Figure 639. Directional clock encoder mode (CC1P = CC2P = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2670
Figure 640. Directional clock encoder mode (CC1P = CC2P = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2670
Figure 641. Index gating options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2672
Figure 642. Jittered Index signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2672
Figure 643. Index generation for IPOS[1:0] = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2673
Figure 644. Counter reading with index gated on channel A (IPOS[1:0] = 11) . . . . . . . . . . . . . . . . . 2673
Figure 645. Counter reading with index ungated (IPOS[1:0] = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . 2674
Figure 646. Counter reading with index gated on channel A and B. . . . . . . . . . . . . . . . . . . . . . . . . . 2674
Figure 647. Encoder mode behavior in case of narrow index pulse (IPOS[1:0] = 11) . . . . . . . . . . . . 2675
Figure 648. Counter reset Narrow index pulse (closer view, ARR = 0x07) . . . . . . . . . . . . . . . . . . . . 2676
Figure 649. Index behavior in x1 and x2 mode (IPOS[1:0] = 01). . . . . . . . . . . . . . . . . . . . . . . . . . . . 2677
Figure 650. Directional index sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2677
Figure 651. Counter reset as function of FIDX bit setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2678

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Figure 652. Index blanking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2678

Figure 653. Index behavior in clock + direction mode, IPOS[0] = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 2679
Figure 654. Index behavior in directional clock mode, IPOS[0] = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 2679
Figure 655. State diagram for quadrature encoded signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2680
Figure 656. Up-counting encoder error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2681
Figure 657. Down-counting encode error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2682
Figure 658. Encoder mode change with preload transferred on update (SMSPS = 0) . . . . . . . . . . . 2683
Figure 659. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2685
Figure 660. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2686
Figure 661. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2686
Figure 662. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . 2688
Figure 663. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2688
Figure 664. Master/slave connection example with 1 channel only timers . . . . . . . . . . . . . . . . . . . . 2689
Figure 665. Gating TIM_slv with tim_oc1ref of TIM_mstr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2690
Figure 666. Gating TIM_slv with Enable of TIM_mstr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2691
Figure 667. Triggering TIM_slv with update of TIM_mstr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2692
Figure 668. Triggering TIM_slv with Enable of TIM_mstr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2692
Figure 669. Triggering TIM_mstr and TIM_slv with TIM_mstr tim_ti1 input . . . . . . . . . . . . . . . . . . . . 2693
Figure 670. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2734
Figure 671. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 2735
Figure 672. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 2737
Figure 673. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 2737
Figure 674. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2738
Figure 675. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2739
Figure 676. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2739
Figure 677. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2740
Figure 678. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2740
Figure 679. Counter timing diagram, update event when ARPE = 1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2741
Figure 680. Dithering principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2742
Figure 681. Data format and register coding in dithering mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2742
Figure 682. FCnt resolution vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2743
Figure 683. PWM dithering pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2743
Figure 684. General-purpose timer block diagram (TIM9/TIM12) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2756
Figure 685. General-purpose timer block diagram (TIM10/TIM11/TIM13/TIM14) . . . . . . . . . . . . . . . 2757
Figure 686. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 2760
Figure 687. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 2760
Figure 688. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2761
Figure 689. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2762
Figure 690. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2762
Figure 691. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2763
Figure 692. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2763
Figure 693. Counter timing diagram, update event when ARPE = 1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2764
Figure 694. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 2765
Figure 695. tim_ti2 external clock connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2765
Figure 696. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2766
Figure 697. Capture/compare channel 1 input stage (TIM10/TIM11/TIM13/TIM14) . . . . . . . . . . . . . 2767
Figure 698. Capture/compare channel 1 input stage (TIM9/TIM12) . . . . . . . . . . . . . . . . . . . . . . . . . 2767
Figure 699. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2768

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Figure 700. Output stage of capture/compare channel 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2768

Figure 701. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2770
Figure 702. Output compare mode, toggle on tim_oc1.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2772
Figure 703. Edge-aligned PWM waveforms (ARR = 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2773
Figure 704. Dithering principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2774
Figure 705. Data format and register coding in dithering mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2774
Figure 706. PWM resolution vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2775
Figure 707. PWM dithering pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2776
Figure 708. Combined PWM mode on channel 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2778
Figure 709. Example of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2779
Figure 710. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2780
Figure 711. Measuring time interval between edges on 2 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 2781
Figure 712. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2782
Figure 713. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2783
Figure 714. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2783
Figure 715. TIM15 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2819
Figure 716. TIM16/TIM17 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2820
Figure 717. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 2824
Figure 718. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 2825
Figure 719. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2826
Figure 720. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2827
Figure 721. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2827
Figure 722. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2828
Figure 723. Counter timing diagram, update event when ARPE = 0
(TIMx_ARR not preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2828
Figure 724. Counter timing diagram, update event when ARPE = 1
(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2829
Figure 725. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . 2830
Figure 726. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 2831
Figure 727. tim_ti2 external clock connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2831
Figure 728. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2832
Figure 729. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 2833
Figure 730. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2833
Figure 731. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . 2834
Figure 732. Output stage of capture/compare channel (channel 2 for TIM15) . . . . . . . . . . . . . . . . . 2834
Figure 733. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2837
Figure 734. Output compare mode, toggle on tim_oc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2839
Figure 735. Edge-aligned PWM waveforms (ARR = 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2840
Figure 736. Dithering principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2841
Figure 737. Data format and register coding in dithering mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2841
Figure 738. PWM resolution vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2842
Figure 739. PWM dithering pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2843
Figure 740. Combined PWM mode on channel 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2845
Figure 741. Complementary output with symmetrical dead-time insertion. . . . . . . . . . . . . . . . . . . . . 2846
Figure 742. Asymmetrical deadtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2847
Figure 743. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . 2847
Figure 744. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . 2847
Figure 745. Break circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2849
Figure 746. Output behavior in response to a break event on tim_brk . . . . . . . . . . . . . . . . . . . . . . . 2851
Figure 747. Output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2853
Figure 748. tim_ocref_clr input selection multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2854
Figure 749. 6-step generation, COM example (OSSR = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2855

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Figure 750. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2856

Figure 751. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2858
Figure 752. Measuring time interval between edges on 2 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 2858
Figure 753. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2859
Figure 754. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2860
Figure 755. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2861
Figure 756. LPTIM1/2/3 block diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2927
Figure 757. LPTIM4/5 block diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2928
Figure 758. Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2932
Figure 759. LPTIM output waveform, single-counting mode configuration
when repetition register content is different than zero (with PRELOAD = 1) . . . . . . . . . 2934
Figure 760. LPTIM output waveform, single-counting mode configuration
and Set-once mode activated (WAVE bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2935
Figure 761. LPTIM output waveform, Continuous counting mode configuration . . . . . . . . . . . . . . . . 2935
Figure 762. Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2937
Figure 763. Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2941
Figure 764. Continuous counting mode when repetition register LPTIM_RCR
different from zero (with PRELOAD = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2942
Figure 765. Capture/compare input stage (channel 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2943
Figure 766. Capture/compare output stage (channel 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2943
Figure 767. Edge-aligned PWM mode (PRELOAD = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2945
Figure 768. Edge-aligned PWM waveforms (ARR=8 and CCxP = 0) . . . . . . . . . . . . . . . . . . . . . . . . 2946
Figure 769. PWM mode with immediate update versus preloaded update . . . . . . . . . . . . . . . . . . . . 2947
Figure 770. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2977
Figure 771. Reset timing due to timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2979
Figure 772. Reset timing due to refresh in the not allowed area . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2980
Figure 773. Changing PR, RL, and performing a refresh(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2981
Figure 774. Window comparator update(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2982
Figure 775. Independent watchdog interrupt timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2984
Figure 776. Early wake-up comparator update(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2985
Figure 777. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2993
Figure 778. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2995
Figure 779. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3001
Figure 780. TAMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3056
Figure 781. Backup registers protection zones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3060
Figure 782. Tamper sampling with precharge pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3065
Figure 783. Low level detection with precharge and filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3065
Figure 784. Active tamper filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3068
Figure 785. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3103
Figure 786. I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3105
Figure 787. Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3107
Figure 788. I2C initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3109
Figure 789. Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3110
Figure 790. Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3111
Figure 791. Target initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3114
Figure 792. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . . . . . . . . . . . 3116
Figure 793. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . . . . . . . . . . . 3117
Figure 794. Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . . . . . . . 3118
Figure 795. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . . . . . . . . . . . . . 3119
Figure 796. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . . . . . . . . . . . . . 3120
Figure 797. Transfer bus diagrams for I2C target receiver
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3120

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Figure 798. Controller clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3122

Figure 799. Controller initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3124
Figure 800. 10-bit address read access with HEAD10R = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3124
Figure 801. 10-bit address read access with HEAD10R = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3125
Figure 802. Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . . . . . . . . . . . . 3126
Figure 803. Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . . . . . . . . . . . . 3127
Figure 804. Transfer bus diagrams for I2C controller transmitter
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3128
Figure 805. Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . . . . . . . . . . . . . 3130
Figure 806. Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . . . . . . . . . . . . . . 3131
Figure 807. Transfer bus diagrams for I2C controller receiver
(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3132
Figure 808. Timeout intervals for tLOW:SEXT, tLOW:MEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3136
Figure 809. Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . . . . . . . . . . . 3139
Figure 810. Transfer bus diagram for SMBus target transmitter (SBC = 1). . . . . . . . . . . . . . . . . . . . 3140
Figure 811. Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . . . . . . . . . . . . . 3141
Figure 812. Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . . . . . . . . . . . . . . . . . . 3142
Figure 813. Bus transfer diagrams for SMBus controller transmitter . . . . . . . . . . . . . . . . . . . . . . . . . 3143
Figure 814. Bus transfer diagrams for SMBus controller receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 3145
Figure 815. I3C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3169
Figure 816. I3C (primary) controller state and programming sequence diagram. . . . . . . . . . . . . . . . 3173
Figure 817. I3C target state and programing sequence diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3178
Figure 818. I3C CCC messages, as controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3192
Figure 819. I3C broadcast ENTDAA CCC, as controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3193
Figure 820. I3C broadcast, direct read and direct write RSTACT CCC, as controller . . . . . . . . . . . . 3194
Figure 821. I3C CCC messages, as target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3196
Figure 822. I3C broadcast ENTDAA CCC, as target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3197
Figure 823. I3C broadcast DEFTGTS CCC, as target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3198
Figure 824. I3C broadcast DEFGRPA CCC, as target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3199
Figure 825. I3C private read/write messages, as controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3201
Figure 826. I3C private read/write messages, as target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3202
Figure 827. Legacy I2C read/write messages, as controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3203
Figure 828. IBI transfer, as controller/target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3204
Figure 829. Hot-join request transfer, as controller/target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3206
Figure 830. Controller-role request transfer, as controller/target . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3207
Figure 831. C-FIFO management, as controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3208
Figure 832. TX-FIFO management, as controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3210
Figure 833. RX-FIFO management, as controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3212
Figure 834. S-FIFO management, as controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3215
Figure 835. RX-FIFO management, as target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3216
Figure 836. TX-FIFO management with I3C_TGTTDR, as target . . . . . . . . . . . . . . . . . . . . . . . . . . . 3218
Figure 837. TX-FIFO management by software without I3C_TGTTDR
if reading less bytes than TX-FIFO size, as target. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3220
Figure 838. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3278
Figure 839. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3282
Figure 840. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3284
Figure 841. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3286
Figure 842. Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3287
Figure 843. usart_ker_ck clock divider block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3290
Figure 844. Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3291
Figure 845. Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3292
Figure 846. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3299

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Figure 847. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3300

Figure 848. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . 3303
Figure 849. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . 3304
Figure 850. USART example of synchronous master transmission. . . . . . . . . . . . . . . . . . . . . . . . . . 3305
Figure 851. USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3305
Figure 852. USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3306
Figure 853. USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3307
Figure 854. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3309
Figure 855. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3311
Figure 856. IrDA SIR ENDEC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3315
Figure 857. IrDA data modulation (3/16) - normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3315
Figure 858. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3317
Figure 859. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3318
Figure 860. Hardware flow control between two USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3318
Figure 861. RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3319
Figure 862. RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3320
Figure 863. Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . . . . . . . 3323
Figure 864. Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3323
Figure 865. LPUART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3368
Figure 866. LPUART word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3371
Figure 867. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3373
Figure 868. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3375
Figure 869. lpuart_ker_ck clock divider block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3379
Figure 870. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3383
Figure 871. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3384
Figure 872. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3386
Figure 873. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3387
Figure 874. Hardware flow control between two LPUARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3388
Figure 875. RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3388
Figure 876. RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3389
Figure 877. Wake-up event verified (wake-up event = address match,
FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3392
Figure 878. Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3392
Figure 879. SPI/I2S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3424
Figure 880. Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3427
Figure 881. Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3428
Figure 882. Simplex single master / single slave application
(master in transmit-only / slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 3429
Figure 883. Master and three independent slaves connected in star topology . . . . . . . . . . . . . . . . . 3430
Figure 884. Master and three slaves connected in circular (daisy chain) topology . . . . . . . . . . . . . . 3431
Figure 885. Multimaster application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3432
Figure 886. Scheme of SS control logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3434
Figure 887. Data flow timing control (SSOE = 1, SSOM = 0, SSM = 0) . . . . . . . . . . . . . . . . . . . . . . 3434
Figure 888. SS interleaving pulses between data (SSOE = 1, SSOM = 1, SSM = 0) . . . . . . . . . . . . 3435
Figure 889. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3437
Figure 890. Data alignment when data size is not equal to 8, 16 or 32 bits . . . . . . . . . . . . . . . . . . . 3438
Figure 891. TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3447

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Figure 892. Optional configurations of the slave behavior when an underrun condition is detected . 3449
Figure 893. Waveform examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3457
Figure 894. Master I2S Philips protocol waveforms (16/32-bit full accuracy) . . . . . . . . . . . . . . . . . . 3458
Figure 895. I2S Philips standard waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3458
Figure 896. Master MSB-justified 16- or 32-bit full-accuracy length . . . . . . . . . . . . . . . . . . . . . . . . . 3459
Figure 897. Master MSB-justified 16- or 24-bit data length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3459
Figure 898. Slave MSB-justified 16-, 24- or 32-bit data length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3460
Figure 899. LSB-justified 16 or 24-bit data length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3460
Figure 900. Master PCM when the frame length is equal the data length . . . . . . . . . . . . . . . . . . . . . 3461
Figure 901. Master PCM standard waveforms (16 or 24-bit data length) . . . . . . . . . . . . . . . . . . . . . 3461
Figure 902. Slave PCM waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3462
Figure 903. Startup sequence, I2S Philips standard, master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3465
Figure 904. Startup sequence, I2S Philips standard, slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3466
Figure 905. Stop sequence, I2S Philips standard, master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3466
Figure 906. I2S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3467
Figure 907. Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3469
Figure 908. Handling of underrun situation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3471
Figure 909. Handling of overrun situation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3472
Figure 910. Frame error detection, with FIXCH = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3473
Figure 911. Frame error detection, with FIXCH = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3473
Figure 912. SAI functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3498
Figure 913. Audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3502
Figure 914. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . . . . . . . 3504
Figure 915. FS role is start of frame (FSDEF = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3505
Figure 916. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . . . . . . . . . . . . . . . . . . . . . 3506
Figure 917. First bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3506
Figure 918. Audio block clock generator overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3508
Figure 919. PDM typical connection and timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3512
Figure 920. Detailed PDM interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3513
Figure 921. Start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3514
Figure 922. SAI_ADR format in TDM mode, 32-bit slot width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3515
Figure 923. SAI_ADR format in TDM mode, 16-bit slot width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3516
Figure 924. SAI_ADR format in TDM mode, 8-bit slot width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3517
Figure 925. AC’97 audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3520
Figure 926. Example of typical AC’97 configuration on devices featuring at least
two embedded SAIs (three external AC’97 decoders) . . . . . . . . . . . . . . . . . . . . . . . . . . 3521
Figure 927. SPDIF format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3522
Figure 928. SAI_xDR register ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3523
Figure 929. Data companding hardware in an audio block in the SAI . . . . . . . . . . . . . . . . . . . . . . . . 3526
Figure 930. Tristate strategy on SD output line on an inactive slot . . . . . . . . . . . . . . . . . . . . . . . . . . 3528
Figure 931. Tristate on output data line in a protocol like I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3529
Figure 932. Overrun detection error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3530
Figure 933. FIFO underrun event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3530
Figure 934. SPDIFRX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3564
Figure 935. S/PDIF sub-frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3565
Figure 936. S/PDIF block format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3566
Figure 937. S/PDIF Preambles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3566
Figure 938. Channel coding example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3567
Figure 939. SPDIFRX decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3568
Figure 940. Noise filtering and edge detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3568
Figure 941. Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3570
Figure 942. Synchronization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3572

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Figure 943. Synchronization process scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3573

Figure 944. SPDIFRX States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3574
Figure 945. SPDIFRX_FMTx_DR register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3576
Figure 946. Channel/user data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3577
Figure 947. S/PDIF overrun error when RXSTEO = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3579
Figure 948. S/PDIF overrun error when RXSTEO = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3580
Figure 949. SPDIFRX interface interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3583
Figure 950. MDIOS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3598
Figure 951. MDIO protocol write frame waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3599
Figure 952. MDIO protocol read frame waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3599
Figure 953. CAN subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3612
Figure 954. FDCAN block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3614
Figure 955. Transceiver delay measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3619
Figure 956. Pin control in bus monitoring mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3621
Figure 957. Pin control in loop back mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3623
Figure 958. CAN error state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3624
Figure 959. Message RAM configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3625
Figure 960. Standard message ID filter path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3628
Figure 961. Extended message ID filter path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3629
Figure 962. Example of mixed configuration dedicated Tx buffers / Tx FIFO . . . . . . . . . . . . . . . . . . 3635
Figure 963. Example of mixed configuration dedicated Tx buffers / Tx queue . . . . . . . . . . . . . . . . . 3635
Figure 964. Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3637
Figure 965. Bypass operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3639
Figure 966. FSM calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3640
Figure 967. Cycle time and global time synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3655
Figure 968. TTCAN level 0 and level 2 drift compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3656
Figure 969. Level 0 schedule synchronization state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3663
Figure 970. Level 0 master to slave relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3664
Figure 971. USB subsystem overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3741
Figure 972. USB2 OTG high-speed Port 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3742
Figure 973. USB2 OTG high-speed Port 1 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3743
Figure 974. USB2 OTG high-speed Port 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3746
Figure 975. USB2 OTG high-speed Port 2 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3747
Figure 976. USB Type-C implementation: OTG HS Port 1 example . . . . . . . . . . . . . . . . . . . . . . . . . 3750
Figure 977. USB Type-C and power delivery block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3751
Figure 978. USB Type-C and power delivery reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3752
Figure 979. Multiplexing of debug signals in the USB subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . 3753
Figure 980. OTG1/OTG2 high-speed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3757
Figure 981. OTG A-B device connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3759
Figure 982. OTG peripheral-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3760
Figure 983. OTG host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3764
Figure 984. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . . . . . . . . . . . . 3767
Figure 985. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3769
Figure 986. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . 3770
Figure 987. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . . 3771
Figure 988. Interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3775
Figure 989. Transmit FIFO write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3868
Figure 990. Receive FIFO read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3869
Figure 991. Normal bulk/control OUT/SETUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3870
Figure 992. Bulk/control IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3874
Figure 993. Normal interrupt OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3877
Figure 994. Normal interrupt IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3882

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List of figures RM0486

Figure 995. Isochronous OUT transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3884

Figure 996. Isochronous IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3887
Figure 997. Normal bulk/control OUT/SETUP transactions - DMA . . . . . . . . . . . . . . . . . . . . . . . . . . 3889
Figure 998. Normal bulk/control IN transaction - DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3891
Figure 999. Normal interrupt OUT transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3892
Figure [Link] interrupt IN transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3893
Figure [Link] isochronous OUT transaction - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3894
Figure [Link] isochronous IN transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3895
Figure [Link] FIFO packet read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3901
Figure [Link] a SETUP packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3903
Figure [Link] OUT transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3910
Figure [Link] max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3919
Figure [Link] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3932
Figure [Link] division and timing elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3933
Figure 1009.K-code transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3935
Figure [Link] order for various sizes of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3937
Figure [Link] format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3937
Figure [Link] format of Hard Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3938
Figure [Link] format of Cable Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3938
Figure [Link] test data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3939
Figure [Link] Carrier Mode 2 frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3940
Figure [Link] BMC transmitter architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3940
Figure [Link] BMC receiver architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3942
Figure [Link] high-level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3974
Figure [Link] transmission flow (standard mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3976
Figure [Link] transmission flow (OSP mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3978
Figure [Link] DMA flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3980
Figure [Link] of MAC transmission flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3983
Figure [Link] reception flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3985
Figure [Link] filtering sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4002
Figure [Link] time synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4016
Figure [Link] delay calculation in clocks supporting
peer-to-peer path correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4017
Figure [Link] time update using fine correction method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4027
Figure [Link] aware shaper implementation for traffic scheduling. . . . . . . . . . . . . . . . . . . . . . . . 4039
Figure [Link] a guard band to avoid delays due to interfering frames . . . . . . . . . . . . . . 4040
Figure [Link] governing gate close and open events block diagram
(from IEEE 802.1 Qbv specifications) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4041
Figure [Link] and associated registers - BaseTime and CycleTime . . . . . . . . . . . . . . . . . . . . . . 4045
Figure [Link] and associated registers - BaseTime and CycleTime list execution
time > CycleTime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4046
Figure [Link] to a new Configuration that is Aligned with the Existing Configuration. . . . . . 4047
Figure [Link] to the New List by Truncating the Current List . . . . . . . . . . . . . . . . . . . . . . . . 4049
Figure [Link] to New List By Extending the Current List . . . . . . . . . . . . . . . . . . . . . . . . . . . 4050
Figure [Link] formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4054
Figure [Link] data Alignment Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4059
Figure [Link]-based scheduler implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4067
Figure [Link]-based scheduling flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4068
Figure [Link] segmentation offload overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4074
Figure [Link] segmentation offload flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4075
Figure [Link] and payload fields of segmented packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4078
Figure [Link] PHY interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4088

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Figure [Link] Interface block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4089

Figure [Link] packet structure (Clause 45) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4090
Figure [Link] packet structure (Clause 22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4091
Figure [Link] write operation flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4092
Figure [Link] data packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4093
Figure [Link] data packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4093
Figure [Link] independent interface (MII) signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4095
Figure [Link] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4097
Figure [Link] bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4098
Figure [Link] bit order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4099
Figure [Link] block diagram and interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4100
Figure [Link] transitions (Transmit, 100 Mbds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4109
Figure [Link] Tx clock gating (when LPITCSE = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4110
Figure [Link] transitions (receive, 100 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4111
Figure [Link] ring structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4142
Figure [Link] descriptor ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4144
Figure [Link] tail pointer example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4144
Figure [Link] tail pointer example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4145
Figure [Link] descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4146
Figure [Link] descriptor write-back format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4151
Figure [Link] context descriptor format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4156
Figure [Link] normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4159
Figure [Link] normal descriptor (write-back format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4162
Figure [Link] context descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4170
Figure [Link] normal descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4172
Figure [Link] normal descriptor (write format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4173
Figure [Link] context descriptor (read format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4174
Figure [Link] context descriptor (write format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4175
Figure [Link] of ETH_DMAISR flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4194
Figure [Link] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4370
Figure [Link] diagram of debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4377
Figure [Link] reset control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4379
Figure [Link] TAP state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4384
Figure [Link] successful data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4387
Figure [Link] and access port connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4396
Figure [Link]-M55 debug topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4418
Figure [Link] subsystem CoreSight topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4497
Figure [Link] timestamp distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4503
Figure [Link] cross trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4511
Figure [Link] trigger inputs to outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4514
Figure [Link] state transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4560
Figure [Link]-gather operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4561
Figure [Link] trace macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4620

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1 Documentation conventions

1.1 General information

The STM32N6x7xx devices have an Arm®(a) Cortex®-M55 core.

1.2 List of abbreviations for registers

The following abbreviations(b) are used in register descriptions:

read/write (rw) Software can read and write to this bit.

read-only (r) Software can only read this bit.
write-only (w) Software can only write to this bit. Reading this bit returns the reset value.
read/clear write0 (rc_w0) Software can read as well as clear this bit by writing 0. Writing 1 has no
effect on the bit value.
read/clear write1 (rc_w1) Software can read as well as clear this bit by writing 1. Writing 0 has no
effect on the bit value.
read/clear write (rc_w) Software can read as well as clear this bit by writing to the register. The
value written to this bit is not important.
read/clear by read (rc_r) Software can read this bit. Reading this bit automatically clears it to 0.
Writing this bit has no effect on the bit value.
read/set by read (rs_r) Software can read this bit. Reading this bit automatically sets it to 1.
Writing this bit has no effect on the bit value.
read/set (rs) Software can read as well as set this bit. Writing 0 has no effect on the bit
value.
read/write once (rwo) Software can only write once to this bit and can also read it at any time.
Only a reset can return the bit to its reset value.
toggle (t) The software can toggle this bit by writing 1. Writing 0 has no effect.
read-only write trigger (rt_w1) Software can read this bit. Writing 1 triggers an event but has no effect on
the bit value.
Reserved (Res.) Reserved bit, must be kept at reset value.

1.3 Register reset value

Bits (binary notation) or bits nibbles (hexadecimal notation) of which the reset value is
undefined are marked as X.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
b. This is an exhaustive list of all abbreviations applicable to STMicroelectronics microcontrollers, some of
them may not be used in the current document.

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Bits (binary notation) or bits nibbles (hexadecimal notation) of which the reset value is
unmodified are marked as U.

1.4 Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
• Debug port definition/acronyms:
– JTAG: Joint Test Action Group protocol, provides 4-pin standard + 1 optional
– SWD: Serial Wire Debug protocol, provides 2-pin interface
• Double word: data of 65-bit length.
• Word: data of 32-bit length.
• Half-word: data of 16-bit length.
• Byte: data of 8-bit length.
• Option bytes: product configuration bits stored in internal fuses.
• OTP: one-time programming (fuses).
• AHB: advanced high-performance bus.
• APB: advanced peripheral bus.
• AXI: Advanced extensible interface protocol.
• ECC: error code correction.
• DMA: direct memory access.

1.5 Availability of peripherals

For availability of peripherals and their number across all devices, refer to the particular
device datasheet.

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2 Memory and bus architecture

2.1 System architecture

2.1.1 Introduction
The device architecture relies on an Arm Cortex-M55 core optimized for execution:
• Main masters:
– Cortex-M55 with Arm TrustZone mainline with two master ports:
> M-AXI provides access to the memory and to peripherals
> P-AHB provides access to peripherals
– NPU (neural processor unit), which includes two master AXI ports
• Memories:
– AHB and APB peripherals
– 4.2 Mbytes of SRAM
– 64 Kbytes I-TCM RAM with ECC for critical real-time routines, and 128 Kbytes of
D-TCM RAM with ECC for critical real-time data
– 8 Kbytes of backup SRAM (BKPSRAM) active in VBAT mode
– 2 x 16-Kbyte AHB RAMs
– Flexible external memory controller (FLEXMEM) with cypher engine supporting up
to 32-bit data bus: SRAM, PSRAM, SDRAM, LPSDR SDRAM, NOR/NAND flash
memories
– XSPIM port2 8-bit configuration with cypher engine
– XSPIM port1 16-bit configuration with cypher engine

2.1.2 Bus architecture

The bus architecture is divided in two domains, high- and low-performance (see Figure 1).

High-speed, multi-frequency domain, AXI compliant interconnect

This high-performance interconnect is mainly used by the CPU, the NPU, and by the
high-bandwidth masters (GPU, DMA2D, GFXMMU, VENC, DCMIPP, LTDC, ETH1,
OTG1/2, SDMMC1/2, HPDMA1 AXI port).
This domain manages accesses to:
• external flash memories and SRAMs (through the FMC and the XSPI manager)
• main system internal memories AXISRAM1/2/3/4/5/6, boot ROM, VENCRAM (when
the VENC is off), and CACHEAXI RAM (when the NPU is off)
• the CPU internal memory (TCM) when accessed by the HPDMA1 AXI and the NPU
Note: The CPU has internally access to the TCM.
• the GFXMMU
• the STM (system trace macrocell)
The CPU uses its M-AXI master port to access the above-described targets.

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The NPU uses a local interconnect (NPU_NIC) to have a direct access to AXISRAM3/4/5/6
and to the CPU TCM. This results in a high-performance and low-latency bus when
accessing these targets.
In addition, data interleaving can be enabled on AXISRAM3/4/5/6 to balance the traffic and
to improve access performance.
The CPU and high-bandwidth masters use another local interconnect called CPU_NOC to
have high-performance access on AXISRAM1/2 and external flash memories.
Note: The boot ROM is accessible only by the CPU through an intermediate interconnect called
CPU_NIC.

Multi-layer AHB interconnect

This interconnect is used to access AHBSRAM1/2, BKPSRAM, and peripherals.
The CPU can reach peripherals mapped in the peripheral region (address range from
0x4000 0000 to 0x5FFF FFFF), using the following masters ports:
• the CPU P-AHB master port for data accesses
• the CPU M-AXI master port for instruction accesses
When P-AHB is disabled, data accesses are performed on M-AXI.
The CPU accesses AHBSRAM1/2 and BKPSRAM through its M-AXI master port. The CPU
memory accesses start on the high-performance interconnect before reaching the AHB
interconnect.
GPDMA1 and HPDMA1 AHB ports are the other masters on this interconnect.
The GPDMA1_P has a dedicated access to APB1/2/4 peripherals.

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 Figure 1. Interconnect top view - STM32N6x7 devices
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Memory and bus architecture

APB1

CK_ICN_M_NPU NPU RAMS GP-DMA3_1

FC ADC1-2
4 x 448KB
NPU
AXISRAM3 AXISRAM4 AXISRAM5
CK_ICN_M_DMA3GP
AXISRAM6 CK_ICN_AHB1
CPU SS AHB1
64 64 + Debug SS APB1
CK_ICN_S_ CK_ICN_S_ CK_ICN_S_ CK_ICN_S_ DMA_APB1
NPU_RAM1 NPU_RAM2 NPU_RAM3 NPU_RAM4 APB
bridge
APB1
DMA_APB2 targets
FC AHB
NPU NIC ITCM & DTCM for DMA3 busmatrix
TCM Async
64 bits D TCM for NPU up DMA
XHB40
CK_ICN_NPUC 0
CK_ICN_NPU CK_CPU 32 bits
DMA_APB4
S-AHB
64

NPU Cacheabale
traffic to FLASHs
P-AHB FC APB2
NPU NON Cacheable

A Sync

32
Traffic + AHB RAMs

CK_ICN_M_GPU2D down APB

APB2 bridge APB2
CK_ICN_M_ CK_ICN_M_ CK_ICN_M_ CK_ICN_M_
FC
OTGHS1 OTGHS2 SDMMC1 SDMMC2 M-AXI targets
GPUSS MDF1

CK_ICN_M_DMA2D
64
GPU2.5D ADF (MDF2)
FC CPU
FC FC FC FC RAMCFG
High Async
NPU Speed USB USB down
NPU CACHE RAM+ TCMs (DMA3)

SD SD
CACH Link HS HS MMC MMC CK_ICN_M_CPU
E CK_ICN_AHB2 APB3
master_ ETH 1 2 1 2
NPU_CACHE_ 256KB 64 64 64 AHB2
AXISRAM3/4/5/6 +

RAM_AUX STM CK_ICN_M_DMA3HP

MEM
TRACE AXI-AP
GPDMA1 APB APB3
FC FC
Video
bridge targets
GPU
CACHE DMA2D GFXMMU VENC DISPLAY RISAFs 3/4/5/6/7
32KB SYNC
RISAF 13 FMC
CG HPDMA1 CK_ICN_AHB3 RISAF 14/22
32 32 32 32 AHB3_NORTH
GPU_M0 AHB2AXI AHB2AXI AHB2AXI AHB2AXI
CPU NIC
64 64 bits
AHB2AXI
DCMIPP
LTDC 64 bits 32 bits SYN
C
RISAFs
XSPIs 10/11/12
CK_ICN_AHB3
BOOTROM
AHB3_SOUTH_WEST

CK_NOC_ETH CK_NOC_CPU CK_NOC_DBG

CK_NOC_USB_SD
AHB1
APB3

64 64 64 64 64 RNG
CK_NOC_CPU CK_NOC_VID

2AXI
CK_NOC_NPUC

AHB
CK_NOC_NPU AHB2 HASH
AHBM
STNOC AXI CRYPT
RM0486 Rev 2

64bits CK_ICN_AHBM AHB3 SAES

PKA + RAM

64 to 32
32 bits
XHB400
RIFSC
CK_NOC_CPU
CK_NOC_AHB CK_ICN_AHB3 IAC
M AHB3_SOUTH
AHB4 RISAFs 0/1/2/8/20/21
APB4
AHB5

FlexMem (400KB) Symbol description APB

APB4
bridge
AXISRAM1 (624KB) Flash Interface GPIO C/D/E/H/Q targets
VENC AXI4 master
BACKUP SYNC
CK_ICN_AHB4
AXISRAM2 (1MB) FMC AHB SRAM1/2 RAM
RAM AXI4 slave (2x16 KB) 8KB AHB4_NORTH
OCTOSPI1/2/3
128KB AHB5 master
System RAMs
2MB AHB5 slave
CK_ICN_S_OCTOSPI2
FC FC CK_ICN_P_IOMNGR APB slave
GPIO O/P/N
FC FC AXI frequency converter
FC
CK_ICN_S_OCTOSPI1 SYNC AHB2AHB Sync bridge HPDMA1 SYNC
CK_ICN_AHB4
CK_ICN_S_OCTOSPI3 MMCx
AHB4_SOUTH_WEST
DB_MMCx
FC FC AHB frequency converter GPU
FC on OCTOSPI 1, 2, 3, IO
slave ports Async ASync GPU_CACHE
USBx
FC
AHB frequency converter on slave port USBx_SYSCO APB4
NF
NON interconnect component (integrated at TOP level) NPU_CACHE GPIO A/F/G
NPU SYNC GPIO B
CK_ICN_AHB5 SYNC FMC RCC
CG Automatic clock gating enabled by default AHB5_NORTH SYNC MCE4 POWERCTL
APB5
CK_ICN_AHB4 CRC
AHB5
CK_NOC_VID Clocks in line with RCC AHB4_SOUTH EXTI
APB
DMA2D bridge
APB5
RISAF_X1 JPEG targets
OCTOSPIx
PSSI
DCMI
SYNC MCE1/2/3
GFXMMU
CK_ICN_AHB5 ETH1
AHB5_SOUTH
MS70497V3

1. The high-performance domain is shown in pink. The low-performance domain is shown in blue.

RM0486
RM0486 Memory and bus architecture

2.2 Bus network-on-chip (NoC)

2.2.1 STNoC AXI

The STM32N6x7xx STNoC AXI interconnect is built out of the ST in-house network-on-chip.
Its main features are:
• Source routed, packet based, wormhole switching forwarding scheme for simultaneous
and parallel/pipelined accesses from master to slave
• Independent read and write input/output points to cope with AXI independent channels
• Size and frequency conversion, asynchronism management
• Fine grain automatic clock gating shutting down the clocks to unused network parts at
any point in time, with zero delay clock resume
• Internal packets buffering for improved traffic efficiency
• Independent request and response network
• Software accessible registers to observe and report traffic statistics, performance,
blocking sources (if any) over the network.

2.2.2 NPU_NIC network interconnect

The NPU_NIC interconnect is based on Arm NIC-400 Network Interconnect. Its main
features are:
• High-performance and low-latency interconnect
• Independent read/write request/response channel as defined in AXI protocol
• Asynchronism management
• Address interleaving to AXISRAM3/4/5/6 (can be disabled by software)
• Static QoS assigned by software used at any arbitration node. The highest value has
the highest priority. Arbitration with same QoS value uses an LRU (least recently used)
algorithm.

2.2.3 Multi-layer AHB interconnect (AHBM)

The multi-layer AHB main features are:
• 32-bit bus matrix running at 200 MHz using a master clock from the RCC
• Simultaneous accesses from different masters to the slaves connected to separated
layers
• Five master ports: CPU P-AHB, HPDMA1, GPDMA1_P /M, and CPU_NOC
• Nine slave ports: memories (AHB SRAM1/2 and BKPSRAM), peripherals for
AHBx/APBx targets, and CPU_NOC target to reach AXI.
Note: The GPDMA1_P has a direct path to APB1, APB2, and APB4 targets. It bypasses this
multi-layer AHB.

RM0486 Rev 2 161/4691

161
 RM0486

2.3 Memory organization

2.3.1 Introduction
Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word’s least significant byte and the highest numbered byte the most
significant.

162/4691 RM0486 Rev 2

RM0486

2.3.2 Memory map and register boundary addresses

Program memory, data memory, registers, and I/O ports are organized within the same
linear 4-Gbyte address space.
The bytes are coded in memory in little-endian format. The lowest numbered byte in a word
is considered the word least significant byte, and the highest numbered byte the most
significant.
All memory map areas that are not allocated to on-chip memories and peripherals are
considered reserved.
The IDAU mapping indicates if a particular memory address is secure or nonsecure.

Table 1. Memory map based on IDAU mapping

IDAU security type Mapping Description

- 0xFFFFFFFF Reserved
- 0xE0100000 Reserved
Cortex-M55 nonsecure 0xE0000000 Cortex-M55 internal peripherals, debug and trace
0xD0000000 SDRAM 2
SDRAM nonsecure
0xC0000000 SDRAM 1
- 0xA0000000 Reserved
0x90000000 XSPI1
XSPI bank nonsecure 0x80000000 XSPI3
0x70000000 XSPI2
SDRAM nonsecure 0x60000000 FMC NOR/SRAM

RM0486 Rev 2 163/4691

179
 RM0486

Table 1. Memory map based on IDAU mapping (continued)

IDAU security type Mapping Description

0x5E000000 Trace and debug

0x58120000 Reserved
0x58020000 AHB5 peripherals
0x58010000 Reserved for APB
0x58000000 APB5 peripherals
0x56030000 Reserved
0x56020000 AHB4 peripherals
0x56010000 Reserved for APB
0x56000000 APB4 peripherals
0x54040000 Reserved
Reserved peripheral secure 0x54020000 AHB3 peripherals
0x54010000 Reserved for APB
0x54000000 APB3 peripherals
0x52040000 Reserved
0x52020000 AHB2 peripherals
0x52010000 Reserved for APB
0x52000000 APB2 peripherals
0x50188000 Reserved
0x50020000 AHB1 peripherals
0x50010000 Reserved
0x50000000 APB1 peripherals

164/4691 RM0486 Rev 2

RM0486

Table 1. Memory map based on IDAU mapping (continued)

IDAU security type Mapping Description

0x4E000000 Trace and debug

0x48120000 Reserved
0x48020000 AHB5 peripherals
0x48010000 Reserved for APB
0x48000000 APB5 peripherals
0x46030000 Reserved
0x46020000 AHB4 peripherals
0x46010000 Reserved for APB
0x46000000 APB4 peripherals
0x44040000 Reserved
Peripherals nonsecure 0x44020000 AHB3 peripherals
0x44010000 Reserved for APB
0x44000000 APB3 peripherals
0x42040000 Reserved
0x42020000 AHB2 peripherals
0x42010000 Reserved for APB
0x42000000 APB2 peripherals
0x40188000 Reserved
0x40020000 AHB1 peripherals
0x40010000 Reserved
0x40000000 APB1 peripherals
0x3C002000 Reserved
0x3C000000 Backup SRAM (8 Kbytes)
0x38008000 Reserved
0x38004000 AHBSRAM2
0x38000000 AHBSRAM1
0x37F00000 STM500 channels (system trace)
0x37EFF000 FMC-NAND
Reserved SRAM/AXI bank secure
0x36000000 Reserved
0x35000000 GFXMMU SLV
0x34420000 Reserved
0x34400000 VENCRAM
0x343C0000 CACHEAXI
0x34350000 AXISRAM6
0x342E0000 AXISRAM5

RM0486 Rev 2 165/4691

179
 RM0486

Table 1. Memory map based on IDAU mapping (continued)

IDAU security type Mapping Description

0x34270000 AXISRAM4
0x34200000 AXISRAM3
Reserved SRAM/AXI bank secure
0x34100000 AXISRAM2
0x34000000 AXISRAM1 (FLEXMEM extension bites on the lower end)
0x30040000 Reserved
Data secure
0x30000000 DTCM - Baseline
0x2C002000 Reserved
0x2C000000 Backup SRAM (8 Kbytes)
0x28008000 Reserved
0x28004000 AHBSRAM2
0x28000000 AHBSRAM1
0x27F00000 STM500 channels (system trace)
0x27EFF000 FMC-NAND
0x26000000 Reserved
0x25000000 GFXMMU SLV
SRAM/AXI bank nonsecure
0x24420000 Reserved
0x24400000 VENCRAM
0x243C0000 CACHEAXI
0x24350000 AXISRAM6
0x242E0000 AXISRAM5
0x24270000 AXISRAM4
0x24200000 AXISRAM3
0x24100000 AXISRAM2
0x24000000 AXISRAM1 (FLEXMEM extension bites on the lower end)
0x20040000 Reserved
Data nonsecure
0x20000000 DTCM - Baseline
0x18020000 Reserved
0x18000000 BootROM 128 Kbytes
Code secure
0x10040000 Reserved
0x10000000 ITCM
0x08020000 Reserved
0x08000000 BootROM 128 Kbytes
Code nonsecure
0x00040000 Reserved
0x00000000 ITCM

166/4691 RM0486 Rev 2

 RM0486
Table 2. Memory map and peripheral register boundary addresses

(Mbytes)
Size
Zone Name IDAU security type Mapping Description

Reserved - 0xE0100000 - 0xFFFFFFFF Reserved

- 512
- - 0xE0000000 - 0xE00FFFFF Cortex-M55 internal peripherals, trace and debug
0xD0000000 - 0xDFFFFFFF SDRAM 2 - Reserved (through FMC) 256
External device 0xC0000000 - 0xCFFFFFFF SDRAM 1 - Remap NOR/SRAM bank (through FMC) 256
0xA0000000 - 0xBFFFFFFF Reserved 512
AXI(D1)

nonsecure 0x90000000 - 0x9FFFFFFF XSPI1 256

0x80000000 - 0x8FFFFFFF XSPI3 256
External RAM
0x70000000 - 0x7FFFFFFF XSPI2 256
RM0486 Rev 2

0x60000000 - 0x6FFFFFFF NOR/SRAM - Remap SDRAM 1 (through FMC) 256

Trace and debug 0x5E000000 - 0x5FFFFFFF Trace and debug 32
Reserved 0x5C000000 - 0x5DFFFFFF Reserved 32
Reserved 0x5A000000 - 0x5BFFFFFF Reserved 32
Reserved Secure 0x58120000 - 0x59FFFFFF Reserved
Peripherals

AHB5 0x58020000 - 0x5811FFFF AHB5 peripherals

32
Reserved 0x58010000 - 0x5801FFFF Reserved for APB
APB5 0x58000000 - 0x5800FFFF APB5 peripherals
Reserved 0x56030000 - 0x57FFFFFF Reserved
AHB4 0x56020000 - 0x5602FFFF AHB4 peripherals
Secure 32
Reserved 0x56010000 - 0x5601FFFF Reserved for APB
APB4 0x56000000 - 0x5600FFFF APB4 peripherals
167/1999
 Table 2. Memory map and peripheral register boundary addresses (continued)
168/1999

(Mbytes)
Size
Zone Name IDAU security type Mapping Description

Reserved 0x54040000 - 0x55FFFFFF Reserved

AHB3 0x54020000 - 0x5403FFFF AHB3 peripherals
32
Reserved 0x54010000 - 0x5401FFFF Reserved for APB
Reserved 0x54000000 - 0x5400FFFF APB3 peripherals
Reserved 0x52040000 - 0x53FFFFFF Reserved
AHB2 0x52020000 - 0x5203FFFF AHB2 peripherals
Secure 32
Reserved 0x52010000 - 0x5201FFFF Reserved for APB
Reserved 0x52000000 - 0x5200FFFF APB2 peripherals
RM0486 Rev 2

Reserved 0x50188000 - 0x51FFFFFF Reserved

AHB1 0x50020000 - 0x50187FFF AHB1 peripherals
32
Peripherals

APB2 0x50010000 - 0x5001FFFF Reserved

APB1 0x50000000 - 0x5000FFFF APB1 peripherals
Trace and debug 0x4E000000 - 0x4FFFFFFF Trace and debug 32
Reserved 0x4C000000 - 0x4DFFFFFF Reserved 32
Reserved 0x4A000000 - 0x4BFFFFFF Reserved 32
Reserved 0x48120000 - 0x49FFFFFF Reserved
AHB5 0x48020000 - 0x4811FFFF AHB5 peripherals
32
Reserved nonsecure 0x48010000 - 0x4801FFFF Reserved for APB
APB5 0x48000000 - 0x4800FFFF APB5 peripherals
Reserved 0x46030000 - 0x47FFFFFF Reserved
AHB4 0x46020000 - 0x4602FFFF AHB4 peripherals
32

RM0486
Reserved 0x46010000 - 0x4601FFFF Reserved for APB
APB4 0x46000000 - 0x4600FFFF APB4 peripherals
 Table 2. Memory map and peripheral register boundary addresses (continued)

RM0486
(Mbytes)
Size
Zone Name IDAU security type Mapping Description

Reserved 0x44040000 - 0x45FFFFFF Reserved

AHB3 0x44020000 - 0x4403FFFF AHB3 peripherals
32
Reserved 0x44010000 - 0x4401FFFF Reserved for APB
Reserved 0x44000000 - 0x4400FFFF APB3 peripherals
Reserved 0x42040000 - 0x43FFFFFF Reserved
Peripherals

AHB2 0x42020000 - 0x4203FFFF AHB2 peripherals

nonsecure 32
Reserved 0x42010000 - 0x4201FFFF Reserved for APB
Reserved 0x42000000 - 0x4200FFFF APB2 peripherals
RM0486 Rev 2

Reserved 0x40188000 - 0x41FFFFFF Reserved

AHB1 0x40020000 - 0x40187FFF AHB1 peripherals
32
APB2 0x40010000 - 0x4001FFFF Reserved
APB1 0x40000000 - 0x4000FFFF APB1 peripherals
- 0x3C002000 - 0x3FFFFFFF Reserved
64
AHB_IC2_L5 0x3C000000 - 0x3C001FFF Backup SRAM
SRAM

- Secure 0x38008000 - 0x3BFFFFFF Reserved

AHB_IC2_L1 0x38004000 - 0x38007FFF AHBSRAM2 64
AHB_IC2_L0 0x38000000 - 0x38003FFF AHBSRAM1
169/1999
 Table 2. Memory map and peripheral register boundary addresses (continued)
170/1999

(Mbytes)
Size
Zone Name IDAU security type Mapping Description

- 0x37F00000 - 0x37FFFFFF STM channels (system trace)

- 0x37EFF000 - 0x37EFFFFF FMC-NAND
AXI_ICI_GFX 0x36000000 - 0x37EFEFFF Reserved
- 0x35000000 - 0x35FFFFFF GFXMMU SLV
- 0x34420000 - 0x34FFFFFF Reserved
- 0x34400000 - 0x3441FFFF VENCRAM
AXI_IC1_L4-C 0x343C0000 - 0x343FFFFF CACHEAXI 64
- 0x34350000 - 0x343BFFFF AXISRAM6
Secure
RM0486 Rev 2

AXI_IC1_L4 0x342E0000 - 0x3434FFFF AXISRAM5

- 0x34270000 - 0x342DFFFF AXISRAM4
SRAM

AXI_IC1_L3 0x34200000 - 0x3426FFFF AXISRAM3

AXI_IC1_L2 0x34100000 - 0x341FFFFF AXISRAM2
AXI_IC1_L1 0x34000000 - 0x340FFFFF AXISRAM1 (FLEXMEM extension bites on the lower end)
0x30040000 - 0x33FFFFFF Reserved
DTCM 0x30020000 - 0x3003FFFF DTCM - FLEXMEM extension 64
0x30000000 - 0x3001FFFF DTCM - Base line
- 0x2C002000 - 0x2FFFFFFF Reserved
64
AHB_IC2_L5 0x2C000000 - 0x2C001FFF BKPSRAM
- nonsecure 0x28008000 - 0x2BFFFFFF Reserved
AHB_IC2_L1 0x28004000 - 0x28007FFF AHBSRAM2 64
AHB_IC2_L0 0x28000000 - 0x28003FFF AHBSRAM1

RM0486
 Table 2. Memory map and peripheral register boundary addresses (continued)

RM0486
(Mbytes)
Size
Zone Name IDAU security type Mapping Description

- 0x27F00000 - 0x27FFFFFF STM channels (system trace)

- 0x27EFF000 - 0x27EFFFFF FMC-NAND
AXI_ICI_GFX 0x26000000 - 0x27EFEFFF Reserved
- 0x25000000 - 0x25FFFFFF GFXMMU SLV
- 0x24420000 - 0x24FFFFFF Reserved
- 0x24400000 - 0x2441FFFF VENCRAM
AXI_IC1_L4-C 0x243C0000 - 0x243FFFFF CACHEAXI 64
- 0x24350000 - 0x243BFFFF AXISRAM6
SRAM

nonsecure
RM0486 Rev 2

AXI_IC1_L4 0x242E0000 - 0x2434FFFF AXISRAM5

- 0x24270000 - 0x242DFFFF AXISRAM4
AXI_IC1_L3 0x24200000 - 0x2426FFFF AXISRAM3
AXI_IC1_L2 0x24100000 - 0x241FFFFF AXISRAM2
AXI_IC1_L1 0x24000000 - 0x240FFFFF AXISRAM1 (FLEXMEM extension bites on the lower end)
0x20040000 - 0x23FFFFFF Reserved
DTCM 0x20020000 - 0x2003FFFF DTCM - FLEXMEM extension 64
0x20000000 - 0x2001FFFF DTCM - Base line
0x1C080000 - 0x1FFFFFFF Reserved
0x1C000000 - 0x1C07FFFF Reserved
AXI_IC1_L0 128
0x18020000 - 0x1BFFFFFF Reserved
CODE

Secure 0x18000000 - 0x1801FFFF BootROM

0x10040000 - 0x17FFFFFF Reserved
171/1999

ITCM 0x10010000 - 0x1003FFFF ITCM - FLEXMEM extension 128

0x10000000 - 0x1000FFFF ITCM - Base line
 Table 2. Memory map and peripheral register boundary addresses (continued)
172/1999

(Mbytes)
Size
Zone Name IDAU security type Mapping Description

0x0C080000 - 0x0FFFFFFF Reserved

0x0C000000 - 0x0C07FFFF Reserved
AXI_IC1_L0 128
0x08020000 - 0x0BFFFFFF Reserved
CODE

nonsecure 0x08000000 - 0x0801FFFF BootROM

0x00040000 - 0x07FFFFFF Reserved
ITCM 0x00010000 - 0x0003FFFF ITCM - FLEXMEM extension 128
0x00000000 - 0x0000FFFF ITCM - Baseline
RM0486 Rev 2

RM0486
RM0486

Table 3. Peripheral register boundary addresses

nonsecure Size
Bus Secure boundary address Description
boundary address (Kbytes)

0x58100000 - 0x5811FFFF 0x48100000 - 0x4811FFFF Reserved (for AHB periph) 128

0x580E0000 - 0x580FFFFF 0x480E0000 - 0x480FFFFF NPU 128
0x580DFC00 - 0x580DFFFF 0x480DFC00 - 0x480DFFFF CACHEAXI 1
0x580C0400 - 0x580DFBFF 0x480C0400 - 0x480DFBFF Reserved (NPU) 126
0x580C0000 - 0x580C03FF 0x480C0000 - 0x480C03FF OTG2PHYCTL 1
0x58080000 - 0x580BFFFF 0x48080000 - 0x480BFFFF OTG2_HS 256
0x58040000 - 0x5807FFFF 0x48040000 - 0x4807FFFF OTG1_HS 256
0x5803FC00 - 0x5803FFFF 0x4803FC00 - 0x4803FFFF OTG1PHYCTL 1
0x58037400 - 0x580377FF 0x48037400 - 0x480377FF Reserved 34
0x58036000 - 0x580373FF 0x48036000 - 0x480373FF ETH1 5
0x58035400 - 0x58035FFF 0x48035400 - 0x48035FFF Reserved (ETH1) 3
0x58035000 - 0x580353FF 0x48035000 - 0x480353FF GPU cache (ICACHE) 1
0x58034000 - 0x58034FFF 0x48034000 - 0x48034FFF GPU2D 4
0x58030000 - 0x58033FFF 0x48030000 - 0x48033FFF GFXMMU 16
0x5802E400 - 0x5802FFFF 0x4802E400 - 0x4802FFFF Reserved 7
0x5802E000 - 0x5802E3FF 0x4802E000 - 0x4802E3FF MCE4 1
AHB5

0x5802D000 - 0x5802DFFF 0x4802D000 - 0x4802DFFF XSPI3 4

0x5802C400 - 0x5802CFFF 0x4802C400 - 0x4802CFFF Reserved (XSPI3) 3
0x5802C000 - 0x5802C3FF 0x4802C000 - 0x4802C3FF MCE3 1
0x5802BC00 - 0x5802BFFF 0x4802BC00 - 0x4802BFFF MCE2 (former OTFDEC2) 1
0x5802B800 - 0x5802BBFF 0x4802B800 - 0x4802BBFF MCE1 (former OTFDEC1) 1
0x5802B400 - 0x5802B7FF 0x4802B400 - 0x4802B7FF XSPIM (XSPI I/O manager) 1
0x5802B000 - 0x5802B3FF 0x4802B000 - 0x4802B3FF Reserved (delay block XSPI2) 1
0x5802A000 - 0x5802AFFF 0x4802A000 - 0x4802AFFF XSPI2 4
0x58028800 - 0x58029FFF 0x48028800 - 0x48029FFF Reserved 6
0x58028400 - 0x580287FF 0x48028400 - 0x480287FF DCMI 1
0x58028000 - 0x580283FF 0x48028000 - 0x480283FF DLYB1 1
0x58027000 - 0x58027FFF 0x48027000 - 0x48027FFF SDMMC1 4
0x58026C00 - 0x58026FFF 0x48026C00 - 0x48026FFF DLYB2 1
0x58026800 - 0x58026BFF 0x48026800 - 0x48026BFF SDMMC2 1
0x58026400 - 0x580267FF 0x48026400 - 0x480267FF PSSI 1
0x58026000 - 0x580263FF 0x48026000 - 0x480263FF Reserved (delay block XSPI1) 1
0x58025000 - 0x58025FFF 0x48025000 - 0x48025FFF XSPI1 4

RM0486 Rev 2 173/4691

179
 RM0486

Table 3. Peripheral register boundary addresses (continued)

nonsecure Size
Bus Secure boundary address Description
boundary address (Kbytes)

0x58024000 - 0x58024FFF 0x48024000 - 0x48024FFF FMC 4

0x58023000 - 0x58023FFF 0x48023000 - 0x48023FFF JPEG 4
0x58022000 - 0x58022FFF 0x48022000 - 0x48022FFF Reserved 4
AHB5

0x58021000 - 0x58021FFF 0x48021000 - 0x48021FFF DMA2D 4

0x58020000 - 0x58020FFF 0x48020000 - 0x48020FFF HPDMA1 4
0x5602A000 - 0x5602FFFF 0x4602A000 - 0x4602FFFF Reserved (for AHB peripherals) 24
0x56028000 - 0x56029FFF 0x46028000 - 0x46029FFF RCC 8
0x56025400 - 0x56027FFF 0x46025400 - 0x46027FFF Reserved 11
0x56025000 - 0x560253FF 0x46025000 - 0x460253FF EXTI 1
0x56024C00 - 0x56024FFF 0x46024C00 - 0x46024FFF CRC 1
0x56024800 - 0x56024BFF 0x46024800 - 0x46024BFF PWR 1
0x56024400 - 0x560247FF 0x46024400 - 0x460247FF Reserved 1
0x56024000 - 0x560243FF 0x46024000 - 0x460243FF GPIO Q 1
0x56023C00 - 0x56023FFF 0x46023C00 - 0x46023FFF GPIO P 1
0x56023800 - 0x56023BFF 0x46023800 - 0x46023BFF GPIO O 1
AHB4

0x56023400 - 0x560237FF 0x46023400 - 0x460237FF GPIO N 1

0x56022000 - 0x560233FF 0x46022000 - 0x460233FF Reserved 5
0x56021C00 - 0x56021FFF 0x46021C00 - 0x46021FFF GPIO H 1
0x56021800 - 0x56021BFF 0x46021800 - 0x46021BFF GPIO G 1
0x56021400 - 0x560217FF 0x46021400 - 0x460217FF GPIO F 1
0x56021000 - 0x560213FF 0x46021000 - 0x460213FF GPIO E 1
0x56020C00 - 0x56020FFF 0x46020C00 - 0x46020FFF GPIO D 1
0x56020800 - 0x56020BFF 0x46020800 - 0x46020BFF GPIO C 1
0x56020400 - 0x560207FF 0x46020400 - 0x460207FF GPIO B 1
0x56020000 - 0x560203FF 0x46020000 - 0x460203FF GPIO A 1

174/4691 RM0486 Rev 2

RM0486

Table 3. Peripheral register boundary addresses (continued)

nonsecure Size
Bus Secure boundary address Description
boundary address (Kbytes)

0x54038000 - 0x5403FFFF 0x44038000 - 0x4403FFFF Reserved (for AHB peripherals) 32

0x54037000 - 0x54037FFF 0x44037000 - 0x44037FFF RISAF23: backup RAM 4
0x54036000 - 0x54036FFF 0x44036000 - 0x44036FFF RISAF22: AHB RAM 1 4
0x54035000 - 0x54035FFF 0x44035000 - 0x44035FFF RISAF21: AHB RAM 0 4
0x54034000 - 0x54034FFF 0x44034000 - 0x44034FFF RISAF15: cache configuration port 4
AHB3

0x54033000 - 0x54033FFF 0x44033000 - 0x44033FFF RISAF14: FMC2 4

0x54032000 - 0x54032FFF 0x44032000 - 0x44032FFF RISAF13: XSPI3 4
0x54031000 - 0x54031FFF 0x44031000 - 0x44031FFF RISAF12: XSPI2 4
0x54030000 - 0x54030FFF 0x44030000 - 0x44030FFF RISAF11: XSPI1 4
0x5402F000 - 0x5402FFFF 0x4402F000 - 0x4402FFFF Reserved 4
0x5402E000 - 0x5402EFFF 0x4402E000 - 0x4402EFFF RISAF9: VENCRAM 4
0x5402D000 - 0x5402DFFF 0x4402D000 - 0x4402DFFF RISAF8: CACHEAXI 4
0x5402C000 - 0x5402CFFF 0x4402C000 - 0x4402CFFF RISAF7: FLEXMEM 4
0x5402B000 - 0x5402BFFF 0x4402B000 - 0x4402BFFF RISAF6: CPU_MST 4
0x5402A000 - 0x5402AFFF 0x4402A000 - 0x4402AFFF RISAF5: NPU_MST1 4
0x54029000 - 0x54029FFF 0x44029000 - 0x44029FFF RISAF4: NPU_MST0 4
0x54028000 - 0x54028FFF 0x44028000 - 0x44028FFF RISAF3: CPU_axiRAM1 4
0x54027000 - 0x54027FFF 0x44027000 - 0x44027FFF RISAF2: CPU_axiRAM0 4
0x54026000 - 0x54026FFF 0x44026000 - 0x44026FFF RISAF1: TCMs 4
AHB3

0x54025400 - 0x54025FFF 0x44025400 - 0x44025FFF Reserved 3

0x54025000 - 0x540253FF 0x44025000 - 0x440253FF IAC 1
0x54024000 - 0x54024FFF 0x44024000 - 0x44024FFF RIFSC 4
0x54022000 - 0x54023FFF 0x44022000 - 0x44023FFF PKA + RAM 8
0x54021400 - 0x54021FFF 0x44021400 - 0x44021FFF Reserved 3
0x54021000 - 0x540213FF 0x44021000 - 0x440213FF SAES 1
0x54020C00 - 0x54020FFF 0x44020C00 - 0x44020FFF Reserved 1
0x54020800 - 0x54020BFF 0x44020800 - 0x44020BFF CRYP1 1
0x54020400 - 0x540207FF 0x44020400 - 0x440207FF HASH 1
0x54020000 - 0x540203FF 0x44020000 - 0x440203FF RNG 1

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Table 3. Peripheral register boundary addresses (continued)

nonsecure Size
Bus Secure boundary address Description
boundary address (Kbytes)

0x52027000 - 0x5203FFFF 0x42027000 - 0x4203FFFF Reserved (for AHB peripherals) 100

0x52026000 - 0x52026FFF 0x42026000 - 0x42026FFF ADF1 (MDF2) 4
0x52025000 - 0x52025FFF 0x42025000 - 0x42025FFF MDF1 4
AHB2

0x52024000 - 0x52024FFF 0x42024000 - 0x42024FFF Reserved 4

0x52023000 - 0x52023FFF 0x42023000 - 0x42023FFF RAMCFG 4
0x52020000 - 0x52022FFF 0x42020000 - 0x42022FFF Reserved 12
0x50100000 - 0x50187FFF 0x40100000 - 0x40187FFF Reserved (for AHB peripherals) 544
0x50022400 - 0x500FFFFF 0x40022400 - 0x400FFFFF Reserved 887
AHB1

0x50022000 - 0x500223FF 0x40022000 - 0x400223FF ADC1/2 1

0x50021000 - 0x50021FFF 0x40021000 - 0x40021FFF GPDMA1 4
0x50020000 - 0x50020FFF 0x40020000 - 0x40020FFF Reserved 4
0x58008000 - 0x5800FFFF 0x48008000 - 0x4800FFFF Reserved (for APB peripherals) 32
0x58006000 - 0x58007FFF 0x48006000 - 0x48007FFF CSI2 HOST wrapper 8
APB5

0x58005000 - 0x58005FFF 0x48005000 - 0x48005FFF VENC H264/JPEG encoder 4

0x58004000 - 0x58004FFF 0x48004000 - 0x48004FFF GFXTIM 4
0x58003000 - 0x58003FFF 0x48003000 - 0x48003FFF Reserved 4
0x58002000 - 0x58002FFF 0x48002000 - 0x48002FFF DCMIPP 4
APB5

0x58001000 - 0x58001FFF 0x48001000 - 0x48001FFF LTDC 4

0x58000000 - 0x58000FFF 0x48000000 - 0x48000FFF Reserved 4

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Table 3. Peripheral register boundary addresses (continued)

nonsecure Size
Bus Secure boundary address Description
boundary address (Kbytes)

0x5600C000 - 0x5600FFFF 0x4600C000 - 0x4600FFFF Reserved 16

0x5600B000 - 0x5600BFFF 0x4600B000 - 0x4600BFFF Reserved 4
0x5600A000 - 0x5600AFFF 0x4600A000 - 0x4600AFFF DTS (16FF version) 4
0x56009000 - 0x56009FFF 0x46009000 - 0x46009FFF BSEC 4
0x56008000 - 0x56008FFF 0x46008000 - 0x46008FFF SYSCFG 4
0x56004C00 - 0x56007FFF 0x46004C00 - 0x46007FFF Reserved(WDG_LS_D2) 13
0x56004800 - 0x56004BFF 0x46004800 - 0x46004BFF IWDG (WDG_LS_D1) 1
0x56004400 - 0x560047FF 0x46004400 - 0x460047FF TAMP 1
0x56004000 - 0x560043FF 0x46004000 - 0x460043FF RTC and backup registers 1
0x56003C00 - 0x56003FFF 0x46003C00 - 0x46003FFF VREFBUF 1
0x56003400 - 0x56003BFF 0x46003400 - 0x46003BFF Reserved 2
APB4

0x56003000 - 0x560033FF 0x46003000 - 0x460033FF LPTIMER5 1

0x56002C00 - 0x56002FFF 0x46002C00 - 0x46002FFF LPTIMER4 1
0x56002800 - 0x56002BFF 0x46002800 - 0x46002BFF LPTIMER3 1
0x56002400 - 0x560027FF 0x46002400 - 0x460027FF LPTIMER2 1
0x56002000 - 0x560023FF 0x46002000 - 0x460023FF Reserved 1
0x56001C00 - 0x56001FFF 0x46001C00 - 0x46001FFF I2C4 1
0x56001800 - 0x56001BFF 0x46001800 - 0x46001BFF Reserved 1
0x56001400 - 0x560017FF 0x46001400 - 0x460017FF SPI6/I2S 1
0x56001000 - 0x560013FF 0x46001000 - 0x460013FF Reserved 1
0x56000C00 - 0x56000FFF 0x46000C00 - 0x46000FFF LPUART1 1
0x56000800 - 0x56000BFF 0x46000800 - 0x46000BFF HDP 1
0x56000000 - 0x460007FF 0x46000000 - 0x460007FF Reserved 2
0x54002400 - 0x5400FFFF 0x44002400 - 0x4400FFFF Reserved (for APB peripherals) 55
0x54002000 - 0x540023FF 0x44002000 - 0x440023FF DFT APB registers 1
APB3

0x54001000 - 0x54001FFF 0x44001000 - 0x44001FFF DBG_MCU 4

0x54000000 - 0x54000FFF 0x44000000 - 0x44000FFF DAP ROM table 4
0x52008000 - 0x5200FFFF 0x42008000 - 0x4200FFFF Reserved (for APB peripherals) 32
APB2

0x52006000 - 0x52007FFF 0x42006000 - 0x42007FFF Reserved 7

0x52005C00 - 0x52005FFF 0x42005C00 - 0x42005FFF SAI2 1

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Table 3. Peripheral register boundary addresses (continued)

nonsecure Size
Bus Secure boundary address Description
boundary address (Kbytes)

0x52005800 - 0x52005BFF 0x42005800 - 0x42005BFF SAI1 1

0x52005400 - 0x520057FF 0x42005400 - 0x420057FF Reserved 1
0x52005000 - 0x520053FF 0x42005000 - 0x420053FF SPI5 1
0x52004C00 - 0x52004FFF 0x42004C00 - 0x42004FFF TIMER9 1
0x52004800 - 0x52004BFF 0x42004800 - 0x42004BFF TIMER17 1
0x52004400 - 0x520047FF 0x42004400 - 0x420047FF TIMER16 (16-bit) 1
0x52004000 - 0x520043FF 0x42004000 - 0x420043FF TIMER15 (16-bit) 1
0x52003C00 - 0x52003FFF 0x42003C00 - 0x42003FFF TIMER18 (16-bit) 1
0x52003800 - 0x52003BFF 0x42003800 - 0x42003BFF Reserved 1
APB2

0x52003400 - 0x520037FF 0x42003400 - 0x420037FF SPI4 1

0x52003000 - 0x520033FF 0x42003000 - 0x420033FF SPI1/I2S1 1
0x52002000 - 0x52002FFF 0x42002000 - 0x42002FFF Reserved 4
0x52001C00 - 0x52001FFF 0x42001C00 - 0x42001FFF USART10 1
0x52001800 - 0x52001BFF 0x42001800 - 0x42001BFF UART9 1
0x52001400 - 0x520017FF 0x42001400 - 0x420017FF USART6 1
0x52001000 - 0x520013FF 0x42001000 - 0x420013FF USART1 1
0x52000800 - 0x52000FFF 0x42000800 - 0x42000FFF Reserved 2
0x52000400 - 0x520007FF 0x42000400 - 0x420007FF TIMER8 (16-bit)/PWM2 1
0x52000000 - 0x520003FF 0x42000000 - 0x420003FF TIMER1 (16-bit)/PWM1 1
0x50010000 - 0x5000FFFF 0x40010000 - 0x4000FFFF Reserved (for APB peripherals) 0
0x5000FC00 - 0x5000FFFF 0x4000FC00 - 0x4000FFFF UCPD 1
0x5000EC00 - 0x5000FBFF 0x4000EC00 - 0x4000FBFF Reserved 4
0x5000E800 - 0x5000EBFF 0x4000E800 - 0x4000EBFF FDCAN3 1
0x5000C000 - 0x5000E7FF 0x4000C000 - 0x4000E7FF CAN memory 10
0x5000AC00 - 0x5000BFFF 0x4000AC00 - 0x4000BFFF Reserved 5
0x5000A800 - 0x5000ABFF 0x4000A800 - 0x4000ABFF CAN calibration unit 1
APB1

0x5000A400 - 0x5000A7FF 0x4000A400 - 0x4000A7FF FDCAN2 1

0x5000A000 - 0x5000A3FF 0x4000A000 - 0x4000A3FF FDCAN1 1
0x50009800 - 0x50009FFF 0x40009800 - 0x40009FFF Reserved 2
0x50009400 - 0x500097FF 0x40009400 - 0x400097FF MDIOS 5
0x50008000 - 0x500093FF 0x40008000 - 0x400093FF Reserved 1
0x50007C00 - 0x50007FFF 0x40007C00 - 0x40007FFF UART8 1
0x50007800 - 0x50007BFF 0x40007800 - 0x40007BFF UART7 4
0x50006800 - 0x500077FF 0x40006800 - 0x400077FF Reserved 1

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Table 3. Peripheral register boundary addresses (continued)

nonsecure Size
Bus Secure boundary address Description
boundary address (Kbytes)

0x50006400 - 0x500067FF 0x40006400 - 0x400067FF I3C2 1

0x50006000 - 0x500063FF 0x40006000 - 0x400063FF I3C1 1
0x50005C00 - 0x50005FFF 0x40005C00 - 0x40005FFF I2C3 1
0x50005800 - 0x50005BFF 0x40005800 - 0x40005BFF I2C2 1
0x50005400 - 0x500057FF 0x40005400 - 0x400057FF I2C1 1
0x50005000 - 0x500053FF 0x40005000 - 0x400053FF UART5 1
0x50004C00 - 0x50004FFF 0x40004C00 - 0x40004FFF UART4 1
0x50004800 - 0x50004BFF 0x40004800 - 0x40004BFF USART3 1
0x50004400 - 0x500047FF 0x40004400 - 0x400047FF USART2 1
0x50004000 - 0x500043FF 0x40004000 - 0x400043FF SPDIFRX 1
0x50003C00 - 0x50003FFF 0x40003C00 - 0x40003FFF SPI3 / I2S3 1
0x50003800 - 0x50003BFF 0x40003800 - 0x40003BFF SPI2 / I2S2 1
0x50003400 - 0x500037FF 0x40003400 - 0x400037FF TIMER11 (basic) 1
APB1

0x50003000 - 0x500033FF 0x40003000 - 0x400033FF TIMER10 (basic) 1

0x50002C00 - 0x50002FFF 0x40002C00 - 0x40002FFF WWDG 1
0x50002800 - 0x50002BFF 0x40002800 - 0x40002BFF Reserved 1
0x50002400 - 0x500027FF 0x40002400 - 0x400027FF LPTIMER1 1
0x50002000 - 0x500023FF 0x40002000 - 0x400023FF TIMER14 (light) 1
0x50001C00 - 0x50001FFF 0x40001C00 - 0x40001FFF TIMER13 (light) 1
0x50001800 - 0x50001BFF 0x40001800 - 0x40001BFF TIMER12 (light) 1
0x50001400 - 0x500017FF 0x40001400 - 0x400017FF TIMER7 (basic) 1
0x50001000 - 0x500013FF 0x40001000 - 0x400013FF TIMER6 (basic) 1
0x50000C00 - 0x50000FFF 0x40000C00 - 0x40000FFF TIMER5 (32-bit) 1
0x50000800 - 0x50000BFF 0x40000800 - 0x40000BFF TIMER4 (32-bit) 1
0x50000400 - 0x500007FF 0x40000400 - 0x400007FF TIMER3 (32-bit) 1
0x50000000 - 0x500003FF 0x40000000 - 0x400003FF TIMER2 (32-bit) 1

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3 System security

3.1 Key security features

• Security isolation using the TrustZone technology of the Arm Cortex-M55
• OS and dynamic user isolation using the Cortex-M55 MPU technology with firewalling
• Multi-tenancy support: configurable firewalls to allow a trusted OS to ensure software
apps installed by different AI providers cannot use the NPU engine or DMA engines to
access each other’s data
• Secure provisioning of customer keys and firmware
• Secure boot-from-ROM authenticating and decrypting images loaded from an external
flash memory or downloaded through UART, USB, I2C, SPI, FDCAN, or JTAG
• Nonvolatile antifuse storage of, for example:
– hardware-unique key (HUK) directly wired to DPA-resistant AES engine
– private key used for secure provisioning of customer keys
– customer-provisioned firmware signing and encryption keys
– customer-provisioned key for managing return material analysis (RMA)
– irreversible counters for key/certificates revocation, updates, factory resets
• Battery-backed volatile storage of, for example:
– customer-provisioned secret boot hardware key (BHK), directly wired to
DPA-resistant AES engine, automatically erased in case of tamper
– anti-rollback counters
• Provisioning of AES keys in non-volatile storage (for example external flash memory),
encrypted with unviewable device-unique keys derived from HUK: a provisioned AES
key is never again viewable on the device, and is only used directly in AES hardware
accelerators to encrypt and decrypt data
• General-purpose cryptographic acceleration:
– Two AES 256-bit engine, supporting ECB, CBC, CTR, GCM, and CCM chaining
modes: one engine DPA-resistant with side-channel counter-measures, and one
fast-implementation engine without DPA-resistance
– HASH processor, supporting SHA-2 secure hash
– PKA (public key accelerator) for RSA/DH (up to 4096 bits) and ECC (up to 640
bits): implements side-channel counter measures and mitigations when
manipulating secrets
– RNG (true random number generator), NIST SP800-90B pre-certified
• Memory cipher engines for on-the-fly decryption of data in external memories:
implements a key derivation function to increase protection against side-channel
attacks (SCA)
• Low-latency encryption engines on NPU bus interfaces: allows AI data to be stored in
encrypted format in both external and internal memories
• Arm PSA temporal isolation enforced by hardware using HDPL (hide protection level)
• Debug authentication scheme based on certificates: confers rights on the debugger at
an authorized security level

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• Active tamper and protection against temperature, voltage, and frequency attacks:
– Up to seven (inputs, outputs) tamper pins, available in all power modes
– Immediate erase of battery-backed volatile secrets on confirmed tamper detection

3.2 Secure boot

On an application reset, the Cortex-M55 always boots from the start of an on-chip ROM.
This ROM code is used to authenticate and decrypt images loaded into the internal memory
from an external flash memory, or through UART, USB, I2C, SPI, FDCAN, or JTAG.
The lifecycle state of the device is represented in the values of specific fuses. Transforming
from one lifecycle state to the next always involves blowing fuses. The boot ROM acts in
accordance with what it finds to be the current lifecycle state.
Lifecycle states can be partitioned into two underlying categories: BSEC-open or
BSEC-closed (refer to Section 4.3.7: Lifecycle management for more details). This is
determined by hardware on every system reset by examining the state of the lifecycle fuses.
If the hardware determines at power-up that the device is BSEC-open, it immediately
enables debug, and disables any access to fused secrets and secure parts of the ROM.
This is referred to as nonsecure boot. The device is in a BSEC-open lifecycle state at the
start of manufacturing. It can be transformed back into a BSEC-open lifecycle state if there
is a fault requiring the part to be returned for analysis.
If the hardware determines that the device is BSEC-closed, the debug remains disabled.
The secure boot from ROM is then enforced, and the boot ROM then consults additional
fuses to determine the precise lifecycle state.
Devices are delivered to customers in a BSEC-closed state, so the boot ROM execution
is enforced.
On a BSEC-closed device, if the secure_boot fuse bit (see Section 5: OTP mapping (OTP))
is still unblown, then the boot ROM behavior depends on the DEV_BOOT pin:
• If the DEV_BOOT pin is set, the boot ROM disables the access to secrets, and opens
the debug to allow customer development.
• If the DEV_BOOT pin is not set, the boot ROM executes the boot image regardless
of whether it is correctly signed.
However, on a BSEC-closed device, once the secure_boot fuse bit is blown, authenticated
secure boot is enforced.
STMicroelectronics supplies signing tools to allow customers to create signed and
encrypted boot images. The boot image is sometimes referred as an FSBL (first-stage
bootloader), or as an uRoT (updatable root-of-trust firmware).

3.3 Secure provisioning

ST supplies customers with an RSSe (Root Security Services extension) code image to
implement SFI (secure firmware install) functionality. The boot ROM authenticates this
RSSe code with a hard-coded public key. ST also provisions an ST-certified device-unique
key pair into fuses. When customers receive the device, they can boot the supplied SFI
image to securely provision their own keys into fuses. The boot ROM uses these keys,
whenever it boots, to authenticate and decrypt the customer boot images. The ST-certified

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device-unique key pair ensures that this provisioning process is secure and counted. This
protects against cloning.
The boot ROM supports up to eight irreversible revocations of firmware signing keys.
The boot image header contains a constant decrypted by the boot ROM using the
provisioned firmware encryption key. This derived key is used to decrypt the actual image.

3.4 Temporal isolation

The Arm PSA specification states:
1. The code in each stage must execute its tasks, complete, then terminate, and
handover execution to the next stage.
2. The code in each stage must leave boot state to carry forward results and data from
one stage to the next.
3. Private data for one stage (especially secrets) must not be directly accessible
from later stages.
The STM32N6x7xx devices define four HDPL:
• 0: Boot ROM
• 1: Updatable root of trust (uRoT)
• 2: Level 2
• 3: Level 3
The HDPL is represented with a monotonically increasing 2-bit counter register
BSEC_HDPLSR (on the system reset), which does not wrap back to zero. Only a secure
privileged software increments this counter (see Section 4: Boot and security control
(BSEC)).
The SAES (secure AES engine) uses an HDPL input when performing a derivation of the
fused HUK to create the DHUK (derived-HUK). The HDPL value seen by the SAES can be
increased to a value higher than the current value, to provision data ready for the next
temporal stage. However, the generated DHUK with a particular HDPL value cannot be re-
generated during later temporal stages (see Section 48: Secure AES coprocessor (SAES)).
Temporal isolation can also be implemented in the fuse wrapper (BSEC) via sticky read
locks and sticky programming locks. The BSEC hardware also ensures that only the boot
ROM accesses certain fuse secrets.

3.5 Resource isolation

In STM32N6x7xx, the runtime software isolation is based on TrustZone.
Each memory address is defined to exist either in the secure or the non-secure world. Some
CPU resources (such as stack-pointer registers, MPU registers, interrupt vector tables, or
timers), are physically banked between worlds. When the CPU executes a secure code
(that is, code fetched from secure-world addresses), it uses the secure-world versions of
these resources. When the CPU executes nonsecure code (that is, code fetched from
nonsecure world addresses), it uses the nonsecure world versions of these resources.
However, for the most part, secure and nonsecure codes use the same CPU hardware.

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A nonsecure code is blocked from accessing secure world addresses. It can call only secure
code (that is, move into the secure world) via SG (secure gate) instructions, which reside in
special secure-world NSC (nonsecure callable) regions.
Trustzone ensures that the operation of a secure code and its data cannot be corrupted by
nonsecure code.

3.5.1 Trustzone filtering using IDAU/SAU

The 256-Mbyte address ranges starting at the even addresses 0x00000000, 0x20000000,
and 0x40000000, are physically aliased at ranges starting at the odd addresses
0x10000000, 0x30000000, and 0x50000000, respectively.
The intention is that the secure world accesses resources via the odd aliases, and the
non-secure world accesses resources via the even aliases.
The address security (S for secure, NSC for nonsecure callable, or NS for non-secure, in
descending security order) is determined by the device IDAU (implementation defined
attribution unit), and the SAU (security attribution unit). Each of these two units proposes a
security level for each address, the resulting level is the higher of the two proposals. The
accesses to addresses determined to be S or NSC travel out on the bus marked as secure,
those determined to be NS travel out on the bus marked as nonsecure.
The secure OS can define up to eight SAU regions, each of which can be configured as NS
or NSC. Any address falling outside a defined SAU region remains secure, hence, at reset,
the SAU unilaterally determines that the entire memory is secure.
The SAU is typically configured to open up NS regions for nonsecure code, data, and
peripherals in the even address aliases. Locations from 0x10000000 to 0x1FFFFFFF (that
contain SG instructions) must be covered by explicit SAU regions configured as NSC.
The IDAU determination of the security of each address is hardwired fixed.
Table 4 shows aliased targets, and the IDAU security assignment.

Table 4. Aliasing
Address region IDAU assignment Aliased targets

0x5------- NSC (secure)

Peripherals
0x4------- NS (nonsecure)
0x3------- NSC (secure)
Internal RAMs, DTCM
0x2------- NS (nonsecure)
0x1------- NSC (secure)
Boot ROM, ITCM
0x0------- NS (nonsecure)

If the SAU is configured sensibly, the IDAU is normally irrelevant. The only potential effect of
the IDAU is to prevent any attempt via the SAU to demote any of the three “odd” NSC
regions listed above to be nonsecure.
A secure software configures the firewalls in front of physical resources (aliased in ranges
listed in Table 4) to determine in which world the access destination resides. This blocks
accesses that arrive marked with a mismatching security attribute. A nonsecure code
cannot access destinations that reside in the secure world (as designated by the firewall).
Destinations are then dedicated for use by the secure world.

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External memories are mapped at addresses from 0x60000000 upwards (not aliased).
The SAU can be configured to allocate portions of these memories to the non-secure world.
These memories have RISAF firewalls in front of them, that can be configured to mirror SAU
settings, and to ensure that DMAs are subject to the same restrictions as CPU code.

3.5.2 Privileged OS-controlled isolation

The Cortex-M55 MPU (memory protection unit) facilitates the isolation between a privileged
operating system, and the user processes it schedules.
The MPU is banked between the secure and nonsecure worlds as follows:
• Secure-world accesses to MPU registers update physical registers in the MPU_S,
which filters accesses that emerge from the SAU marked secure.
• Nonsecure world accesses to MPU registers update physical registers in the MPU_NS,
which filters accesses emerging from the SAU marked nonsecure.
For each world, attributes are defined for 16 non-overlapping regions, and for the remaining
background. The MPU blocks user code from accessing regions marked privileged.
If the MPU is configured to designate a memory region as normal, then all transactions
initiated by the Cortex-55 on the AXI bus emerge as privileged (even if originated from a
user process). Only the MPU prevents CPU user processes from accessing privileged
normal data in SRAM and external flash memories.
When switching from one user process to another, the OS can re-program the MPU and
peripheral firewalls to ensure each process can only access its own data. A user application
may need to use a peripheral with an AXI initiator that continues to operate in background
after the user has been descheduled. To avoid the peripheral being blocked by a modified
MPU regime, the user process must ask the OS to configure the peripheral to operate in
privilege mode on the user's behalf. It is up to the OS to sanity-check the requested
operation. The HPDMA on the AXI bus is a special case (see Section 3.5.4).
The Cortex-M55 PAHBCR register must enable the P-AHB, and configure it to allow
accesses to the peripheral region on the P-AHB bus. The MPU must be configured so that
the peripheral region is execute-never device memory. Accesses to peripherals on the
P-AHB carry the correct privilege level: to save wasting MPU regions, the MPU can be
configured to make the whole peripheral region user-accessible, and to rely on the RISUP
downstream filtering to restrict certain peripherals to OS control.
The Cortex-M55 introduces a PXN (privilege-execute-never) region attribute to prevent
the OS from being tricked into jumping to user code.

3.5.3 RIF infrastructure

Thanks to hardware mechanisms in the bus, the secure OS ensures that resources and
data are available only to agents that operate in the appropriate world, and at the
appropriate privilege level. This infrastructure is named RIF (resource isolation framework).
The RIF consists of five components:
• RIMU: placed on AXI bus initiators to determine which attributes are attached to
accesses
• RISUP: firewalls placed in front of peripheral bus targets to determine which security
and privilege level is allowed to access that peripheral
• RIFSC: centralized block that contains the configuration registers controlling all RIMUs
and RISUPs, and determining other general RIF parameters

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• RISAF: firewalls placed in front of each memory target, with self-contained (local)
configuration registers
• IAC (interrupt access controller): recording all security violation events from all firewalls
around the device, in order to present a single interrupt to the CPU
Some peripherals have built-in firewalls, which are configured locally inside the peripheral.
These peripherals are called RIF-aware.
The IAC has room for 256 interrupt sources, each corresponding to an IAC index from 0 to
255. Interrupts from the RISUPs occupy most of the first 128 indexes. Interrupts from
RIF-aware peripherals and RISAFs occupy indexes from 128 onwards. RISUP and IAC
indexes are aligned. The RISUP associated with the IAC index 32 x + y is programmed to
be secure by setting RISC_SECCFGx[y]. It is programmed to be privileged by setting
RISC_PRIVCFGx[y].
For all RIF firewalling, the security setting of a resource can be configured only by a secure
privileged access: the secure OS can assign a RISAF base region to the nonsecure OS.
The nonsecure OS determines the position, privilege, and readability of subregions within
the base region.
If the resource is set to secure, nonsecure accesses to this resource are blocked. If the
resource is set to nonsecure, secure accesses to memories are blocked (no restrictions
for peripherals).
For all RIF firewalling, the privilege setting of a resource is only configurable by a privileged
access: if the resource has already been configured to be secure, the access must also be
secure. If a resource is set to privileged, only privileged accesses are allowed (no restriction
if set to unprivileged).
By default, the reset condition for peripheral firewalls is nonsecure unprivileged, for
memories is secure privileged. In any case, the Cortex-55 boots in secure mode: the secure
software can immediately establish a security regime.
On detecting a violation, a RISAF records locally the attributes of the violating access, and
sets an output error signal: its rising edge is captured in the IAC, which can then interrupt
the CPU. The handler must first clear the associated flag in the IAC, then clear the error
condition recorded in the RISAF.
An illegal access generates a bus error only if it is an instruction fetch.

3.5.4 Multi-tenancy
Several AI network providers may need to have their private NPU data on the device at the
same time. This is referred to as multi-tenancy, where providers are considered as tenants
on the device.
The secure OS needs to ensure that one tenant cannot snoop or corrupt the private NPU
data of another tenant.
Note: Tenants must all trust the secure OS to implement the isolation.
To facilitate the isolation between the NPU networks of distinct tenants, and other CPU
software, the RIF and bus infrastructure support the concept of compartments. An AXI bus
transaction carries a 3-bit CID value that identifies the transaction initiator compartment.
The secure OS configure the RISAF firewalls in front of memories on the AXI buses to filter
accesses according to the carried CID.

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A RISAF treats a CID = 7 as a wildcard: if it allows an access with CID = n, it also allows it
with CID = 7 instead. The CID used by AXI transactions from the DAP is defined by DAPCID
in RIFSC_RIMC_CR. This bitfield is reset to seven, but can be changed by a secure
privileged access.
The CPU always issues transactions on the AXI bus with CID = 1. Only the CPU initiates
transactions on the AHB bus (directly, or indirectly via the DMA). The AHB does not carry
a CID bus: implicitly all transactions to peripherals occurring on the AHB bus have CID = 1.
In a multi-tenancy scenario, a distinct CID (values ≠ 1 and ≠7) is assigned to each tenant.
The secure OS configures the RISAFs to ensure tenant data are only accessible by
accesses carrying the tenant CID. Before allocating temporary exclusive NPU use to a
particular tenant, the secure OS configures the RIFSC: the NPU RIMUs ensure AXI reads
and writes are made with the CID of this tenant. This ensures the NPU cannot be used to
snoop the data of a different tenant.
A mechanism on STM32N6x7xx devices allows a secure tenant to use the HPDMA to move
its own data, but no-one else's. The secure OS can allocate an HPDMA channel n to a
tenant c by setting SCID = c in HPDMA_CnCIDCFGR. This ensures that transfers on this
channel can be set up only by configuration writes that carry CID = c. Tenants operate as
user processes, so such an allocated channel n must be configured with bit n = 0 in
HPDMA_PRIVCFGR (unprivileged). The mechanism is available only for tenants operating
in the secure world, so the secure OS must set bit n = 1 in HPDMA_SECCFGR. AXI
transactions made by the channel carry security, privilege, and cid attributes that match
what these registers are set to.
Just before scheduling a tenant's user process, the secure OS must write the tenant CID
in SYSCFG_SEC_AIDCR. This ensures that all AHB secure user accesses which arrive at
the HPDMA, appear to carry that CID. The tenant’s secure user process is then only able to
use secure HPDMA channels allocated to its own CID. When descheduling the tenant’s
secure user process, the secure OS resets SYSCFG_SEC_AIDCR to 1. The tenant’s
HPDMA job continues to operate in the background. Other user processes cannot interfere
with HPDMA channels belonging to that tenant.
The SYSCFG_SECPRIV_AIDCR register plays the same role for AHB secure privileged
accesses which arrive at the HPDMA. The interrupt handler for a DMA channel allocated
to a tenant user must configure this register in order to interrogate and clear the interrupt
registers in this DMA channel.
SYSCFG_SEC_AIDCR and SYSCFG_SECPRIV_AIDCR affect only the CID of secure
accesses. Nonsecure accesses always carry a CID of 1 (for example the CPU).
All other AXI initiators have RIMUs: what was described above for the NPU can be applied
to other AXI initiators (but using the RISUP and RIMUs).

3.5.5 NPU timeslicing

If two AI networks come from different tenants who expect their data to be isolated from
each other, a privileged software (trusted by both networks and running at a higher privilege
or security level) must decide which tenant has exclusive use of the NPU at any given time.
The OS only opens the RISUP on the NPU configuration port to user accesses while this
particular tenant user process is running.
Before allocating exclusive NPU use to a tenant network, the secure OS arranges
for the following:
• Reprogram all keys in the NPU.

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• Clean the internal NPU state (registers and internal RAM).

• Program the NPU RIMC with a CID used in the RISAFs to protect the tenant data.
The RIMUs on the NPU initiator ports ensure that NPU accesses made on behalf of the
tenant are made with the appropriate CID.
Note: Any software that accesses the NPU configuration port thereby accesses any data that
the NPU accessed to. Each tenant trusts the secure OS to ensure that, while the NPU
operates with a tenant CID, only the tenant software driver process accesses the NPU
configuration port via the RISUP. When the secure OS switches to another tenant driver
process, it must close the NPU RISUP: other processes cannot take control of the NPU
while it is still processing the current tenant data.

3.5.6 NPU cache (CACHEAXI) management

The CID and security bits of an access that arrives at the CACHEAXI are treated exactly as
if they were four extra address tag bits. This implies that cached data cannot be shared
between two NPU networks with distinct CIDs: this may result in the same physical memory
data appearing in two distinct cache lines (incoherency). The software must ensure that
such shared data is uncacheable.
The privileged bit of an access is also stored in the cache line, and used during eviction. It is
not treated as an address tag bit (not taken into account in deciding whether there is a HIT
or MISS). The code must not attempt to lower the privilege level in the NPU RIMC without
first flushing the cache: this may result in the user-level network reading data that had been
left in the cache when the network was privileged.
With these mechanisms, it is not necessary to flush the whole CACHEAXI when the secure
OS hands the NPU use from one tenant to another, at a time period boundary.
The CACHEAXI has a configuration port that allows the software to perform maintenance
operations. For example, the user software may need to ensure dirty cache lines are
cleaned (written back to memory) in order to restore system coherency with the CPU. Some
dirty cache lines may must be invalidated without cleaning them (for example, when there is
a problem with the downstream memory). Such an invalidate-only operation could be used
by an NPU user to subvert the operation of another NPU user. The RISAF filter in front of
each cache configuration port can be configured to ensure that invalidate-only operations
are performed only by commands (written on the cache configuration port) coming from the
secure OS (highest authority).

3.5.7 Memory firewalls

Each RISAF protecting a memory supports up to seven base regions: two subregions are
associated with each base region.
Only the secure OS configures the permissions of a base region. Locations outside any
enabled region belong to the secure OS.
If the secure OS configures a base region to reside in the nonsecure world, it can delegate
control of the corresponding two subregions to the nonsecure OS. The nonsecure OS can
then position subregion windows for tenants.
Note: The security level of a subregion cannot be raised relative to its encompassing base region.
Although a base region can be made accessible by several CIDs, a subregion is dedicated
to a single CID.

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If the nonsecure OS needs to control more subregions (for example four), the secure OS
can set up two identical base regions, both delegated to the nonsecure OS.

3.5.8 RIF-aware peripherals

Direct memory access controllers (GP/HPDMA)
The security attributes of each DMA channel can be configured separately. When a DMA
channel is configured as secure, the source and destination transfers can be independently
set as secure or nonsecure by a secure application: this is done with SSEC and DSEC
in GP/HPDMA_CxTR1. Linked lists must be in the secure-world memory.
When a DMA channel is configured to be nonsecure, linked lists must be in the nonsecure
world memory. SSEC and DSEC must also both be zero, otherwise the transfer does not
proceed.
When a DMA channel is configured to be unprivileged, the linked lists, source, and
destination must all be in unprivileged locations.
As mentioned in Section 3.5.4, HPDMA channels can be allocated to a compartment. The
OS can allow a scheduled user process to use this channel. Accesses made by this channel
(even after a user process descheduling) carry the compartment CID: this facilitates
isolation between user processes.
See Section 18: High-performance direct memory access controller (HPDMA). The software
should leave HPDMA_CxCIDCFGR[SEM_EN] = 0, since a semaphore mechanism is
intended to allow multiple concurrent CPUs to share a resource, and there is only one CPU.

Power control (PWR)

PWR registers are secured through PWR_SECCFGR and PWR_PRIVCFGR, individually
protecting the following features:
• system supply configuration
• voltage scaling
• low-power mode
• wake-up (WKUP) pins
• voltage detection and monitoring
• backup domain control.
When a GPIOx is configured as secure (respectively privileged), the corresponding bits
in PWR_IORETENRx and PWR_IORETRx (control the pin standby configuration) become
secure (respectively privileged) (see Section 13: Power control (PWR) for details).

Secure clock and reset (RCC)

RIFSC security settings are transmitted to the RCC. If a peripheral RISUP is programmed
as secure (respectively privileged), the peripheral clock and reset bits become secure
(respectively privileged).
The following configurations can be made secure-only and/or privileged-only,
using RCC_SECCFGR and RCC_PRIVCFGR:
• external clock (such as HSE or LSE), internal oscillator (such as HSI, MSI, or LSI)
• main PLL and AHB prescaler
• system clock-source selection

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• MCO clock output

• reset flag
• automatic internal oscillator wake-up configuration
See Section 14: Reset and clock control (RCC) for details.

Real time clock (RTC)

The following RTC features can be individually made secure-only and/or privileged-only:
alarm A, alarm B, calibration, initialization, timestamping, and wake-up (see Section 61:
Real-time clock (RTC) for details).
Note: The RTC security configuration is not affected by a system reset.

Tamper and backup registers (TAMP)

The control of the main tamper functionality can be made secure-only and/or privileged-only.
The TAMP also contains a monotonic counter register for anti-rollback functions. Its use can
be made secure-only and/or privileged-only.
The backup registers can be partitioned by a secure privileged software into three zones:
• protection zone 1: fully accessible for both secure and nonsecure
• protection zone 2: secure read/write, but read-only for nonsecure
• protection zone 3: secure-privileged
The privilege level of zones 1 and 2 can also be individually configured (see Section 62:
Tamper and backup registers (TAMP) for details).

Liquid-crystal thin-film transistor display controller (LTDC)

The LTDC address space is split into three sections (common, layer1, and layer2), which
are protected by a RISUP. Security and privilege settings of each region are determined
by RIFSC registers.
The hardware ensures that, if both layers are configured to occupy the same virtual level,
layer2 is displayed on top of layer1. When both secure and nonsecure softwares use
a layer, the secure software must configure:
• layer1 as nonsecure
• layer2 as secure
• layer2 to occupy the top virtual layer (malicious nonsecure software never obscures it)
The common section can be set as secure or nonsecure.

General-purpose I/Os (GPIO)

Each GPIO port contains two 16-bit registers: GPIOx_SECCFGR and GPIOx_PRIVCFGR.
These registers are only writable by the secure OS. They determine the security and
privilege levels to configure each of the 16 pins of a GPIO port. Outputs of these registers
are also wired to the PWR, where they determine permission to configure the retention
behavior of each pin.
At reset, unlike all other peripherals, each GPIO pin is configured as secure by default. This
simply an extra-physical-robustness feature: the CPU boots in secure-privileged mode, and
can initialize all GPIOs as secure anyway.

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When a digital AF is used (input/output mode), if the peripheral is configured as secure,

the I/O pin must also be secure, otherwise input and output are zeroed. This stops
non-secure software snooping or interfering with a secure I/O communication.
The ADC12 can control an analog switch in the GPIO. This switch is forced open when
the ADC12 is nonsecure and the I/O is secure: this prevents secure analog inputs to be
directed to a nonsecure peripheral.
Table 5 lists input/output signals that are not blocked when the I/O is set as secure and the
associated peripheral is nonsecure.
Example: when a secure application sets PA0 as secure to be used as UART4_TX, if TAMP
is nonsecure, it can be programmed to capture the USART input traffic through
the TAMP_IN signal.
For each case described in the table below, the secure application must decide whether
there is a potential effect on data integrity or confidentiality, and whether it is critical or not.

Table 5. Nonsecure peripheral functions that can be connected to secure I/Os

Bitfield to set to make the
Peripheral Signal(1) Input Output
peripheral secure

TAMP_INx (x = 1 to 7) X -
TAMP TAMPSEC in TAMP_SECCFGR
TAMP_OUTx (x = 1 to 6, 8) - X
RTC_OUTx (x = 1, 2) - X SEC in RTC_SECCFGR
RTC
RTC_TS X - TSSEC in RTC_SECCFGR
PWR WKUPx (x = 1 to 8) X - WUPxSEC in PWR_SECCFGR
RCC LSCO - X LSSEC in RCC_SECCFGR
EXTI EXTIx (x=0 to 22) X - SECx in EXTI_SECCFGR
1. To find the I/O corresponding to the signal/function on the package, refer to the product datasheet.

Refer to Section 15: General-purpose I/Os (GPIO) for more details.

Extended interrupts and event controller (EXTI)

The EXTI can be configured to make individual events secure-only and/or privileged-only
(see Section 25: Extended interrupts and event controller (EXTI) for more details).

System configuration controller (SYSCFG)

All SYSCFG registers are secure-writable only (see Section 16: System configuration
controller (SYSCFG) for more details).

Microcontroller debug unit (DBGMCU)

The MCU debug component (DBGMCU) contains registers to stop (freeze) a peripheral.
If a secure debug is not authorized, the DAP is only able to make nonsecure accesses
on the bus. It is not possible to freeze secure peripherals. The stop bits are writable
in accordance with the security level of the associated peripheral.
Refer to Section 78: Debug support (DBG) for more details

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3.6 Secure storage

3.6.1 Battery backup registers

Secrets can be stored in backup registers. The secure-privileged software ensures that
some or all registers are not accessible to lower security or privileged levels.
The 256-bit BHK is wired directly to a key derivation block in the SAES: it is used to derive
further secret keys. The BHK can be made unreadable after being written.
Use of the BHK and access to backup registers and backup RAM, are blocked while
a potential tamper is flagged.
The secrets are erased by a reset of the VBAT battery-backup domain. Such a reset may be
as a result of a legitimate “factory-reset” procedure, or because of a confirmed tamper.
The secrets can subsequently be updated, if the device needs to be re-deployed.

3.6.2 Secure RAM and registers

The 16-Kbyte AHB SRAM2 aliased at 0x28004000 and 0x38004000 is called secure RAM:
it is erased on reset and on a confirmed tamper, and blocked during a potential tamper
(reads are zeroed, writes are ineffective). See Section 62: Tamper and backup registers
(TAMP) for details of the tamper mechanism.
MCE key registers are also considered as security assets: they are immediately erased on a
confirmed tamper.
Some SRAMs are erased by hardware on reset (see Section 10.3: RAMCFG functional
description).

3.6.3 Fuse secrets

These are provisioned by ST, or by the customer. The secrets can only be read from the
BSEC by secure-privileged software. The BSEC offers the possibility to sticky-read-lock
fuse secrets: a secure software can hide a secret after it has been used (that is, implement
HDPL). Fused secrets can never subsequently be updated.
Fuse words 376 to 383 (HUK) are provisioned automatically with a random number during
manufacturing. The fused value is wired directly to the hardware SAES engine, and cannot
be handled by software. It is unique to the device, and not readable by it. It constitutes a PU
(physically unclonable function).

3.6.4 Hardware key management

Figure 2 shows how key management service applications use the DPA-resistant SAES
engine to provision keys to the external flash memory, or fuses in encrypted form (encrypted
with a device-unique key derived from HUK and/or BHK). The provisioned key can
subsequently be used to encrypt/decrypt data, it cannot be directly handled by the software.

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Figure 2. Key management principle

BSEC fuses Battery-powered always-on domain (VBAT)

RTC
Epoch HUK
BHK

SAES
TIL Derivation
Software key

KMOD

Data in DPA AES Data

out
Software
key

CRYP
Data
Data in Fast AES
out

Private bus, inaccessible by any software Standard communication bus

MSv70105V2

The mechanism is based on KMOD[1:0] and KEYSEL[2:0] in SAES_CR The decryption

result is read out and handled by software only when KMOD = 0b00. If KMOD ≠ 0 and
KEYSEL is selecting the output of the derivation function, the decryption result goes directly
on dedicated buses to key registers in the SAES (when KMOD = 0b01), or (when
KMOD = 0b10) to the fast CRYP1. KMOD is also an input to the derivation function that
processes the device secret HUK and BHK
A key to be provisioned in the device can be encrypted with a device-unique key (derived
from HUK and/or BHK) with KMOD = 0b01 or 0b10 in SAES_CR. This key is then stored
somewhere in encrypted format. When this encrypted key needs to be used, it can only be
successfully decrypted with the same KMOD setting. The key cannot now be output as clear
text and handled by software: it can only be directly placed in unreadable key registers, and
used to decrypt or encrypt data. Once the key has been provisioned, it can never again be
viewed on the device in clear.
The derivation function depends on the epoch input from the BSEC: if epoch fuses are
incremented, any keys provisioned during a previous epoch are never again usable.

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The derivation function also depends on the 2-bit TIL input from the BSEC. The software
can set this input value to something later than the current HDPL, but can never set it to
anything earlier. Keys are always provisioned for use up to a particular HDPL stage. Once
that stage has finished, this key is no longer usable.
The KEYSEL field in SAES_CR selects the source of the key used in the SAES.
• 0b001: derived key based only on the HUK
• 0b010: derived key based only on the BHK
• 0b100: derived key based on a combination of HUK and BHK
• 0b000: software loadable (but unreadable) key register

3.6.5 Unique ID
The device stores a 96-bit ID, unique to each device (see Section 79: Device electronic
signature).
Application services use this unique identity key to identify the product in the cloud network,
or to make it difficult for counterfeit devices or clones to inject untrusted data in the network.
Alternatively, the 256-bit device unique key (HUK) can be used (see Section 3.8.1).

3.7 Tamper detection and response

The STM32N6x7xx devices include active protection of critical security assets against
temperature, voltage, and frequency attacks. The detection of such attacks is managed in
the RTC, which resides on VBAT domain (see Section 61: Real-time clock (RTC) for details.
The devices support eight input/output tamper pins, which allow four independent
active-tamper meshes (or up to seven if the same output pin is shared by several input
pins). Four pins are in the VBAT domain.
Active pins are clocked by the LSE, and are functional in all system operating modes (Run,
Sleep, Stop, Standby, or Shutdown), and in VBAT mode.
The detection time is programmable, and a digital filtering is available (tamper triggered
after two false comparisons in four consecutive comparison samples).
Timestamps are automatically generated when a tamper event occurs.

Table 6. Internal tampers in TAMP

Tamper input NOER bit number in TAMP_CR3 Tamper source

ITAMP1 0 RTC voltage domain (VSW) monitoring

ITAMP2 1 Temperature monitoring
ITAMP3 2 LSE monitoring(1)
ITAMP4 3 HSE monitoring
ITAMP5 4 RTC calendar overflow (rtc_calovf)
ITAMP6 5 JTAG/SWD access when closed
ITAMP7 6 VCORE monitoring
ITAMP8 7 Monotonic counter overflow

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Table 6. Internal tampers in TAMP (continued)

Tamper input NOER bit number in TAMP_CR3 Tamper source

ITAMP9 8 Fault detected in SAES, PKA, SAES, or RNG

ITAMP10 - Reserved
ITAMP11 10 IWDG_reset and TAMP_potential_tamper
1. LSE missing or over frequency detection (> 2 MHz), glitch filter (> 2 MHz).

Each tamper source, whether internal or external, can be enabled or disabled.

When the event associated with an enabled tamper source occurs, it is called tamper event,
and it results in the following:
• BHK and HUK (dedicated keybuses to SAES) are masked to zero and invalidated.
• PKA, SAES, CRYP, and HASH are reset, unless the boot ROM has set the
SYSCFG_POTTAMPRSTCR register to indicate it safely controls them.
• The backup RAM and registers, and the secure RAM (16-Kbyte AHB SRAM2 aliased
at 0x28004000 and 0x38004000) are inaccessible (read-as-zero).
• Fuse secrets are un-reloadable by anyone except the boot ROM.
Each tamper source can be further configured to generate an immediate erase of device
secrets. An event on a tamper that is configured to do no erase, is called a potential tamper.
The secure software must decide on the response.
Note: The boot ROM always sets SYSCONF_POTTAMPRSTCR to override any potential tamper,
and to ensure it can access the firmware key, and use the crypto accelerators.
The boot ROM can load the FSBL even if a potential tamper occurs before or during boot.
Once the application analyzes the situation following a potential tamper event notification,
there are two possible cases:
• The application launches secret erase with a software command by setting BKERASE
in TAMP_CR2.
• The application just clears the flags to release secret blocking (false tamper).
An event on a tamper configured to perform immediate erase of device secrets is called a
confirmed tamper. The device secrets consist of the backup registers, MCE key registers,
the content of the PKA SRAM, and the secure AHB SRAM2 (erased as soon as VDD is
present). There is a configurable option that says that the content of the backup RAM must
also be considered as device secrets, and erased on a confirmed tamper. It is optional
because the expectation is that the backup RAM only ever contains secrets stored in a form
encrypted by a key in backup registers, and when they need to be used, they are decrypted
into the secure AHB SRAM2.
Each source of tamper can be configured to trigger the following events:
• Generate an interrupt, able to wake up the device from Stop and Standby modes.
• Generate an hardware trigger for the low-power timers.

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The system includes a watchdog that the software needs to refresh regularly (and
eventually fires if the software hangs). If the watchdog fires, and there is a potential tamper
flagged (not yet analyzed by the software), ITAMP11 is set.
ITAMP11 must be configured as a confirmed tamper (performs an immediate erase of
device secrets).
Note: SYSCONF_POTTAMPRSTCR only overrides a potential tamper. If a confirmed tamper
occurs while the boot ROM operates, fuse secrets are made inaccessible until the next
system reset. This may cause the authentication to fail, and a system reset is eventually
triggered by the watchdog. By this time, all device secrets have been erased, and
SYSCONF_POTTAMPRSTCR can override blocks that caused the flagging of a tamper
event. The software can boot, and, for example, display a message indicating
the occurrence of the confirmed tamper.
The effect of low-power modes on a tamper detection are summarized in the table below.

Table 7. Effect of low-power modes on TAMP

Mode Description

No effect on tamper detection features

Sleep
TAMP interrupts cause the device to exit Sleep mode.
No effect on tamper detection features, except for level detection with filtering and active
Stop tamper modes that remain active only when the clock source is LSE or LSI.
Tamper events cause the device to exit Stop mode.
No effect on tamper detection features, except for level detection with filtering and active
Standby tamper modes which remain active only when the clock source is LSE or LSI.
Tamper events cause the device to exit Standby mode.
No effect on tamper detection features, except for level detection with filtering and active
Shutdown tamper modes which remain active only when the clock source is LSE.
Tamper events cause the device to exit Shutdown mode.

3.8 Crypto engines

3.8.1 Accelerators
The device implements cryptographic algorithms as recommended by national security
agencies (such as NIST for the U.S.A, BSI for Germany, or ANSSI for France). These
algorithms are used to support privacy, authentication, integrity, entropy, and identity
attestation.
The embedded crypto engines enable lower processing times, and lower power
consumption when performing cryptographic operations. This offloads these computations
from the Cortex-M55. The SAES engine offers two important features, which cannot be
implemented by software: pure hardware key handling, and DPA resistance.
For product certification purposes, ST provides certified device information on how these
security functions are implemented and validated.
For more information on crypto engine processing times, refer to the dedicated section in
the reference manual.

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Table 8 lists the available accelerated cryptographic operations.

Table 8. Accelerated cryptographic operations

Key lengths
Operations Algorithm Specification Modes
(in bit)

Software and hardware(2) modes

Get entropy RNG NIST SP800-90B(1) N/A
running in parallel
FIPS PUB 197
Encryption, decryption ECB, CBC, CTR
NIST SP800-38A
128, 256
Authenticated encryption or NIST SP800-38C
AES(3) (192 in GCM, CCM
decryption NIST SP800-38D CRYP only)
Cipher-based message
NIST SP800-38D GMAC
authentication code
Checksum SHA-1 N/A Digest 160-bit
FIPS PUB 180-4 SHA-224, SHA-256, SHA-384,
Cryptographic hash SHA-2
SHA-512
Keyed-hashing for message FIPS PUB 198-1
HMAC Short, long All supported algorithms
authentication IETF RFC 2104

Encryption/decryption IETF RFC 8017

RSA Up to 4160 RSAES-OAEP
key-pair generation(4) NIST SP800-56B
IETF RFC 8017
RSA Up to 4160 PKCS1-v1_5, PSS
FIPS PUB 186-4
Signature(4)with hashing
ANSI X9.62
Signature verification
ECDSA IETF RFC 7027 Refer to the Section 52: Public key
Up to 640
FIPS PUB 186-4 accelerator (PKA) for details
Key agreement ECDH ANSI X9.42
1. Certifiable using STMicroelectronics reviewed documents.
2. Random number distribution to the SAES and the PKA, using a dedicated hardware bus.
3. ECB, CBC, CTR, GCM, and CCM chaining modes are protected against side-channel and timing attacks in SAES
(see Section 3.8.2).
4. Private-key cryptography is protected against side-channel and timing attacks.

The PKA accelerates asymmetric crypto operations (such as key pair generation, ECC
scalar multiplication, point on curve check). See Section 52: Public key accelerator (PKA)
for more details.
The STM32N6x7xx devices have two AES engines:
• The CRYP includes a fast AES engine with 11 cycles per 16-byte block
(see Section 49: Cryptographic processor (CRYP)).
• The SAES contains a DPA-resistant AES engine, which implements counter-measures
and mitigations against power and electromagnetic side-channel attacks. The SAES is
much slower.
SAES and CRYP engines support the chaining modes mentioned in Table 8.

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As shown in Section 3.6, the SAES can be used for extra-secure on-chip storage for
sensitive information. For more information, refer to Section 48: Secure AES coprocessor
(SAES).

3.8.2 Memory cipher engine (MCE)

The MCE implements an on-the-fly encryption/decryption of data to/from external
memories, which are more vulnerable to side-channel attack than internal memories (traffic
on the interface is accessible). The MCE is then designed to make such attacks prohibitively
expensive.
The MCE is instantiated in front of each external memory interface (memory-mapped at
addresses above 0x60000000). The MCE is used to define four non-overlapping regions of
target memory. Each region can be configured to be encrypted in a different way.
Secure software writes master keys into unreadable MCE registers, and then configure
each region: define which master key is used for encrypting data in this region.
For each 32-byte memory block in a region, the MCE uses this block address to derive
a specific key for encrypting data in this block. This is done on-the-fly, using the selected
master-key. Side-channel attacks are then much more expensive, since an individual attack
only uncovers 32 bytes of data.
The user chooses once, at application start, whether to use AES (128 or 256) or NOEKEON
for the final data encryption (NOEKEON being faster).
Each master key is defined with an algorithm attribute that determines one of the following:
• It is input to a strong derivation for each block.
• It is input to a faster but weaker derivation.
• It is used directly as a very-fast but weak stream cipher (only suitable for read-only
data).
Each key and its attributes are sticky-lockable. A key cannot be partially overwritten.
If its attributes are changed, the key is zeroed.
When a tamper event is confirmed in the TAMP, all MCE keys are erased, encrypted regions
are read as zero, and writes ignored, until the MCE is properly initialized again.
A typical MCE use is detailed in Section 3.8.2. For more details on the MCE programming,
refer to Section 51: Memory cipher engine (MCE).

3.8.3 NPU encryption

The encryption that uses the MCE has a latency of at least 11 cycles, and a block size of
16 bytes. This imposes an heavy overhead on NPU memory transactions. Therefore
the NPU is equipped with its own low-latency encryption engines on its 8-byte-wide AXI
initiator ports.
The formula for creating a 64-bit ciphertext Cx, from plaintext Px, which resides at an
address addrx, is:
Cx = Px ⊕ H(K128 , addrx , IDy)
where:
• H is the cryptographic function.
• K128 is a 128-bit key written to configuration registers in the NPU.

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• IDy is a value that software can modify when the NPU rewrites a new value to the same
address.
The latency through the NPU encryption engine is 3 or 4 cycles (depending on a strength
option selected by the software). See Section 20: Neural-ART accelerator™ (NPU).

3.9 Access controlled debug

The BSEC and DBGMCU hardware support an Arm PSA-compliant debug authentication
mechanism.
A secure debug is where the debugger arranges to make secure privileged accesses on
its AXI initiator. A nonsecure debug is more restricted: the debugger can only make
non-secure privileged accesses via its AXI port.
On power-up, regardless of whether or not the reset pin is still asserted, fuses are
immediately read to determine whether the device is BSEC-open or BSEC-closed. If the
device is BSEC-open, an attached debugger can perform a “chip discovery” (reading
various CPU identification registers), even while holding the device in reset via the RESET
pin.
On a BSEC-closed device, the debug access depends on the content of BSEC_DBGCR
and BSEC_AP_UNLOCK, which are only writable once by secure-privileged code after
the boot ROM has completed. The debug opens when both conditions are met:
• DBG_UNLOCK = 0xB4 in BSEC_DBGCR.
• UNLOCK = 0xB4 in BSEC_AP_UNLOCK.
The current HDPL (reported in BSEC_HDPLSR) must also be non-zero. It must reach the
level defined by DBG_AUTH_TIL in BSEC_DBGCR. DBG_AUTH_SEC in BSEC_DBGCR
determines whether it is secure or nonsecure debug (see Section 4: Boot and security
control (BSEC) for more details).
In order to control the debug reopening, the uRoT can impose a debug authentication
protocol. This protocol must implement a challenge response mechanism based on
asymmetric cryptography to authenticate requests from the host (relying on an OEM debug
public key stored in the device by the OEM).
The protocol can implement a bidirectional communication between the host and the device
through a mailbox interface located in the DBGMCU. The host debugger writes to
the mailbox via the JTAG/SWD interface, and expects to get responses and messages from
the device via the same mailbox.
The debug authentication protocol is launched on a power-up of the device, when
an open-request message is posted by the host, while the device is still under reset.
Trusted DBG_AUTH code sees this, and generates a random challenge token.
The debugger appends this token to a certificate chain that confers certain rights to the
debugger, signs this "debug certificate" structure, and submits it back to the device.
The DBG_AUTH code validates it with respect to a root public key provisioned in fuses
by the OEM. The random token stops any later replay of the same interaction.
The debug certificate determines whether the debug is secure or nonsecure.
BSEC_DBGCR is only reset on power-up: it retains its value through warm resets.
The debugger does not have to repeat the authentication procedure on system resets.

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4 Boot and security control (BSEC)

4.1 Introduction
The boot and security control (BSEC) peripheral manages the accesses to an embedded
one time programmable (OTP) array of fuses. Those fuses are used to store on-chip,
non-volatile data like boot and security parameters.
Embedded non-volatile secrets are stored in BSEC upper area that is only accessible while
BSEC is operating in its BSEC-closed state. When the BSEC state is BSEC-open, those
non-volatile secrets are permanently hidden.

4.2 BSEC main features

• APB peripheral, accessible through 32-bit word accesses only.
• 12 Kbits of OTP (effective)
– 4096 lower OTP bits, bitwise (1-bit) programmable
– 4096 middle OTP bits, bulk (32-bit) programmable
– 4096 upper OTP bits, bulk (32-bit) programmable, only accessible when BSEC is
in the BSEC-closed state.
• Reading and programming of OTP fuses, with detailed status reporting
• Shadowing in register flops of predefined fuse words, loaded at BSEC cold and warm
resets. Shadow fuse registers are writable unless write locked until next BSEC cold or
warm reset.
• Locking of OTP word programming, permanently or until next BSEC cold and warm
resets. Option of global programming lock until next BSEC cold and warm reset.
• Read locking of fuse words (word granularity) until next BSEC cold or warm reset
– Locked shadowed words cannot be reloaded from the fuse array (fixed value)
– Locked unshadowed words read as 0.
• Device lifecycle management.
– Read as 0 of upper fuse words (including RHUK) when STMicroelectronics
engineering modes are enabled (BSEC-open state).
– Possibility to go to BSEC open state using a 128-bit password (four trials).
– Non-volatile key storage revocation counter (epoch).
• Four 32-bit scratch registers to store values persistent across device warm reboot.
• IN and OUT 32-bit registers to communicate information with external agent via JTAG.
• Monotonic hide protection level counter allowing temporal isolation of keys and debug
ability.
• Support for TrustZone® and STM32 resource isolation framework (RIF).
• Non-volatile storage of randomly generated 256-bit root hardware unique key (RHUK),
directly delivered to SAES peripheral. This key is never readable by any software, and
it can be zeroed until next BSEC cold or warm reset.

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4.3 BSEC functional description

4.3.1 BSEC block diagram

Figure 3 shows the BSEC block diagram.

Figure 3. BSEC block diagram

RCC TAMP ROM i/f

bsec_hrst
bsec_srst
bsec_rst

hide_sec
block_sec

unmap
Debug &
BSEC Trace

Control debug_ctrl
registers
Wrapper
JTAG

JTAG obk_hdpl, epoch_sel, epoch

logic

jtaginout
registers
SAES
Shadow RHUK
registers
control

feature_ctrl
32-bit APB bus

APB slave i/f

Fuses
Array
Core logic
sec
cid
MSv67591V1

4.3.2 BSEC internal signals

Table 9 describes the user relevant internal signals interfacing the BSEC peripheral.

Table 9. BSEC internal input/output signals

Signal name Signal type Description

bsec_rst
BSEC cold/warm resets from RCC (see Section 4.3.17).
bsec_srst Digital input
bsec_hrst BSEC hot reset from RCC (see Section 4.3.17).
Digital input
jtaginout Interface to JTAG, including clock and reset.
and output
hide_sec Digital input Set by TAMP in case of confirmed tamper (see Section 4.3.17).
block_sec Digital input Set by TAMP in case of potential tamper (see Section 4.3.17).
rhuk Digital output 256-bit root hardware unique key output to SAES peripheral.

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Table 9. BSEC internal input/output signals (continued)

Signal name Signal type Description

Control outputs to SAES peripheral to influence generation of

obk_hdpl Digital output
DHUK.
epoch_sel Control outputs to SAES peripheral to influence generation of
Digital output
epoch DHUK.
debug_ctrl Digital output Device debug and trace control signals (see Section 4.3.11).
feature_ctrl Digital output Device feature control signals (see Section 4.3.12)
bsec_done Digital output End of BSEC cold/warm reset operation to RCC.

4.3.3 BSEC reset and clocks

BSEC is clocked by a device-embedded oscillator (RCBSEC). Because BSEC is clocked by
an internal oscillator, an access to fuse array is robust against external fault injection on
clocks.
The BSEC has three resets:
• a cold POR (power-on reset) directly driving bsec_srst.
• a warm system reset (bsec_rst) asserted when POR is asserted, but also by other
sources of system reset, including a PAD reset.
• a hot reset input (bsec_hrst), driven directly by bsec_done.
BSEC flops on the cold reset retain their values through warm reset, while the rest of the
system remains in reset until the auto-load process has completed (bsec_done = 1) and
fuse output values are stable.
On a POR, the BSEC temporarily emerges from warm reset for the duration of the auto-load
process, even if bsec_rst remains asserted, so that the auto-load process can determine
values for flops on the cold reset. This means when the device is powered up, the security
state is immediately established, so that a debugger may be allowed to perform discovery
operations soon after power-up, even if the PAD reset is still being asserted.
Some flops in the BSEC are on bsec_hrst, so they remain in reset until bsec_done is
asserted. This reset is asserted while the Cortex-M is under reset.

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4.3.4 Organization and use of fuses

Organization of fuses
One-time programmable fuse bits are organized in three groups of 32-bit words, as shown
on Figure 4.

Figure 4. BSEC fuse mapping overview

Secure privileged only

Word 127

Word 128

Word 255

Word 256

Word 375
Word 0

...

...

...

Upper OTP (*)

Middle OTP
Lower OTP
SFW127

SFW128

SFW255

SFW256

SFW375
SFW0

(*) Only accessible in closed state

MSv67517V1

The lower fuses region is used to store non-volatile, non-secret information that may
require bitwise update during the life of the product.
The middle fuses region is used to store non-volatile, non-secret information that are
written once, in 32-bit words bulk.
The upper fuses region is similar to the middle region, except that it is hidden when in the
BSEC-open state (see Section 4.3.7). Hence it is used to store secrets like symmetric keys
or private asymmetric keys.
Each fuse word w is either “shadowed” or “unshadowed”, as defined by flag bit SFWw in
corresponding BSEC_SFSRx register. A shadowed fuse word is loaded into flops at cold or
warm reset, and can be read quickly by software. An unshadowed fuse word is not read out
of the fuse memory at reset, then stored permanently in flops. It needs to be reloaded from
the fuse memory each time it is needed. See Reading fuses in Section 4.3.5 for details.
Note: The whole OTP space can only be controlled by a secure privileged CPU.
Each individual lower fuse bit is one-time programmable, from 0 to 1. Transitions from 1 to 0
are not possible.
Details on fuse usage are described in Section 5: OTP mapping (OTP).

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4.3.5 Operations on fuses

Reading fuses
If fuse word w is shadowed (SFWw bit set in corresponding BSEC_SFSRx register), and
either the state is BSEC-closed or w < 256, then BSEC_FVRw register is auto-loaded at
cold or warm reset with the contents of fuse word w.
If fuse word w is accessible and shadowed, then if SRLOCKw = 0 the contents of fuse w
can be reloaded by software into BSEC_FVRw register.
If fuse word w is accessible and unshadowed (SFWw bit cleared in corresponding
BSEC_SFSRx register), a read to BSEC_FVRw register returns the content of fuse word w
if the last operation on the fuse memory successfully reloaded word w, and if no
unshadowed fuse word has been read since that reload.
Each time the application reloads the content of a word stored in fuse memory using
BSEC_OTPCR register with PROG bit cleared, BUSY bit and error status should be
checked in BSEC_OTPSR (see Section 4.3.6).
Note: Unshadowed fuse word information stored in BSEC_FVRw is cleared as soon as it is read.

Writing shadow registers

When a fuse word w = {i + 32 * x} above word 9 is shadowed (SFWw bit set in
BSEC_SFSRx) the application can update its shadowed value by writing directly to
BSEC_FVRw register, if SWLOCKw bit is cleared in BSEC_SWLOCKx register.
Note: A shadow register write does not change the underlying fuse value.

Programming fuses
When programming is not blocked, lower fuse words can be blown bit-per-bit at different
times. Middle and upper fuses must be programmed 32-bits at a time, only once. As
reprogramming middle and upper fuses can let them with invalid content (an ECC error
might be reported), it is strongly recommended to set PPLOCK = 1 after the first (and only)
programming of the middle and upper fuses.
The procedure for blowing fuse word w is as follows:
1. Write the value to be blown in BSEC_WDR, then set ADDR = w, PROG = 1 and
PPLOCK = 0 in BSEC_OTPCR register.
2. When BUSY bit is cleared in BSEC_OTPSR, verify that PROGFAIL is cleared. If
PROGFAIL is set try again step 1.
3. Reload the fuse word w using BSEC_OTPCR with PROG bit cleared.
4. When BUSY bit is cleared in BSEC_OTPSR, verify that BSEC_FVRw register returns
the correct value. If not, try again step 1.
Note: OTP bits are initially set to 0 and once a bit is set to 1 it cannot be programmed back to 0
(bit stays at 1). Bitfields with 0s in BSEC_WDR are not programmed, while bitfields with 1s
are programmed.
As lower fuse words can be programmed multiple times, when the application requests a
specific bit to be programmed to 1 more than once, BSEC does the burning only once.

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Permanent program lock (PPLOCK)

The application can make further programming of fuse word w impossible by following the
sequence:
1. Clear BSEC_WDR register, then set ADDR = w, PROG = 1 and PPLOCK = 1
in BSEC_OTPCR register.
2. When BUSY bit is cleared in BSEC_OTPSR, verify that PROGFAIL is cleared.
If PROGFAIL is set try again step 1.
3. Reload the fuse word w using BSEC_OTPCR with PROG bit cleared.
4. When BUSY bit is cleared in BSEC_OTPSR, verify that the PPLF in BSEC_OTPSR is
set. If not, try again step 1.
There is no register in BSEC to store PPLOCK information. When the application needs to
know if a fuse word programming is permanently locked, it has first to perform a reload of
this word using BSEC_OTPCR and then check if the PPLF bit in BSEC_OTPSR register is
set. See Table 11 for details.

Fuse word locking features

In order to make fuse usage suitable for security, for example to implement the isolation
scheme detailed in Section 4.3.10, BSEC has the following locking features:
Sticky program lock (SPLOCK)
The application can prevent fuse word w = {i + 32* x} programming until next BSEC reset
(cold or warm) by setting the SPLOCKw bit in BSEC_SPLOCKx register.
Sticky write lock (SWLOCK)
The application can make the BSEC_FVRw register of a shadowed fuse word
w = {i + 32 * x} unwritable until next BSEC reset (cold or warm) by setting the SWLOCKw bit
in BSEC_SWLOCKx register.
Sticky reload lock (SRLOCK)
Reload of word w = {i + 32 * x} using BSEC_OTPCR register can be blocked until next
BSEC reset (cold or warm) by setting the SRLOCKw bit in BSEC_SRLOCKx register.
When read is sticky-locked, unshadowed fuse words return 0 while shadowed fuse words
return their current value (value is not zeroed).
Upper fuses read and write locking (HIDEUP)
When HIDEUP bit is set by hardware in BSEC_OTPSR, neither read nor write are possible
to fuse words located in the upper region.

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4.3.6 BSEC read and programming status reporting

After a cold and warm reset BSEC performs a first set of OTP reads, reporting the specific
status structure defined in Table 10.

Table 10. BSEC initial status reporting structure

Bit BSEC_ Error
Name Meaning when bit is set
offset OTPSR bit flag

0 [0] BUSY BSEC ongoing operation is not completed.

1 [1] INIT_DONE BSEC initialized following a cold or warm reset.
No
2 [2] HIDEUP Upper fuses are not accessible to the application.
4 [4] OTPNVIR BSEC is not virgin. This bit should always be set.
At least one error has been detected during the reading of shadowed
fuse words, as reported in BSEC_OTPVLDR registers (VLDF bit = 0).
5 [5] OTPERR The recommended mitigation is to reload the faulty fuse word using
BSEC_OTPCR and analyze the 8-bit error structure in BSEC_OTPSR,
as detailed below.
Yes
At least one single-error has been corrected during the reading of
shadowed fuse words, as reported in BSEC_OTPVLDR registers
6 [6] OTPSEC (VLDF bit = 0). In this case the shadowed fuse word value is correct,
hence if OTPSEC = 1 and OTPERR = 0 the application does not need
to reload the faulty fuse word.

After any read or programming request, the BUSY bit is cleared, and BSEC reports the
specific status structure defined in Table 11. When this structure is different than 0 the read
or program operation might have failed, as indicated in the table.

Table 11. BSEC ad-hoc error/status reporting structure

Bit BSEC_ Failed Retry if
Name Error description
offset OTPSR bit operation error(1)

0 [16] PROGFAIL Write Programming operation failed.

1 [17] DISTURB Yes Integrity of the fuse value is not guaranteed.
2 [18] DEDF Double error detected. Fuse word is corrupted.
3 [19] SECF Single bit error correction.
4 [20] PPLF Read Permanent programming lock detected.
No
Permanent programming lock information on the two
5 [21] PPLMF
lower fuse values in the array is not identical.
Fuse address mismatch. Fuse value cannot be trusted,
6 [22] AMEF(2) Yes
and should be read again.
1. For reads: need to reload the fuse (reported value cannot be trusted). For writes: need to retry the programming operation.
2. Always be 0 in normal operating conditions.

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4.3.7 Lifecycle management

BSEC state initialization
Following a cold or warm reset BSEC can be in the following possible security states,
defined in Table 12.

Table 12. BSEC states definition

DHUK in Full BootROM
BSEC states(1) Upper fuses Fuse programming
SAES(2) debug access

BSEC-open Inaccessible(3) Unusable yes(4) partial

Hardware Enabled
BSEC-closed Accessible no(5) full(6)
unique
BSEC-invalid Inaccessible(3) Unusable no partial Disabled
1. Defined in NVSTATE bitfield in BSEC_SR register (0x16: BSEC-open, 0x0D: BSEC-closed).
2. Derived hardware unique key in SAES peripheral uses RHUK information from BSEC (see
Section 4.3.15).
3. Cannot be read or programmed by any means (functional or non-functional).
4. ST engineering modes are also available.
5. Root of trust application can unlock debug features unless any of the debug_lock bits (25/24/23/22) is
blown in WORD18. ST engineering modes are disabled, by hardware, provided bit 20 of fuse word 124 is
blown.
6. At the end of its execution the boot ROM writes 0xB9D8 FF1F to BSEC_UNMAPR, reverting boot ROM
access to partial.

Errors following a BSEC initialization are detailed in Section 4.3.6. Details about reset
management can be found in Section 4.3.17.
When neither BSEC-open nor BSEC-closed state (NVSTATE different than 0x16 or 0x0D),
the security state is considered invalid, and the most conservative security configuration is
applied: that is, fuse programming is disabled, upper fuses read as 0, debug is disabled,
ROM is partially unmapped and shadow registers are read only. When NVSTATE = 0x23,
a confirmed tamper is active in the device (see Section 4.3.17).
Note: On any reset, including hot reset, if the state is BSEC-closed, the BSEC_UNMAPR register
is set to 0xA1C0 DE0D, ensuring the whole boot ROM is visible.

Opening BSEC
BSEC can transition from BSEC-closed to BSEC-open only if the user enters the
programmed 128-bit password via JTAG, and then performs a global reset (JTAG + device),
clearing all secrets.
The recommended JTAG password programming sequence is:
1. Write the four password words to upper fuses words 256 to 259 with PPLOCK bit
cleared in BSEC_OTPCR. JTAG_PSWD0 is stored in word 256, while JTAG_PSWD3
is stored in word 259.
2. Read back password value to verify it is correct
3. Write 0x0 to the same fuse words 256 to 259, with PPLOCK bit set in BSEC_OTPCR.
After this, password words cannot be read nor programmed anymore by the
application.

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The BSEC opening sequence is described below:

1. Bring the device TAP out of reset, and enter the device secret password sequentially
using the JTAG commands 0100 (SET_JTAG_PSWD0), 0101 (SET_JTAG_PSWD1),
0110 (SET_JTAG_PSWD2) then 0111 (SET_JTAG_PSWD3).
2. Trigger a device reset, without causing a TAP reset. When BSEC emerges from reset,
it blows the RMA fuse word with adequate values.
3. Trigger a TAP reset to destroy any record of the entered password, and after the next
cold or warm reset, the BSEC changes its NVSTATE to “BSEC-open” in BSEC_SR. It
can be verified using the JTAG command 0011 (READ_SEC). BSEC returns 0x1 for an
BSEC-open device, 0x2 for a BSEC-closed device.
4. Ship the device to STMicroelectronics for field return analysis (RMA)
Once the device has been opened it can be closed again by blowing to 0xF the next
unblown 4-bit nibble in BSEC_FVR1 (see Closing BSEC). At most four device re-opening
attempts are allowed, regardless of whether they are successful or unsuccessful.
By blowing at least one bit in BSEC_FVR1[27:24], the application can reduce the number of
re-opening cycles to only one.
If the application blows at least one bit in BSEC_FVR1[31:28] a closed device can never be
re-opened.
The application can also ensure that if a closed device is ever re-opened, it is not possible to
subsequently re-close it again. It is done by blowing the permanent programming lock
(PPLOCK) of fuse word 1, writing 0x00000000 to BSEC_WDR then writing 0x00006001 to
BSEC_OTPCR.
Note: By default BSEC opening password is 0x0. It is advised to change it.

Closing BSEC
BSEC can transition from BSEC-open to BSEC-closed by blowing some bits such that s[7:0]
becomes greater than r[7:0], or s[7] = 1. Bytes s[7:0] and r[7:0] are defined as follows:
s[7:0] = OR(BSEC_FVR1[31:28]) | OR(BSEC_FVR1[27:24]) | ... |
OR(BSEC_FVR1[3:0])
r[7:0] = AND(BSEC_FVR2[31:28]) | AND(BSEC_FVR2[27:24]) | ... |
AND(BSEC_FVR2[3:0])
With the following conventions:
• “|” is concatenation operand
• OR(bits[1:0])= bit[1] OR bit[0]
• AND(bits[1:0])= bit[1] AND bit[0]
When the device is being closed, the application can limit re-opening cycles to only one
attempt by blowing at least one bit in BSEC_FVR1[27:24]. To reduce re-opening cycles to
zero, the application must blow at least one bit in BSEC_FVR1[31:28].
Note: For the device to become BSEC-closed, the application must perform a BSEC cold or warm
reset.

4.3.8 Epoch registers

There are two 32-bit readable registers, BSEC_EPOCHR0 and BSEC_EPOCHR1, that are
writable only by boot ROM accesses. It is the responsibility of the boot ROM to read bitwise
fuses and populate these registers.

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There is a 1-bit programmable register BSEC_EPOCHSELCR (output on epoch_sel) that,

when programmed to n, ensures that BSEC_EPOCHRn is output on epoch. Both epoch and
epoch_sel are wired to the SAES where they influence the generation of DHUK, derived
from the RHUK.
Secure software can blow additional bits in the appropriate fuse word to increment an
Epoch, thereby making impossible the use of all keys derived from the RHUK prior to that
point.

4.3.9 BSEC local access control

Any access that is not both secure and privileged is blocked, with read data zeroed and
write accesses ignored.

4.3.10 Temporal isolation in BSEC

In order to enforce isolation between boot stages the running application in each boot level
must hide the secrets it was using before proceeding to the next level of code in the boot
chain. Such protections must remain until the next boot sequence.
Four boot levels, with its corresponding hide protection level (HDPL), are defined:
• Level 0 (HDPL0) corresponds to hardware state machine or ROM code execution.
• Level 1 (HDPL1) corresponds to the execution of STMicroelectronics signed code or
ROMed code. This code is the first stage of the secure boot.
• Level 2 (HDPL2) corresponds to the execution of the OEM signed code, stored in
embedded SRAM. This code is the second stage of the secure boot.
• Level 3 (HDPL3) corresponds to the application run-time.
To help enforcing such isolation between boot stages, the ROM code and the application
secure boot can use the following temporal isolation hardware capabilities of BSEC:
• When BSEC is in a closed state, ROM partially hides itself at the end of its execution in
level 0 or level 1, writing 0xB9D8 FF1F to BSEC_UNMAPR register.
• When BSEC is in a closed state, fuse words 364 to 375 are reloadable only when
BSEC_UNMAP=0xA1C0DE0D
• Any 32-bit OTP word can be made non-readable and/or non-writable until next cold or
warm reset. It can also be made non-programmable, permanently. See Fuse word
locking features and Permanent program lock (PPLOCK) methods in Section 4.3.5.
Note: Details on fuse usage are described in Section 5: OTP mapping (OTP).
The register BSEC_HDPLSR determines the current hide protection level of the device. The
encoding offers physical robustness.

Table 13. Current HDPL coding

BSEC_HDPLSR[HDPL] Level

0xB4 0
0x51 1
0x8A 2
0x6F 3
others undefined

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The register is reset to 0xB4 by bsec_hrst. The register is not directly writable. If less than 3,
the current level can be incremented by writing a value of 0x60B166E7 to BSEC_HDPLCR.
The 2-bit INCR field of the BSEC_NEXTHDPLCR register is added to the level given by
BSEC_HDPLSR (but clamped at a ceiling of 3), and the result is output on obk_hdpl[7:0] as
follows.

Table 14. BSEC Next HDPL register usage

BSEC_NEXTHDPLCR [INCR]
obk_hdpl [7:0]
0 1 2 3

0 (0xB4) 0xB4 0x51 0x8A

1 (0x51) 0x51 0x8A
0x6F
BSEC_HDPLSR [HDPL] 2 (0x8A) 0x8A 0x6F
0x6F
3 (0x6F) 0x6F
others (0xPQ) 0xPQ

The obk_hdpl output goes to the SAES where it influences the generation of DHUK, derived
from the RHUK. This mechanism allows keys for a later temporal level to be generated in
advance.

4.3.11 BSEC debug and trace control

The wrapper contains a BSEC_DBGCR register, reset to zero on the scratch reset, and
writeable only once per warm reset. The bytes of this register are named as follows

Table 15. BSEC debug register legal values

BSEC_DBGCR field name legal values

31:24 AUTH_SEC 0x00, 0xB4

23:16 AUTH_HDPL 0x00, 0xB4,0x51,0x8A,0x6F
15:8 UNLOCK 0x00, 0xB4
7:0 reserved -

AUTH_HDPL encodes levels in the same way as HDPL field in BSEC_HDPLSR register.
Any attempt to write a non-legal byte value into these fields results in a 0x00 being written in
that byte field.
The register is forced to zero (writes have no effect) whenever the device is BSEC-open.
The dbg_unlocked output, when taking the value of 0xB4, signifies that nonsecure debug is
possible. The dbg_unlocked_sec output, when it also takes the value of 0xB4, signifies that
secure debug is possible.
Both outputs are set to 0xB4 whenever the state is BSEC-open.
Whenever the BSEC state is not BSEC-open, then if HDPL = 0xB4, or AUTH_HDPL is
undefined or indicates a level greater than that given by HDPL, they are both set to 0x00,
otherwise dbg_unlocked takes the value of UNLOCK, and dbg_unlocked_sec takes the

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value of AUTH_SEC. This implies that secure boot is enforced on a BSEC-closed device. It
is the responsibility of the customer’s signed code to decide on whether debug becomes
unlocked at a certain level. This decision (i.e. the register write) only has to made once per
power cycle, since the register is on the scratch reset and retains its value across warm
resets.
Note: If a warm reset occurs during a debug session, then during the reset, the debugger
becomes temporarily locked, since HDPL is reset to 0. On a BSEC-open device, it becomes
unlocked again as soon as the BSEC has booted. On a BSEC-closed device, it becomes
unlocked again as soon as HDPL is non-zero and matches or surpasses AUTH_HDPL.
The BSEC_AP_UNLOCK register is forced to zero (writes have no effect) whenever the
state is BSEC-open. The ap_unlocked output, when taking the value 0xB4, indicates that
the debugger can access the CM55 Debug Subsystem. It is set to 0xB4 whenever the state
is BSEC-open, otherwise it is directly driven by the BSEC_AP_UNLOCK register, which is
reset to 0 on a scratch reset.
A rising edge on hide_sec (a confirmed tamper) resets these registers to zero, and close
debug. They are not writeable until the next cold or warm reset.
Note: These registers are on the scratch reset so that if software authorizes a debug, that
authorization survives subsequent warm resets, and doesn’t have to be re-authorized.

4.3.12 Device features control

Device features are controlled through read-only shadowed fuse word [Link] Section 5:
OTP mapping (OTP) for details.

4.3.13 Scratch registers

The four BSEC_SCRATCHRx registers are only reset by a cold boot. They are therefore
useful to store values that must remain persistent for the application across warm boots.
The eight BSEC_WOSCRx registers are only reset by a cold or warm boot. They are
therefore useful to store values that must remain persistent for the application across hot
boots.
Note: BSEC_WOSCRx registers are write once.

4.3.14 JTAG registers

The BSEC_JTAGINR and BSEC_JTAGOUTR registers are available to facilitate
communication between the application (for example ROM) and the debug tools connected
through the JTAG interface.

4.3.15 STM32 root hardware unique key (RHUK)

BSEC stores a root HUK that has been programmed by STMicroelectronics during the
device manufacturing. A successful provisioning is indicated with HVALID bit set
in BSEC_SR register.
The value of this key is obtained from the RNG peripheral of the device, without disclosure
to the outside word. This key cannot be read or programmed by any secure application nor
debugger.

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When BSEC detects an integrity issue while reading the key information from non-volatile
memory, or when application sets the sticky HKLOCK bit in BSEC_LOCKR, the key is
indicated as invalid. When the key is invalid the SAES peripheral uses a default fixed value.

4.3.16 BSEC error management

Shadowed fuse word automatic readout errors
After a cold or warm reset, shadowed fuse words are automatically loaded into BSEC_FVR
registers. At the end of this process, when INIT_DONE is set in BSEC_OTPSR, additional
error information can be found in this register, as described in Section 4.3.6.

Individual fuse loading errors

Upon each fuse loading from OTP memory array, an 8-bit error structure in BSEC_OTPSR
register is updated to tell the application if there was a problem with this particular fuse load.
This structure is defined in Section 4.3.6.

4.3.17 BSEC tamper response mechanisms

This device uses tamper-detection and response mechanisms that can make it immediately
inoperable, resulting in the automatic and immediate erasure of any sensitive data that may
be stored in the device. The device also supports the concept of potential tamper event,
where the device secrets are blocked while application software verifies that such tamper
event is confirmed or not.
BSEC manages above mechanisms in the following way:
• When a tamper source triggers a potential tamper event in TAMP peripheral
(NOERASE = 1), BSEC masks the RHUK value to SAES, and upper fuses read as 0
(unless BSEC_UNMAP = 0xA1C0 DE0D, meaning that the boot CPU is executing).
• When a tamper source triggers a confirmed tamper event in TAMP peripheral
(NOERASE = 0), or a potential tamper becomes a confirmed tamper, fuses cannot be
blown or reloaded, upper fuses read as 0, BSEC_DBGCR and BSEC_AP_UNLOCK
registers are cleared, RHUK information is physically cleared to 0 & invalidated, and
NVSTATE is set to 0x23 in BSEC_SR register. These limitations are deactivated after
device secrets have been erased, and a SoC reset has been applied.
Above limitations are deactivated when the application clears the active tamper source(s) in
TAMP [Link] Section 62: Tamper and backup registers (TAMP) for details.
Note: While tamper events are active the boot CPU can always execute the application firmware
following an application reset or an exit from Standby for the boot CPU.

4.4 BSEC interrupts

BSEC does not support any interrupt.

4.5 BSEC registers

Those registers are accessible through the register interface of the BSEC peripheral.

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4.5.1 BSEC fuse word w value register (BSEC_FVRw)

Address offset: 0x000 + 0x4 * w, (w = 0 to 375)
Reset value: 0xXXXX XXXX
Note: The reset value is 0x0000 0000 if the fuse word is unshadowed, defined by the fuse value if
the fuse word is shadowed.
Secure privileged read and write only. Illegal reads return 0, illegal writes are ignored.
See the bitfield description for further details on fuse word accessibility.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FV[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FV[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 FV[31:0]: fuse value

If fuse word {w} is shadowed (SFW{w} bit set in corresponding BSEC_SFSRx register), and
either the state is BSEC-closed or {w} < 256, then this register is auto-loaded at cold or warm
reset with the contents of fuse word w.
If fuse word {w} is accessible and shadowed, then:
– if SRLOCK{w} = 0, fuse word {w} can be reloaded by software into this register
– if SWLOCK{w} = 0, and {w} > 9, this register can be written to (otherwise, writes are
ignored).
If fuse word {w} is accessible and unshadowed (SFW{w} bit cleared in corresponding
BSEC_SFSRx register), writes are ignored and provided:
– the last operation on the fuse memory successfully reloaded word {w}
– no unshadowed fuse words have been read since that reload
then a read to this register returns the content of fuse word {w} (otherwise it returns 0).
If the fuse word {w} is inaccessible, then writes are ignored and reads return 0.
Unshadowed fuse word information stored in this register is cleared as soon as it is read.
When the state is BSEC-closed:
– Fuse words 364 to 375 are accessible only when BSEC_UNMAP=0xA1C0DE0D and when
the access is from boot CPU.
– Fuse words 256 to 259 read as zero when permanent programming lock is set for those
words.

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4.5.2 BSEC sticky programming lock register x (BSEC_SPLOCKx)

Address offset: 0x800 + 0x4 * x (x = 0 to 11)
Reset value: 0x0000 0000
Secure privileged read and write only. Illegal reads return 0, illegal writes are ignored.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLOCK{i + 32 * x}
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPLOCK{i + 32 * x}
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs

Bits 31:0 SPLOCK{i + 32 * x}: Sticky programming lock for word {i + 32 * x} (i = 0 to 31)
Setting this bit prevents permanent programming for the fuse word {i + 32 * x} until next cold
or warm reset.
0: Fuse word {i + 32 * x} can be burnt in fuse memory array
1: Attempt to program fuse word {i + 32 * x} in OTP memory array is silently ignored
While BUSY is set in BSEC_OTPSR, writes have no effect, and reads return 0.

4.5.3 BSEC sticky write lock register x (BSEC_SWLOCKx)

Address offset: 0x840 +0x4 * x (x=0 to 11)
Reset value: 0x0000 0000
Secure privileged read and write only. Illegal reads return 0, illegal writes are ignored.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWLOCK{i + 32 * x}
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWLOCK{i + 32 * x}
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs

Bits 31:0 SWLOCK{i + 32 * x}: sticky write lock for shadow register {i + 32 * x} (i = 0 to 31)
When fuse word {i + 32 * x} is shadowed, setting this bit prevents the writing of the shadow
register of this fuse word until next cold or warm reset.
0: Write to shadow register BSEC_FVR{i + 32 * x} is allowed
1: Writes to shadow register BSEC_FVR{i + 32 * x} are silently ignored
While BUSY is set in BSEC_OTPSR, writes have no effect, and reads return 0.

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4.5.4 BSEC sticky reload lock register x (BSEC_SRLOCKx)

Address offset: 0x880 + 0x4 * x (x = 0 to 11)
Reset value: 0x0000 0000
Secure privileged read and write only. Illegal reads return 0, illegal writes are ignored.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRLOCK{i + 32 * x}
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRLOCK{i + 32 * x}
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs

Bits 31:0 SRLOCK{i + 32 * x}: sticky reload lock for fuse word {i + 32 * x} (i = 0 to 31)
Setting this bit locks reloading of fuse word {i + 32 * x} from the OTP memory array until next
cold or warm reset.
0: Fuse word {i + 32 * x} loading through BSEC_OTPCR is authorized.
1: Fuse word {i + 32 * x} loading through BSEC_OTPCR is denied until next cold or warm
reset.
While BUSY is set in BSEC_OTPSR, writes have no effect, and reads return 0.

4.5.5 BSEC OTP valid register x (BSEC_OTPVLDRx)

Address offset: 0x8C0 + 0x4 * x (x = 0 to 11)
Reset value: 0x0000 0000
Secure privileged read only (return 0 otherwise).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VLDF{i + 32 * x}
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VLDF{i + 32 * x}
r r r r r r r r r r r r r r r r

Bits 31:0 VLDF{i + 32 * x}: Valid flag for shadow register {i + 32 * x} (i = 0 to 31)
This bit represents the validity of the last reload of fuse word {i + 32 * x}.
0: An error occurred while fuse word {i + 32 * x} was last reloaded. The value read from
BSEC_FVR{i + 32 * x} register cannot be relied on.
1: Last reload of fuse word {i + 32 * x} was done without error.
Each VLDF bit is updated when BSEC or the allowed application reloads corresponding fuse
word from the OTP array.

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4.5.6 BSEC shadowed fuses status register x (BSEC_SFSRx)

Address offset: 0x940 + 0x4 * x (x = 0 to 11)
Reset value: 0x0001 EBFF (SFSR0)
Reset value: 0xFF00 000F (SFSR3)
Reset value: 0x0000 000F (SFSR8)
Reset value: 0xFF00 0000 (SFSR11)
Reset value: 0x0000 0000 (others)
Secure privileged read-only (return 0 otherwise).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFW{i + 32 * x}
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SFW{i + 32 * x}
r r r r r r r r r r r r r r r r

Bits 31:0 SFW{i + 32 * x}: Shadowed fuse word {i + 32 * x} (i = 0 to 31)

This bit indicates whether fuse word {i + 32 * x} is shadowed or not.
0: Fuse word {i + 32 * x} is not shadowed. Fuse value must be reloaded using BSEC_OTPCR
before reading BSEC_FVR{i + 32 * x} register.
1: Fuse word is shadowed in BSEC_FVR{i + 32 * x} register. Reloading the fuse value using
BSEC_OTPCR is only required if the fuse value changed since the last BSEC cold or
warm reset.

4.5.7 BSEC OTP control register (BSEC_OTPCR)

Address offset: 0xC04
Reset value: 0x0000 0000
Writing to this register causes an access to be made to the fuse memory.
Secure privileged read and write only. Illegal reads return 0, illegal writes are ignored.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LASTCID[2:0] Res. Res. Res.
r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PP
Res. PROG Res. Res. Res. Res. ADDR[8:0]
LOCK
rw rw rw rw rw rw rw rw rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:19 LASTCID[2:0]: Last CID
This always returns the value 001.
Bits 18:15 Reserved, must be kept at reset value.

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Bit 14 PPLOCK: Permanent programming lock

When this bit is set together with PROG bit, no further write to this fuse word is possible.
0: Fuse word at address ADDR[8:0] is programmed normally.
1: Fuse word at address ADDR[8:0] is locked, preventing further modifications.
Permanent programming lock mechanism is immutable, as it is committed in the fuse
memory.
Bit 13 PROG: Fuse word programming
This bit determines whether BSEC operation is a read or a write. If a write is selected, the
data stored in BSEC_WDR is programmed in the fuse word indexed by ADDR bitfield.
0: Fuse word read operation is required
1: Fuse word programming operation is required
While BUSY is set in BSEC_OTPSR, writes to PROG bit have no effect.
Bits 12:9 Reserved, must be kept at reset value.
Bits 8:0 ADDR[8:0]: Fuse word address
This bitfield represents the address of the fuse word in the OTP memory array.
When a lower fuse address is selected two fuse words are addressed by BSEC.
When fuse words 376 to 383 are selected, read or programming requests are denied.
When fuse words 368 to 375 are selected, programming requests are ignored.

4.5.8 BSEC write data register (BSEC_WDR)

Address offset: 0xC08
Reset value: 0x0000 0000
Secure privileged write only. Any reads return 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRDATA[31:16]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRDATA[15:0]
w w w w w w w w w w w w w w w w

Bits 31:0 WRDATA[31:0]: OTP write data

The value written to this register can be written to fuse memory. This happens when the
BSEC_OTPCR register is written with the PROG bit set.
When a lower fuse address is selected in BSEC_OTPCR (ADDR=0x0 to 0x3F), two fuse
words are programmed by BSEC (one fuse word is programmed otherwise).
While BUSY is set in BSEC_OTPSR, writes to this register have no effect.

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4.5.9 BSEC scratch register x (BSEC_SCRATCHRx)

Address offset: 0xE00 + 0x4 * x (x = 0 to 3)
Reset value: 0x0000 0000
This register is reset when bsec_srst is asserted.
Secure privileged read and write only. Illegal reads return 0, illegal writes are ignored.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDATA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDATA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 SDATA[31:0]: Scratch data

This register can be used to store values that needs to be persistent across warm reset.

4.5.10 BSEC lock register (BSEC_LOCKR)

Address offset: 0xE10
Reset value: 0x0000 0000
Secure privileged read and write only. Illegal reads return 0, illegal writes are ignored.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HK GW
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LOCK LOCK
rs rs

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 HKLOCK: Hardware key lock
0: Derived hardware unique key (DHUK) in SAES peripheral is usable if HVALID is set in
BSEC_SR
1: Derived hardware unique key (DHUK) in SAES peripheral is not usable.
Once set, this bit is cleared only by BSEC cold or warm reset.
Bit 1 Reserved, must be kept at reset value.
Bit 0 GWLOCK: Global write lock
0: Writes to BSEC registers are allowed
1: Writes to BSEC registers are ignored (fuse programming and fuse reload disabled)
Once set, this bit is cleared only by BSEC cold or warm reset.

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4.5.11 BSEC JTAG input register (BSEC_JTAGINR)

Address offset: 0xE14
Reset value: 0x0000 0000
Secure privileged read only (return 0 otherwise).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATAIN[31:16]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATAIN[15:0]
r r r r r r r r r r r r r r r r

Bits 31:0 JDATAIN[31:0]: JTAG input data

Reads give the last input value from the JTAG interface

4.5.12 BSEC JTAG output register (BSEC_JTAGOUTR)

Address offset: 0xE18
Reset value: 0x0000 0000
Secure privileged write only (write ignored otherwise).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATAOUT[31:16]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATAOUT[15:0]
w w w w w w w w w w w w w w w w

Bits 31:0 JDATAOUT[31:0]: JTAG output data

Application can write any value in this field to be output on the JTAG interface.

4.5.13 BSEC unmap register (BSEC_UNMAPR)

Address offset: 0xE24
Reset value: 0xXXXX XXXX
Note: The reset value is 0xA1C0 DE0D on a BSEC-closed device, 0xFFFF FFFF on a
BSEC-open device.

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Register bits cannot be cleared by application, they can only be set to 1.

Secure privileged read and write only. Illegal reads return 0, illegal writes are ignored. Only
BootROM code can access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UNMAP[31:16]
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNMAP[15:0]
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs

Bits 31:0 UNMAP[31:0]: Unmap key

If this bitfield equals 0xA1C0 DE0D, the whole ROM is visible, else ROM is partially hidden.

4.5.14 BSEC status register (BSEC_SR)

Address offset: 0xE40
Reset value: 0x0000 0000
Secure privileged read only (return 0 otherwise).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBGR
NVSTATE[5:0] Res. Res. Res. Res. Res. Res. Res. Res. Res.
EQ
r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. HVALID Res.
r

Bits 31:26 NVSTATE[5:0]: Non-volatile state

0x16: BSEC-open state
0x0D: BSEC-closed state
0x7: BSEC-invalid state
0x23: BSEC-invalid state, with an active confirmed tamper triggered in the device
The BSEC state is evaluated each time INIT_DONE is set in BSEC_OTPSR.
For more information, refer to Section 4.3.7: Lifecycle management
Bits 25:17 Reserved, must be kept at reset value.
Bit 16 DBGREQ: debug request
0: Host debugger is not requesting debug
1: Host debugger is requesting debug
Bits 15:2 Reserved, must be kept at reset value.
Bit 1 HVALID: Hardware key valid
0: Derived hardware unique key (DHUK) feature cannot be used in SAES peripheral.
1: Derived hardware unique key (DHUK) feature can be used in SAES peripheral.
Bit 0 Reserved, must be kept at reset value.

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4.5.15 BSEC OTP status register (BSEC_OTPSR)

Address offset: 0xE44
Reset value: 0x0000 0000
This register is refreshed each time a fuse operation is triggered through BSEC_OTPCR.
Secure privileged read only (return 0 otherwise).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DISTU PROG
Res. Res. Res. Res. Res. Res. Res. Res. Res. AMEF PPLMF PPLF SECF DEDF
RBF FAIL
r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTP OTP OTP HIDE INIT_
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BUSY
SEC ERR NVIR UP DONE
r r r r r r

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 AMEF: Addresses mismatch error flag
This bit is set when the address used by BSEC to read a fuse word is different from the
programmed address (either by BSEC or by the application). Such event should never
happen in normal BSEC operations.
Bit 21 PPLMF: Permanent programming lock mismatch flag
This bit is set when the two words constituting a lower fuse word are reporting different
permanent programming lock statuses after BSEC reset or after the latest read.
For more details about permanent programming lock, refer to PPLOCK in BSEC_OTPCR.
Bit 20 PPLF: Permanent programming lock flag
This bit is set when the most recently read word is detected permanently locked.
For more details about permanent programming lock, refer to PPLOCK in BSEC_OTPCR.
Bit 19 SECF: Single error correction flag
This bit is set when a single-bit-error correction is detected after BSEC reset or after the
latest read.
Bit 18 DEDF: Double error detection flag
This bit is set when a double error is detected after BSEC reset or after the latest read.
When DEDF bit is set after reading fuse word w, the value in BSEC_FVRw is the one read
from OTP memory.
Bit 17 DISTURBF: Disturb flag
This bit is set when an unexpected error occurred after BSEC reset or after the latest read.
When DISTURBF bit is set after reading fuse word w, the value in BSEC_FVRw is the one
read from OTP memory.
Bit 16 PROGFAIL: Programming failed
This bit is set when last OTP programming by BSEC failed.
Bits 15:7 Reserved, must be kept at reset value.
Bit 6 OTPSEC: OTP with single error correction
This bit is set when at least one single-error correction is detected during BSEC reset
operations. In this case shadow registers are usable.

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Bit 5 OTPERR: OTP with error

This bit is set when at least one error is detected during BSEC reset operations.
Bit 4 OTPNVIR: OTP not virgin
This bit is set when first fuse word 0 is detected non-0 after BSEC reset operations.
Bit 3 Reserved, must be kept at reset value.
Bit 2 HIDEUP: Hide upper fuse words
This bit is set when application secret fuse words 256 to 383 becomes physically
inaccessible, that is functionally hidden fuse words read as 0 and programming requests are
ignored.
Bit 1 INIT_DONE: Initialization done
This bit is set when BSEC reset operations are completed. All shadowed fuses are readable
in BSEC_FVRw registers, and status bits in BSEC_SR and BSEC_OTPSR are up to date.
Bit 0 BUSY: Busy flag
0: BSEC is idle.
1: BSEC is busy.

4.5.16 BSEC epoch register (BSEC_EPOCHRx)

Address offset: 0xE80 + 0x4 * x (x = 0 to 1)
Reset value: 0x0000 0000
Writeable by boot ROM only, readable by secure privileged trusted domain or BootROM
code only. Illegal reads return 0, illegal writes are ignored.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPOCH[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPOCH[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rs

Bits 31:0 EPOCH[31:0]: epoch

This value is wired out to the SAES peripheral, depending on the EPOCH_SEL bit
in BSEC_EPOCHSELCR.

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4.5.17 BSEC epoch selection control register (BSEC_EPOCHSELCR)

Address offset: 0xE88
Reset value: 0x0000 0000
Secure privileged read and write only. Illegal reads return 0, illegal writes are ignored.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EPOC
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
H_SEL
rw

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 EPOCH_SEL: Selection of the epoch value to be sent to the SAES
0: SAES peripheral uses BSEC_EPOCHR0 as EPOCH value.
1: SAES peripheral uses BSEC_EPOCHR1 as EPOCH value.

4.5.18 BSEC debug control register (BSEC_DBGCR)

Address offset: 0xE8C
Reset value: 0x0000 0000
Secure privileged read and write only. Writeable only on a BSEC-closed device, once per
warm reset. Illegal reads return 0, illegal writes are ignored. Reset to zero on bsec_srst
(cold reset).
The AUTH_HDPL byte field indicates a temporal isolation level, as follows: the value 0xB4
means level 0, the value 0x51 means level 1, the value 0x8A means level 2, and the value
0x6F means level 3. All other byte values are undefined.
When the state is BSEC-open, the dbg_unlocked and dbg_unlocked_sec outputs to the
DBG_MCU block are set to 0xB4, and the register is zeroed.
When the state is not BSEC-open, both outputs are zeroed whenever either AUTH_HDPL
or BSEC_HDPLSR[HDPL] are undefined, or BSEC_HDPLSR[HDPL] = 0xB4, or the level
indicated by AUTH_HDPL is greater than that of BSEC_HDPLSR[HDPL]. Otherwise, the
UNLOCK is placed on the dbg_unlocked output, and (UNLOCK and AUTH_SEC) is placed
on the dbg_unlocked_sec output.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

AUTH_SEC[7:0] AUTH_HDPL[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNLOCK[7:0] Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw rw rw rw rw

222/4691 RM0486 Rev 2

RM0486 Boot and security control (BSEC)

Bits 31:24 AUTH_SEC[7:0]:

0xB4: Secure debug authorized when UNLOCK = 0xB4 and the level indicated in
BSEC_HDPLSR is greater than or equal to the level indicated by AUTH_HDPL
Others: Secure debug not authorized (provided state is not BSEC-open)
Bits 23:16 AUTH_HDPL[7:0]: level at which debug may be opened.
0xB4: Level 0
0x51: Level 1
0x8A: Level 2
0x6F: Level 3
Others: Undefined
Bits 15:8 UNLOCK[7:0]:
0xB4: Nonsecure debug authorized when the level indicated in BSEC_HDPLSR is greater
than or equal to the level given by AUTH_HDPL
Others: Debug not authorized (provided state is not BSEC-open)
Bits 7:0 Reserved, must be kept at reset value.

4.5.19 BSEC AP unlock (BSEC_AP_UNLOCK)

Address offset: 0xE90
Reset value: 0x0000 0000
Secure privileged read and write only. Writeable only on a BSEC-closed device, once per
warm reset. Illegal reads return 0, illegal writes are ignored. Reset to zero on bsec_srst
(cold reset). Bit 5 is reset to zero on every warm reset.
When the state is BSEC-open, the ap_unlocked output to the DBG_MCU block is set to
0xB4. and the register is zeroed. When the BSEC state is not BSEC-open, it takes the value
of the 8-bit UNLOCK field.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. UNLOCK[7:0]

rw rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 UNLOCK[7:0]:
0xB4: Unlock debug access port.
Others: Do not unlock.

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228
Boot and security control (BSEC) RM0486

4.5.20 BSEC HDPL status register (BSEC_HDPLSR)

Address offset: 0xE94
Reset value: 0x0000 00B4
Secure privileged read only. Illegal reads return 0, writes are ignored. Reset to 0xB4 on
bsec_hrst (hot reset).
When coding a value of less than 3, it can be incremented by writing 0x60B166E7 to
BSEC_HDPLCR.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. HDPL[7:0]

r r r r r r r r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 HDPL[7:0]: Current HDPL
0xB4: Level 0
0x51: Level 1
0x8A: Level 2
0x6F: Level 3
Others: Undefined

4.5.21 BSEC HDPL control register (BSEC_HDPLCR)

Address offset: 0xE98
Reset value: 0x0000 0000
Secure privileged write only. Illegal reads return 0, writes are ignored.
When BSEC_HDPLSR codes a value of less than 3, BSEC_HDPLSR can be incremented
by writing 0x60B166E7 to BSEC_HDPLCR.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INCR_HDPL[31:16]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INCR_HDPL[15:0]
w w w w w w w w w w w w w w w w

Bits 31:0 INCR_HDPL[31:0]: Increment HDPL

When HDPL is less than 3, writing 0x60B1 66E7 increments HDPL by one in
BSEC_HDPLSR.
Otherwise, writes are ignored. Reads return zero.

224/4691 RM0486 Rev 2

RM0486 Boot and security control (BSEC)

4.5.22 BSEC next HDPL control register (BSEC_NEXTHDPLCR)

Address offset: 0xE9C
Reset value: 0x0000 0000
Secure privileged read and write only. Illegal reads return 0, writes are ignored.
This value determines the amount to add to the level indicated by BSEC_HDPLSR to output
to the SAES on obk_hdpl.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. INCR[1:0]
rw rw

Bits 31:2 Reserved, must be kept at reset value.

Bits 1:0 INCR[1:0]: Increment
Amount to add to BSEC_HDPLSR to generate obk_hdpl[7:0] output (clamped at 3).

4.5.23 BSEC write once scratch register x (BSEC_WOSCRx)

Address offset: 0xF40 + 0x4 * x (x = 0 to 7)
Reset value: 0x0000 0000
This register is reset when bsec_rst is asserted.
Secure privileged read and write only. Illegal reads return 0, illegal writes are ignored.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WOSDATA[31:16]
rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WOSDATA[15:0]
rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo

Bits 31:0 WOSDATA[31:0]: Write once scratch data

ROM code can use this register to store values that needs to be persistent across hot resets.
It is writable once, reset by either cold or warm BSEC reset.

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Boot and security control (BSEC) RM0486

4.5.24 BSEC hot reset count register (BSEC_HRCR)

Address offset: 0xFE8
Reset value: 0x0000 0000
This register is reset when bsec_rst is asserted.
Secure privileged read only (return 0 otherwise).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HRC[31:16]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HRC[15:0]
r r r r r r r r r r r r r r r r

Bits 31:0 HRC[31:0]: Hot reset counter

This bitfield counts the number of hot resets since the last BSEC cold/warm reset.
See Section 4.3.3: BSEC reset and clocks for details about resets.

4.5.25 BSEC warm reset count register (BSEC_WRCR)

Address offset: 0xFEC
Reset value: 0x0000 0000
This register is reset when bsec_srst is asserted.
Secure privileged read only (return 0 otherwise).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRC[31:16]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRC[15:0]
r r r r r r r r r r r r r r r r

Bits 31:0 WRC[31:0]: Warm reset counter

This bitfield counts the number of warm resets since the last BSEC cold reset.
See Section 4.3.3: BSEC reset and clocks for details about resets.

4.5.26 BSEC register map

Table 16. BSEC register map and reset values

Register name
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0

Reset value

0x000 + BSEC_FVRw FV[31:0]

0x4 * w,
(w=0 to Reset value(1) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
375)
0x5E0 -
Reserved Res.
0x7FC

226/4691 RM0486 Rev 2

RM0486 Boot and security control (BSEC)

Table 16. BSEC register map and reset values (continued)

Register name
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
Reset value

0x800 + BSEC_
SPLOCK{i + 32 * x} (i = 31 to 0)
0x4 * x, SPLOCKx
(x=0 to 11) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x830 -
Reserved Res.
0x83C
0x840 + BSEC_
SWLOCK{i + 32 * x} (i = 31 to 0)
0x4 * x SWLOCKx
(x=0 to 11) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x870 -
Reserved Res.
0x87C
0x880 + BSEC_
SRLOCK{i + 32 * x} (i = 31 to 0)
0x4 * x SRLOCKx
(x=0 to 11) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x8B0 -
Reserved Res.
0x8BC
0x8C0 + BSEC_
VLDF{i + 32 * x} (i = 31 to 0)
0x4 * x OTPVLDRx
(x=0 to 11) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x8F0 -
Reserved Res.
0x93C
0x940 + BSEC_SFSRx SFW{i + 32 * x} (i = 31 to 0)
0x4 * x (1)
(x=0 to 11) Reset value x x x x x x x x 0 0 0 0 0 0 0 x x x x 0 x 0 x x x x x x x x x x
0x970 -
Reserved Res.
0xC00
PPLOCK
PROG

LASTCID
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
BSEC_OTPCR ADDR[8:0]
0xC04 [2:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BSEC_WDR WRDATA[31:0]
0xC08
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0xC0C -
Reserved Res.
0xDFC
0xE00 + BSEC_
SDATA[31:0]
0x4 * x SCRATCHRx
(x=0 to 3) Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

GWLOCK
HKLOCK
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
BSEC_LOCKR
0xE10

Reset value 0 0
BSEC_
JDATAIN[31:0]
0xE14 JTAGINR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BSEC_
JDATAOUT[31:0]
0xE18 JTAGOUTR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0xE1C Reserved Reserved
0xE20 Reserved Res.
BSEC_
UNMAP[31:0]
0xE24 UNMAPR
(1)
Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
0xE28 -
Reserved Res.
0xE3C
DBGREQ

HVALID
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

BSEC_SR NVSTATE[5:0]
0xE40

Reset value 0 0 0 0 0 0 0 0

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228
Boot and security control (BSEC) RM0486

Table 16. BSEC register map and reset values (continued)

Register name
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
Reset value

INIT_DONE
PROGFAIL
DISTURBF

OTPNVIR
OTPERR
OTPSEC

HIDEUP
PPLMF
AMEF

DEDF

BUSY
SECF
PPLF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
BSEC_OTPSR
0xE44

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0
0xE48 -
Reserved Res.
0xE7C
0xE80 + BSEC_
EPOCH[31:0]
0x4 * x EPOCHRx
(x= 0 to 1) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EPOCH_SEL
BSEC_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0xE88 EPOCHSELCR

Reset value 0

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BSEC_DBGCR AUTH_SEC[7:0] AUTH_HDPL[7:0] UNLOCK[7:0]
0xE8C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BSEC_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
UNLOCK[7:0]
0xE90 AP_UNLOCK
Reset value 0 0 0 0 0 0 0 0
BSEC_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
HDPL[7:0]
0xE94 HDPLSR
Reset value 0 0 0 0 0 0 B 4
BSEC_
INCR_HDPL[31:0]
0xE98 HDPLCR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BSEC_NEXTHD INCR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0xE9C PLCR [1:0]
Reset value 0 0
0xEA0 -
Reserved Reserved
0xEA8
0xEAC -
Reserved Reserved
0xEBC
0xEC0 -
Reserved Reserved
0xF3C
0xF40 + BSEC_
WOSDATA[31:0]
0x4*x WOSCRx
(x=0 to 7) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0xF60 -
Reserved Res.
0xFE4
BSEC_HRCR HRC[31:0]
0xFE8
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BSEC_WRCR WRC[31:0]
0xFEC
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1. See register description.

Refer to Section 2.3 for the register boundary addresses.

228/4691 RM0486 Rev 2

RM0486 OTP mapping (OTP)

5 OTP mapping (OTP)

STM32N6x7xx devices have 12032 OTP (one-time programmable) bits, which can be
read-accessed in 376 words: BSEC_OTP_DATAx (x = 0 to 375).
OTP bits are read or programmed by the BSEC (boot, security, and OTP control),as detailed
in Section 4: Boot and security control (BSEC). They are organized in regions:
• Lower OTP region (OTP0 to OTP127)
• Mid OTP region (OTP128 to OTP255)
• Upper OTP region (OTP256 to OTP375)
Before being programmed, the OTP bits are at 0. The OTP words are listed in Table 17:
• Description: acronym and function. Words marked “Available to customer” have no
predefined usage.
• Shadowed: loaded into a register after reset, can be read without a reload. A shadowed
word may be sticky-write-locked by earlier software (such as BOOTROM). The first ten
shadowed words are never writable.
• Prog-locked by ST: words locked during manufacturing.

Table 17. OTP mapping

Word Description Shadowed Prog-locked by ST

Lower OTP region

OTP0 OTP_HW_WORD0 Yes Yes
OTP1 OTP_HW_WORD1 Yes No
OTP2 OTP_HW_WORD2 Yes No
OTP3 OTP_HW_WORD3 Yes No
OTP4 OTP_HW_WORD4 Yes Yes
OTP5 ID0 Yes Yes
OTP6 ID1 Yes Yes
OTP7 ID2 Yes Yes
OTP8 OTP_RPN_OPTION Yes Yes
OTP9 OTP_RPN_CODING Yes Yes
OTP10 BOOTROM_CONFIG_1 No No
OTP11 BOOTROM_CONFIG_2 Yes No
OTP12 BOOTROM_CONFIG_3 No No
OTP13 BOOTROM_CONFIG_4 Yes No
OTP14 BOOTROM_CONFIG_5 Yes No
OTP15 BOOTROM_CONFIG_6 Yes No
OTP16 BOOTROM_CONFIG_7 Yes No
OTP17 BOOTROM_CONFIG_8 No No
OTP18 BOOTROM_CONFIG_9 No No

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OTP mapping (OTP) RM0486

Table 17. OTP mapping (continued)

Word Description Shadowed Prog-locked by ST

OTP19 BOOTROM_CONFIG_10 No No
OTP20 BOOTROM_CONFIG_11 No No
OTP21 BOOTROM_CONFIG_12 No No
OTP22 BOOTROM_CONFIG_13 No No
OTP23 BOOTROM_CONFIG_14 No Yes
OTP24 BOOT_TZ_EPOCH0 No No
OTP25 BOOT_TZ_EPOCH1 No No
OTP26 BOOT_TZ_EPOCH2 No No
OTP27 BOOT_TZ_EPOCH3 No No
OTP28 BOOT_TZ_EPOCH4 No No
OTP29 BOOT_TZ_EPOCH5 No No
OTP30 BOOT_TZ_EPOCH6 No No
OTP31 BOOT_TZ_EPOCH7 No No
OTP32 BOOT_NS_EPOCH0 No No
OTP33 BOOT_NS_EPOCH1 No No
OTP34 BOOT_NS_EPOCH2 No No
OTP35 BOOT_NS_EPOCH3 No No
OTP36 BOOT_NS_EPOCH4 No No
OTP37 BOOT_NS_EPOCH5 No No
OTP38 BOOT_NS_EPOCH6 No No
OTP39 BOOT_NS_EPOCH7 No No
OTP40 to OTP55 Available to customer No No
OTP56 TAMP_EN No No
OTP57 TAMP_CFM No No
OTP58 TAMP_CFG No No
OTP59 to OTP95 Available to customer No No
OTP96 to OTP99 Reserved - -
OTP100 to OTP103 Reserved - -
OTP104 to OTP123 Reserved - -
OTP124 HCONF1 Yes No
OTP125 to OTP127 Reserved - -
Mid OTP region
OTP128 STM32_CERTIF0 No Yes
OTP129 STM32_CERTIF1 No Yes
OTP130 STM32_CERTIF2 No Yes

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RM0486 OTP mapping (OTP)

Table 17. OTP mapping (continued)

Word Description Shadowed Prog-locked by ST

OTP131 STM32_CERTIF3 No Yes

OTP132 STM32_CERTIF4 No Yes
OTP133 STM32_CERTIF5 No Yes
OTP134 STM32_CERTIF6 No Yes
OTP135 STM32_CERTIF7 No Yes
OTP136 STM32_CERTIF8 No Yes
OTP137 STM32_CERTIF9 No Yes
OTP138 STM32_CERTIF10 No Yes
OTP139 STM32_CERTIF12 No Yes
OTP140 STM32_CERTIF12 No Yes
OTP141 STM32_CERTIF13 No Yes
OTP142 STM32_CERTIF14 No Yes
OTP143 STM32_CERTIF15 No Yes
OTP144 STM32PUBKEY0 No Yes
OTP145 STM32PUBKEY1 No Yes
OTP146 STM32PUBKEY2 No Yes
OTP147 STM32PUBKEY3 No Yes
OTP148 STM32PUBKEY4 No Yes
OTP149 STM32PUBKEY5 No Yes
OTP150 STM32PUBKEY6 No Yes
OTP151 STM32PUBKEY7 No Yes
OTP152 STM32PUBKEY8 No Yes
OTP153 STM32PUBKEY9 No Yes
OTP154 STM32PUBKEY10 No Yes
OTP155 STM32PUBKEY11 No Yes
OTP156 STM32PUBKEY12 No Yes
OTP157 STM32PUBKEY13 No Yes
OTP158 STM32PUBKEY14 No Yes
OTP159 STM32PUBKEY15 No Yes
OTP160 OTP_ROT_HASH0 No No
OTP161 OTP_ROT_HASH1 No No
OTP162 OTP_ROT_HASH2 No No
OTP163 OTP_ROT_HASH3 No No
OTP164 OTP_ROT_HASH4 No No
OTP165 OTP_ROT_HASH5 No No

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OTP mapping (OTP) RM0486

Table 17. OTP mapping (continued)

Word Description Shadowed Prog-locked by ST

OTP166 OTP_ROT_HASH6 No No
OTP167 OTP_ROT_HASH7 No No
OTP168 ST_RSSE_EDMK_DERIV_CSTE_FUSE No Yes
OTP169 OTP_MAC1_ADDR_LOW No No
OTP170 OTP_MAC1_ADDR_HIGH No No
OTP171 OTP_MAC2_ADDR_LOW No No
OTP172 OTP_MAC2_ADDR_HIGH No No
OTP173 to OTP255 Available to customer No No
Upper OTP region
OTP256 OTP_RMA_LOCK_PSWD0 Yes No
OTP257 OTP_RMA_LOCK_PSWD1 Yes No
OTP258 OTP_RMA_LOCK_PSWD2 Yes No
OTP259 OTP_RMA_LOCK_PSWD3 Yes No
OTP260 to OTP363 OEM secrets available to customer No No
OTP364 OEM_SECRET_FOR_CRYPTED_BOOT0 No No
OTP365 OEM_SECRET_FOR_CRYPTED_BOOT1 No No
OTP366 OEM_SECRET_FOR_CRYPTED_BOOT2 No No
OTP367 OEM_SECRET_FOR_CRYPTED_BOOT3 No No
OTP368 STM32PRVKEY0 No Yes
OTP369 STM32PRVKEY1 No Yes
OTP370 STM32PRVKEY2 No Yes
OTP371 STM32PRVKEY3 No Yes
OTP372 STM32PRVKEY4 No Yes
OTP373 STM32PRVKEY5 No Yes
OTP374 STM32PRVKEY6 No Yes
OTP375 STM32PRVKEY7 No Yes

The following OTP words are described in detail inTable 18 or by BSEC:

• OTP0 to OTP4: used by BSEC for the security life cycle (see Section 4: Boot and
security control (BSEC))
• OTP9: used to code device part number (see Section 79: Device electronic signature)
• OTP10 to OTP22: used for the boot ROM configuration
• OTP56 to OTP58: used to record tamper configuration
• OTP96 to OTP99 and OTP104 to OTP 111: used for analog calibration parameters, set
by ST
• OTP112 to OTP 119: used for engineering purposes, set by ST

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RM0486 OTP mapping (OTP)

• OTP120 to OTP123: used for settings such as analog trimming, set by ST

• OTP124: used for the product configuration by the user
• OTP125 to OTP 127: used for memory repair, set by ST.

Table 18. OTP fuse description (lower OTP region)

OTP OTP
Name or description Detailed description
word bits

OTP0 - OTP_HW_WORD0 OTP check word (virgin → non-virgin)

OTP1 - OTP_HW_WORD1 OTP security word to close security state
OTP word for reopening (close → open) via RMA password:
OTP2 - OTP_HW_WORD2
RMA bits
OTP word for reopening (close → open) via RMA password:
OTP3 - OTP_HW_WORD3
RMA tries bits
OTP4 - OTP_HW_WORD4 OTP word for TK retries (ECIES) and retention cell disabling
OTP5 - ID0
OTP6 - ID1 96-bit unique ID for engineering purpose
OTP7 - ID2
OTP8 - OTP_RPN_CODING Reserved
OTP9 - RPN_CODING See Section 79: Device electronic signature
- BOOTROM_CONFIG_1 Boot source configuration word
Status of ECIES ST key provisioning when it was attempted:
– 0 (failed): ECIES ST key provisioning last attempt failed
[0] stkeyprov_ecies_attempted
– 1 (successful): ECIES ST key provisioning last attempt
successful
– 0 (no): HWKEY not provisioned
[1] stkeyprov_ecies_ok
– 1 (yes): HWKEY provisioned
[6:2] Reserved Reserved
OTP10 Security counter involved in product ID for chip certificate
[14:7] security_counter
verification by HSM-OEM in SFI context
ST ECDSA public key ID (ST key instance fuse part) involved
[18:15] st_pub_key_id in product ID for chip certificate verification by HSM-OEM in
SFI context
[1-256] → [1-8]: Value of monotonic counter is X, where X is
the position of the most significant bit at 1.
[26:19] rssefw_active_signing_key
Eight possible ST public keys (ST key revocation feature for
RSSe_FW authentication)
[31:27] Reserved Reserved
- BOOTROM_CONFIG_2 -
– 0 (enabled): DCACHE used by boot ROM
[0] no_data_cache
OTP11 – 1 (disabled): DCACHE not used by boot ROM
– 0 (enabled): PLLs for CPU/AXI enabled for cold boot
[1] no_cpu_pll
– 1 (disabled): PLLs for CPU/AXI not enabled for cold boot

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OTP mapping (OTP) RM0486

Table 18. OTP fuse description (lower OTP region) (continued)

OTP OTP
Name or description Detailed description
word bits

– 0 (no): SDMMC1 uses default hard coded AFmux

[2] sdmmc1_not_default_af
– 1 (yes): SDMMC1 uses AFmux defined in OTP
– 0 (no): SDMMC2 uses default hard coded AFmux
[3] sdmmc2_not_default_af
– 1 (yes): SDMMC2 uses AFmux defined in OTP
[4] Reserved Reserved
If different from 0, identifies the flash memory used to boot:
– 1 (sdcard): SD-Card SDMMC1
– 2 (emmc): [Link] SDMMC1
– 3 (snor): XSPI NOR
– 4 (snand): XSPI NAND
[8:5] flash_boot_source
– 5 (hflash): XSPI HyperFlash
– 6 (pnand): FMC pNAND
– 7 (sdcard): SD-Card SDMMC2
– 8 (emmc): [Link] SDMMC2
– others: invalid
Each bit disables a boot source (default to UART if all
disabled):
– 0x01 (usb): USB boot source disabled
[16:9] boot_source_disable – 0x02 (uart): UART boot source disabled
– 0x04 (fdcan): FDCAN boot source disabled
OTP11 – 0x08 (spi): SPI boot source disabled
– 0x10 (i2c): I2C boot source disabled
– 0b001: SPI1 disabled
[19:17] spi_instance_disable – 0b010: SPI2 disabled
– 0b100: SPI3 disabled
– 0b001: USART1 disabled
[22:20] uart_instance_disable – 0b010: USART2 disabled
– 0b100: USART3 disabled
– 0b001: disable FDCAN1 disabled
[25:23] fdcan_instance_disable – 0b010: disable FDCAN2 disabled
– 0b100: disable FDCAN3 disabled
– 0b001: I2C1 disabled
[28:26] i2c_instance_disable – 0b010: I2C2 disabled
– 0b100: I2C3 disabled
– 0: boot on confirmed tamper
[29] dont_boot_on_cfm_tamper
– 1: do not boot on confirmed tamper
Enable the configuration of tampers in boot ROM before boot:
[30] tamp_boot_cfg_glob_enable – 0: configuration of tampers is disabled
– 1: configuration of tampers is enabled
[31] Reserved Reserved

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RM0486 OTP mapping (OTP)

Table 18. OTP fuse description (lower OTP region) (continued)

OTP OTP
Name or description Detailed description
word bits

- BOOTROM_CONFIG_3 -
OTP12 [1-0xFFFF] → [1-32]: Value of monotonic counter is X, where
[31:0] st_fsbl_monotonic_counter
X is the position of the most significant bit at 1
- BOOTROM_CONFIG_4 Boot source configuration word
– 0 (af_nopull_ls): AF; no pull; low speed
– 1 (af_nopull_ms): AF; no pull; medium speed
– 2 (af_nopull_hs): AF; no pull; high speed
– 3 (af_pullup_ls): AF; pull up; low speed
– 4 (af_pullup_ms): AF; pull up; medium speed
– 5 (af_pullup_hs): AF; pull up; high speed
– 6 (af_pulldown_ls): AF; pull down; low speed
– 7 (af_pulldown_ms): AF; pull down; medium speed
[3:0] mode0
– 8 (af_pulldown_hs): AF; pull down; high speed
– 9 (gpio_out_high): GPIO output high
– 10 (gpio_out_low): GPIO output low
– 11 (gpio_in): GPIO input
– 12 (gpio_open_nopull): GPIO open drain; No pull
– 13 (gpio_open_pullup): GPIO open drain; pull up
– 14 (gpio_open_pulldown): GPIO open drain; pull down
– 15 (gpio_analog): GPIO analog mode
[7:4] afmux0 Values between 0 and 15
– [0-15]: pin ID between 0 and 15 for GPIOA to GPIOG
OTP13 and GPIOP
[11:8] pin0 – [0-12]: pin ID between 0 and 12 for GPION
– [0-8]: pin ID between 0 and 8 for GPIOH and GPIOQ
– [0-5]: pin ID between 0 and 5 for GPIOO
– 0: reserved
– 1 (PA): Bank A
– 2 (PB): Bank B
– 3 (PC): Bank C
– 4 (PD): Bank D
– 5 (PE): Bank E
– 6 (PF): Bank F
[15:12] port0
– 7 (PG): Bank G
– 8 (PH): Bank H
– 9 (PN): Bank N
– 10 (PO): Bank O
– 11 (PP): Bank P
– 12 (PQ): Bank Q
– 0b1111: Invalid configuration
[19:16] mode1 idem BOOTROM_CONFIG_4.mode0
[23:20] afmux1 idem BOOTROM_CONFIG_4.afmux0

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Table 18. OTP fuse description (lower OTP region) (continued)

OTP OTP
Name or description Detailed description
word bits

[27:24] pin1 idem BOOTROM_CONFIG_4.pin0

OTP13
[31:28] port1 idem BOOTROM_CONFIG_4.port0
- BOOTROM_CONFIG_5 -
[3:0] mode0 idem BOOTROM_CONFIG_4.mode0
[7:4] afmux0 idem BOOTROM_CONFIG_4.afmux0
[11:8] pin0 idem BOOTROM_CONFIG_4.pin0
OTP14 [15:12] port0 idem BOOTROM_CONFIG_4.port0
[19:16] mode1 idem BOOTROM_CONFIG_4.mode0
[23:20] afmux1 idem BOOTROM_CONFIG_4.afmux0
[27:24] pin1 idem BOOTROM_CONFIG_4.pin0
[31:28] port1 idem BOOTROM_CONFIG_4.port0
- BOOTROM_CONFIG_6 -
[3:0] mode0 idem BOOTROM_CONFIG_4.mode0
[7:4] afmux0 idem BOOTROM_CONFIG_4.afmux0
[11:8] pin0 idem BOOTROM_CONFIG_4.pin0
OTP15 [15:12] port0 idem BOOTROM_CONFIG_4.port0
[19:16] mode1 idem BOOTROM_CONFIG_4.mode0
[23:20] afmux1 idem BOOTROM_CONFIG_4.afmux0
[27:24] pin1 idem BOOTROM_CONFIG_4.pin0
[31:28] port1 idem BOOTROM_CONFIG_4.port0
- BOOTROM_CONFIG_7 -
– 0 (no): boot ROM traces disabled
[0] disable_traces
– 1 (yes): boot ROM traces enabled
– 0 (no): HSE frequency auto-detection disabled
[1] disable_hse_freq_detect
– 1 (yes): HSE frequency auto-detection enabled
– 0 (no): HSE bypass detection disabled
[2] disable_hse_bypass_detect
– 1 (yes): HSE bypass detection enabled
OTP16 [4:3] Reserved Reserved
[5] fmc_force_sw_reset -
– 0 (no): emergency debug not requested
[6] emergency_debug_req
– 1 (yes): emergency debug requested
– 0 (no): BootROM does not support [Link] with 128-Kbyte
boot partition
[7] emmc_128k_boot_partition
– 1 (yes): BootROM supports [Link] with 128-Kbyte boot
partition

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RM0486 OTP mapping (OTP)

Table 18. OTP fuse description (lower OTP region) (continued)

OTP OTP
Name or description Detailed description
word bits

[8] Reserved Reserved

[9] iomgr_port -
[10] iomgr_muxen -
– 0b000 (auto): HSE value is auto-detected among 10, 12, 14,
16, 20, 24, 28, 32, 36, 40, and 48 MHz.
– 0b001: HSE = 19.2 MHz
– 0b010: HSE = 20 MHz
[13:11] HSE_value – 0b011: HSE = 24 MHz
– 0b100: HSE = 38.4 MHz
– 0b101: HSE = 40 MHz
– 0b110: HSE = 48 MHz
– 0b111: Reserved
– 0 (no): serial NAND plane select not needed
[14] snand_need_plane_select_1
– 1 (yes): serial NAND plane select needed
– 0 (unset): ECC unset
OTP16
– 1 (hamming): ECC 1 bit (Hamming)
[17:15] pnand_number_of_ecc_bits_1 – 2 (bch4): ECC 4 bits (BCH4)
– 3 (bch8): ECC 8 bits (BCH8)
– 4 (ondie): on-die ECC
– 0 (8 bits): data width is 8 bits
[18] pnand_bus_width_1
– 1 (16 bits): data width is 16 bits
[26:19] nand_nb_of_blocks_1 [1-256]: number of block = 256 × value
[28:27] nand_block_size_1 [1-4]: block size in number of pages
– 0 (64): 64 pages per block
[30:29] nand_page_size_1 – 1 (128): 128 pages per block
– 2 (256): 256 pages per block
– 0 (no): BootROM uses ONFI parameter table to get parallel
NAND parameters
[31] pnand_param_stored_in_otp
– 1 (yes): parallel NAND parameters are defined in bank1 or
bank2, depending on nand_config_distribution value
- BOOTROM_CONFIG_8 -
[1-256] → [1-8]: Value of monotonic counter is X, where X is
the position of the most significant bit at 1.
OTP17 [7:0] oem_ecdsa_active_key
Eight possible OEM public keys (OEM key revocation feature
for OEM-FSBL authentication)
[31:8] Reserved Reserved

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OTP mapping (OTP) RM0486

Table 18. OTP fuse description (lower OTP region) (continued)

OTP OTP
Name or description Detailed description
word bits

- BOOTROM_CONFIG_9 -
– 0 (closed_unlocked): device in CLOSED_UNLOCKED state.
Secure boot is not enforced (OEM FSBL authentication is
not mandatory).
[3:0] secure_boot
– 1 (closed_locked): device in CLOSED_LOCKED state.
Secure boot is enforced (OEM FSBL authentication is
mandatory).
– 0 (cryp): BootROM uses CRYP to decrypt FSBL
[4] fsbl_decrypt_prio
– 1 (saes): BootROM uses SAES to decrypt FSBL
– 0 (no): provisioning not done or not finished successfully.
Device is CLOSED_LOCKED_UNPROVD and accepts only
[8:5] prov_done ST-BootExtension FSBL.
– 1 (yes): provisioning successfully completed. Device is
CLOSED_LOCKED_PROVD and accepts only OEM FSBL.
OTP18
– 0 (yes): fingerprint feature is disabled
[12:9] enable_fingerprint
– 1 (no): fingerprint feature is enabled
[15:13] Reserved Reserved
Number of OTP words located in upper area
[360 -nb_added_stsecrets ... 359] provisioned (in encrypted
[21:16] nb_added_secrets mode) with ST secrets. These will be decoded and used by
RSSE fw. Coding up to 64 ST secrets to provision in EWS
(with DEV_BOOT)
– 0: do not lock debug enabling
[25:22] debug_lock
– [1-64]: lock debug enabling
– 0: the BootROM only sets bsec_epoch0
[26] ns_epoch_enable
– 1: the BootROM set both bsec_epoch0 and bsec_epoch1
[31:27] Reserved Reserved

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RM0486 OTP mapping (OTP)

Table 18. OTP fuse description (lower OTP region) (continued)

OTP OTP
Name or description Detailed description
word bits

- BOOTROM_CONFIG_10 -
[17:0] Reserved Reserved
– 1: 0xA2B3
– 2: 0xAA74
– 3: 0xA6BA
[20:18] rng_htcr_value – 4: 0x9AAE
– 5: 0x72AC
– 6: 0xAAC7
– others: RNG HTCR not modified
– 0: reserved
– 1 (PA): Bank A
– 2 (PB): Bank B
– 3 (PC): Bank C
OTP19 – 4 (PD): Bank D
– 5 (PE): Bank E
[24:21] dev_boot_port – 6 (PF): Bank F
– 7 (PG): Bank G
– 8 (PH): Bank H
– 9 (PN): Bank N
– 10 (PO): Bank O
– 11 (PP): Bank P
– 12 (PQ): Bank Q
– [0-15]: pin ID between 0 and 15 for GPIOA to GPIOG,
and GPIOP
[28:25] dev_boot_pin – [0-12]: pin ID between 0 and 12 for GPION
– [0-8]: pin ID between 0 and 8 for GPIOH and GPIOQ
– [0-5]: pin ID between 0 and 5 for GPIOO
[31:29] Reserved Reserved
- BOOTROM_CONFIG_11 -
OTP20 [1-0xFFFF] → [1-32]: Value of monotonic counter is X, where
[31:0] oem_fsbl_monotonic_counter
X is the position of the most significant bit at 1
- BOOTROM_CONFIG_12 -
OTP21 [1-0xFFFF] → [33-64]: Value of monotonic counter is 32 + X,
[31:0] oem_fsbl_monotonic_counter
where X is the position of the most significant bit at 1
OTP22 - BOOTROM_CONFIG_13 Reserved
OTP23 - BOOTROM_CONFIG_14 Reserved

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OTP mapping (OTP) RM0486

Table 18. OTP fuse description (lower OTP region) (continued)

OTP OTP
Name or description Detailed description
word bits

OTP24 - BOOTROM_TZ_EPOCH0
OTP25 - BOOTROM_TZ_EPOCH1
OTP26 - BOOTROM_TZ_EPOCH2
OTP27 - BOOTROM_TZ_EPOCH3 If the highest blown bit is the nth of these 256 bits,
OTP28 - BOOTROM_TZ_EPOCH4 the boot ROM sets BSEC3_EPOCH_TZ = n

OTP29 - BOOTROM_TZ_EPOCH5
OTP30 - BOOTROM_TZ_EPOCH6
OTP31 - BOOTROM_TZ_EPOCH7
OTP32 - BOOTROM_NS_EPOCH0
OTP33 - BOOTROM_NS_EPOCH1
OTP34 - BOOTROM_NS_EPOCH2
OTP35 - BOOTROM_NS_EPOCH3 If the highest blown bit is the nth of these 256 bits,
OTP36 - BOOTROM_NS_EPOCH4 the boot ROM sets BSEC3_EPOCH_NS = n

OTP37 - BOOTROM_NS_EPOCH5
OTP38 - BOOTROM_NS_EPOCH6
OTP39 - BOOTROM_NS_EPOCH7
OTP40
to - Customer zone Customer values
OTP55

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RM0486 OTP mapping (OTP)

Table 18. OTP fuse description (lower OTP region) (continued)

OTP OTP
Name or description Detailed description
word bits

- TAMP_EN -
[0] tamp1_enable 0: disabled, 1: enabled
[1] tamp2_enable 0: disabled, 1: enabled
[2] tamp3_enable 0: disabled, 1: enabled
[3] tamp4_enable 0: disabled, 1: enabled
[4] tamp5_enable 0: disabled, 1: enabled
[5] tamp6_enable 0: disabled, 1: enabled
[6] tamp7_enable 0: disabled, 1: enabled
[7] tamp8_enable 0: disabled, 1: enabled
[8] itamp1_enable 0: disabled, 1: enabled
OTP56 [9] itamp2_enable 0: disabled, 1: enabled
[10] itamp3_enable 0: disabled, 1: enabled
[11] itamp4_enable 0: disabled, 1: enabled
[12] itamp5_enable 0: disabled, 1: enabled
[13] itamp6_enable 0: disabled, 1: enabled
[14] itamp7_enable 0: disabled, 1: enabled
[15] itamp8_enable 0: disabled, 1: enabled
[16] itamp9_enable 0: disabled, 1: enabled
[17] Reserved Reserved
[18] itamp11_enable 0: disabled, 1: enabled
[31:19] Reserved Reserved

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OTP mapping (OTP) RM0486

Table 18. OTP fuse description (lower OTP region) (continued)

OTP OTP
Name or description Detailed description
word bits

- TAMP_CFM -
[0] tamp1_confirmed 0: potential tamper, 1: confirmed tamper
[1] tamp2_confirmed 0: potential tamper, 1: confirmed tamper
[2] tamp3_confirmed 0: potential tamper, 1: confirmed tamper
[3] tamp4_confirmed 0: potential tamper, 1: confirmed tamper
[4] tamp5_confirmed 0: potential tamper, 1: confirmed tamper
[5] tamp6_confirmed 0: potential tamper, 1: confirmed tamper
[6] tamp7_confirmed 0: potential tamper, 1: confirmed tamper
[7] tamp8_confirmed 0: potential tamper, 1: confirmed tamper
[8] itamp1_confirmed 0: potential tamper, 1: confirmed tamper
OTP57 [9] itamp2_confirmed 0: potential tamper, 1: confirmed tamper
[10] itamp3_confirmed 0: potential tamper, 1: confirmed tamper
[11] itamp4_confirmed 0: potential tamper, 1: confirmed tamper
[12] itamp5_confirmed 0: potential tamper, 1: confirmed tamper
[13] itamp6_confirmed 0: potential tamper, 1: confirmed tamper
[14] itamp7_confirmed 0: potential tamper, 1: confirmed tamper
[15] itamp8_confirmed 0: potential tamper, 1: confirmed tamper
[16] itamp9_confirmed 0: potential tamper, 1: confirmed tamper
[17] Reserved Reserved
[18] itamp11_confirmed 0: potential tamper, 1: confirmed tamper
[31:19] Reserved Reserved
- TAMP_CFG -
[1:0] tamp1_cfg 00: level low, 01: level high, 10: edge falling, 11: edge rising
[3:2] tamp2_cfg 00: level low, 01: level high, 10: edge falling, 11: edge rising
[5:4] tamp3_cfg 00: level low, 01: level high, 10: edge falling, 11: edge rising
[7:6] tamp4_cfg 00: level low, 01: level high, 10: edge falling, 11: edge rising
OTP58
[9:8] tamp5_cfg 00: level low, 01: level high, 10: edge falling, 11: edge rising
[11:10] tamp6_cfg 00: level low, 01: level high, 10: edge falling, 11: edge rising
[13:12] tamp7_cfg 00: level low, 01: level high, 10: edge falling, 11: edge rising
[15:14] tamp8_cfg 00: level low, 01: level high, 10: edge falling, 11: edge rising
[31:16] Reserved Reserved
OTP59
to - Reserved Reserved
OTP95

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RM0486 OTP mapping (OTP)

Table 18. OTP fuse description (lower OTP region) (continued)

OTP OTP
Name or description Detailed description
word bits

OTP96
to - Reserved Reserved
OTP99
OTP100
to - Reserved Reserved
OTP102
OTP103 - Reserved Reserved
OTP104
to - Reserved Reserved
OTP123
- HCONF1 -
[0] IWDG1_HW IWDG1 start on reset
[1] IWDG1_FZ_STOP IWDG1 freeze in Stop mode
[2] IWDG1_FZ_STANDBY IWDG1 freeze in Standby mode
[9:3] Reserved Reserved
[10] RST_STOP Reset caused if the device is put in Stop mode
[11] RST_STDBY Reset caused if the device is put in Standby mode
– 0: BOR disabled
[12] SELINBORH
– 1: BOR = 2.7 V
VDDIO5 I/O segment below 2.5 V for I/O mode.
[13] HSLV_VDDIO5
OTP124 The I/O segment is used by SDMMC2 port.
VDDIO4 I/O segment below 2.5 V for I/O mode (I/O segment
[14] HSLV_VDDIO4
used by SDMMC1 port)
VDDIO3 I/O segment below 2.5 V for I/O mode (I/O segment
[15] HSLV_VDDIO3
used by XSPIM port 2)
VDDIO2 I/O segment below 2.5 V for I/O mode (I/O segment
[16] HSLV_VDDIO2
used by XSPIM port 1)
[17] HSLV_VDD Main I/O segment below 2.5 V for I/O mode
[19:18] Reserved Reserved
– 0: scan and bist available
[20] DFT_DISABLE
– 1: scan and bist only available on an OPEN part
[31:21] Reserved Reserved
OTP125
to - Reserved Reserved
OTP127

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OTP mapping (OTP) RM0486

Table 19. OTP fuse description (mid OTP region)

OTP words Name or description Detailed description

OTP128 STM32CERTIF0
OTP129 STM32CERTIF1
OTP130 STM32CERTIF2
OTP131 STM32CERTIF3
OTP132 STM32CERTIF4
OTP133 STM32CERTIF5
OTP134 STM32CERTIF6
OTP135 STM32CERTIF7 STM32 device certificate
OTP136 STM32CERTIF8 (signature of the public key)

OTP137 STM32CERTIF9
OTP138 STM32CERTIF10
OTP139 STM32CERTIF11
OTP140 STM32CERTIF12
OTP141 STM32CERTIF13
OTP142 STM32CERTIF14
OTP143 STM32CERTIF15
OTP144 STM32PUBKEY0
OTP145 STM32PUBKEY1
OTP146 STM32PUBKEY2
OTP147 STM32PUBKEY3
OTP148 STM32PUBKEY4
OTP149 STM32PUBKEY5
OTP150 STM32PUBKEY6
OTP151 STM32PUBKEY7
STM32 device public key
OTP152 STM32PUBKEY8
OTP153 STM32PUBKEY9
OTP154 STM32PUBKEY10
OTP155 STM32PUBKEY11
OTP156 STM32PUBKEY12
OTP157 STM32PUBKEY13
OTP158 STM32PUBKEY14
OTP159 STM32PUBKEY15

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RM0486 OTP mapping (OTP)

Table 19. OTP fuse description (mid OTP region) (continued)

OTP words Name or description Detailed description

OTP160 OTP_ROT_HASH0
OTP161 OTP_ROT_HASH1
OTP162 OTP_ROT_HASH2
OTP163 OTP_ROT_HASH3
Hash of Table of hashes of OEM public keys
OTP164 OTP_ROT_HASH4
OTP165 OTP_ROT_HASH5
OTP166 OTP_ROT_HASH6
OTP167 OTP_ROT_HASH7
ST Encryption Decryption Master Key Derivation
OTP168 ST_RSSE_EDMK_DERIV_CSTE_FUSE
constant
OTP169 OTP_MAC1_ADDR_LOW
MAC_ADDR1
OTP170 OTP_MAC1_ADDR_HIGH
OTP171 OTP_MAC2_ADDR_LOW
MAC_ADDR2
OTP172 OTP_MAC2_ADDR_HIGH
OTP173 to
Available to customer -
OTP255
OTP256 OTP_RMA_LOCK_PSWD
OTP257 OTP_RMA_LOCK_PSWD
RMA password
OTP258 OTP_RMA_LOCK_PSWD
OTP259 OTP_RMA_LOCK_PSWD
OTP260 to
OEM secrets available to customer -
OTP363
OTP364 OEM_SECRET_FOR_CRYPTED_BOOT0
OTP365 OEM_SECRET_FOR_CRYPTED_BOOT1
OEM secret used to derive FSBL decryption key
OTP366 OEM_SECRET_FOR_CRYPTED_BOOT2
OTP367 OEM_SECRET_FOR_CRYPTED_BOOT3
OTP368 STM32PRVKEY0
OTP369 STM32PRVKEY1
OTP370 STM32PRVKEY2
OTP371 STM32PRVKEY3
STM32 device private key (ST)
OTP372 STM32PRVKEY4
OTP373 STM32PRVKEY5
OTP374 STM32PRVKEY6
OTP375 STM32PRVKEY7

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Resource isolation framework security controller (RIFSC) RM0486

6 Resource isolation framework security controller

(RIFSC)

6.1 Introduction
Resource isolation framework (RIF) is a set of hardware blocks designed to enforce and
manage isolation of STM32 hardware resources like memory and peripherals. Some
resources (such as GP/HPDMA) manage their own security configuration internally
(they are configured locally). Such resources are called “RIF-aware”. Most resources are
“non-RIF-aware”. The RIFSC centralizes the security configuration of such non-RIF-aware
resources.

6.2 RIFSC main features

• RISC registers associated with RISUP logic (resource isolation slave unit for
peripherals) sitting in front of the configuration port of non-RIF-aware peripherals, and
with RCC peripheral clock control logic, assigning security and privilege levels to
peripheral access and peripheral clock control.
• RIMC registers associated with RIMU logic (resource isolation master unit), assigning
non-RIF-aware bus masters the secure, privilege and compartment (CID) information
they drive onto the system bus when initiating AXI transactions.
• Secure guard, where an AXI bus master port is forced to be nonsecure when its
associated configuration port is programmed nonsecure
• Support for a special debug domain, giving greater access for the debugger

6.3 RIFSC functional description

6.3.1 RIFSC reset and clocks

The RIFSC has a single reset. After a system reset, all non-RIF-aware peripherals become
non-secure and unprivileged, reachable by any CID.

6.3.2 RISUP
RISUP blocks are instantiated in front of the AHB configuration port of non-RIF-aware
peripherals to filter configuration accesses.
Each non-RIF-aware peripheral is assigned a unique “RISUP index” p < 128. Whenever the
RISUP in front of peripheral p blocks an illegal access, it sends an “illegal access event”
pulse to the IAC. The IAC records this event in the IAFp bit of the relevant IAC_ISRx
register. Thus, the RISUP index is aligned with the IAC index.
For x < 4 and i < 32, the filtering is determined as follows.
• If RIFSC_RISC_SECCFGx[i] = 1, then nonsecure accesses to peripheral p = i + 32x
are blocked. Also, nonsecure world attempts to program RCC registers to turn off the
clock of (or reset) peripheral p are blocked.

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• If RIFSC_RISC_PRIVCFGRx[i] = 1, then user accesses to peripheral p = i + 32x are

blocked. Also, attempts by a user process to program RCC registers to turn off the
clock of (or reset) peripheral p are blocked.
Whenever the RCC detects an illegal attempt to turn off a clock of (or reset) a peripheral,
it sends an event pulse to the IAC (recorded in the IAF136 bit of the relevant IAC_ISRx
register).
Note: There is no record of which peripheral was the object of this illegal attempt.
Table 20 identifies the RISUP index of each non-RIF-aware peripheral.

Table 20. RISUP indexes

RISUPs 31 to 0 (see RIFSC_RISC_PRIVCFGR0 / SECCFGR0 / RCFGLOCKR0)
31
30
29
28
27
26
LPUART1 25
USART10 24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
SPI6/I2S6 5
4
3
SPI3/I2S3 2
SPI2/I2S2 1
SPI1/I2S1 0
FDCAN1

USART6

USART3
USART2
USART1
UART9
UART8
UART7

UART5
UART4
TIM5
TIM4
TIM3
TIM2
TIM1

SAI2

SAI1

SPI5
SPI4
I3C2
I3C1
I2C4
I2C3
I2C2
I2C1

-
..

RISUPs 63 to 32 (see RIFSC_RISC_PRIVCFGR1 / SECCFGR1 / RCFGLOCKR1)

63
62
61
60
59
58
OTG2_HS 57
OTG1_HS 56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
SDMMC2
SDMMC1
SPDIFRX
SYSCFG

GFXTIM
LPTIM5
LPTIM4
LPTIM3
LPTIM2
LPTIM1
UCPD1

MDIOS

TIM18
TIM17
TIM16
TIM15
TIM14
TIM13
TIM12

TIM10
TIM11
MDF1
ADF1
ETH1

TIM9
TIM8
TIM7
TIM6
-

..

RISUPs 95 to 64 (see RIFSC_RISC_PRIVCFGR2 / SECCFGR2 / RCFGLOCKR2)

95
94
93
CSI2HOST 92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
VREFBUF
DCMIPP

WWDG
CRYP1

ADC12
XSPIM
XSPI3
XSPI2
XSPI1

MCE4
MCE3
MCE2
MCE1

HASH

IWDG
SAES
DCMI

RNG
FMC

CRC
PKA
-

-
-
-
-
-
-

-
..

RISUPs 127 to 96 (see RIFSC_RISC_PRIVCFGR3 / SECCFGR3 / RCFGLOCKR3)

127
126
125
124
123
122
121
120

109
108
107
106
105
104
103
LTDC_CMN 102
101
100
119
118
117
116
115
114
113
112

110
111

99
98
97
96
GFXMMU
LTDC_L2
LTDC_L1

ICACHE
DMA2D

VENC
JPEG
GPU
NPU
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

The RISUP generates a bus error if an instruction fetch arrives at the peripheral.

6.3.3 RCC security settings for RIF-aware peripherals and RAMs

Table 21 shows the use made of the RIFSC to configure the security and privilege access
rights for resetting or gating the clock of RIF-aware peripherals and RAMs (resources that
do not have RISUPs in front of them). Just as for all the non-RIF-aware peripherals with
RISUPs mentioned above, the outputs of the registers below are also wired to the RCC.

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Table 21. RISC indexes purely for RCC security control

RCC security controls 159 to 128 (RIFSC_RISC_PRIVCFGR4 / SECCFGR4 / RCFGLOCKR4)
159
158
157
156
155
154
153
152
151
150
149
148
147
CACHEAXI RAM 146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
CPU RAM1
CPU RAM0
NPU config

VENCRAM
BKPSRAM
AHBRAM2
AHBRAM1

FLEXRAM

GPDMA1
HPDMA1
GPIOA

RTC
-

-
-
-
-
-

-
-
-

-
-
-
-
-
-

-
-
...
RCC security controls 191 to 160 (RIFSC_RISC_PRIVCFGR5 / SECCFGR5 / RCFGLOCKR5)
191
190
189
188
187
186
185
184
183
XSPIPHYCOMP 182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
NPU_RAM3
NPU_RAM2
NPU_RAM1
NPU_RAM0
XSPIPHY2
XSPIPHY1
RAMCFG

GPIOQ

GPIOO

GPIOG
GPION

GPIOH

GPIOD
GPIOC
GPIOP

GPIOE

GPIOB
GPIOF
MCO2
MCO1
HDP

DTS
-

-
-

-
-

-
Note: For the RIF-aware peripherals, it is the responsibility of the trusted domain software to make
sure this security configuration of the control of the clock and reset of the peripheral is
consistent with the internal security configuration of this peripheral.

6.3.4 RIMU
The security attributes (CID, security, privilege) of accesses made by a non-RIF-aware
peripheral that is an AXI bus master, can be configured in RIMC_ATTRx registers, where
x is the “RIMU index” of the peripheral. Table 22 gives the index of each of these AXI bus
master peripherals, and the index of the related RISUP protecting the configuration port of
this peripheral. If nonsecure world software is permitted to configure the peripheral, then the
RIMU_ATTRx[MSEC] setting is ignored, and all AXI accesses initiated by the peripheral are
forced to be nonsecure too. This override mechanism is referred to as “secure guard”.
..

Table 22. RIMU resource assignment

Master index Master name Secure guard RISUP index

0 Trace (ETR) No RISUP

1 NPU 106
2 SDMMC1 53
3 SDMMC2 54
4 OTG1 56
5 OTG2 57
6 ETH1 60
7 GPU 99
8 DMA2D 101

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Table 22. RIMU resource assignment (continued)

Master index Master name Secure guard RISUP index

9 DCMIPP 93
10 LTDC_L1 103
11 LTDC_L2 104
12 VENC 97

RIMC registers must be initialized by the secure privileged software after the device reset.
Optionally, this software can set the GLOCK bit in RIMC_CR, preventing further writes to all
RIMC registers. This bit can only be cleared by a power-on reset.
The RISC_RIMC_CR register contains a DAPCID field that gives the CID value used by
debugger (DAP) accesses onto the AXI bus. The reset value of this register is 0x7.
All RISAFs treat a 0x7 as a legal CID value, regardless of their configuration. The secure
privileged master can reprogram the DAPCID to allow the DAP to mimic another
compartment (for example, to debug the security configuration).

6.4 RIFSC registers

These registers are accessible through the register interface of the RIFSC peripheral.

6.4.1 RIFSC RISC slave configuration register x (RIFSC_RISC_CR)

Address offset: 0x000
Reset value: 0x0000 0000
Secure privileged write access only. Any read access is allowed on this register. Writes are
ignored if GLOCK is set in this register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. GLOCK

rs

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 GLOCK: Global lock
This bit locks the configuration of RIFSC RISC registers until next reset. This bit is cleared by
default and, once set, it cannot be reset until global RIFSC reset.
0: RIFSC RISC registers are writable.
1: All writes to RIFSC RISC registers are ignored.

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6.4.2 RIFSC RISC slave security configuration register x

(RIFSC_RISC_SECCFGRx)
Address offset: 0x010 + 0x4 * x, (x = 0 to 5)
Reset value: 0x0000 0000
Nonsecure or unprivileged writes to this register are ignored, while any read is allowed.
Writes are ignored if GLOCK is set in RIFSC_RISC_CR.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SEC{i + 32 * x}

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SEC{i + 32 * x}

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 SEC{i + 32 * x}: security configuration for peripheral {i + 32 * x} (i = 0 to 31)

0: Secure and nonsecure data access are granted to the peripheral {i + 32 * x}.
1: Secure data access only are granted to the peripheral {i + 32 * x}.

6.4.3 RIFSC RISFC slave privileged register x

(RIFSC_RISC_PRIVCFGRx)
Address offset: 0x030 + 0x4 * x, (x = 0 to 5)
Reset value: 0x0000 0000
Unprivileged writes to this register are ignored, while any read is allowed. Writes are ignored
if GLOCK is set in RIFSC_RISC_CR.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PRIV{i + 32 * x}

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PRIV{i + 32 * x}

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 PRIV{i + 32 * x}: privileged-only access permission for peripheral {i + 32 * x} (i = 0 to 31)
0: Privileged and unprivileged data access are granted to the peripheral {i + 32 * x}.
1: Privileged data access only are granted to the peripheral {i + 32 * x}.
Note: If corresponding SEC{i + 32 * x} bit is set in RIFSC_RISC_SECCFGRx, this bit can only
be written by a secure privileged application.

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6.4.4 RIFSC RISC slave resource configuration lock register x

(RIFSC_RISC_RCFGLOCKRx)
Address offset: 0x050 + 0x4 * x, (x = 0 to 5)
Reset value: 0x0000 0000
Secure privileged write access only. Any read access is allowed on this register. Writes are
ignored if GLOCK is set in this register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RLOCK{i + 32 * x}

rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RLOCK{i + 32 * x}

rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs

Bits 31:0 RLOCK{i + 32 * x}: resource lock for peripheral {i + 32 * x} (i = 0 to 31)

This bit is set to lock the peripheral resource {i + 32 * x}. It is cleared by default and, once set,
this bit cannot be cleared until the RIFSC RISC peripheral is reset.
0: SEC{i + 32 * x} in RIFSC_RISC_SECCFGRx and PRIV{i + 32 * x} in
RIFSC_RISC_PRIVCFGRx are writable.
1: Writes to SEC{i + 32 * x} and PRIV{i + 32 * x} are ignored.

6.4.5 RIFSC RIMC master configuration register (RIFSC_RIMC_CR)

Address offset: 0xC00
Reset value: 0x0000 0710
Secure privileged write access only. Any read access is allowed on this register. Writes are
ignored if GLOCK is set in RIFSC_RISC_CR.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. DAPCID[2:0] Res. Res. Res. Res. Res. Res. Res. GLOCK

rw rw rw rs

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:8 DAPCID[2:0]: debug access port compartment ID
This bitfield defines the CID of the DAP.
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 GLOCK: global lock
This bit is used to lock the configuration of RIFSC RIMC registers until next reset. This bit is
cleared by default and, once set, it cannot be reset until global RIFSC reset.
0: RIFSC RIMC registers are writable.
1: All writes to RIFSC RIMC registers are ignored.

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6.4.6 RIFSC RIMC master attribute register x (RIFSC_RIMC_ATTRx)

Address offset: 0xC10 + x * 0x4 (x = 0 to 12)
Reset value: 0x0000 0000
Secure privileged write access only. Any read access is allowed on this register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. MPRIV MSEC Res. MCID[2:0] Res. Res. Res. Res.

rw rw rw rw rw

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 MPRIV: master privileged
Value of the privileged flag on the interconnect for this master.
0: This master is unprivileged.
1: This master is privileged.
Bit 8 MSEC: master secure
Value of the secure flag on the interconnect for this master.
0: This master is nonsecure.
1: This master is secure.
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 MCID[2:0]: master CID
Value of the CID flag on the interconnect for this master. This bitfield cannot be written with
a value of 0x7 (write to MCID[2:0] is ignored).
Bits 3:0 Reserved, must be kept at reset value.

6.4.7 RIFSC peripheral protection status register 0 (RIFSC_PPSR0)

Address offset: 0xFB0
Reset value: 0xFFFF FF7F

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PPEN{i}

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PPEN{i}

r r r r r r r r r r r r r r r r

Bits 31:0 PPEN{i}: peripheral protection enable {i} (i = 0 to 31)

0: SEC{i}, PRIV{i}, and RLOCK{i} bits are not present.
1: SEC{i}, PRIV{i}, and RLOCK{i} bits are present.

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6.4.8 RIFSC peripheral protection status register 1 (RIFSC_PPSR1)

Address offset: 0xFB4
Reset value: 0x77FF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PPEN{i + 32}

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PPEN{i + 32}

r r r r r r r r r r r r r r r r

Bits 31:0 PPEN{i + 32}: peripheral protection enable {i + 32} (i = 0 to 31)

0: SEC{i + 32}, PRIV{i + 32}, and RLOCK{i + 32} bits are not present.
1: SEC{i + 32}, PRIV{i + 32}, and RLOCK{i + 32} bits are present.

6.4.9 RIFSC peripheral protection status register 2 (RIFSC_PPSR2)

Address offset: 0xFB8
Reset value: 0xF7DF F03B

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PPEN{i + 64}

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PPEN{i + 64}

r r r r r r r r r r r r r r r r

Bits 31:0 PPEN{i + 64}: peripheral protection enable {i + 64} (i = 0 to 31)

0: SEC{i + 64}, PRIV{i + 64}, and RLOCK{i + 64} bits are not present.
1: SEC{i + 64}, PRIV{i + 64}, and RLOCK{i + 64} bits are present.

6.4.10 RIFSC peripheral protection status register 3 (RIFSC_PPSR3)

Address offset: 0xFBC
Reset value: 0x0000 05FF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PPEN{i + 96}

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PPEN{i + 96}

r r r r r r r r r r r r r r r r

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Bits 31:0 PPEN{i + 96}: peripheral protection enable {i + 96} (i = 0 to 31)

0: SEC{i + 96}, PRIV{i + 96}, and RLOCK{i + 96} bits are not present.
1: SEC{i + 96}, PRIV{i + 96}, and RLOCK{i + 96} bits are present.

6.4.11 RIFSC peripheral protection status register 4 (RIFSC_PPSR4)

Address offset: 0xFC0
Reset value: 0xBBEF FFEF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PPEN{i + 128}

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PPEN{i + 128}

r r r r r r r r r r r r r r r r

Bits 31:0 PPEN{i + 128}: peripheral protection enable {i + 128} (i = 0 to 31)

0: SEC{i + 128}, PRIV{i + 128}, and RLOCK{i + 128} bits are not present.
1: SEC{i + 128}, PRIV{i + 128}, and RLOCK{i + 128} bits are present.

6.4.12 RIFSC peripheral protection status register 5 (RIFSC_PPSR5)

Address offset: 0xFC4
Reset value: 0x7DDE EF7F

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PPEN{i + 160}

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PPEN{i + 160}

r r r r r r r r r r r r r r r r

Bits 31:0 PPEN{i + 160}: peripheral protection enable {i + 160} (i = 0 to 31)

0: SEC{i + 160}, PRIV{i + 160}, and RLOCK{i + 160} bits are not present.
1: SEC{i + 160}, PRIV{i + 160}, and RLOCK{i + 160} bits are present.

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6.4.13 RIFSC register map

Table 23. RIFSC register map and reset values

Register
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11
name

9
8
7
6
5
4
3
2
1
0 GLOCK
RIFSC_RISC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x000 _CR

Reset value 0
0x010 + RIFSC_RISC_
SEC{i + 32 * x}
0x4 * x SECCFGRx
(x = 0 to 5)
Last
address: Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x024
0x028-
Reserved Reserved
0x02C
0x030 + RIFSC_RISC_
PRIV{i + 32 * x}
0x4 * x PRIVCFGRx
(x = 0 to 5)
Last
address: Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x044
0x048-
Reserved Reserved
0x04C
0x050 + RIFSC_RISC_
RLOCK{i + 32 * x}
0x4 * x RCFGLOCKRx
(x = 0 to 5)
Last
address: Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x064
0x68-
Reserved Reserved
0xBFC

GLOCK
RIFSC_RIMC DAPCID
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
0xC00 _CR [2:0]

Reset value 1 1 1 0
0xC04-
Reserved Reserved
0xC0C
0xC10 +
MPRIV

RIFSC_RIMC
MSEC

0x4 * x
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.
Res.
Res.
MCID[2:0]
(x = 0 to _ATTRx
12) Last
address: Reset value 0 0 0 0 0
0xC40
0xC44 to
Reserved Reserved
0xFAC
RIFSC_PPSR0 PPEN{i}
0xFB0
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
RIFSC_PPSR1 PPEN{i + 32}
0xFB4
Reset value 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
RIFSC_PPSR2 PPEN{i + 64}
0xFB8
Reset value 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 0 1 1
RIFSC_PPSR3 PPEN{i + 96}
0xFBC
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1
RIFSC_PPSR4 PPEN{i + 128}
0xFC0
Reset value 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1
RIFSC_PPSR5 PPEN{i + 160}
0xFC4
Reset value 0 1 1 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1

Refer to Section 2.3 for the register boundary addresses.

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7 Resource isolation slave unit for address space

protection (full version) (RISAF)

7.1 RISAF introduction

The RIF (resource isolation framework) is a comprehensive set of hardware blocks
designed to enforce and manage isolation of STM32 hardware resources, like memory and
peripherals.
Through RISAF registers, a secure privileged software application or the application to
whom the configuration has been delegated, assigns memory regions and subregions to
one or more security domains (secure, privileged, compartment).

7.2 RISAF main features

• Assign variable sized address space regions and subregions to security domains.
• Make memory regions:
– Restricted to one or more than one hardware compartments
– Secure-only or nonsecure-only
– Privileged-only or privileged/unprivileged
– Read-only, write-only, or read/write
• The secure privileged software can delegate configuration and positioning of a
subregion (within a region) to another security domain.
• The secure privileged software can delegate configuration and positioning of
a subregion (within a nonsecure region) to a nonsecure privileged software.

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7.3 RISAF implementation

The following table describes the characteristics of the available RISAFs, including
watermark programming details (such as granularity and protected address space).

Table 24. RISAF resource assignment

Number of Address space
Protected Resource Target IAC CID
configurable Granularity size and
memory name bus index management
base regions alignment

TCM RISAF1 139 1 Gbyte

CPUAXI RAM0 RISAF2 140 7
1 Mbyte
CPU AXI RAM1 RISAF3 141
AXI 4 Kbytes
NPU master 0 RISAF4 142
NPU master 1 RISAF5 143 11 4 Gbytes Programmable
CID filtering on
CPU master RISAF6 144
system bus
FLEXRAM RISAF7 145 512 Kbytes (CID=0 to 7).
To delegate to
CACHEAXI RAM RISAF8 146 256 Kbytes
nonsecure set
VENCRAM RISAF9 147 128 Kbytes DCCID = 1.
XSPI1 RISAF11 AXI 149 7 4 Kbytes
XSPI2 RISAF12 150
256 Mbytes
XSPI3 RISAF13 151
FMC RISAF14 152
CACHEAXI Fixed CID0
RISAF15 153 2 4 bytes 4 Kbytes
configuration port filtering on
AHB RAM1 RISAF21 154 system bus.
AHB
7 16 Kbytes To delegate to
AHB RAM2 RISAF22 155 512 bytes nonsecure set
Backup RAM RISAF23 156 3 4 Kbytes DCCID = 0.

RISAF4/5/6 are used to partition the 2-Mbyte NPU RAM. This memory is implemented as
four RAM cuts, each with its own AXI target port, but using an interleaved (re-mapped)
addressing scheme. To retain the software normal view of memory addressing, the RISAFs
protecting these RAMs are placed on the three entry ports of the NPU interconnect. The
user must program an identical partitioning into each of the three RISAFs. These RISAFs
are furnished with two extra regions that the secure privileged software must configure to be
transparent (permissive) to all accesses either side of the NPU RAMs.
As summarized in the CID management column of Table 24, the AHB bus does not carry
CID information (it is fixed at 0). The RISAFs on the AHB bus only filter on security and
privilege, in read or in write (using RDENC0 or WRENC0 bits, respectively). All accesses
are effectively assumed to be owned by the CPU. When a secure privileged application
delegates to the nonsecure world the access control configuration of subregions in a
nonsecure base region, DCEN must be set, and DCCID and SRCID must stay at 0 for this
specific base region.

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As summarized in Table 24 the AXI bus does carry CID information. All AHB configuration
accesses to AXI RISAF registers are assumed to come from CID1. When a secure
privileged application delegates to the nonsecure world the access control configuration of
subregions in a nonsecure base region, DCEN must be set and DCCID must equal 0x1.
The AHB configuration port of the CACHEAXI is protected by a small RISAF that only offers
two base regions. These are expected to be configured to cover the register address spaces
either side of the registers controlling cache invalidation. The cache invalidation operation
can thus be reserved for use only by the secure privileged software, because the controlling
registers are left in the default region 0.

7.4 RISAF functional description

7.4.1 RISAF block diagram

The following figure shows the block diagram of the RISAF associated with the IAC, and
optionally, a memory controller.

Figure 5. RISAF block diagram

32-bit AHB bus
hck

IAC

tdcid AHB interface RISAF

risaf_ilac
Base-region registers
Subregions registers
Master

Memory-mapped
... sck sck

Master RIF gate

area
cid

MSv67866V1

1. The tdcid input value is equal to CID = 1.

7.4.2 RISAF internal signals

Table 25 describes internal signals available at RISAF level, not at product level (on pins).

Table 25. RISAF internal input/output signals

Name Type Description

risaf_sck System bus clock, also used by the protected memory controller
Digital input
risaf_hclk AHB bus clock
risaf_ilac Digital output Illegal access signal to IAC

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7.4.3 RISAF reset and clocks

The RISAF peripheral has two clocks, one for its AHB register interface, and one for its
system bus interfaces. The system bus clock is shared with the system bus memory
controller target.
The RISAF peripheral has a single reset input.
Address spaces protected by the RISAF are by default secure, privileged, and CID = 1 only.

7.4.4 RISAF address space management

Through RISAF registers, a secure privileged software application, or the application to
which the configuration has been delegated, assigns memory regions to one or more
security domains (secure, privilege, compartment ID). Figure 6 illustrates the principle of this
allocation.

Figure 6. RISAF region programming

Accesses 1: Accesses 2: Accesses 3: Accesses 4:
Primary region Base region Subregion filtering Overlapped area
filtering applies filtering applies applies (*) filtering applies (*)

Subregion 2B
(*) Base region filtering
Subregion 1A Subregion 2A does not apply
Base region 1 (nested) Base region 2 (nested)

Primary region (default region 0)

MSv67868V2

As shown in Figure 6, there are multiple types of access filtered by RISAF:

• Accesses 1 - Default region: access to an area not belonging to any enabled base
region. Filtering for such access is fixed to secure, privileged and CID = 1 only.
• Accesses 2 - Application region > 0: access to an area in an enabled base region, not
belonging to any enabled subregion. Filtering for such access is defined in the base
region, where one or more compartments can be granted specific accesses.
• Accesses 3 - Non overlapped subregion: access to an area in an enabled nested
subregion. Filtering for such access is defined in the subregion, with only one
compartment that can be granted access.
• Accesses 4 - Overlapped subregion: accesses to an area overlapping two enabled
nested subregions. In this case, filtering rules for these subregions are used by the
RISAF as follows:
– If both subregions are secure (resp. nonsecure), the overlap is secure
(resp. nonsecure).
– If one subregion is nonsecure (resp. unprivileged), the overlap is nonsecure (resp.
unprivileged).
– If one of the two subregions grants access to a compartment, the access can go
through. Up to two compartments can be granted access to an overlapped
subregion.

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Note: When a base or subregion is disabled, the associated filtering is disabled as well. For
access types 3 or 4 (detailed above), base region filtering rules do not apply.

7.4.5 RISAF programming

Only the secure privileged software can set up the access configuration to base region x
through RISAF_REGx_CFGR, RISAF_REGx_CIDCFGR, RISAF_REGx_STARTR, and
RISAF_REGx_ENDR.
The secure privileged software, or the application to which the subregion z configuration has
been delegated in RISAF_REGx_zNESTR, can set up the access configuration to
subregion z of base region x through RISAF_REGx_zCFGR, RISAF_REGx_zSTARTR, and
RISAF_REGx_zENDR (z = A or B).
As shown in Table 26, subregion right options depend upon the base region privileged and
security rights. Base regions can be defined only as privileged.

Table 26. RISAF subregion security setup matrix

Nested subregion rights
Base region rights
Secure, Secure, Nonsecure, Nonsecure,
privileged unprivileged privileged unprivileged

Secure, privileged OK(1) OK OK OK

Secure, unprivileged Not allowed OK(1) Not allowed OK
Nonsecure, privileged Not allowed Not allowed OK(1) OK
Nonsecure, unprivileged Not allowed Not allowed Not allowed OK(1)
1. Default configuration

Configuring base regions in RISAF

If the secure privileged software must use a base region x (for example at boot time), the
following steps are recommended.
1. The secure privileged software sets start and end addresses for each of the required
base region x, using RISAF_REGx_STARTR and RISAF_REGx_ENDR:
– These registers are initialized with 32-bit physical addresses when protected
address space size is 4 Gbytes. For different sizes, refer to the register
description.
– Base regions must be defined within their primary region. The hardware enforces
this rule if the application does not follow it.
2. For each of the above region x, the secure privileged software programs
RISAF_REGx_CIDCFGR, granting read and/or write access to any compartment.
3. For each of the above region x, the secure privileged software finalizes the
programming by configuring RISAF_REGx_CFGR, setting up security parameters
(secure or encrypted if applicable), and granting privileged-only access, or not, to each
compartment that has access to the region (see step 2). Privileged parameter is fixed
to privileged only.
4. After a final check on the above configuration, the secure privileged software enables
each required base region x, setting the BREN bit in RISAF_REGx_CFGR.

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Note: The number of regions, the region watermark granularity, and the address space size
depend upon the RISAF instance (see Section 7.3).
At any time the secure privileged software can lock the RISAF configuration until the next
reset, by setting the GLOCK bit in RISAF_CR. Subregion registers are the exception to this
rule, as explained in Configuring subregions in RISAF.

Configuring subregions in RISAF

Note: The number of subregions, the subregion watermark granularity, and the primary region
address space size depend on the RISAF resource described in Section 7.3.
Important notes on access control programming and delegation are in Section 7.3.
When an application needs to use the subregion z defined in the base region x, there are
two configuration options in RISAF_REGx_zNESTR:
• The secure privileged software programs the RIF configuration for this subregion.
In this case, DCEN is cleared.
• The secure privileged software delegates the RIF configuration to a single CID, defined
with DCCID. In this case, DCEN must also be set.
Configuring a subregion z consists in the following steps.
1. Define the start and end address of the subregion using RISAF_REGx_zSTARTR and
RISAF_REGx_zENDR registers.
– When programming subregion watermarks, use similar rules as for base regions
(see Configuring base regions in RISAF).
– Subregions must be defined within their base region. The RISAF enforces this rule
if the application does not follow it.
2. Modify WREN and RDEN in RISAF_REGx_zCFGR to modify the access right of
allowed compartment (defined with SCID bits).
3. In the same registers, modify the security and privileged access rights for the allowed
compartment, if needed (see Table 26 for applicable restrictions).
4. After a final check on the above configuration, the subregion must be enabled by
setting SREN bit in RISAF_REGx_zCFGR.
After a secure privileged software has locked all base regions (using GLOCK bit), subregion
owners can lock their configuration using the RLOCK bit in RISAF_REGx_zCFGR.
Note: Only a secure application can change SEC in RISAF_REGx_zCFGR. If the base region is
secure, only a secure application can configure subregion registers.

7.4.6 RISAF runtime modification of region or subregion configuration

The RISAF supports the on-the-fly update of the base region and subregion programming,
except for the start- and end-address boundaries:
• To change RISAF_REGx_STARTR and RISAF_REGx_ENDR, the base region must
be disabled (BREN = 0). In this case, the default primary region access rules apply
immediately (secure, privileged, CID = 1 only).
• To change RISAF_REGx_zSTARTR and RISAF_REGx_zENDR (z = A or B), the
subregion must be disabled (SREN = 0). In this case, the base region access rules
apply immediately.

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If the first solution introduces too many constraints, a workaround is shown in Figure 7.

Figure 7. RISAF region on-the-fly resizing

Base region
Base region #1
1 filtering applies 2 filtering applies 3a 3b
(#15, same as #1)

Base region 1 Base region 1 (disabled) Base region 1 Base region 1

Base region 15 (same rights) Base region 15 (same rights) Base region 15 Base region 15 (disabled)

MSv67870V2

The recommended on-the-fly resizing of base region 1 becomes:

1. Define a spare base region (for example 15), exactly as current region 1.
2. Disable region 1 by clearing [Link] region 15 access control (identical to region 1)
immediately applies. No effect is experienced at system level. The region 1 can be
safely resized.
3. Enable region 1, then disable region 15. The new region 1 access control immediately
applies. Optionally, subregions can be added on top.

7.4.7 Managing illegal accesses

As a RIF component, the RISAF does not use the standard interrupt lines toward NVIC or
GIC concentrators. The IAC captures all RIF interrupt events, called illegal access events.
Refer to Section 8: Illegal access controller (IAC) for more information on the way illegal
accesses are managed.

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7.5 RISAF registers

The registers are accessible through the interface of the RISAF. Only word accesses
(32 bits) are supported.

7.5.1 RISAF configuration register (RISAF_CR)

Address offset: 0x000
Reset value: 0x0000 0000
Secure, privileged, trusted domain CID = 1, write access only. Any read access is allowed,
writes are ignored if GLOCK is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. GLOCK
rs

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 GLOCK: Global lock
This bit locks the. configuration of RISAF registers until next reset. It is cleared by default,
and, once set, cannot be reset until global RISAF reset.
0: RISAF registers are writable.
1: All writes to RISAF registers are ignored, except RISAF_IACR, RISAF_REGx_zCFGR,
RISAF_REGx_zSTARTR, and RISAF_REGx_zENDR (z = A to B).

7.5.2 RISAF illegal access status register (RISAF_IASR)

Address offset: 0x008
Reset value: 0x0000 0000
Secure, privileged, trusted domain CID = 1, read access only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. IAEF CAEF
r r

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 IAEF: Illegal access error flag
This bit is set when an illegal access is detected on the system bus. More details on the error
can be found in RISAF_IAESR and RISAF_IADDR.
This bit is cleared by setting corresponding bit in RISAF_IACR.

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Bit 0 CAEF: Configuration access error flag

This bit is set when an illegal access to any RISAF configuration register is detected. It is
cleared by setting the corresponding bit in RISAF_IACR.

7.5.3 RISAF illegal access clear register (RISAF_IACR)

Address offset: 0x00C
Reset value: 0x0000 0000
Secure, privileged, trusted domain CID = 1, write access only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. IAEF CAEF
w w

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 IAEF: Illegal access error flag
Set this bit to clear IAEF0 in RISAF_IASR, allowing the capture of a new error information
from RIF in RISAF_IAESR and RISAF_IADDR registers.
Note: Clearing this bit does not clear RISAF_IADDR.
Bit 0 CAEF: Configuration access error flag
Set this bit to clear CAEF in RISAF_IASR.

7.5.4 RISAF illegal access error status register (RISAF_IAESR)

Address offset: 0x020
Reset value: 0x0000 0000
Secure, privileged, trusted domain CID = 1, read access only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. IANRW Res. IASEC IAPRIV Res. IACID[2:0]
r r r r r r

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 IANRW: Illegal access read/write
When IAEF = 1 in RISAF_IASR, IANRW captures the access type of the illegal access that
has been detected by RIF gate x.
0: Illegal access was a data read or an instruction fetch
1: Illegal access was a data write
Bit 6 Reserved, must be kept at reset value.

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Bit 5 IASEC: Illegal access security

When IAEF = 1 in RISAF_IASR, IASEC captures the security type of the illegal access that
has been detected by RIF gate x.
0: Illegal access was nonsecure
1: Illegal access was secure
Bit 4 IAPRIV: Illegal access privileged
When IAEF = 1 in RISAF_IASR, IAPRIV captures the privilege state of the master that issued
the illegal access detected by RIF gate x.
0: Illegal access was unprivileged
1: Illegal access was privileged
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 IACID[2:0]: Illegal access compartment ID
When IAEF = 1 in RISAF_IASR, IACID[2:0] captures the compartment ID of the master that
issued the illegal access detected by RIF gate x.

7.5.5 RISAF illegal address register (RISAF_IADDR)

Address offset: 0x024
Reset value: 0x0000 0000
Secure, privileged, trusted domain CID = 1, read access only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IADD[31:16]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IADD[15:0]
r r r r r r r r r r r r r r r r

Bits 31:0 IADD[31:0]: Illegal address

When IAEF = 1 in RISAFB_IASR, IADD[31:0] captures the address of the erroneous access.
Additional information can be found in RISAF_IAESR. Captured address information is the
byte offset from the base of the protected address space.

7.5.6 RISAF region x configuration register (RISAF_REGx_CFGR)

Address offset: 0x040 + 0x40 * (x - 1) (x = 1 to 15)
Reset value: 0x0000 0000
Secure, privileged, trusted domain CID = 1, write access only. Any read access is allowed
on this register. Writes are ignored if GLOCK is set in RISAF_CR.
Refer to Section 7.3 to verify the number of base regions supported by this RISAF instance.

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV PRIV PRIV PRIV PRIV PRIV PRIV PRIV
Res. Res. Res. Res. Res. Res. Res. Res.
C7 C6 C5 C4 C3 C2 C1 C0
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. SEC Res. Res. Res. Res. Res. Res. Res. BREN
rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 PRIVC[7:0]: Privileged access for compartment y (y = 7 to 0)
This bit is taken into account only if BREN = 1.
0: Application running in compartment y can access to region x in privileged and unprivileged
mode.
1: Application running in compartment y can access to region x in privileged mode only.
Bits 15:9 Reserved, must be kept at reset value.
Bit 8 SEC: Secure region
This bit is taken into account only if BREN = 1.
0: Only nonsecure privileged requests can access region x. SEC value in
RISAF_REGx_zCFGR is internally treated as 0-ed by RISAF (only nonsecure requests to
subregions).
1: Only secure privileged requests can access region x, and optional subregions can be
defined as secure or nonsecure.
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 BREN: Base region enable
0: Base region x is disabled. Access control of primary region 0 (secure, privileged, trusted
domain CID = 1) applies to any access between region x start and end addresses.
Associated subregions are also disabled.
1: Base region x is enabled. Access controls defined in region x apply to any access between
region x start and end addresses.
Note: The filtering starts from start address RISAF_REGx_STARTR (included) and ends at
end address RISAF_REGx_ENDR (included).

7.5.7 RISAF region x start-address register (RISAF_REGx_STARTR)

Address offset: 0x044 + 0x40 * (x - 1) (x = 1 to 15)
Reset value: 0x0000 0000
Secure, privileged, trusted domain CID = 1, write access only. Any read access is allowed
on this register. Writes are ignored if GLOCK is set in RISAF_CR, or if BREN is set in
RISAF_REGx_CFGR.
Refer to Section 7.3 to verify the number of base regions supported by this RISAF instance,
and for details on protected address space size and watermark granularity.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BADDSTART[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BADDSTART[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:0 BADDSTART[31:0]: Base region address start

This bitfield defines the byte-address offset (relative to the base address of the protected
address space) of the lowest byte-address in base region x.
Address bits less than the granularity and greater than the protected address space size
cannot be written to, and remain 0.

7.5.8 RISAF region x end-address register (RISAF_REGx_ENDR)

Address offset: 0x048 + 0x40 * (x - 1) (x = 1 to 15)
Reset value: 0x0000 0FFF
The reset value given here applies when the granularity is 4 Kbytes. If the granularity is 2n,
the reset value is 2n - 1.
Secure, privileged, trusted domain CID = 1, write access only. Any read access is allowed
on this register. Writes are ignored if GLOCK is set in RISAF_CR, or if BREN is set in
RISAF_REGx_CFGR.
Refer to Section 7.3 to verify the number of base regions supported by this RISAF instance,
and for details on protected address space size and watermark granularity.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BADDEND[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BADDEND[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 BADDEND[31:0]: Base region address end

This bitfield defines the byte-address offset (relative to the base address of the protected
address space) of the highest byte-address in base region x.
Address bits less than the granularity cannot be modified, and remain 1.
Address bits greater than the protected address space size cannot be written, and remain 0.

7.5.9 RISAF region x CID configuration register

(RISAF_REGx_CIDCFGR)
Address offset: 0x04C + 0x40 * (x - 1) (x = 1 to 15)
Reset value: 0x0000 0000
Secure, privileged, trusted domain CID = 1, write access only. Any read access is allowed
on this register. Writes are ignored if GLOCK is set in RISAF_CR.
Refer to Section 7.3 to verify the number of base regions supported by this RISAF instance.

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WREN WREN WREN WREN WREN WREN WREN WREN
Res. Res. Res. Res. Res. Res. Res. Res.
C7 C6 C5 C4 C3 C2 C1 C0
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDEN RDEN RDEN RDEN RDEN RDEN RDEN RDEN
Res. Res. Res. Res. Res. Res. Res. Res.
C7 C6 C5 C4 C3 C2 C1 C0
rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 WRENC[7:0]: Write enable for compartment y (y = 7 to 0)
This bit is taken into account only if BREN = 1 in RISAF_REGx_CFGR.
0: Application running in compartment y cannot write to region x (write ignored).
1: Application running in compartment y can write to region x. Additional control defined by
SEC and PRIVCy in RISAF_REGx_CFGR, also applies.
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 RDENC[7:0]: Read enable for compartment y (y = 7 to 0)
This bit is taken into account only if BREN = 1 in RISAF_REGx_CFGR.
0: Application running in compartment y cannot read region x (read as 0).
1: Application running in compartment y can read region x. Additional control defined by SEC
and PRIVCy in RISAF_REGx_CFGR, also applies.

7.5.10 RISAF region x subregion A configuration register

(RISAF_REGx_ACFGR)
Address offset: 0x050 + 0x40 * (x - 1) (x = 1 to 15)
Reset value: 0x0000 0000
Unprivileged writes are ignored. Nonsecure writes are ignored if SEC = 1 in
RISAF_REGx_CFGR, or if DCEN = 0 in RISAF_REGx_ANESTR. Any read access is
allowed to this register. Writes are ignored if RLOCK = 1 in this register.
When the delegated configuration is enabled (DCEN = 1 in RISAF_REGx_ANESTR), only
the compartment DCCID defined in RISAF_REGx_ANESTR can write to this register.
When the delegation is disabled (DCEN = 0), only the secure privileged software can
program this register.
Refer to Section 7.3 to verify the number of base regions and subregions supported by this
RISAF instance.
Caution: Check Section 7.3 before programming SRCID[2:0] bitfield.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRCID[ SRCID[ SRCID[
Res. Res. WREN RDEN Res. Res. PRIV SEC Res. Res. Res. RLOCK SREN
2] 1] 0]
rw rw rw rw rw rw rw rs rw

Bits 31:14 Reserved, must be kept at reset value.

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Bit 13 WREN: Write enable

This bit is taken into account only if SREN = 1 in this register.
0: Any writes to subregion A of region x are ignored
1: Subregion A of region x can be written to
Bit 12 RDEN: Read enable
This bit is taken into account only if SREN = 1 in this register.
0: Any read to subregion A of region x returns 0
1: Subregion A of region x can be read
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 PRIV: Privileged subregion
This bit is taken into account only if SREN = 1 in this register.
0: Privileged and unprivileged accesses are granted in subregion A of region x
1: Only privileged accesses are granted in subregion A of region x
Note: When base region x is defined as unprivileged for the SCID compartment (PRIVCy = 0
in RISAF_REGx_CFGR, with SRCID = Cy), unprivileged accesses to subregion A are
always granted.
Bit 8 SEC: Secure subregion
This bit is taken into account only if SREN = 1 in this register. Nonsecure modification to it are
discarded.
0: Only nonsecure requests can access subregion A of region x
1: Only secure requests can access subregion A of region x
Note: When base region x is defined as nonsecure (SEC = 0 in RISAF_REGx_CFGR), only
nonsecure accesses to subregion A are granted.
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 SRCID[2:0]: Subregion CID
When SREN = 1 in this register, SRCID[2:0] defines which compartment has access to
subregion A of RISAF region x.
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 RLOCK: Resource lock
When this bit is set, the subregion resource is locked.
0: RISAF_REGx_ACFGR, RISAF_REGx_ASTARTR, and RISAF_REGx_AENDR are
writable
1: Writes to RISAF_REGx_ACFGR, RISAF_REGx_ASTARTR, and RISAF_REGx_AENDR
are ignored
Note: This bit is set once, cleared only by RISAF reset. It cannot be set if GLOCK = 0 in
RISAF_CR.
Bit 0 SREN: Subregion enable
0: Subregion A is disabled. Access control of base region x applies to any access between
this subregion start and end addresses.
1: Subregion A of region x is enabled. Access control defined in subregion A applies to any
access between subregion A start and end addresses.
Note: The filtering starts from address RISAF_REGx_ASTARTR (included), and ends at
address RISAF_REGx_AENDR (included).

7.5.11 RISAF region x subregion A start-address register

(RISAF_REGx_ASTARTR)
Address offset: 0x054 + 0x40 * (x - 1) (x = 1 to 15)

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Reset value: 0x0000 0000

Unprivileged writes are ignored. Nonsecure writes are ignored if SEC = 1 in
RISAF_REGx_CFGR, or if DCEN = 0 in RISAF_REGx_ANESTR. Any read access is
allowed to this register. Writes are ignored if RLOCK = 1 or SREN = 1 in
RISAF_REGx_ACFGR.
When the delegated configuration is enabled (DCEN = 1 in RISAF_REGx_ANESTR), only
the compartment DCCID defined in RISAF_REGx_ANESTR can write to this register. When
the delegation is disabled (DCEN = 0), only the secure privileged software can program this
register.
Refer to Section 7.3 to verify the number of base regions and subregions supported by this
RISAF instance, and for details on protected address space size and watermark granularity.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SADDSTART[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SADDSTART[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 SADDSTART[31:0]: Subregion address start

This bitfield defines the byte-address offset (relative to the base address of the protected
address space) of the lowest byte-address in subregion A in base region x.
Address bits less than the granularity and greater than the protected address space size
cannot be written, and remain 0.
The effective subregion is the intersection of the subregion and its base region (there is no
point in programming SADDSTART below the associated BADDSTART).

7.5.12 RISAF region x subregion A end-address register

(RISAF_REGx_AENDR)
Address offset: 0x058 + 0x40 * (x - 1) (x = 1 to 15)
Reset value: 0x0000 0FFF
Unprivileged writes are ignored. Nonsecure writes are ignored if SEC = 1 in
RISAF_REGx_CFGR, or if DCEN = 0 in RISAF_REGx_ANESTR. Any read access is
allowed to this register. Writes are ignored if RLOCK = 1 or SREN = 1 in
RISAF_REGx_ACFGR.
When the delegated configuration is enabled (DCEN = 1 in RISAF_REGx_ANESTR), only
the compartment DCCID defined in RISAF_REGx_ANESTR can write to this register. When
the delegation is disabled (DCEN = 0), only the secure privileged software can program this
register.
Refer to Section 7.3 to verify the number of base regions and subregions supported by this
RISAF instance, and for details on protected address space size and watermark granularity.

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RM0486 Resource isolation slave unit for address space protection (full version) (RISAF)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SADDEND[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SADDEND[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 SADDEND[31:0]: Subregion address end

This bitfield defines the byte-address offset (relative to the base address of the protected
address space) of the highest byte-address of subregion A in base region x.
Address bits less than the granularity cannot be modified, and remain 1.
Address bits greater than the protected address space size cannot be written, and remain 0.
The effective subregion is the intersection of the subregion and its base region (there is no
point in programming SADDEND higher than the associated BADDEND).

7.5.13 RISAF region x subregion A nested mode register

(RISAF_REGx_ANESTR)
Address offset: 0x05C + 0x40 * (x - 1) (x = 1 to 15)
Reset value: 0x0000 0000
Secure, privileged, trusted domain CID = 1, write access only. Any read access is allowed
on this register. Writes are ignored if GLOCK is set in RISAF_CR.
Refer to Section 7.3 to verify the number of base regions and subregions supported by this
RISAF instance.
Caution: Check Section 7.3 before setting DCEN bit.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. DCCID[2:0] Res. DCEN Res. Res.
rw rw rw rw

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:4 DCCID[2:0]: Delegated configuration CID
The secure privileged software can use this bitfield to statically define which compartment
can program the RIF configuration of subregion A if DCEN = 1 in this register.
Bit 3 Reserved, must be kept at reset value.
Bit 2 DCEN: Delegated configuration enable
0: RIF configuration for subregion A can be written only by the secure privileged software.
1: RIF configuration for subregion A can be written only by compartment DCCID, defined in
this register. If base region x is defined as secure (SEC = 1), nonsecure write accesses to
this subregion RIF configuration by compartment DCCID are ignored.
Note: RIF configuration of subregion A is defined as RISAF_REGx_ACFGR,
RISAF_REGx_ASTARTR, and RISAF_REGx_AENDR.
Bits 1:0 Reserved, must be kept at reset value.

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7.5.14 RISAF region x subregion B configuration register

(RISAF_REGx_BCFGR)
Address offset: 0x060 + 0x40 * (x - 1) (x = 1 to 15)
Reset value: 0x0000 0000
Unprivileged writes are ignored. Nonsecure writes are ignored if SEC = 1 in
RISAF_REGx_CFGR, or if DCEN = 0 in RISAF_REGx_BNESTR. Any read access is
allowed to this register. Writes are ignored if RLOCK = 1 in this register.
When the delegated configuration is enabled (DCEN = 1 in RISAF_REGx_BNESTR), only
the compartment DCCID defined in RISAF_REGx_BNESTR can write to this register.
When the delegation is disabled (DCEN = 0), only the secure privileged software can
program this register.
Refer to Section 7.3 to verify the number of base regions and subregions supported by this
RISAF instance.
Caution: Check Section 7.3 before programming SRCID[2:0] bitfield.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRCID[ SRCID[ SRCID[
Res. Res. WREN RDEN Res. Res. PRIV SEC Res. Res. Res. RLOCK SREN
2] 1] 0]
rw rw rw rw rw rw rw rs rw

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 WREN: Write enable
This bit is taken into account only if SREN = 1 in this register.
0: Any writes to subregion B of region x are ignored
1: Subregion B of region x can be written to
Bit 12 RDEN: Read enable
This bit is taken into account only if SREN = 1 in this register.
0: Any read to subregion B of region x returns 0
1: Subregion B of region x can be read
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 PRIV: Privileged subregion
This bit is taken into account only if SREN = 1 in this register.
0: Privileged and unprivileged accesses are granted in subregion B of region x
1: Only privileged accesses are granted in subregion B of region x
Note: When base region x is defined as unprivileged for the SCID compartment (PRIVCy = 0
in RISAF_REGx_CFGR, with SRCID = Cy), unprivileged accesses to subregion B are
always granted.

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Bit 8 SEC: Secure subregion

This bit is taken into account only if SREN = 1 in this register. Nonsecure modification to it are
discarded.
0: Only nonsecure requests can access subregion B of region x
1: Only secure requests can access subregion B of region x
Note: When base region x is defined as nonsecure (SEC = 0 in RISAF_REGx_CFGR), only
nonsecure accesses to subregion B are granted.
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 SRCID[2:0]: Subregion CID
When SREN = 1 in this register, SRCID[2:0] defines which compartment has access to
subregion B of RISAF region x.
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 RLOCK: Resource lock
When this bit is set, the subregion resource is locked.
0: RISAF_REGx_BCFGR, RISAF_REGx_BSTARTR, and RISAF_REGx_BENDR are
writable
1: Writes to RISAF_REGx_BCFGR, RISAF_REGx_BSTARTR, and RISAF_REGx_BENDR
are ignored
Note: This bit is set once, cleared only by RISAF reset. It cannot be set if GLOCK = 0 in
RISAF_CR.
Bit 0 SREN: Subregion enable
0: Subregion B of region x is disabled. Access control of base region x applies to any access
between this subregion start and end addresses.
1: Subregion B of region x is enabled. Access control defined in subregion B applies to any
access between subregion B start and end addresses.
Note: The filtering starts from address RISAF_REGx_BSTARTR (included), and ends at
address RISAF_REGx_BENDR (included).

7.5.15 RISAF region x subregion B start-address register

(RISAF_REGx_BSTARTR)
Address offset: 0x064 + 0x40 * (x - 1) (x = 1 to 15)
Reset value: 0x0000 0000
Unprivileged writes are ignored. Nonsecure writes are ignored if SEC = 1 in
RISAF_REGx_CFGR, or if DCEN = 0 in RISAF_REGx_BNESTR. Any read access is
allowed to this register. Writes are ignored if RLOCK = 1 or SREN = 1 in
RISAF_REGx_BCFGR.
When the delegated configuration is enabled (DCEN = 1 in RISAF_REGx_BNESTR), only
the compartment DCCID defined in RISAF_REGx_BNESTR can write to this register. When
the delegation is disabled (DCEN = 0), only the secure privileged software can program this
register.
Refer to Section 7.3 to verify the number of base regions and subregions supported by this
RISAF instance, and for details on protected address space size and watermark granularity.

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Resource isolation slave unit for address space protection (full version) (RISAF) RM0486

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SADDSTART[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SADDSTART[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 SADDSTART[31:0]: Subregion address start

This bitfield defines the byte-address offset (relative to the base address of the protected
address space) of the lowest byte-address in subregion B in base region x.
Address bits less than the granularity and greater than the protected address space size
cannot be written, and remain 0.
The effective subregion is the intersection of the subregion and its base region (there is no
point in programming SADDSTART below the associated BADDSTART).

7.5.16 RISAF region x subregion B end-address register

(RISAF_REGx_BENDR)
Address offset: 0x068 + 0x40 * (x - 1) (x = 1 to 15)
Reset value: 0x0000 0FFF
Unprivileged writes are ignored. Nonsecure writes are ignored if SEC = 1 in
RISAF_REGx_CFGR, or if DCEN = 0 in RISAF_REGx_BNESTR. Any read access is
allowed to this register. Writes are ignored if RLOCK = 1 or SREN = 1 in
RISAF_REGx_BCFGR.
When the delegated configuration is enabled (DCEN = 1 in RISAF_REGx_BNESTR), only
the compartment DCCID defined in RISAF_REGx_BNESTR can write to this register. When
the delegation is disabled (DCEN = 0), only the secure privileged software can program this
register.
Refer to Section 7.3 to verify the number of base regions and subregions supported by this
RISAF instance, and for details on protected address space size and watermark granularity.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SADDEND[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SADDEND[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 SADDEND[31:0]: Subregion address end

This bitfield defines the byte-address offset (relative to the base address of the protected
address space) of the highest byte-address of subregion B in base region x.
Address bits less than the granularity cannot be modified, and remain 1.
Address bits greater than the protected address space size cannot be written, and remain 0.
The effective subregion is the intersection of the subregion and its base region (there is no
point in programming SADDEND higher than the associated BADDEND).

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RM0486 Resource isolation slave unit for address space protection (full version) (RISAF)

7.5.17 RISAF region x subregion B nested mode register

(RISAF_REGx_BNESTR)
Address offset: 0x06C + 0x40 * (x - 1) (x = 1 to 15)
Reset value: 0x0000 0000
Secure, privileged, trusted domain CID = 1, write access only. Any read access is allowed
on this register. Writes are ignored if GLOCK is set in RISAF_CR.
Refer to Section 7.3 to verify the number of base regions and subregions supported by this
RISAF instance.
Caution: Check Section 7.3 before setting DCEN bit.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. DCCID[2:0] Res. DCEN Res. Res.
rw rw rw rw

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:4 DCCID[2:0]: Delegated configuration CID
The secure privileged software can use this bitfield to statically define which compartment
can program the RIF configuration of subregion B if DCEN = 1 in this register.
Bit 3 Reserved, must be kept at reset value.
Bit 2 DCEN: Delegated configuration enable
0: RIF configuration for subregion B can be written only by the secure privileged software.
1: RIF configuration for subregion B can be written only by compartment DCCID, defined in
this register. If base region x is defined as secure (SEC = 1), nonsecure write accesses to
this subregion RIF configuration by compartment DCCID are ignored.
Note: RIF configuration of subregion B is defined as RISAF_REGx_BCFGR,
RISAF_REGx_BSTARTR, and RISAF_REGx_BENDR.
Bits 1:0 Reserved, must be kept at reset value.

7.5.18 RISAF register map

Table 27. RISAF register map and reset values

Register
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

name
9
8
7
6
5
4
3
2
1
0 GLOCK
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

RISAF_CR
0x000

Reset value 0
CAEF
IAEF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

RISAF_IASR
0x008
Reset value 0 0
CAEF
IAEF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

RISAF_IACR
0x00C
Reset value 0 0
0x010-
Reserved Reserved
0x01C

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Resource isolation slave unit for address space protection (full version) (RISAF) RM0486

Table 27. RISAF register map and reset values (continued)

Register
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11
name

9
8
7
6
5
4
3
2
1
0
IANRW

IAPRIV
IACID

IASEC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
RISAF_IAESR
0x020 [2:0]

Reset value 0 0 0 0 0 0
RISAF_IADDR IADD[31:0]
0x024
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x028-
Reserved Reserved
0x03C
0x040 + RISAF_REGx

PRIV7
PRIV6
PRIV5
PRIV4
PRIV3
PRIV2
PRIV1
PRIV0

BREN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
SEC
0x040*(x-1) _CFGR
(x=1 to 15)
Last
address: Reset value 0 0 0 0 0 0 0 0 0 0
0x3C0
0x044 + RISAF_REGx
BADDSTART[31:0]
0x40*(x-1) _STARTR
(x=1 to 15)
Last
address: Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x3C4
0x048 + RISAF_REGx
BADDEND[31:0]
0x40*(x-1) _ENDR
(x=1 to 15)
Last
address: Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FFF
0x3C8
0x04C +
WRENC7
WRENC6
WRENC5
WRENC4
WRENC3
WRENC2
WRENC1
WRENC0

RDENC7
RDENC6
RDENC5
RDENC4
RDENC3
RDENC2
RDENC1
RDENC0
0x40*(x-1) RISAF_REGx
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
(x=1 to 15) _CIDCFGR
Last
address:
0x3CC Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x050 +

RLOCK
RISAF_REGx
WREN

SRCID
RDEN

SREN
PRIV
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.

Res.
Res.
0x40*(x-1)
_ACFGR SEC [2:0]
(x=1 to 15)
Last
address: Reset value 0 0 0 0 0 0 0 0 0
0x3D0
0x054 + RISAF_REGx
SADDSTART[31:0]
0x40*(x-1) _ASTARTR
(x=1 to 15)
Last
address: Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x3D4
0x058 + RISAF_REGx
SADDEND[31:0]
0x40*(x-1) _AENDR
(x=1 to 15)
Last
address: Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x3D8
0x05C + RISAF_REGx DCCID
DCEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.

0x40*(x-1) _ANESTR [2:0]

(x=1 to 15)
Last
address: Reset value 0 0 0 0
0x3DC
0x060 +
RLOCK
WREN

RISAF_ SRCID
RDEN

SREN
PRIV
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.

Res.
Res.
SEC

0x40*(x-1)
(x=1 to 15) REGx_BCFGR [2:0]
Last
address: Reset value 0 0 0 0 0 0 0 0 0
0x3E0
0x064 + RISAF_REGx
SADDSTART[31:0]
0x40*(x-1) _BSTARTR
(x=1 to 15)
Last
address: Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x3E4

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RM0486 Resource isolation slave unit for address space protection (full version) (RISAF)

Table 27. RISAF register map and reset values (continued)

Register
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11
name

9
8
7
6
5
4
3
2
1
0
0x068 + RISAF_REGx
SADDEND[31:0]
0x040*(x-1) _BENDR
(x=1 to 15)
Last
address: Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FFF
0x3E8
0x06C + RISAF_REGx DCCID

DCEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.
0x40*(x-1) _BNESTR [2:0]
(x=1 to 15)
Last
address: Reset value 0 0 0 0
0x3EC

Refer to Section 2.3 for the register boundary addresses.

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277
Illegal access controller (IAC) RM0486

8 Illegal access controller (IAC)

8.1 IAC introduction

The RIF (resource isolation framework) is a comprehensive set of hardware blocks
designed to enforce and manage the isolation of STM32 hardware resources, such as
memory and peripherals.
The RIF uses the IAC (illegal access controller) to centralize the detection of RIF-related
illegal accesses, managed by a secure application.

8.2 IAC main features

• Centralized detection of RIF-related illegal accesses, managed by a secure
application. Supported illegal accesses are: secure, privileged.
• Only accessible by secure privileged CPU

8.3 IAC implementation

The index of the peripherals managed by the IAC in this device is defined in Table 28.
Indexes 0 to 127 are also used in the RIFSC to configure the proper access control using
RISUP blocks.

Table 28. Peripheral indexes in IAC

Peripherals 31 to 0
31
30
29
28
27
26
LPUART1 25
USART10 24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
SPI6/I2S6 5
4
3
SPI3/I2S3 2
SPI2/I2S2 1
SPI1/I2S1 0
FDCAN1

USART6

USART3
USART2
USART1
UART9
UART8
UART7

UART5
UART4

-
TIM5
TIM4
TIM3
TIM2
TIM1

SAI2

SAI1

SPI5
SPI4
I3C2
I3C1
I2C4
I2C3
I2C2
I2C1

Peripherals 63 to 32
63
SYSCONF 62
61
60
59
58
57
OTG1_HS 56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
OTG1_FS
SPDIFRX

SDMMC2
SDMMC1
GB-ETH

GFXTIM
LPTIM5
LPTIM4
LPTIM3
LPTIM2
LPTIM1
MDIOS

TIM18
TIM17
TIM16
TIM15
TIM14
TIM13
TIM12

TIM10
UCPD

TIM11
MDF1
-

ADF1

TIM9
TIM8
TIM7
TIM6

Peripherals 95 to 64
95
94
93
CSI2HOST 92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
VREFBUF
DCMIPP

WWDG
CRYP1

ADC12
XSPIM
XSPI3
XSPI2
XSPI1

MCE4
MCE3
MCE2
MCE1

HASH

IWDG
-

SAES

-
-
-
-
-
-

-
DCMI

RNG
FMC

CRC
PKA

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 - 159 - 127

8.4

8.4.1
RIFSC 158 - 126
RM0486

RISAF23 (BKPSRAM) 157 - 125

RISAF22 (AHB RAM2) 156 - 124
RISAF21 (AHB RAM1) 155 - 123
- 154 - 122
Peripherals 127 to 96

Peripherals 159 to 128

RISAF15 (Cache config) 153 - 121
RISAF14 (FMC) 152 - 120
RISAF13 (XSPI3) 151 - 119
RISAF12 (XSPI2) 150 - 118
RISAF11 (XSPI1) 149 - 117

IAC block diagram

...
- 148 - 116
RISAF9 (VENCRAM) 147 - 115

(memory gate)
peripheral #n
peripheral #1

RIF-protected
RIF-protected

RIFcomponent
RISAF8 (CACHAXI) 146 - 114
RISAF7 (FLEXRAM) 145 - 113
RISAF6 (CPU_MST) 144 - 112

IAC functional description

ILAC events
RISAF5 (NPU_MST1) 143 - 111
Masking and routing RISAF4 (NPU_MST0) 142 - 110

RM0486 Rev 2
RISAF3 (AXISRAM1) 141 - 109

Figure 8 shows the IAC block diagram, in context.

iac_it
IAC ISR/ICR IER
RISAF2 (AXISRAM0) 140 - 108
RISAF1 (TCM) 139 - 107
control IAC 138 NPU 106

Figure 8. IAC block diagram

Interrupt AHB bus PWR_CTRL 137 - 105

iac_hclk
Table 28. Peripheral indexes in IAC (continued)

RCC 136 LTDC_L2 104

BSEC 135 LTDC_L1 103

sec_irq
TAMP 134 LTDC_CMN 102
RTC 133 DMA2D 101
CPU
- 132 GFXMMU 100
Trusted CPU
HPDMA1 131 GPU 99
GPDMA1 130 ICACHE 98
EXTI 129 VENC 97

MSv67853V2
CM55 128 JPEG 96

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8.4.2 IAC internal signals

Table 29 lists the internal signals available at IAC level, not at product level.

Table 29. IAC internal signals

Name Type Description

iac_hclk Digital input AHB bus clock

iac_it Digital output Global interrupt request

8.4.3 IAC reset and clocks

The IAC peripheral has a dedicated clock and reset control in the RCC.
The IAC requires its clock in order to trigger an interrupt request event.

8.4.4 IAC use in RIF

The IAC gathers illegal events generated within the system when an illegal access is
detected. The IAC can then generate a secure interrupt towards the secure CPU, if needed.
By default, all events in the IAC are masked.
The IAC has room for 256 interrupt sources. Each source corresponds to an IAC index
from 0 to 255. The interrupt sources from non-RIF-aware peripherals occupy most of the
first 128 indexes. The interrupt sources from RIF-aware peripherals and RIF firewalls
occupy indexes from 128 onwards. All these sources are defined in Section 8.3.

8.4.5 IAC management by trusted application

For each interrupt source of index <i>, an illegal access sets the IAFi flag in IAC_ISRx. A
secure privileged application can clear this flag using the corresponding bit in IAC_ICRx. An
IAC interrupt is triggered when IAFi is set while IAIEi is set in IAC_IERx.
Indexes between 0 to 127 are assigned to non-RIF-aware peripherals, with a RISUP block
instantiated in front of its configuration port to filter configuration accesses. The
programming of these RISUP blocks (in the RIFSC) uses the same index as the IAC.
Indexes 128 and above are assigned to RIF components and RIF-aware peripherals. These
peripherals can block illegal accesses to their configuration registers (without RISUP).
For RIF-aware peripherals that protect a memory, a secure privileged application can
obtain, in the peripheral, more details about the cause of the illegal access event:
• The illegal access status register (xx_IASR) indicates if it is a configuration access
error (CAEF= 1), or/and a system bus access error (IAEF = 1).
• The illegal access error status register (xx_IAESR) and the illegal address register
(xx_IADDR) give detailed information on the system bus access error.
The IAC interrupt handler must clear IAFi in IAC_ISR before clearing the error flag(s) in the
firewall peripheral xx (using xx_IACR register). Otherwise, an illegal access can occur
between clearing the flags in the firewall and clearing the flag in the IAC, and the application
is unaware of this error.

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8.5 IAC interrupts

The RIF interrupt management in the IAC is summarized in Table 30.
Note: Only secure privileged application can enable, read, and clear illegal access interrupts.
If there is an illegal access to the IAC itself, the status flag corresponding to the IAC index in
Section 8.3 is set.

Table 30. IAC interrupt request

Acronym Interrupt event Event flag in IAC_ISR Enable control bit in IAC_IER Interrupt clear method

IAC Illegal access error IAF IAIE Set IAF bit in IAC_ICR

8.6 IAC registers

All IAC registers are accessed only by words (32 bits).

8.6.1 IAC interrupt enable register x (IAC_IERx)

Address offset: 0x000 + 0x4 * x (x = 0 to 5)
Reset value: 0x0000 0000
Secure privileged, read and write only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IAIE{i + 32 * x}
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IAIE{i + 32 * x}
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 IAIE{i + 32 * x}: Illegal access interrupt enable for peripheral {i + 32 * x} (i = 0 to 31)
Each bit is set to unmask illegal access events from peripheral {i + 32 * x}.
0: Illegal access event from peripheral {i + 32 * x} does not generate interrupt (masked).
1: Illegal access event from peripheral {i + 32 * x} can generate interrupts (unmasked).

8.6.2 IAC interrupt status register x (IAC_ISRx)

Address offset: 0x080 + 0x4 * x (x = 0 to 5)
Reset value: 0x0000 0000
Secure privileged, read only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IAF{i + 32 * x}
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IAF{i + 32 * x}
r r r r r r r r r r r r r r r r

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Bits 31:0 IAF{i + 32 * x}: Illegal access interrupt enable for peripheral {i + 32 * x} (i = 0 to 31)
Each bit is set when an illegal access event occurs in the peripheral {i + 32 * x} (see
Section 8.3 for details). This bit is cleared when the corresponding IAF bit is set in IAC_ICRx.
0: No illegal access event detected for peripheral {i + 32 * x} (since reset or the last time this
bit was cleared).
1: At least one illegal access event has been detected for peripheral {i + 32 * x} (since the last
time this bit was cleared).

8.6.3 IAC interrupt clear register x (IAC_ICRx)

Address offset: 0x100 + 0x4 * x (x = 0 to 5)
Reset value: 0x0000 0000
Secure privileged, write only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IAF{i + 32 * x}
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IAF{i + 32 * x}
w w w w w w w w w w w w w w w w

Bits 31:0 IAF{i + 32 * x}: Illegal access flag clear for peripheral {i + 32 * x} (i = 0 to 31)
Setting each bit clears the status flag of the illegal access event {i + 32 * x} in IAC_ISRx.
0: IAF {i + 32 * x} flag status not affected
1: IAF {i + 32 * x} flag status cleared in IAC_ISRx

8.6.4 IAC ILAC input status register x (IAC_IISRx)

Address offset: 0x36C + 0x4 * x (x = 0 to 5)
Reset value: 0xFFFF FF7F, 0x77FF FFFF, 0x77DF F03B, 0x0000 05FF, 0x7BEF FFEF,
0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ILACIN{i + 32 * x}
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ILACIN{i + 32 * x}
r r r r r r r r r r r r r r r r

Bits 31:0 ILACIN{i + 32 * x}: Illegal access input {i + 32 * x} (i = 0 to 31)

0: ILAC input {i + 32 * x} to IAC not present
1: ILAC input {i + 32 * x} to IAC present

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8.6.5 IAC register map

Table 31. IAC register map and reset values

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name
0x000 +0x4*x IAC_IERx IAIE{i + 32 * x}
(x = 0 to 5)
Last address: Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x014
0x018-0x07C Reserved Reserved
0x080 +0x4*x IAC_ISRx IAF{i + 32 * x}
(x = 0 to 5)
Last address: Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x094
0x098-0x0FC Reserved Reserved
0x100 +0x4*x IAC_ICRx IAF{i + 32 * x}
(x = 0 to 5)
Last address: Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x114
0x118-0x368 Reserved Reserved
0x36C +0x4*x IAC_IISRx ILACIN{i + 32 * x}
(x = 0 to 5)
Last address: Reset value 0xFFFF FF7F, 0x77FF FFFF, 0x77DF F03B, 0x0000 05FF, 0x7BEF FFEF, 0x0000 0000
0x384

Refer to Section 2.3 for the register boundary addresses.

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9 Boot modes

9.1 Boot after system reset

The ROM code is the first one executed after any system reset.
The boot mode is determined by BOOT0 and BOOT1 pins, and one OTP word.

Table 32. Boot modes

BOOT0 BOOT1 Boot source #1

- 1 Development boot
0 0 Flash boot
1 0 Serial boot

BOOT0 is a dedicated pin latched upon reset release.

The BOOT1 is a non dedicated boot pin. The BOOT1 value comes from BOOT1 pin (default
pin), or any other pin defined by BSEC BOOTROM_CONFIG10 - OTP_WORD19[28:21] =
dev_boot_port + dev_boot_pins, see Table 18: OTP fuse description (lower OTP region).

9.1.1 Flash boot

If a flash boot is selected, the firmware is loaded from an external flash memory. The flash
source selection is done through BOOTROM_CONFIG2 - OTP_WORD11[8:5] =
boot_source (4 bits). The possible sources are listed below:
• XSPI serial NOR (in SPI mode, single)
• XSPI HyperFlash™ (8-bit)
• [Link]™ SDMMC1 or [Link]™ SDMMC2 (up to JEDEC v5.1)
• SD-Card SDMMC1 (up to SD standard v6.0)
See Table 18: OTP fuse description (lower OTP region).
If no boot source is programmed in OTP, default source is serial NOR.

9.1.2 Serial boot

If serial boot is selected, the image is loaded from a serial interface. Serial interfaces and
serial instances can be disabled by BOOTROM_CONFIG2 - OTP_WORD11[16:9] =
boot_source_disable (8 bits).
Possible sources are:
• USB boot: USB 2.0 OTG HS
• UART boot: USART1, USART2, and UART4
See Table 18: OTP fuse description (lower OTP region).

9.1.3 Development boot

If BOOT1 is selected, the BootROM code finishes in an endless loop after having reopened
debug in a secure way.

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RM0486 Boot modes

This boot mode is available only when the device is in development.

Secure installation
The ROM code is the root-of-trust of secure firmware installation.

9.2 Boot from a low-power mode

In case of boot from a low-power mode (such as Standby mode with SRAM retention), the
bootROM is not executed, and the CPU starts from the boot address defined in
Section 16.1: SYSCFG registers).

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10 SRAM configuration controller (RAMCFG)

10.1 RAMCFG introduction

The RAMCFG configures the features of the internal SRAMs: AHBSRAM1/2,
AXISRAM1 to 6, BKPSRAM, FLEXRAM, and VENCRAM.

10.2 RAMCFG main features

The internal SRAM supports the following features, configured in the RAMCFG:
• Error code correction (ECC):
– Single-error detection and correction with interrupt generation
– Double-error detection with interrupt generation
– Status with failing address
• SRAM hardware erase: on reset or dedicated event, the RAM content is automatically
erased (written as zero).
• SRAM software erase: the software can trigger an SRAM erase through
RAMCFG registers.

10.3 RAMCFG functional description

10.3.1 Internal SRAM features
The following SRAMs are embedded in the devices, each with specific features:
• AXISRAM1 to 6 are the main SRAMs. AHBSRAM1/2 are preferably for DMA-controlled
peripheral-to-memory data flow.
AXISRAM2 to 6 can be shut down when the application is in Run mode.
• FLEXMEM can be either allocated as Cortex-M55 TCM, or as system RAM
(FLEXRAM).
80 Kbytes of the FLEXMEM are retained in Standby mode, either allocated as
extended ITCM (64 +16-Kbyte ECC), or allocated as FLEXRAM.
• The BKPSRAM content is retained in low-power modes, even when VDD is off
in VBAT mode. On a tamper-event detection, the BKPSRAM content is erased.
• The VENCRAM implements hardware and software erases. It can be used at system
level when the VENC is not used by the application. Writing one to VENCRAM_EN
in SYSCFG_VENCRAMCR allocates the VENCRAM to the system (static allocation).
• The RAMCFG embeds registers that are related to the internal SRAMs ECC, shutdown
control, and software erase.
Note: The baseline I/D-TCM content can be retained in Standby mode (as BKPSRAM and
80 Kbytes of FLEXMEM), but this is not under RAMCFG control.
The CACHEAXI internal RAM can be used at system level when the NPU does not use its
cache (as the VENCRAM). This is controlled directly in the CACHEAXI, and is not under
RAMCFG.

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Table 33 summarizes the features supported by each internal SRAM.

Table 33. Internal SRAM features

AHBSRAM1

AHBSRAM2
AXISRAM1

AXISRAM2

AXISRAM3

AXISRAM4

AXISRAM5

AXISRAM6

VENCRAM

BKPSRAM
FLEXRAM
SRAM feature

Size (Kbytes) 624 1024 Up to 400 448 448 448 448 16 16 128 8
Word size 64 64 64 64 64 64 64 32 32 64 39(1)
Retention in Standby mode - - X(2) - - - - - - - X
Retention in VBAT mode - - - - - - - - - - X
Block on potential tamper,
- - - - - - - - X - X
erase on confirmed tamper
Hardware erase on reset X X - - - - - - X - -
Software erase X X X X X X X X X X X
(3)
ECC - - X - - - - - - - X
1. 32 bits of effective data, and 7 bits of embedded ECC.
2. Only the 80 Kbytes that correspond to the first portion of the I-TCM extension can be retained.
3. The ECC concerns only the FLEXMEM when used as extended TCM. It is under control of the Cortex-M55 TCM interface.

Table 34 details the conditions for the hardware erase.

Table 34. Hardware-erase conditions for internal SRAMs

SRAM Conditional hardware erase Condition

AXISRAM1
No Erase on system reset
AXISRAM2
AHBSRAM2 No Erase on system reset and on confirmed tamper

10.3.2 FLEXRAM control

STM32N6x7xx devices include a Cortex-M55 core that exposes a TCM interface. This TCM
interface is spread in one 39-bit (32 effective data bits + 7 ECC protection bits) I-TCM
(instruction TCM interface), and four parallel 39-bit D-TCMs (data TCM interfaces).
STM32N6x7xx devices also embed 4096 Kbytes of RAM accessible on the AXI
interconnect. The first half of this memory (FLEXRAM, AXISRAM1/2) is in the CPU
frequency domain, and is preferably used for CPU storage. The second half of this memory
(AXISRAM3/4/5/6) is in the NPU frequency domain, and is preferably used for the AI
computing storage.
To let customers tailor the SRAM use to their needs, the FLEXMEM offers the possibility to
allocate part of the CPU side SRAM (FLEXRAM part) as extended TCM, both on I-TCM and
D-TCM interfaces. Table 35 lists the supported allocations.

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SRAM configuration controller (RAMCFG) RM0486

Table 35. FLEXRAM supported configurations

Config Config I-TCM I-TCM flex I-TCM D-TCM D-TCM flex D-TCM AXI-side
I-TCM D-TCM fix (+ ECC) total fix (+ ECC) total FLEXRAM

0 0 1 x 64 0 64 4 × 32 0 128 400
0 1 1 x 64 0 64 4 × 32 4 × 32 (+ 8) 256 240
1 0 1 x 64 1 x 64 (+16) 128 4 × 32 0 128 320
1 1 1 x 64 1 x 64 (+16) 128 4 × 32 4 × 32 (+ 8) 256 160
2 0 1 x 64 1 x 192 (+ 48) 256 4 × 32 0 128 160
2 1 1 x 64 1 x 192 (+ 48) 256 4 × 32 4 × 32 (+ 8) 256 0

The retention regions are detailed in Table 36 and Figure 9, sharing the same color code.

Table 36. FLEXMEM versus retention

FLEXRAM I-TCM D-TCM
Configuration Retention region
base address(1) extension extension

00 0x2400 0000 0 KB RAM region: 0x2400 0000 to 0x2401 3FFF

64 KB
10 0x2401 4000
(+16 KB ECC) 0 KB
I-TCM extension: first 64 KB (+16 KB ECC)
192 KB
20 0x2403 C000
(+48 KB ECC)
01 0x2402 8000 0 KB RAM region: 0x2402 8000 to 0x2403 BFFF
64 KB
11 0x2403 C000 128 KB
(+16 KB ECC)
(+32 KB ECC) I-TCM extension: first 64 KB (+16 KB ECC)
192 KB
21 No RAM
(+48 KB ECC)
1. All addresses considered as their non secure aliases.

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Figure 9. FLEXMEM versus retention

VENCRAM VENCRAM VENCRAM VENCRAM VENCRAM VENCRAM

128 KB 128 KB 128 KB 128 KB 128 KB 128 KB
S 0x3440 0000
NS 0x2440 0000
NPURAM NPURAM NPURAM NPURAM NPURAM NPURAM
256 KB 256 KB 256 KB 256 KB 256 KB 256 KB
S 0x343C 0000
NS 0x243C 0000
AXISRAM6 AXISRAM6 AXISRAM6 AXISRAM6 AXISRAM6 AXISRAM6
448 KB 448 KB 448 KB 448 KB 448 KB 448 KB
S 0x3435 0000
NS 0x2435 0000
AXISRAM5 AXISRAM5 AXISRAM5 AXISRAM5 AXISRAM5 AXISRAM5
448 KB 448 KB 448 KB 448 KB 448 KB 448 KB
S 0x342E 0000
NS 0x242E 0000
AXISRAM4 AXISRAM4 AXISRAM4 AXISRAM4 AXISRAM4 AXISRAM4
448 KB 448 KB 448 KB 448 KB 448 KB 448 KB
S 0x3427 0000
NS 0x2427 0000
AXISRAM3 AXISRAM3 AXISRAM3 AXISRAM3 AXISRAM3 AXISRAM3
448 KB 448 KB 448 KB 448 KB 448 KB 448 KB
S 0x3420 0000
NS 0x2420 0000
AXISRAM2 AXISRAM2 AXISRAM2 AXISRAM2 AXISRAM2 AXISRAM2
1024 KB 1024 KB 1024 KB 1024 KB 1024 KB 1024 KB
S 0x3410 0000
NS 0x2410_0000
AXISRAM1 AXISRAM1 AXISRAM1 AXISRAM1 AXISRAM1 AXISRAM1
624 KB 624 KB 624 KB 624 KB 624 KB 624 KB
S 0x3406 4000
NS 0x2406 4000

RAM RAM RAM

160 KB 160 KB 160 KB
FLEXRAM

0x2403 C000 RAM RAM

320 KB 320 KB RAM
retention
80 KB
0x2402 8000

0x2401 4000
RAM
retention
80 KB
0x2400 0000

0x2004 0000

D-TCM D-TCM D-TCM

128 KB 128 KB 128 KB
DTCM

0x2002_0000

D-TCM D-TCM D-TCM D-TCM D-TCM D-TCM

baseline baseline baseline baseline baseline baseline
128 KB 128 KB 128 KB 128 KB 128 KB 128 KB

0x2000_0000

0x0004_0000

ITCM ITCM
retention retention
128 KB 128 KB
ITCM

0x0002_0000
ITCM ITCM I-TCM ITCM
retention retention retention retention
64 KB 64 KB 64 KB 64 KB
0x0001_0000
ITCM ITCM ITCM ITCM ITCM ITCM
baseline (ret.) baseline (ret.) baseline (ret.) baseline (ret.) baseline (ret.) baseline (ret.)
64 KB 64 KB 64 KB 64 KB 64 KB 64 KB
MS71162V2

0x0000_0000
00 10 20 01 11 21

Note: AXISRAM1 start address is 0x2406 4000 (aliased at 0x3406 4000 in secure boundary),
whatever the FLEXMEM configuration.

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The FLEXMEM configuration depends upon CFGDTCMSZ[3:0] and CFGITCMSZ[3:0] in

SYSCFG_CM55TCMCR. It configuration cannot be changed at runtime, a reboot is needed.

Use in low-power modes

The I-TCM and D-TCM baselines can be kept in retention when the device is in Standby
mode. This allows the CPU to restart from the TCM content.
The first 64 Kbytes (+16 Kbytes for ECC) of extended I-TCM through the FLEXMEM can
also be kept in retention. This allows a maximum of 128 Kbytes of I-TCM in retention.
When only the I-TCM baseline is used for the Cortex-M55, 80 Kbytes of the AXI RAM can
be kept in retention.
The total amount of TCM that can be kept in retention is 320 Kbytes:
• 64 Kbytes of I-TCM baseline (+ 16 Kbytes for ECC)
• 64 Kbytes of I-TCM extended (+ 16 Kbytes for ECC)
• 4 x 32 Kbytes of D-TCM baseline (+ 4 x 8 Kbytes for ECC)

10.3.3 ECC (BKPSRAM)

The ECC is supported by the BKPSRAM. Seven ECC bits are added per 32 bits of SRAM:
this allows a 2-bit error detection, and a 1-bit error correction on memory read access.
As the ECC is calculated and checked for a 32-bit word, byte and half-word write accesses
are managed by the SRAM interface: it first reads the whole word, then writes the word
again with the new byte/half-word value. ECC double errors are also detected during
these byte or half-word AHB write accesses (read/modify/write done by the interface).
The byte or half-word write access latency is two AHB clock cycles.
Caution: In case of a byte or half-word write on the SRAM with ECC, the read/modify/write operation
is done in a buffer. The buffer content is written into the SRAM two AHB clock cycles after
the SRAM AHB is released (when the SRAM is no more accessed).
The ECC is also available on the Cortex-M55 I-TCM and D-TCM.
When the FLEXMEM is used as I/D-TCM, it supports ECC through specific memory
cut/word organization. When the FLEXMEM is used as FLEXRAM, it does not support ECC,
even for the part that can be set in retention

Single and double ECC errors

When a single error is detected, it is automatically corrected, and SEDC (single error
detected and corrected) is set in RAMCFG_BKPSRAMISR.
An interrupt is generated if enabled by SEIE in RAMCFG_BKPSRAMIER. The failing
address is stored in RAMCFG_BKPSRAMESEAR, if ALE is set in RAMCFG_BKPRAMCR.
Caution: Single errors are not reported if SEDC is not cleared in time when a new error happens.
When a double error is detected, DED is set in RAMCFG_BKPSRAMISR. An interrupt is
generated if enabled by DEIE in RAMCFG_BKPSRAMIER. The failing address is stored in
RAMCFG_BKPSRAMEDEAR if ALE is set in RAMCFG_BKPSRAMCR.
Caution: Double errors are not reported if DED is not cleared. Double errors are not corrected, and
must be managed by exception.
The ECC can be activated/deactivated by executing the following software sequence:

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1. Write 0xAE in RAMCFG_BKSRAMECCKEYR.

2. Write 0x75 in RAMCFG_BKSRAMECCKEYR.
3. Write 1 to ECCE in RAMCFG_BKPSRAMCR to activate the ECC (write 0 to this bit to
deactivate the ECC).

Fault injection
The RAMCFG supports a software loop for runtime fault injection in the BKPSRAM when
the ECC is activated:
1. With the ECC enabled, the application writes at a given address.
2. The application disables the ECC writing.
3. The application writes a different data at the same address as previously.
Data are updated but the matching ECC word is not modified.
4. The application enables ECC writing.
5. The application reads at the same address as previously. An interrupt is expected due
to either one error corrected, or several errors detected. The application can check that
the desired address appears in RAMCFG_BKPSRAMSEAR or _BKPSRAMDEAR.

10.4 RAMCFG low-power modes

When the NPU is in Run mode, AXISRAM2 to 6 can be set in power down (shutdown) under
software control.
When RAMs are in shutdown mode, their content is not retained. SRAMSD in
AXISRAMx_CR (x = 2, 3, 4, 5, or 6) controls if the RAM is in shutdown or not. At reset,
RAMs are accessible (SRAMSD cleared to 0).
When a RAM is in shutdown, writing in it has no effect, and reading it returns zero.
When exiting from shutdown state, the memory is not instantly accessible. A safe period
of 40 ns must elapse before the memory is functional.
AXISRAM3 to 6 are interleaved at system level under control of the software through
SYSCFG_NPU_ICNCR. Interleaving must be deactivated before shutting down these
memories, especially if only part of them are set in shutdown.
The following sequence is proposed to enter/exit safely the memory from to/from shutdown:
• To enter shutdown:
a) Disable the RAM clock through the RCC.
b) Shut the RAM down by writing 1 to SRAMSD in RAMCFG_AXISRAMxCR.
• To exit shutdown:
a) Power the RAM up by writing 0 to SRAMSD in RAMCFG_AXISRAMxCR.
b) Read back the value from the RAMCFG (alternatively wait 40 ns).
c) Enable the RAM clock through the RCC.
d) The RAM is now ready for use.
When the NPU is in Stop mode, RAMs are put in low-power mode under control of PWR.
When the NPU is in Standby mode, the BKPSRAM and 80 Kbytes of the FLEXRAM can be
set in retention under software control.

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Table 37 details the effect of low-power modes on RAMCFG.

Table 37. Effect of low-power modes on RAMCFG

Mode Description

Sleep No effect. RAMCFG interrupts cause the device to exit Sleep mode.
Stop The content of RAMCFG registers is kept.
Standby The RAMCFG is powered down.

10.5 RAMCFG interrupts

Two interrupts (maskable by software) are generated internally, and a global interrupt
request is exported to the interrupt controller. Table 38 lists RAMCFG interrupt requests.

Table 38. RAMCFG interrupt requests

Interrupt Event Enable Interrupt clear
Memory Interrupt event
acronym flag(1) control bit method

ECC single error detection and correction SEDC SEIE Write 1 in CSEDC
RAMCFG BKPSRAM
ECC double error detection DED DEIE Write 1 in CDED
1. All these bits are in RAMCFG_BKPSRAMISR.

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RM0486 SRAM configuration controller (RAMCFG)

10.6 RAMCFG registers

The RAMCFG registers can be accessed in word, half-word, and byte format, unless
differently specified.

10.6.1 RAMCFG AXISRAM1 control register (RAMCFG_AXISRAM1CR)

Address offset: 0x000
Reset value: 0x0000 0000
Reset on any system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ER
rw

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SRAMER: SRAM erase
This bit can be set by software only after writing the unlock sequence in ERASEKEY
of RAMCFG_AXISRAM1ERKEYR. Setting this bit starts the SRAM erase. This bit is
automatically cleared by hardware at the end of the erase operation.
0: No erase operation ongoing
1: Erase operation ongoing
Bits 7:0 Reserved, must be kept at reset value.

10.6.2 RAMCFG AXISRAMx interrupt status register

(RAMCFG_AXISRAMxISR)
Address offset: 0x008 + 0x80 * (x - 1), (x = 1 to 6)
Reset value: 0x0000 0000
Reset on any system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
BUSY
r

Bits 31:9 Reserved, must be kept at reset value.

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Bit 8 SRAMBUSY: SRAM busy with erase operation

Depending on the SRAM, the erase operation can be performed due to software request,
system reset if the option is not disabled by software and tamper detection (see Table 33).
0: No erase operation ongoing
1: Erase operation ongoing
Bits 7:0 Reserved, must be kept at reset value.

10.6.3 RAMCFG AXISRAMx erase key register

(RAMCFG_AXISRAMxERKEYR)
Address offset: 0x028 + 0x80 * (x - 1), (x = 1 to 6)
Reset value: 0x0000 0000
Reset on any system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. ERASEKEY[7:0]
w w w w w w w w

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 ERASEKEY[7:0]: Erase write protection key
The following steps are required to unlock the write protection of SRAMER
in RAMCFG_AXISRAMxCR.
a) Write 0xCA into this field.
b) Write 0x53 into this field.
Note: Writing a wrong key reactivates the write protection.

10.6.4 RAMCFG AXISRAMx control register (RAMCFG_AXISRAMxCR)

Address offset: 0x080 + 0x80 * (x - 2), (x = 2 to 6)
Reset value: 0x0000 0000, 0x0010 0000, 0x0010 0000, 0x0010 0000, 0x0010 0000
Reset on any system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRAM
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ER
rw

Bits 31:21 Reserved, must be kept at reset value.

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RM0486 SRAM configuration controller (RAMCFG)

Bit 20 SRAMSD: Shutdown AXISRAMx

0: AXISRAMx memory is powered.
1: AXISRAMx memory is in shutdown, and its content is not retained.
Bits 19:9 Reserved, must be kept at reset value.
Bit 8 SRAMER: SRAM erase
This bit can be set by software only after writing the unlock sequence in ERASEKEY
of RAMCFG_AXISRAMxERKEYR. Setting this bit starts the SRAM erase. This bit is
automatically cleared by hardware at the end of the erase operation.
0: No erase operation ongoing
1: Erase operation ongoing
Bits 7:0 Reserved, must be kept at reset value.

10.6.5 RAMCFG AHBSRAMx control register (RAMCFG_AHBSRAMxCR)

Address offset: 0x300 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000
Reset on any system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ER
rw

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SRAMER: SRAM erase
This bit can be set by software only after writing the unlock sequence in ERASEKEY
of RAMCFG_AHBSRAMxERKEYR. Setting this bit starts the SRAM erase. This bit is
automatically cleared by hardware at the end of the erase operation.
0: No erase operation ongoing
1: Erase operation ongoing
Bits 7:0 Reserved, must be kept at reset value.

10.6.6 RAMCFG AHBSRAMx interrupt status register

(RAMCFG_AHBSRAMxISR)
Address offset: 0x308 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000
Reset on any system reset.

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
BUSY
r

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SRAMBUSY: SRAM busy with erase operation
Depending on the SRAM, the erase operation can be performed due to software request,
system reset if the option is not disabled by software and tamper detection (see Table 33).
0: No erase operation ongoing
1: Erase operation ongoing
Bits 7:0 Reserved, must be kept at reset value.

10.6.7 RAMCFG AHBSRAMx erase key register

(RAMCFG_AHBSRAMxERKEYR)
Address offset: 0x328 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000
Reset on any system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. ERASEKEY[7:0]
w w w w w w w w

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 ERASEKEY[7:0]: Erase write protection key
To unlock the write protection of SRAMER in RAMCFG_AHBSRAMxCR.
a) Write 0xCA into this field.
b) Write 0x53 into this field.
Note: Writing a wrong key reactivates the write protection.

10.6.8 RAMCFG VENCRAM control register (RAMCFG_VENCRAMCR)

Address offset: 0x400
Reset value: 0x0000 0000
Reset on any system reset.

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RM0486 SRAM configuration controller (RAMCFG)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ER
rw

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SRAMER: SRAM erase
This bit can be set by software only after writing the unlock sequence in ERASEKEY
of RAMCFG_VENCRAMERKEYR. Setting this bit starts the SRAM erase. This bit is
automatically cleared by hardware at the end of the erase operation.
0: No erase operation ongoing
1: Erase operation ongoing
Bits 7:0 Reserved, must be kept at reset value.

10.6.9 RAMCFG VENCRAM interrupt status register

(RAMCFG_VENCRAMISR)
Address offset: 0x408
Reset value: 0x0000 0000
Reset on any system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
BUSY
r

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SRAMBUSY: SRAM busy with erase operation
Depending on the SRAM, the erase operation can be performed due to software request,
system reset if the option is not disabled by software and tamper detection (see Table 33).
0: No erase operation ongoing
1: Erase operation ongoing
Bits 7:0 Reserved, must be kept at reset value.

10.6.10 RAMCFG VENCRAM erase key register

(RAMCFG_VENCRAMERKEYR)
Address offset: 0x428
Reset value: 0x0000 0000
Reset on any system reset.

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. ERASEKEY[7:0]
w w w w w w w w

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 ERASEKEY[7:0]: Erase write protection key
To unlock the write protection of SRAMER in RAMCFG_VENCRAMCR.
a) Write 0xCA into this field.
b) Write 0x53 into this field.
Note: Writing a wrong key reactivates the write protection.

10.6.11 RAMCFG BKPSRAM control register (RAMCFG_BKPSRAMCR)

Address offset: 0x480
Reset value: 0x0000 0000
Reset on any system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ALE Res. Res. Res. ECCE
ER
rw rw rw

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SRAMER: SRAM erase
This bit can be set by software only after writing the unlock sequence in ERASEKEY
of RAMCFG_BKPSRAMERKEYR. Setting this bit starts the SRAM erase. This bit is
automatically cleared by hardware at the end of the erase operation.
0: No erase operation ongoing
1: Erase operation ongoing
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 ALE: Address latch enable
0: Failing address not stored in RAMCFG_BKPSRAMESEAR or _BKPSRAMEDEAR
1: Failing address stored in RAMCFG_BKPSRAMESEAR or _BKPSRAMEDEAR
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 ECCE: ECC enable
When set, this bit can be cleared by software only after writing the unlock sequence
in RAMCFG_BKPSRAMECCKEYR.
0: ECC disabled
1: ECC enabled

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10.6.12 RAMCFG BKPSRAM interrupt enable register

(RAMCFG_BKPSRAMIER)
Address offset: 0x484
Reset value: 0x0000 0000
Reset on any system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DEIE SEIE
rw rw

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 DEIE: ECC double error interrupt enable
0: Double error interrupt disabled
1: Double error interrupt enabled
Bit 0 SEIE: ECC single error interrupt enable
0: Single error interrupt disabled
1: Single error interrupt enabled

10.6.13 RAMCFG BKPSRAM interrupt status register

(RAMCFG_BKPSRAMISR)
Address offset: 0x488
Reset value: 0x0000 0000
Reset on any system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DED SEDC
BUSY
r r r

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SRAMBUSY: SRAM busy with erase operation
Depending on the SRAM, the erase operation can be performed due to software request,
system reset if the option is not disabled by software and tamper detection (see Table 33).
0: No erase operation ongoing
1: Erase operation ongoing
Bits 7:2 Reserved, must be kept at reset value.

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Bit 1 DED: ECC double-error detected

0: No double error
1: Double error detected
Bit 0 SEDC: ECC single error detected and corrected
0: No single error detected
1: Single error detected and corrected

10.6.14 RAMCFG BKPSRAM single error address register

(RAMCFG_BKPSRAMESEAR)
Address offset: 0x48C
Reset value: 0x0000 0000
Reset on any system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. ESEA[10:0]
w w w w w w w w w w w

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:0 ESEA[10:0]: ECC single error address
When ALE is set in RAMCFG_BKPSRAMCR, this field is updated with the word address
corresponding to the ECC single error.

10.6.15 RAMCFG BKPSRAM double error address register

(RAMCFG_BKPSRAMEDEAR)
Address offset: 0x490
Reset value: 0x0000 0000
Reset on any system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. EDEA[10:0]
w w w w w w w w w w w

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:0 EDEA[10:0]: ECC double error address
When ALE is set in RAMCFG_BKPSRAMCR, this field is updated with the word address
corresponding to the ECC double error.

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RM0486 SRAM configuration controller (RAMCFG)

10.6.16 RAMCFG BKPSRAM interrupt clear register

(RAMCFG_BKPSRAMICR)
Address offset: 0x494
Reset value: 0x0000 0000
Reset on any system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CDED CSEDC
w w

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 CDED: Clear ECC double-error interrupt
Writing 1 to this flag clears DED in RAMCFG_BKPSRAMISR.
Bit 0 CSEDC: Clear ECC single-error interrupt
Writing 1 to this flag clears SEDC in RAMCFG_BKPSRAMISR.

10.6.17 RAMCFG BKPSRAM ECC key register

(RAMCFG_BKPSRAMECCKEYR)
Address offset: 0x4A4
Reset value: 0x0000 0000
Reset on any system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. ECCKEY[7:0]
w w w w w w w w

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 ECCKEY[7:0]: ECC write protection key
The following steps are required to unlock the write protection of ECCE
in RAMCFG_BKPSRAMCR.
a) Write 0xAE into this field.
b) Write 0x75 into this field.
Note: Writing a wrong key reactivates the write protection.

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10.6.18 RAMCFG BKPSRAM erase key register

(RAMCFG_BKPSRAMERKEYR)
Address offset: 0x4A8
Reset value: 0x0000 0000
Reset on any system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. ERASEKEY[7:0]
w w w w w w w w

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 ERASEKEY[7:0]: Erase write protection key
The following steps are required to unlock the write protection of SRAMER
in RAMCFG_BKPSRAMCR.
a) Write 0xCA into this field.
b) Write 0x53 into this field.
Note: Writing a wrong key reactivates the write protection.

10.6.19 RAMCFG FLEXRAM control register

(RAMCFG_FLEXRAMCR)
Address offset: 0x500
Reset value: 0x0000 0000
Reset on any system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ER
rw

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SRAMER: SRAM erase
This bit can be set by software only after writing the unlock sequence in ERASEKEY
of RAMCFG_FLEXRAMERKEYR. Setting this bit starts the SRAM erase. This bit is
automatically cleared by hardware at the end of the erase operation.
0: No erase operation ongoing
1: Erase operation ongoing
Bits 7:0 Reserved, must be kept at reset value.

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RM0486 SRAM configuration controller (RAMCFG)

10.6.20 RAMCFG FLEXRAM interrupt status register

(RAMCFG_FLEXRAMISR)
Address offset: 0x508
Reset value: 0x0000 0000
Reset on any system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
BUSY
r

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SRAMBUSY: SRAM busy with erase operation
Depending on the SRAM, the erase operation can be performed due to software request,
system reset if the option is not disabled by software and tamper detection (see Table 33).
0: No erase operation ongoing
1: Erase operation ongoing
Bits 7:0 Reserved, must be kept at reset value.

10.6.21 RAMCFG FLEXRAM erase key register

(RAMCFG_FLEXRAMERKEYR)
Address offset: 0x528
Reset value: 0x0000 0000
Reset on any system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. ERASEKEY[7:0]
w w w w w w w w

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 ERASEKEY[7:0]: Erase write protection key
The following steps are required to unlock the write protection of SRAMER in
RAMCFG_FLEXRAMCR.
a) Write 0xCA into this field.
b) Write 0x53 into this field.
Note: Writing a wrong key reactivates the write protection.

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 0x428
0x408
0x404
0x400
0x388
0x004
0x000

0x3A8

0x3FC

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0x328 +
0x308 +
0x300 +
0x080 +
0x028 +
0x008 +

0x3AC -
Offset
10.6.22

(x = 1 to 2)
(x = 1 to 2)
(x = 1 to 2)
(x = 2 to 6)
(x = 1 to 6)
(x = 1 to 6)

0x80 * (x - 1)
0x80 * (x - 1)
0x80 * (x - 1)
0x80 * (x - 2)
0x80 * (x - 1)
0x80 * (x - 1)

Last address:

Last address:

0x40C - 0x424
Reserved
Reserved
Reserved
Reserved

RAMCFG_
RAMCFG_

RAMCFG_
RAMCFG_
RAMCFG_

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

AHBSRAMxCR

AHBSRAMxISR

VENCRAMERKEYR
AXISRAMxERKEYR

AHBSRAMxERKEYR
Register name

RAMCFG_VENCRAMCR
RAMCFG_AXISRAMxCR
RAMCFG_AXISRAM1CR

RAMCFG_VENCRAMISR
RAMCFG_AXISRAMxISR
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
RAMCFG register map

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
SRAM configuration controller (RAMCFG)

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21

0
Res. Res. Res. Res. Res. Res. SRAMSD Res. Res. Res.

RM0486 Rev 2
20
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15

Reserved
Reserved
Reserved
Reserved

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12
Table 39. RAMCFG register map and reset values

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 10
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 9

0
0
0
0
0
0
0

Res. SRAMBUSY SRAMER Res. SRAMBUSY SRAMER SRAMER Res. SRAMBUSY SRAMER 8
Res. Res. Res. Res. Res. Res. Res. 7
Res. Res. Res. Res. Res. Res. Res. 6
Res. Res. Res. Res. Res. Res. Res. 5
Res. Res. Res. Res. Res. Res. Res. 4
Res. Res. Res. Res. Res. Res. Res. 3
Res. Res. Res. Res. Res. Res. Res. 2

ERASEKEY[7:0]
ERASEKEY[7:0]
ERASEKEY[7:0]

Res. Res. Res. Res. Res. Res. Res. 1

0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0

Res. Res. Res. Res. Res. Res. Res.

RM0486

0
 0x528
0x508
0x504
0x500
0x494
0x490
0x488
0x484
0x480

0x4A8
0x4A4
0x48C

0x4AC
RM0486

Offset

0x498 - 0x4A0

0x50C - 0x524
0x42C - 0x47C

Reserved
Reserved
Reserved
Reserved
Reserved

RAMCFG_
RAMCFG_

RAMCFG_
RAMCFG_
RAMCFG_

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

BKPSRAMESEAR

BKPSRAMEDEAR

FLEXRAMERKEYR
Register name

BKPSRAMERKEYR
BKPSRAMECCKEYR

RAMCFG_FLEXRAMCR
RAMCFG_BKPSRAMCR

RAMCFG_FLEXRAMISR
RAMCFG_BKPSRAMISR
RAMCFG_BKPSRAMIER

RAMCFG_BKPSRAMICR
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

RM0486 Rev 2
20
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 16

Refer to Section 2.3 for the register boundary addresses.

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15

Reserved
Reserved
Reserved
Reserved
Reserved

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11
Res. Res. Res. Res. Res. Res. Res. Res. Res. 10
Res. Res. Res. Res. Res. Res. Res. Res. Res. 9
Table 39. RAMCFG register map and reset values (continued)

0
0
0
0

Res. SRAMBUSY SRAMER Res. Res. Res. SRAMBUSY Res. SRAMER 8

Res. Res. Res. Res. Res. Res. 7
Res. Res. Res. Res. Res. Res. 6
Res. Res. Res. Res. Res. Res. 5
Res. Res. Res. Res. Res. Res. 4
ESEA[10:0]

EDEA[10:0]

Res. Res. Res. Res. Res. Res. 3

Res. Res. Res. Res. Res. Res. 2
ECCKEY[7:0]

ERASEKEY[7:0]
ERASEKEY[7:0]

Res. Res. CDED DED DEIE Res. 1

0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0

0 0
0 0
0 0
0

Res. Res. CSEDC SEDC SEIE ECCE

SRAM configuration controller (RAMCFG)

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11 Texture cache (ICACHE)

11.1 ICACHE introduction

The texture cache (ICACHE) is introduced on the AXI read-only texture port of the GPU to
improve performance when reading texture data from internal and external memories.
The texture cache is an assembly of ICACHE (a peripheral with AHB ports) and an
AXI-to-AHB bus bridge plugged on ICACHE AHB slave port, providing an AXI interface on
the texture cache slave port.
The following sections only describe the AHB ICACHE peripheral itself.
Some specific features like hit-under-miss, and critical-word-first refill policy, allow close to
zero-wait-state performance in most use cases.

11.2 ICACHE main features

The main features of ICACHE are listed below:
• Bus interface
– One 64-bit AHB slave port, the read port (input from GPU texture read interface)
– One 64-bit AHB master port: master1 port (output to texture bus of main AXI/AHB
bus matrix)
– One 32-bit AHB slave port for control (input from AHB peripherals interconnect, for
ICACHE registers access)
• Cache access
– 0 wait-state on hits
– Hit-under-miss capability: ability to serve processor requests (access to cached
data) during an ongoing line refill due to a previous cache miss
– Optimal cache line refill thanks to WRAPw bursts of the size of the cache line
(32-bit word size, w, aligned on cache line size)
– n-way set-associative default configuration with possibility to configure as 1-way,
means direct mapped cache, for applications needing very-low-power
consumption profile
• Replacement and refill
– pLRU-t replacement policy (pseudo-least-recently-used, based on binary tree),
algorithm with best complexity/performance balance
– Critical-word-first refill policy, minimizing processor stalls
• Performance counters
The ICACHE implements two performance counters:
– Hit monitor counter (32-bit)
– Miss monitor counter (16-bit)
• Error management
– Possibility to detect an unexpected cacheable write access, to flag an error and
optionally to raise an interrupt
• Maintenance operation
– Cache invalidate: full cache invalidation, fast command, noninterruptible

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11.3 ICACHE implementation

Table 40. ICACHE features
Feature ICACHE

Number of ways 4
Cache size 32 Kbytes
Cache line width 32 bytes
Number of regions to remap 0
Data size of AHB slave interface 64 bits
Data size of AHB fast master1 interface 64 bits
Data size of AHB slow master2 interface 0

11.4 ICACHE functional description

The purpose of the texture cache is to cache GPU read accesses to texture data. As such,
the ICACHE only manages cacheable read transactions and does not manage cacheable
write transactions.
The noncacheable transactions (both read and write ones) bypass the ICACHE.
For the error management purpose, in case a write cacheable transaction is presented
(this only happens in case of bad software programming), the ICACHE sets an error flag
and, if enabled, raises an interrupt to the processor.

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11.4.1 ICACHE block diagram

Figure 10. ICACHE block diagram

Configuration

AHB
slave port

Configuration interface
Region 0 cfg Region 2 cfg Hit monitor Control

Region 1 cfg Region 3 cfg Miss monitor Status

GPU

Cache control logic

Master port interface

Read port interface
Texture read interface

Read Master1
AXI-to-AHB bridge

slave port

Main AHB
Cache port
FSM AHB
AHB

pLRU-t

Cache memory port

icache_it

Cache Cache
TAG data
memories memories

n ways n ways
ICACHE
MSv69745V2

11.4.2 ICACHE reset and clocks

The ICACHE is clocked on the texture AHB bus clock.
When the ICACHE reset signal is released, a cache invalidate procedure is automatically
launched, making the ICACHE busy (ICACHE_SR = 0x0000 0001).
When this procedure is finished:
• the ICACHE is invalidated: “cold cache”, with all cache line valid bits = 0 (ICACHE must
be filled up)
• ICACHE_SR = 0x0000 0002 (reflecting the cache is no longer busy)
• the ICACHE is disabled: the EN bit in ICACHE_CR holds its reset state (=0).
Note: When disabled, the ICACHE is bypassed: slave input requests are forwarded to the master
port.

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11.4.3 ICACHE TAG memory

The ICACHE TAG memory contains:
• address tags that indicate which data are contained in the cache data memories
• validity bits
There is one valid bit per cache line (per way).
The valid bit is set when a cache line is refilled (after a miss).
Valid bits are reset in any of the below cases:
• after the ICACHE reset is released
• when the cache is disabled, by setting EN = 0 in ICACHE_CR (by software)
• when executing an ICACHE invalidate command, by setting CACHEINV = 1
in ICACHE_CR (by software)
When a cacheable transaction is received at the execution input port, its AHB address
(HADDR_in) is split into the following fields (see Table 41 for B and W definitions):
• HADDR_in[B-1:0]: address byte offset, indicates which byte to select inside
a cache line.
• HADDR_in[B+W-1:B]: address way index, indicates which cache line to select
inside each way.
• HADDR_in[31:B+W]: tag address, to be compared to the TAG memory address
to check if the requested data is already available (meaning valid) inside the ICACHE.
The following table gives a summary of the ICACHE main parameters for TAG memory
dimensioning. Figure 11 shows the functional view of TAG and data memories, for an n-way
set associative ICACHE.

Table 41. TAG memory dimensioning parameters

for n-way set associative operating mode (default)
Parameter Value Example

Cache size S Kbytes = s bytes (s = 1024 x S) 8 Kbytes = 8192 bytes

Cache number of ways n 2
Cache line size L-byte = l-bit (l = 8 x L) 16-byte = 128-bit
Number of cache lines (per way) LpW = s / (n x L) lines / way 256 lines / way
Address byte offset size B = log2(L) bit 4-bit
Address way index size W = log2(LpW) bit 8-bit
TAG address size T = (32 - W - B) bit 20-bit

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Figure 11. ICACHE TAG and data memories functional view

T-bit W-bit B-bit

AHB_address
(HADDR_in) TAG Index Offset

way selection
pLRU-t (for replacement)

Vn-1 TAG_Way(n-1) Data_Way(n-1)

V0 TAG_Way0 Data_Way0

LpW lines / way

LpW lines / way

TAG memory Data memory

n ways n ways
T-bit l-bit

==
== Cache hit/miss, in Way(n-1)
Cache hit/miss, in Way0

MSv48192V2

11.4.4 Direct-mapped ICACHE (1-way cache)

The default configuration (at reset) is an n-way set associative cache (WAYSEL = 1
in ICACHE_CR), but the user can configure the ICACHE as direct mapped by writing
WAYSEL = 0 (only possible when the cache is disabled, EN = 0 in ICACHE_CR).
The following table gives a summary of ICACHE main parameters for TAG memory when
the direct-mapped cache operating mode is selected.

Table 42. TAG memory dimensioning parameters for direct-mapped cache mode
Parameter Value Example

Cache size S Kbytes = s bytes (s = 1024 x S) 8 Kbytes = 8192 bytes

Cache number of ways 1 1
Cache line size L-byte = l-bit (l = 8 x L) 16-byte = 128-bit
Number of cache lines LpW = s / L lines 512 lines
Address byte offset size B = log2(L) bit 4-bit
Address way index size W = log2(LpW) bit 9-bit
TAG address size T = (32 - W - B) bit 19-bit

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All cache operations (such as read, refill, invalidation) remain the same in the direct-mapped
configuration. The only difference is the absence of a replacement algorithm in case of line
eviction (as explained in Section 11.4.7): only one way (the unique one) is possible for any
data refill.

11.4.5 ICACHE enable

To activate the ICACHE, the EN bit must be set to 1 in ICACHE_CR.
When the ICACHE is disabled, it is bypassed and all transactions are copied from the slave
port to the master port in the same clock cycle.
It is recommended to initialize or modify the main memory content (region to be later
cached) with the ICACHE disabled, and to enable the ICACHE only when this region
remains unchanged (an enabled ICACHE detects cacheable write transactions as errors).
To ensure performance determinism, it is recommended to wait for the end of a potential
cache invalidate procedure before enabling the ICACHE. This procedure occurs when the
hardware reset signal is released, when CACHEINV is set, or when EN is cleared in
ICACHE_CR. During the procedure, BUSYF is set in ICACHE_SR, and once finished,
BUSYF is cleared and BSYENDF is set in the same register (raising the ICACHE interrupt if
enabled on such a busy end condition).
The software must test BUSYF and/or BSYENDF values before enabling the ICACHE.
Else, if the ICACHE is enabled before the end of an invalidate procedure, any cache access
(while BUSYF = 1) is treated as noncacheable, and its performance depends on the main
memory access time.
The ICACHE is by default disabled at boot.

11.4.6 Cacheable and noncacheable traffic

The ICACHE is placed on the GPU texture bus, and thus caches all internal and external
memory regions (ranging from address 0x0000 0000 to 0x3FFF FFFF, respectively
0x6000 0000 to 0x9FFF FFFF, of the memory map).
An incoming memory request to the ICACHE is defined as cacheable according to its AHB
transaction memory lookup attribute, as shown in Table 43. This AHB attribute depends on
the GPU setting for the addressed region.

Table 43. ICACHE cacheability for AHB transaction

AHB lookup attribute Cacheability

1 Cacheable
0 Noncacheable

In the case of a noncacheable access (either a noncacheable read or a noncacheable

write), the ICACHE is bypassed, meaning that the AHB transaction is propagated
unchanged to the master output port.
The bypass does not increase the latency of the access to the targeted memory.
In the case of a cacheable access, the ICACHE behaves as explained in Section 11.4.7.

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11.4.7 Cacheable accesses

When the ICACHE receives a cacheable transaction from the GPU, the ICACHE checks if
the address requested is present in its TAG memory, and if the corresponding cache line is
valid.
There are then three alternatives:
• The address is present inside the TAG memory, the cache line is valid: cache hit, the
data is read from the cache and provided to the processor in the same cycle.
• The address is not present in the TAG memory: cache miss, the data is read from
the main memory and provided to the processor, and a cache line refill is performed.
The critical-word-first policy ensures minimum wait cycles for the processor, since read
data can be provided while the cache still performs a cache line refill (associated
latency is the latency of fetching one word from the main memory).
The burst generated on the ICACHE master bus is WRAPw (w being the cache line
width, in words).
The AHB transaction attributes are also propagated to the main AHB bus matrix on the
master port.
• The address is not present in TAG memory, but belongs to the refill burst from the main
memory currently ongoing: cache hit (hit-under-miss feature).
This happens during cache-line refill. The ICACHE can provide the requested data as
soon as the data is available at its master interface, thus avoiding a miss (fetching data
from the main memory).
In the case of cache refill (due to cache miss), the ICACHE selects which cache line is
written with the refill data:
• In direct map (1-way) mode, only one line can be used to store the refill data: the line
pointed by the index of the input address.
• In n-way set associative mode, one line among n can be used (the line pointed by the
address index, in each of the n ways). The way selection is based on a pLRU-t
replacement algorithm that points, for each index, on the way candidate for the next
refill.
If ever the cache line where the refill data must be written is already valid, the targeted
cache line must be invalidated first. This is true whatever the direct map or n-way set
associative cache mode.

11.4.8 ICACHE maintenance

The software can invalidate the whole content of the ICACHE by programming CACHEINV
in the ICACHE_CR register.
When CACHEINV = 1, the ICACHE control logic sets the BUSYF flag in ICACHE_SR and
launches the invalidate cache operation, resetting each TAG valid bit to 0 (one valid bit per
cache line). CACHEINV is automatically cleared.
Once the invalidate operation is finished (all valid bits reset to 0), the ICACHE automatically
clears BUSYF, and sets BSYENDF in the ICACHE_SR register.
If enabled on this flag condition (BSYENDIE = 1 in ICACHE_IER), the ICACHE interrupt
is raised. Then, the (empty) cache is available again.

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11.4.9 ICACHE performance monitoring

The ICACHE provides the following monitors for performance analysis:
• The 32-bit hit monitor counts the cacheable AHB-transactions on the slave cache port
that hits the ICACHE content.
It also takes into account all accesses whose address is present in the TAG memory
or in the refill buffer (due to a previous miss, and whose data is coming, or is soon to
come, from the cache master port) (see Section 11.4.7).
• The 16-bit miss monitor counts the cacheable AHB-transactions on the slave cache
port that misses the ICACHE content.
It also takes into account all accesses whose address is not present neither in
the TAG memory nor in the refill buffer.
Upon reaching their maximum values, these monitors do not wrap over.
Hit and miss monitors can be enabled and reset by software allowing the analysis of specific
pieces of code.
The software can perform the following tasks:
• Enable/stop the hit monitor through HITMEN in ICACHE_CR.
• Reset the hit monitor by setting HITMRST in ICACHE_CR.
• Enable/stop the miss monitor through MISSMEN in ICACHE_CR.
• Reset the miss monitor by setting MISSMRST in ICACHE_CR.
To reduce power consumption, these monitors are disabled (stopped) by default.

11.4.10 ICACHE boot

The ICACHE is disabled (EN = 0 in ICACHE_CR) at boot.
Once the boot is finished, the ICACHE can be enabled (software setting EN = 1
in CACHE_CR).

11.5 ICACHE low-power modes

At device level, using the ICACHE reduces the power consumption by reading textures from
the internal ICACHE most of the time, rather than from the bigger and then more power
consuming main memories. This reduction is even higher if the cached main memories are
external.
Applications with lower performance profile (in terms of hit ratio) and stringent power
consumption constraints may benefit from the lower power consumption of an ICACHE
configured as direct mapped. This single-way cache configuration is obtained by
programming WAYSEL = 0 in ICACHE_CR (see Figure 11). The power consumption is
reduced by accessing, for each request, only the necessary cut of TAG and data memories.
The cache effect still improves memory access performance, even if for most texture
accesses, it is less efficient than with an n-way set associative cache mode.

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11.6 ICACHE error management and interrupts

If an unsupported cacheable write request is detected (functional error), the ICACHE
generates an error by setting the ERRF flag in ICACHE_SR. An interrupt is generated if the
corresponding interrupt enable bit is set (ERRIE = 1 in ICACHE_IER).
The other possible interrupt generation is at the end of a cache invalidation operation.
When the cache-busy state is finished, the ICACHE sets the BSYENDF flag in
ICACHE_SR. An interrupt is generated if the corresponding interrupt enable bit is set
(BSYENDIE = 1 in ICACHE_IER).
All ICACHE interrupt sources raise the same and unique interrupt signal, icache_it, and then
use the same interrupt vector.

Table 44. ICACHE interrupts

Interrupt vector Interrupt event Event flag Enable control bit Interrupt clear method

ERRF ERRIE Set CERRF to 1

Functional error
in ICACHE_SR in ICACHE_IER in ICACHE_FCR
ICACHE
End of busy state BSYENDF BSYENDIE Set CBSYENDF to 1
(invalidate finished) in ICACHE_SR in ICACHE_IER in ICACHE_FCR

The ICACHE also propagates all AHB bus errors (such as address decoding issues) from
the master1 port back to the slave read port.

11.7 ICACHE registers

11.7.1 ICACHE control register (ICACHE_CR)

Address offset: 0x000
Reset value: 0x0000 0004

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MISSM HITM MISSM HITM
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RST RST EN EN
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAY CACHE
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EN
SEL INV
rw w rw

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 MISSMRST: miss monitor reset
0: release the cache miss monitor reset (needed to enable the counting)
1: reset cache miss monitor
Bit 18 HITMRST: hit monitor reset
0: release the cache miss monitor reset (needed to enable the counting)
1: reset cache hit monitor

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Bit 17 MISSMEN: miss monitor enable

0: cache miss monitor switched off. Stopping the monitor does not reset it.
1: cache miss monitor enabled
Bit 16 HITMEN: hit monitor enable
0: cache hit monitor switched off. Stopping the monitor does not reset it.
1: cache hit monitor enabled
Bits 15:3 Reserved, must be kept at reset value.
Bit 2 WAYSEL: cache associativity mode selection
This bit allows user to choose ICACHE set-associativity. It can be written by software only
when cache is disabled (EN = 0).
0: direct mapped cache (1-way cache)
1: n-way set associative cache (reset value)
Bit 1 CACHEINV: cache invalidation
Set by software and cleared by hardware when the BUSYF flag is set (during cache
maintenance operation). Writing 0 has no effect.
0: no effect
1: invalidate entire cache (all cache lines valid bit = 0)
Bit 0 EN: enable
0: cache disabled
1: cache enabled

11.7.2 ICACHE status register (ICACHE_SR)

Address offset: 0x004
Reset value: 0x0000 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSYEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ERRF BUSYF
DF
r r r

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 ERRF: cache error flag
0: no error
1: an error occurred during the operation (cacheable write)
Bit 1 BSYENDF: busy end flag
0: cache busy
1: full invalidate CACHEINV operation finished
Bit 0 BUSYF: busy flag
0: cache not busy on a CACHEINV operation
1: cache executing a full invalidate CACHEINV operation

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11.7.3 ICACHE interrupt enable register (ICACHE_IER)

Address offset: 0x008
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSYEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ERRIE Res.
DIE
rw rw

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 ERRIE: interrupt enable on cache error
Set by software to enable an interrupt generation in case of cache functional error (cacheable
write access)
0: interrupt disabled on error
1: interrupt enabled on error
Bit 1 BSYENDIE: interrupt enable on busy end
Set by software to enable an interrupt generation at the end of a cache invalidate operation.
0: interrupt disabled on busy end
1: interrupt enabled on busy end
Bit 0 Reserved, must be kept at reset value.

11.7.4 ICACHE flag clear register (ICACHE_FCR)

Address offset: 0x00C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CBSY
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CERRF Res.
ENDF
w w

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 CERRF: clear cache error flag
Set by software.
0: no effect
1: clears ERRF flag in ICACHE_SR
Bit 1 CBSYENDF: clear busy end flag
Set by software.
0: no effect
1: clears BSYENDF flag in ICACHE_SR.

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Bit 0 Reserved, must be kept at reset value.

11.7.5 ICACHE hit monitor register (ICACHE_HMONR)

Address offset: 0x010
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HITMON[31:16]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HITMON[15:0]
r r r r r r r r r r r r r r r r

Bits 31:0 HITMON[31:0]: cache hit monitor counter

11.7.6 ICACHE miss monitor register (ICACHE_MMONR)

Address offset: 0x014
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MISSMON[15:0]
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 MISSMON[15:0]: cache miss monitor counter

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 0x014
0x010
0x008
0x004
0x000

0x00C
Offset
11.7.7

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Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

ICACHE_SR
ICACHE_CR

ICACHE_IER

ICACHE_FCR
Register name

ICACHE_HMONR

ICACHE_MMONR
0
Res. Res. Res. Res. Res. 31
Texture cache (ICACHE)

0
Res. Res. Res. Res. Res. 30

0
Res. Res. Res. Res. Res. 29

0
Res. Res. Res. Res. Res. 28

0
Res. Res. Res. Res. Res. 27

0
Res. Res. Res. Res. Res. 26

0
Res. Res. Res. Res. Res. 25
ICACHE register map

0
Res. Res. Res. Res. Res. 24

0
Res. Res. Res. Res. Res. 23

0
Res. Res. Res. Res. Res. 22

0
Res. Res. Res. Res. Res. 21

0
Res. Res. Res. Res. Res. 20

0
0

Res. Res. Res. Res. MISSMRST 19

0
0

Res. Res. Res. Res. HITMRST 18

RM0486 Rev 2
0
0

Res. Res. Res. Res. MISSMEN 17

0
0

Res. Res. Res. Res. HITMEN 16

0
Res. Res. Res. Res. 15

0
HITMON[31:0] Res. Res. Res. Res. 14
0

0
0 Res. Res. Res. Res. 13

0
Res. Res. Res. Res. 12
0

0 Res. Res. Res. Res. 11

Table 45. ICACHE register map and reset values

0
Res. Res. Res. Res. 10
0

Res. Res. Res. Res. 9

0

Res. Res. Res. Res. 8

0

Res. Res. Res. Res. 7

0

Res. Res. Res. Res. 6

MISSMON[15:0]
0

Res. Res. Res. Res. 5

Refer to Section 2.3: Memory organization for the register boundary addresses.
0

Res. Res. Res. Res. 4

0

Res. Res. Res. Res. 3

0

0
0
0
0
1

CERRF ERRIE ERRF WAYSEL 2

0

0
0
0
0
0

CBSYENDF BSYENDIE BSYENDF CACHEINV 1

0

0
1
0

Res. Res. BUSYF EN 0

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RM0486 AXI cache (CACHEAXI)

12 AXI cache (CACHEAXI)

12.1 CACHEAXI introduction

The AXI cache (CACHEAXI) is introduced on the AXI interconnect driven by the
NeuralNetwork peripheral (NPU), to improve the performance of data traffic, by caching the
NPU data accessed in the external memories.
When configured as an SRAM, the CACHEAXI can be accessed by the NPU, and also by
the Cortex-M55 processor or by any AXI master peripheral.

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12.2 CACHEAXI main features

The main features of the CACHEAXI are described below:
• Bus interface
– 64-bit AXI slave port (from AXI interconnect, receiving master requests), with
independent read and write channels (read address and data channels; write
address, data and response channels)
– 64-bit AXI master port (to AXI interconnect, accessing main memories), with
independent read and write channels (read address and data channels; write
address, data, and response channels)
– 32-bit AHB slave port for control (input from AHB peripherals interconnect, for
CACHEAXI registers access)
• The CACHEAXI can be configured to behave as an SRAM:
– Reuse all data SRAM banks (so same size as in cache mode)
– Dedicated 64-bit AXI slave SRAM port, to access the CACHEAXI in SRAM mode,
with independent read and write channels (read address and data channels; write
address, data, and response channels)
– Pipelined AXI accesses with a deep acceptance capability of up to six requests on
the read AXI channel and up to five requests on the write AXI channel
• Cache access
– One read or write access per cycle (priority to write access in case of
simultaneous read and write requests)
– Pipelined AXI accesses with a deep acceptance capability of up to 7 requests on
both read and write AXI channels
– Throughput: 1 read or write hit access served per AXI clock cycle
– N-ways set-associative cache
– Supports both write-back and write-through policies (selectable with AXI
transaction WT/WB attribute)
– Supports both allocate and nonallocate policies (selectable with AXI transaction
allocate attribute):
- Read can allocate or not
- Write-back always allocate
- Write-through always nonallocate (write-around)
– Supports byte (8-bit), half-word (16-bit), word (32-bit), or double-word (64-bit) read
or write transfer beat sizes
• Replacement and refill
– pLRU-t replacement policy (pseudo-least-recently-used, based on binary tree),
algorithm with best complexity/performance balance
– Allocation size: on cache miss, refill request size set as cache line size
– Prefetch hint forwarded to master port to inform downstream logic/memory to
prefetch data
– Two eviction buffers, for missing requests with cache line refill (allocate) not to be
blocked by potential cache line eviction operation
• System compartments support:
– Cache lines tagged by a 3-bit compartment identifier that reflects compartment
attribute of the input request on slave port, and that is used on eviction or clean

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operation to set compartment attribute at the output master port

• TrustZone security support
• Maintenance operations
– Cache invalidate: full cache invalidation (fast command, noninterruptible)
– a Cache clean range: cleans cache lines whose address belongs to programmed
range (background task, interruptible)
– Cache clean and invalidate range: cleans and invalidates cache lines whose
address belongs to a programmed range (background task, interruptible)
• Performance counters
– 2 hit monitor counters (32-bit): number of read hits, number of write hits
– 2 miss monitor counters (32-bit): number of read misses, number of write misses
– 2 allocation monitor counters (32-bit): number of read-allocate misses, number of
write-allocate misses
– Write-through monitor counter: number of write-through transactions
– Eviction monitor counter: number of dirty cache line evictions (on read-allocate
misses or on write-allocate misses).
• Error management
– Propagates the AXI bus error on the AXI master cache port back to the
corresponding AXI slave cache port (on noncacheable request, or on refill of
cacheable request with allocation that misses).
– Detects error for master port request initiated by the CACHEAXI itself (a dirty
cache line written back into the main memory, because of an eviction or a clean
operation), flags this error, and optionally raises an interrupt

12.3 CACHEAXI implementation

In STM32N6xx, the CACHEAXI1 is a read/write cache placed on the AXI interconnect
driven by two master ports of the NeuralNetwork peripheral (NPU).
The CACHEAXI1 caches the external memory regions accessed through Octo-SPI,
Hexa-SPI, or FMC interfaces.
By placing an interconnect demultiplexing node in front of its slave cache port, the
CACHEAXI1 only receives NPU memory requests that address the external memories
(address in range 0x6000 0000:0xDFFF FFFF), and that are cacheable. Noncacheable
memory requests are routed away from the slave cache port and address directly the
external memories.

Table 46. CACHEAXI features

Features CACHEAXI1

RW cache 1 (read-write)
SRAM port 1 (support SRAM port)
Cache size 256 Kbytes
Number of ways 8
Cache line width 64 bytes

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Table 46. CACHEAXI features (continued)

Features CACHEAXI1

Data size of AXI Slave and Master interfaces 64 bits

No Privilege 0 (Privilege bit in TAG)
No CID 0 (CID bits in TAG)

12.4 CACHEAXI functional description

The purpose of the CACHEAXI is to cache external memories data, when accessed by a
master peripheral through an AXI interconnect.
By default (at reset), EN = 0 in CACHEAXI_CR1, and the CACHEAXI behaves as an
SRAM.
When its hardware configuration is read-write cache, the CACHEAXI manages both read
and write transactions (received on its AXI read slave port, AXI write slave port,
respectively).
When configured (by software) to behave as an SRAM, the CACHEAXI manages memory
request received on its slave SRAM port (CACHEAXI internal data memories are mapped
as a dedicated SRAM region in the system global memory map). Both read and write
transactions are supported in SRAM mode.

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12.4.1 CACHEAXI block diagram

Figure 12. CACHEAXI block diagram

Configuration

AHB
slave port

Configuration interface
Rd/Wr Hit Monitors
Control CMD range start @
cacheaxi_it Rd/Wr Miss Write-Through
Status CMD range end @
Rd/Wr-Alloc. Miss Cache line evictions

Main Memories AXI interconnect

Cache control logic
AXI Master

Cache Master
Slave cache
CPU

port Cache port

interface

interface
AXI

Master
FSM
AXI AXI

Maintenance
pLRU-t
Master(s) AXI interconnect(s)

operations

Cache memory port

Peripherals
AXI Master

Cache Cache/SRAM
AXI TAG Data
Memories Memories
n ways n ways

SRAM
Slave SRAM

port
interface

AXI

CACHEAXI
MSv70419V2

12.4.2 CACHEAXI reset and clocks

At reset, cache is disabled (EN = 0 in CACHEAXI_CR1), which means that cache mode is
disabled.
CACHEAXI transactions on slave cache port are clocked on the (Master) AXI interconnect
clock received on slave cache port. The CACHEAXI master port clock is always a copy of
the slave cache port clock, in any of the following conditions:
• The cache mode is disabled, and input requests received on slave cache port are just
copied to the CACHEAXI master port (including the AXI clock).
• The cache mode is enabled, and the CACHEAXI master port drives the refill requests
or the noncacheable transactions (that are forwarded from the slave cache port).

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When the CACHEAXI hardware configuration supports the optional SRAM mode and logic,
and when the CACHEAXI is disabled, it is configured in SRAM mode:
• The CACHEAXI is clocked on the Master AXI interconnect clock received on slave
SRAM port.
• CACHEAXI data memories can be accessed by data request on slave SRAM port.
• The cache mode is disabled, but cache TAG memories are initialized (see invalidate
procedure below).
When the CACHEAXI reset signal is released, a cache invalidate procedure is automatically
launched, making the CACHEAXI busy (CACHEAXI_SR = 0x0000 0001).
When this procedure is finished:
• The cache control logic and TAG memories are initialized: all cache line valid, dirty,
compartment ID and privilege TAG bits = 0.
• CACHEAXI_SR = 0x0000 0002 (reflecting the cache control logic is no longer busy).
• The cache mode is still disabled (EN bit in CACHEAXI_CR1 holds its reset state = 0),
but CACHEAXI is ready to be switched in cache mode.
Then, when cache mode is enabled (EN = 1 in CACHEAXI_CR1):
• The CACHEAXI is clocked on the (Master) AXI interconnect clock received on its slave
cache port.
• The CACHEAXI is in “cold cache” state, and can serve input requests received on its
slave cache port.
When the cache mode is enabled, the SRAM mode is disabled, and input requests received
on slave SRAM port are not served: write requests are ignored, and read requests are
responded with 0s.
Access to CACHEAXI registers is always clocked by the clock of the AHB configuration
slave port.

12.4.3 CACHEAXI TAG memory

The CACHEAXI TAG memory contains:
• Address tags that indicate which data are contained in the cache data memories
• Valid bits
• Dirty bits
• Privilege bits
• Compartment ID (CID) bits
There is one valid bit (V), one privilege bit (P), one 3-bit CID (C[2:0]) and one dirty bit (D) per
cache line (per way).
The valid bit enables/disables access to the data cache line: if the line is not valid, the data
access (read or write) is performed in the main memory.
The valid bit is set when the cache line is written (allocated by either a read-allocate miss or
a write-back miss).

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The valid bits are reset in any of the below cases:

• After CACHEAXI reset is released
• When cache mode is disabled (by setting EN low in CACHEAXI_CR1, by software)
• When executing the full invalidate command, when software sets CACHEINV = 1 in
CACHEAXI_CR1
• When executing the clean and invalidate range command, when software sets
CACHECMD = 0b11 and STARTCMD = 1 in CACHEAXI_CR2.
See Section 12.4.10: CACHEAXI maintenance for details on cache maintenance
commands.
The dirty bit indicates that the cache line has up-to-date values with respect to the main
memory content (in other words, cache has last right value, main memory is not up to date).
The dirty bit is set when the cache line is written by a slave cache port write transaction (only
in case of an access with write-back attribute).
The dirty bits are reset in any of the below cases:
• After CACHEAXI reset is released
• When a line refill is performed on a read miss (on a write-back miss, the refilled cache
line is modified by the written data and dirty bit = 1)
• When cache invalidation is performed
• When executing one of the CACHEAXI clean operations (cache line written back to the
main memory), setting by software CACHECMD = 0b01 or 0b011 in CACHEAXI_CR2
The privilege bit indicates if the data is managed by a privileged entity. It is assigned
according to the value of AXI privileged attribute at slave cache port, for the first access to
this line (it is written only during a line allocation). The privilege bit holds same polarity as
the privileged attribute: 1 for privileged access, 0 for unprivileged access.
The privilege bits are reset:
• After CACHEAXI reset is released
• When the cache is invalidated.
The 3-bit CID indicates to which processing compartment a data belongs to. It is assigned
according to the value of AXI user-defined CID attribute at slave cache port for the first
access to this line (it is written only during a line allocation).
The CID bits (C[2:0]) are reset:
• After CACHEAXI reset is released
• When the cache is invalidated.
When a cacheable transaction is received at the slave cache port, its AXI transfer address
(AxADDR_in[31:0]; either ARADDR_in if on the AXI read channel, or AWADDR_in if on AXI
write channel) is split into the following fields (see the table below for B and W values):
• AxADDR_in[B-1:0]: address byte offset, indicates which byte to select inside
a cache line
• AxADDR_in[B+W-1:B]: address way index indicates which cache line to select inside
each way
• AxADDR_in[31:B+W]: tag address, to be compared to TAG memory address to check if
the requested data is already available (meaning valid) inside CACHEAXI
The table below gives the main CACHEAXI parameters for TAG memory dimensioning.

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Table 47. TAG memory dimensioning parameters

Parameter Value Example

Cache size S Kbytes = s bytes (s = 1024 x S) 256 Kbytes = 262144 bytes

Cache number of ways n 8
Cache line size L-byte = l-bit (l = 8 x L) 64-byte = 512-bit
Number of cache lines (per way) LpW = s / (n x L) lines/way 512 lines/way
Address byte offset size B = log2(L) bit 6-bit
Address way index size W = log2(LpW) bit 9-bit
TAG address size T = (32 - W - B) bit 17-bit

Figure 13. shows the functional view of TAG and data memories, for an n-way set
associative CACHEAXI.

Figure 13. CACHEAXI TAG and data memories functional view

T-bit W-bit B-bit

AXI CID attribute AXI_address

(AxUSER_CID_in[2:0]) TAG Index Offset (AxADDR_in)

way selection
(for replacement) pLRU-t

Vn-1 Pn-1 Dn-1 Cn-1[ ] TAG_Way(n-1) Data_Way(n-1)

V0 P0 D0 C0[2:0] TAG_Way0 Data_Way0
LpW lines / way

LpW lines / way

TAG
G memory Data memory

n ways n ways
T-bit l-bit

==
== Cache hit/miss, in Way(n-1)

Cache hit/miss, in Way0

MSv70420V1

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12.4.4 CACHEAXI enable

To activate the CACHEAXI functioning as a cache, EN must be set in CACHEAXI_CR1.
When the CACHEAXI is disabled, it is in SRAM mode, and then bypassed by input requests
received on the slave cache port (all these transactions are copied from slave cache port to
master port in the same clock cycle, and no comparison is performed with TAG memory).
CACHEAXI is in SRAM mode at boot time (cache mode disabled by default) and can be
addressed by any memory request received on slave SRAM port.

12.4.5 Cacheable and noncacheable AXI traffic to slave cache port

The CACHEAXI is developed for AXI bus master peripheral and, when in cache mode, it
caches the memory regions addressable by the AXI bus connected to its master port.
The AXI bus traffic to the main memory regions can also be cacheable or noncacheable. An
incoming memory request to CACHEAXI slave cache port is defined as cacheable
according to its AXI 4-bit memory attribute (cache attribute).
The CACHEAXI supports the allocate or nonallocate policy for both read or write missing
transactions. In case of write transaction, the CACHEAXI write policy can be defined as
write-through or write-back. Allocation and write policies are defined by the AXI 4-bit
memory attribute. This attribute is driven by the master peripheral that initiates the memory
request.

Table 48. CACHEAXI supported AXI 4-bit memory/cache attribute

Read or write
AXI memory attribute CACHEAXI behavior
AXI channel

Read, noncacheable nonbufferable: no look-up, read from memory

ARCACHE[3:0] = 0010
(cache bypassed, read forwarded to master port)
Read, cacheable allocate: hit read from cache, miss read from
Read ARCACHE[3:0] = 1111
memory, with allocation
Read, cacheable nonallocate: hit read from cache, miss read from
ARCACHE[3:0] = 1010
memory, without allocation
Write, noncacheable nonbufferable: no look-up, write to memory
AWCACHE[3:0] = 0010
(cache bypassed, write forwarded to master port)
Write-back, cacheable allocate: hit write to cache, miss
Write AWCACHE[3:0] = 1111
read-allocate-modify (write data only into allocated cache line)
Write-through, cacheable nonallocate: hit write to cache and to
AWCACHE[3:0] = 0110
memory, miss write to memory only, without allocation.

In case of noncacheable access, the CACHEAXI is bypassed: the AXI transaction is

propagated unchanged from the slave cache port to the master output port, including all the
standard AXI4 attributes (except the cache type ones, which are useless for an AXI request
to a main memory), and also the user-defined attributes.
• A noncacheable read transaction on the AXI read channel (of slave cache port) is
forwarded to the AXI read channel (of master port).
• A noncacheable write transaction on the AXI write channel (of slave cache port) is
forwarded to the AXI write channel (of master port).

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The bypass does not increase the latency of the access to the targeted memory.
AXI attribute signals are set by the master peripheral that initiates the AXI memory request.
In case of cacheable access on slave cache port, the CACHEAXI behaves as explained in
the next section.

12.4.6 Cacheable accesses

When the CACHEAXI receives a cacheable transaction from the AXI master peripheral
on its slave cache port, it checks if the requested address and the compartment ID are
present in its TAG memory, and if the corresponding cache line is valid. Regarding the
hit/miss check, the compartment ID can be seen as a 3-bit extension of the address. In
the next paragraphs, the address considered for the comparison with the TAG
addresses is made of both the address itself and of the CID: the address matches if
both the actual address and the CID match; the address mismatches if one of them
mismatches.
For read transaction, the following alternatives exist:
• The address matches the one of a valid cache line TAG: cache read hit, the data is
read from the cache and provided to the master peripheral.
• The address does not match a valid cache line TAG: cache read miss, the data is read
from the main memory and provided to the master peripheral.
Depending on the read transaction allocate attribute, a cache line refill is performed, or
not. If the allocation must be done, the read request to main memory has the cache line
size. If not, the read request to main memory has simply the size of the input request
(propagated from slave cache port to master port).
The AXI protection attribute and CID/prefetch user-defined attributes are also
propagated from the slave cache port to the master port, for the (nonallocated) simple
data access or cache line refill request.
Note: The first read transaction that misses, blocks the cache slave port: no further
cacheable transaction makes a lookup in cache lines TAG until missing read is served
by the CACHEAXI (data read, and if a read-allocate, cache line refilled).
For write-back transaction (write transaction, with cacheable write-back allocate
attributes, the following alternatives exist:
• The address matches the one of a valid cache line TAG: cache write-back hit, the
data is written in cache (in the matching cache line).
• The address does not match a valid cache line TAG: cache write-back miss.
A line allocation is performed by reading the entire cache line data from main memory.
The AXI protection attribute and the user-defined attribute for the cache line refill
request are propagated from the slave cache port to the master port.
Once the refilled line has been written in the CACHEAXI, the initial data provided on
slave cache port is written in the CACHEAXI (it overwrites a part of the cache line that
was refilled just before).
Note: The first write-back transaction that misses, blocks the cache slave port: no
further cacheable transaction makes a lookup in cache lines TAG until missing
write-back is served by the CACHEAXI (cache line refilled and data written).

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For write-through transaction (write transaction, with cacheable write-through nonallocate

attributes, the following alternatives exist:
• Address matches the one of a valid cache line TAG: cache write-through hit, the data
is written both in cache and in main memory (through master port).
• Address does not match a valid cache line TAG: cache write-through miss, the data
incoming at slave cache port is written only in main memory (unlike the write-back
miss, there is no line allocation and data is not written in cache).
In case of cache refill (due to cache miss), the CACHEAXI selects which cache line is
written with the refill data: as an n-way set associative cache, one line among n can be used
(the line pointed by the address index, in each of the n ways). The way selection is based on
a pLRU-t replacement algorithm. This algorithm points, for each index, on the way
candidate for the next refill.
If ever the cache line where the refill data must be written is already valid, the targeted
cache line must be evicted first:
• If the dirty tag of this line equals 0 (a clean cache line), the line is simply invalidated.
• If the dirty tag of this line equals 1 (a dirty cache line), the evicted cache line is written
into an eviction buffer, before to be written back in the main memory
(see Section 12.4.7).
The CACHEAXI generates an AXI burst write transaction on its master port, with burst
type set to INCR and with AXI memory transaction attribute signals set as detailed
below:
– privileged = evicted line TAG privilege bit (P)
– data (not instruction)
– CID[2:0] = evicted line TAG CID bits (C[2:0])
These AXI attributes cannot be propagated from the slave port (as it is the case for all
other transactions emitted on CACHEAXI master port) because the evicting transaction
has no relation with the initial missing transaction (that made the refill of the cache line
to evict).

12.4.7 AXI traffic to master port

To improve the throughput of the refill traffic generated by the CACHEAXI on its master port
(to improve global CACHEAXI performance), the CACHEAXI implements the following
feature:
• Prefetch hint forwarded from slave read cache port to master port to inform
downstream logic/memory to prefetch extra data from main memory (in addition to the
ones requested by this master port refill request)
In order to improve CACHEAXI eviction performance, the following feature is implemented:
• An eviction buffer receives the AXI write transaction that corresponds to the dirty cache
line evicted from cache. When either a cache read-with-allocation, or a cache
write-back request misses, it initiates a cache line refill operation, that potentially
implies the eviction of a dirty cache line (when the n ways of the cache line index to be
used for the refill are already all valid).
The eviction buffer allows the CACHEAXI not to block a missing request beyond the
occurrence of the refill operation, and not to wait for the evicted cache line operation
(write to main memory) to be performed on the CACHEAXI master port. The eviction
operation is just sent to the eviction buffer, that initiates it on master port in the
background (when the master port is available for that).

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12.4.8 AXI traffic to slave SRAM port

If this optional feature is supported, the CACHEAXI can behave as an SRAM.
The addressable SRAM region is mapped in the system global memory map, and the
SRAM size equals the CACHEAXI (cache) size.
When in SRAM mode (CACHEAXI_CR1.EN = 0), the CACHEAXI SRAM can be addressed
by the Cortex core or other AXI bus master peripheral on its dedicated slave SRAM port
(hardware configuration option).
This AXI slave SRAM port has independent read and write channels (read address and data
channels; write address, data and response channels), as the AXI slave cache port.
The read or write AXI transaction received on AXI slave SRAM port has the following
characteristics:
• The relevant address field is restricted to the CACHEAXI size (for instance, only the
17 last significant bits of the address are relevant to address a 128-Kbyte CACHEAXI).
• Byte (8-bit), half-word (16-bit), word (32-bit) or double-word (64-bit) transfer beat size.
• No cache type attribute (useless to access an SRAM).
• No support of AXI standard protection attributes, and no support of AXI user-defined
attributes (since they are filtered, upstream of AXI slave SRAM port).

12.4.9 CACHEAXI security

The CACHEAXI implements an Armv8-M TrustZone.
CACHEAXI configuration registers are protected at system level.

12.4.10 CACHEAXI maintenance

The CACHEAXI features several maintenance operations that the software can program in
CACHEAXI_CR1 and CACHEAXI_CR2 control registers:
• Full invalidate: invalidates the whole cache, noninterruptible task.
The software can invalidate the whole CACHEAXI content by programming
CACHEINV in CACHEAXI_CR1.
When CACHEINV is set, the CACHEAXI control logic sets the BUSYF flag in
CACHEAXI_SR, and performs the operation of cache invalidation, in each cache line
TAG, reseting:
– the valid bit (V = 0)
– the dirty bit (D = 0)
– the privilege bit (P = 0)
– the compartment ID bits (C[2:0] = 000)
to prevent unknown values at next cache line validation.
CACHEINV in CACHEAXI_CR1 is automatically cleared.
Once the full invalidate operation is finished, the CACHEAXI automatically clears
BUSYF and sets BSYENDF in CACHEAXI_SR.
If enabled on this flag condition (BSYENDIE = 1 in CACHEAXI_IER), the CACHEAXI
interrupt is raised, on cacheaxi_it signal. The (empty) cache is available again.
This full invalidate operation is not interruptible, meaning that the cache does not treat
any cacheable request while BUSYF is set (the incoming request is blocked until the

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full invalidate is finished). However, the noncacheable traffic is treated (since the
request address is not compared to TAG ones) as the CACHEAXI is bypassed in the
same clock cycle (same behavior as when CACHEAXI cache mode is disabled).
• Clean range: cleans a certain range of addresses in the cache, background task
(interruptible).
Cleaning a cache line means making sure that main memory content is up-to-date with
the data which may have been modified in cache. The clean operation consists in
performing the write-back in main memory of the cache lines that are tagged as “dirty”
(the ones with TAG dirty bit set).
The software can clean a given data region in the CACHEAXI by programming
STARTCMD = 1, and CACHECMD = 0b01 in CACHEAXI_CR2, after the address
range was programmed into CACHEAXI_CMDRSADDRR (range start address) and
CACHEAXI_CMDREADDRR (range end address).
The CACHEAXI control logic then parses the whole TAG memory. If the read line
address (TAG address + line index) falls in the programmed address range
(CACHEAXI_CMDRSADDRR ≤ Line Addr ≤ CACHEAXI_CMDREADDRR) and the
corresponding line is dirty, this line is cleaned: the whole cache line is written-back in
memory through the CACHEAXI master port, and its TAG dirty bit is cleared.
When STARTCMD is set, the CACHEAXI control logic sets BUSYCMDF in
CACHEAXI_SR, and launches the clean range operation. STARTCMD in
CACHEAXI_CR2 is also automatically cleared.
Once the operation is finished (all TAG memory parsed), the CACHEAXI automatically
clears BUSYCMDF and sets CMDENDF in CACHEAXI_SR.
If enabled on this flag condition (CMDENDIE = 1 in CACHEAXI_IER), the CACHEAXI
interrupt is raised, on cacheaxi_it signal.
During this clean range operation, the CACHEAXI is interruptible: it can accept new
incoming requests that take higher priority than the cleaning process. The TAG
memory is accessed for clean range operation only if not already accessed by an
external cache request. This implies that clean range execution is usually not
performed in one go, but can be interrupted.
It is under the software responsibility that no bus initiator attempts to change the
content of the region being cleaned until the clean range is completed. The software
must take advantage of BUSYCMDF in CACHEAXI_SR, and polls this flag to prevent
any spurious access to the area being cleaned. Alternatively the software can also rely
on the command end flag (CMDENDF) or on the CACHEAXI interrupt to detect the end
of the clean range execution.
• Clean and invalidate range: cleans and invalidates a certain range of addresses in
the cache, background task (interruptible).
This operation cleans the “dirty” cache lines that belong to the operation address range
(the same as clean range operation), and also invalidates all the (valid) cache lines that
belong to this address range (whether they are dirty or not).
Note: When a cache line is invalidated, the pLRU-t pointer (for this cache line index) is
updated to point to the way that was just invalidated (best candidate for the next
allocation).
The software can launch this clean and invalidate range operation, by programming
STARTCMD = 1, and CACHECMD = 0b11 in CACHEAXI_CR2, after the address

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range was programmed into CACHEAXI_CMDRSADDRR (range start address) and

CACHEAXI_CMDREADDRR (range end address).
This sets and clears the same flags, and potentially the same interrupt as clean range
operation.

12.4.11 CACHEAXI performance monitoring

The CACHEAXI provides the following monitors for performance analysis:
• The read-hit monitor counts the cacheable AXI read transactions on the slave cache
port that hit the CACHEAXI content.
• The write-hit monitor counts the cacheable AXI write transactions on slave cache port
that hit the CACHEAXI content.
• The read-miss monitor counts the cacheable AXI read transactions on slave cache port
that miss the CACHEAXI content.
• The write-miss monitor counts the cacheable AXI write transactions on slave cache
port that miss the CACHEAXI content.
The hit and miss monitors above actually count the number of lookups (in the
CACHEAXI TAG memory) implied by the AXI transactions:
– when an AXI burst transaction results in several data transfers (or beats) that
target the same cache line address range, only one lookup occurs, and the hit or
miss monitor only increments by 1.
– when the data transfers (or beats) of a given AXI burst target several cache line
address ranges, the hit/miss monitor increment globally by the number of
looked-up cache lines (some can hit, others can miss).
• The read-allocate-miss monitor counts the cache line refill operations (main memory
reads) implied by cacheable AXI read-allocate transactions that miss.
• The write-allocate-miss monitor counts the cache line refill operations (main memory
reads) implied by cacheable AXI write-back transactions, that miss (and then allocate).
• The write-through monitor counts the total amount of main memory write operations
implied by cacheable AXI write-through transactions (whether they hit or miss).
• The eviction monitor counts:
– the total amount of (dirty) cache lines evicted by the refill operations resulting from
either read-allocate misses or write-allocate (write-back) misses,
– and also, the amount of cache lines ‘evicted’ by a clean operation, meaning the
number of dirty lines with an address included in the address range specified by a
given 'clean range' or 'clean and invalidate range' maintenance operation, and that
are dirty.
Only dirty cache lines written back to main memory are counted; eviction of non dirty
cache lines, that are simply invalidated, are not counted.
The monitors count is effective only when the CACHEAXI is enabled (in cache mode).
Noncacheable read or write transactions are not counted.
Upon reaching their maximum values, the monitors do not wrap over.

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RM0486 AXI cache (CACHEAXI)

The software can perform the following tasks:

• Enable/stop the read (write) hit monitor, through R(W)HITMEN in CACHEAXI_CR1.
• Reset the read (write) hit monitor, by setting R(W)HITMRST in CACHEAXI_CR1.
• Enable/stop the read (write) miss monitor, through R(W)MISSMEN
in CACHEAXI_CR1.
• Reset the read (write) miss monitor, by setting R(W)MISSMRST in CACHEAXI_CR1.
• Enable/stop the read-allocate (write-allocate) miss monitor, through R(W)AMMEN
in CACHEAXI_CR1.
• Reset the read-allocate (write-allocate) miss monitor, by setting R(W)AMMRST
in CACHEAXI_CR1.
• Enable/stop the write-through monitor, through WTMEN in CACHEAXI_CR1.
• Reset the write-through monitor, by setting WTMRST in CACHEAXI_CR1.
• Enable/stop the eviction monitor, through EVIMEN in CACHEAXI_CR1.
• Reset the eviction monitor, by setting EVIMRST in CACHEAXI_CR1.
To reduce power consumption, these monitors are disabled (stopped) by default.

12.4.12 CACHEAXI boot

The CACHEAXI is disabled (EN = 0 in CACHEAXI_CR1) at boot: cache mode is disabled
and the CACHEAXI behaves as an SRAM.
Once the boot is finished, the CACHEAXI cache mode can be enabled (by setting EN
in CACHEAXI_CR1).

12.5 CACHEAXI low-power modes

Using the CACHEAXI reduces the power consumption at device level by, most of the time,
loading/storing data from/to the internal CACHEAXI rather than from the bigger main
memories (more power consuming). This reduction is even much higher when the cached
main memories are external.
At CACHEAXI level, the access to a given cache line is pipelined: the TAG memory is
accessed first (for lookup operation to determine if the access misses all the ways, or hits a
given way). In case of hit, the data memory is accessed in a second cycle, and only the data
memory cut holding the hitting way is accessed. Accessing only one way among all the n
ways available reduces CACHEAXI power consumption to the minimum.

12.6 CACHEAXI error management and interrupts

A transaction initiated on the CACHEAXI master port may return an error (a write attempt
into a read-only memory, a security issue or an address decoding issue, for instance).
If the master port request was propagated from a slave cache port request (non-cacheable
request, or cacheable request with allocation that misses), the CACHEAXI propagates the
AXI bus error from the AXI master cache port back to the corresponding AXI slave cache
port.
If ever the master port request is initiated by the CACHEAXI itself (dirty cache line written-
back into the main memory because of an eviction or a clean operation), the CACHEAXI

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AXI cache (CACHEAXI) RM0486

receives this functional error, and flags it internally by setting ERRF in CACHEAXI_SR. And
an interrupt is generated if the corresponding interrupt enable bit is set (ERRIE = 1 in
CACHEAXI_IER).
Another case of interrupt generation is at the end of a full invalidate operation: when the
cache busy state is finished, the CACHEAXI sets BSYENDF in CACHEAXI_SR. An
interrupt is then generated if the corresponding interrupt enable bit is set (BSYENDIE = 1 in
CACHEAXI_IER).
The last case is at the end of a maintenance range operation (clean/invalidate range): when
the command busy state is finished, the CACHEAXI sets CMDENDF in CACHEAXI_SR. An
interrupt is generated if the corresponding interrupt enable bit is set (CMDENDIE = 1
in CACHEAXI_IER).
The CACHEAXI has a unique interrupt signal, cacheaxi_it (and then use the same interrupt
vector whatever the interrupt source).

Table 49. CACHEAXI interrupts

Interrupt
Interrupt event Event flag Enable control bit Interrupt clear method
vector

ERRF flag in ERRIE bit in Set CERRF bit to 1 in

CACHEAXI Functional error
CACHEAXI_SR CACHEAXI_IER CACHEAXI_FCR
End of busy state (full BSYENDF flag in BSYENDIE bit in Set CBSYENDF bit to 1 in
CACHEAXI
invalidate finished) CACHEAXI_SR CACHEAXI_IER CACHEAXI_FCR
End of cache range
CMDENDF flag in CMDENDIE bit in Set CCMDENDF bit to 1 in
CACHEAXI operation (address
CACHEAXI_SR CACHEAXI_IER CACHEAXI_FCR
range based)

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RM0486 AXI cache (CACHEAXI)

12.7 CACHEAXI registers

12.7.1 CACHEAXI control register 1 (CACHEAXI_CR1)

Address offset: 0x000
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WMISSMRST

RMISSMRST
WMISSMEN
WHITMRST

RMISSMEN
WAMMRST

RHITMRST
RAMMRST

WHITMEN

RHITMEN
WAMMEN
EVIMRST

RAMMEN
WTMRST

EVIMEN

WTMEN

w w rw rw w w rw rw w w rw rw w w rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CACHEINV

EN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

w rw

Bit 31 EVIMRST: eviction monitor reset

0: no effect
1: reset cache eviction monitor
Bit 30 WTMRST: write-through monitor reset
0: no effect
1: reset cache write-through monitor
Bit 29 EVIMEN: eviction monitor enable
0: cache eviction monitor switched off. Stopping the monitor does not reset it.
1: cache eviction monitor enabled
Bit 28 WTMEN: write-through monitor enable
0: cache write-through monitor switched off. Stopping the monitor does not reset it.
1: cache write-through monitor enabled
Bit 27 WAMMRST: write-allocate miss monitor reset
0: no effect
1: reset cache write-allocate miss monitor
Bit 26 RAMMRST: read-allocate miss monitor reset
0: no effect
1: reset cache read-allocate miss monitor
Bit 25 WAMMEN: write-allocate miss monitor enable
0: cache write-allocate miss monitor switched off. Stopping the monitor does not reset it.
1: cache write-allocate miss monitor enabled
Bit 24 RAMMEN: read-allocate miss monitor enable
0: cache read-allocate miss monitor switched off. Stopping the monitor does not reset it.
1: cache read-allocate miss monitor enabled
Bit 23 WMISSMRST: write-miss monitor reset
0: no effect
1: reset cache write-miss monitor

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Bit 22 WHITMRST: write-hit monitor reset

0: no effect
1: reset cache write-hit monitor
Bit 21 WMISSMEN: write-miss monitor enable
0: cache write-miss monitor switched off. Stopping the monitor does not reset it.
1: cache write-miss monitor enabled
Bit 20 WHITMEN: write-hit monitor enable
0: cache write-hit monitor switched off. Stopping the monitor does not reset it.
1: cache write-hit monitor enabled
Bit 19 RMISSMRST: read-miss monitor reset
0: no effect
1: reset cache read-miss monitor
Bit 18 RHITMRST: read-hit monitor reset
0: no effect
1: reset cache read-hit monitor
Bit 17 RMISSMEN: read-miss monitor enable
0: cache read-miss monitor switched off. Stopping the monitor does not reset it.
1: cache read-miss monitor enabled
Bit 16 RHITMEN: read-hit monitor enable
0: cache read-hit monitor switched off. Stopping the monitor does not reset it.
1: cache read-hit monitor enabled
Bits 15:2 Reserved, must be kept at reset value.
Bit 1 CACHEINV: full cache invalidation
Can be set by software, only when EN = 1.
Cleared by hardware when the BUSYF flag is set (during full cache invalidation operation).
Writing 0 has no effect.
0: no effect
1: invalidate entire cache (all cache lines valid bit = 0)
Bit 0 EN: enable
0: cache mode disabled (cache port bypassed and SRAM port active)
1: cache mode enabled (SRAM port not active)

12.7.2 CACHEAXI status register (CACHEAXI_SR)

Address offset: 0x004
Reset value: 0x0000 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSYCMDF
CMDENDF

BSYENDF

BUSYF
ERRF

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

r r r r r

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RM0486 AXI cache (CACHEAXI)

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 CMDENDF: command end flag
Cleared by writing CACHEAXI_FCR.CCMDENDF = 1.
0: cache busy or in idle
1: CACHECMD command finished
Bit 3 BUSYCMDF: command busy flag
0: cache not busy on a CACHECMD command
1: cache busy on a CACHECMD command (clean or clean-and-invalidate an address range)
Bit 2 ERRF: cache error flag
Cleared by writing CACHEAXI_FCR.CERRF = 1.
0: no error
1: an error occurred during the operation (eviction or clean operation write-back error).
Bit 1 BSYENDF: full invalidate busy end flag
Cleared by writing CACHEAXI_FCR.CBSYENDF = 1.
0: cache busy or in idle
1: full invalidate CACHEINV operation finished
Bit 0 BUSYF: full invalidate busy flag
0: cache not busy on a CACHEINV operation
1: cache executing a full invalidate CACHEINV operation

12.7.3 CACHEAXI interrupt enable register (CACHEAXI_IER)

Address offset: 0x008
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDENDIE

BSYENDIE
ERRIE

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 CMDENDIE: interrupt enable on command end
Set by software to enable an interrupt generation at the end of a cache command (clean or
clean-and-invalidate an address range)
0: interrupt disabled on command end
1: interrupt enabled on command end
Bit 3 Reserved, must be kept at reset value.

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Bit 2 ERRIE: interrupt enable on cache error

Set by software to enable an interrupt generation in case of cache functional error (eviction
or clean operation write-back error)
0: interrupt disabled on error
1: interrupt enabled on error
Bit 1 BSYENDIE: interrupt enable on busy end
Set by SW to enable an interrupt generation at the end of a cache full invalidate operation.
0: Interrupt disabled on busy end
1: Interrupt enabled on busy end
Bit 0 Reserved, must be kept at reset value.

12.7.4 CACHEAXI flag clear register (CACHEAXI_FCR)

Address offset: 0x00C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CCMDENDF

CBSYENDF
CERRF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

w w w

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 CCMDENDF: clear command end flag
Set by software.
0: no effect
1: clears CMDENDF flag in CACHEAXI_SR.
Bit 3 Reserved, must be kept at reset value.
Bit 2 CERRF: clear cache error flag
Set by software.
0: no effect
1: clears ERRF flag in CACHEAXI_SR.
Bit 1 CBSYENDF: clear full invalidate busy end flag
Set by software.
0: no effect
1: clears BSYENDF flag in CACHEAXI_SR.
Bit 0 Reserved, must be kept at reset value.

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RM0486 AXI cache (CACHEAXI)

12.7.5 CACHEAXI read-hit monitor register (CACHEAXI_RHMONR)

Address offset: 0x010
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RHITMON[31:16]

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RHITMON[15:0]

r r r r r r r r r r r r r r r r

Bits 31:0 RHITMON[31:0]: cache read-hit monitor counter

12.7.6 CACHEAXI read-miss monitor register (CACHEAXI_RMMONR)

Address offset: 0x014
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RMISSMON[31:16]

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RMISSMON[15:0]

r r r r r r r r r r r r r r r r

Bits 31:0 RMISSMON[31:0]: cache read-miss monitor counter

12.7.7 CACHEAXI read-allocate miss monitor register

(CACHEAXI_RAMMONR)
Address offset: 0x018
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RAMMON[31:16]

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RAMMON[15:0]

r r r r r r r r r r r r r r r r

Bits 31:0 RAMMON[31:0]: cache read-allocate miss monitor counter

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12.7.8 CACHEAXI eviction monitor register (CACHEAXI_EVIMONR)

Address offset: 0x01C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

EVIMON[31:16]

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EVIMON[15:0]

r r r r r r r r r r r r r r r r

Bits 31:0 EVIMON[31:0]: cache eviction monitor counter

12.7.9 CACHEAXI write-hit monitor register (CACHEAXI_WHMONR)

Address offset: 0x020
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WHITMON[31:16]

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WHITMON[15:0]

r r r r r r r r r r r r r r r r

Bits 31:0 WHITMON[31:0]: cache write-hit monitor counter

12.7.10 CACHEAXI write-miss monitor register (CACHEAXI_WMMONR)

Address offset: 0x024
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WMISSMON[31:16]

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WMISSMON[15:0]

r r r r r r r r r r r r r r r r

Bits 31:0 WMISSMON[31:0]: cache write-miss monitor counter

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RM0486 AXI cache (CACHEAXI)

12.7.11 CACHEAXI write-allocate miss monitor register

(CACHEAXI_WAMMONR)
Address offset: 0x028
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WAMMON[31:16]

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WAMMON[15:0]

r r r r r r r r r r r r r r r r

Bits 31:0 WAMMON[31:0]: cache write-allocate miss monitor counter

12.7.12 CACHEAXI write-through monitor register (CACHEAXI_WTMONR)

Address offset: 0x02C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WTMON[31:16]

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WTMON[15:0]

r r r r r r r r r r r r r r r r

Bits 31:0 WTMON[31:0]: cache write-through monitor counter

12.7.13 CACHEAXI control register 2 (CACHEAXI_CR2)

Address offset: 0x100
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CACHECMD START
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
[1:0] CMD
rw rw w

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AXI cache (CACHEAXI) RM0486

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:1 CACHECMD[1:0]: cache command maintenance operation (clean or clean-and-invalidate an
address range)
This field can be set and cleared by software, only when no maintenance command is
ongoing (BUSYCMDF = 0).
00: no operation
01: clean range
11: clean and invalidate range
others: reserved
Bit 0 STARTCMD: starts maintenance range command (maintenance operation defined in
CACHECMD).
This bit can be set by software, only when EN = 1, BUSYCMDF = 0, BUSYF = 0, and
CACHECMD[1:0] = 0b01 or 0b11.
It is cleared by hardware when BUSYCMDF is set (during cache maintenance operation).
Writing 0 to this bit has no effect.
0: command operation (cache maintenance) finished
1: start maintenance command (cache maintenance)

12.7.14 CACHEAXI command range start address register

(CACHEAXI_CMDRSADDRR)
Address offset: 0x104
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CMDSTARTADDR[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CMDSTARTADDR[15:6] Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw

Bits 31:6 CMDSTARTADDR[31:6]: start address of range to which the cache maintenance command
specified in CACHEAXI_CR2.CACHECMD field applies
This field must be set before CACHEAXI_CR2.CACHECMD is written.
Bits 5:0 Reserved, must be kept at reset value.

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RM0486 AXI cache (CACHEAXI)

12.7.15 CACHEAXI command range end address register

(CACHEAXI_CMDREADDRR)
Address offset: 0x108
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CMDENDADDR[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CMDENDADDR[15:6] Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw

Bits 31:6 CMDENDADDR[31:6]: end address of range to which the cache maintenance command
specified in CACHEAXI_CR2.CACHECMD field applies
This field must be set before CACHEAXI_CR2.CACHECMD is written.
Bits 5:0 Reserved, must be kept at reset value.

12.7.16 CACHEAXI register map

Table 50. CACHEAXI register map and reset values

Register
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name
WMISSMRST

RMISSMRST
WMISSMEN
WHITMRST

RMISSMEN
WAMMRST

RHITMRST

CACHEINV
RAMMRST

WHITMEN
WAMMEN

RHITMEN
EVIMRST

RAMMEN
WTMRST

WTMEN
EVIMEN

CACHEAXI_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

EN
0x000 CR1

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BUSYCMDF
CMDENDF

BSYENDF
BUSYF
ERRF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

CACHEAXI_SR
0x004

Reset value 0 0 0 0 1
CMDENDIE

BSYENDIE
ERRIE

CACHEAXI_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.

0x008 IER

Reset value 0 0 0
CCMDENDF

CBSYENDF
CERRF

CACHEAXI_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.

0x00C FCR

Reset value 0 0 0
CACHEAXI_
RHITMON[31:0]
0x010 RHMONR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CACHEAXI_
RMISSMON[31:0]
0x014 RMMONR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CACHEAXI_
RAMMON[31:0]
0x018 RAMMONR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Table 50. CACHEAXI register map and reset values (continued)

Register
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name
CACHEAXI_
EVIMON[31:0]
0x01C EVIMONR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CACHEAXI_
WHITMON[31:0]
0x020 WHMONR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CACHEAXI_
WMISSMON[31:0]
0x024 WMMONR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CACHEAXI_
WAMMON[31:0]
0x028 WAMMONR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CACHEAXI_
WTMON[31:0]
0x02C WTMONR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x030-
Reserved Reserved
0x0FC

CACHECMD

STARTCMD
CACHEAXI_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

[1:0]
0x100 CR2

Reset value 0 0 0
CACHEAXI_

Res.
Res.
Res.
Res.
Res.
CMDRS CMDSTARTADDR[31:5](1)
0x104 ADDRR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CACHEAXI_

Res.
Res.
Res.
Res.
Res.
CMDRE CMDENDADDR[31:5](1)
0x108 ADDRR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1. Bit 5 is reserved (=0) for CACHEAXI configuration with 64-bytes cache line width.

Refer to Section 2.3 for the register boundary addresses.

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13 Power control (PWR)

13.1 PWR introduction

This section gives an overview of the supply architecture for the different power domains
and of the supply configuration controller. It also describes the features of the power-supply
supervisors, and explains how the VCORE supply domain is configured, depending upon the
operating modes, the selected performance (clock frequency), and the voltage scaling.

13.2 PWR main features

• Power supplies and supply domains
– Core domains (VCORE = VDDCORE)
– VDD domain (VRET)
– Backup domain (VSW, VBKP)
– Analog domain (VDDA18ADC)
• System supply voltage regulation
– Switched-mode power supply power-efficient voltage down-converter
(SMPS step-down converter)
– 0v8 backup regulator (external to the PWR)
• Power supply supervision
– POR/PDR monitor
– BOR monitor
– VDDA18PMU monitor
– PVD monitor
– PVM monitor (VDDIO2, VDDIO3, VDDIO4, VDDIO5, VDD33USB, VDDA18ADC)
– V08CAP thresholds
– Temperature thresholds
– VDDCORE monitor
• Power management
– Operating modes
– Voltage scaling control
– Low-power modes

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13.3 PWR block diagram

Figure 14. Power control block diagram

32-bit
AHB RCC
Register interface
bus

PDR_ON POR/PDR pwr_por_rstn

BOR pwr_bor_rstn
VDD

VBAT Backup domain Temperature

V08CAP thresholds
pwr_wkup
V08CAP
VDDA18AON pwrds
System supply thresholds
VDDA18PMU VDDCORE
VDDSMPS monitor
SMPS
VLXSMPS step-down
converter
VFBSMPS Power
Voltage management
VSSSMPS scaling
VDDCORE

VSS EXTI
PWR_ON PWR control

exti_wkup
VDDA18ADC
VSSA Analog domain
VREF+
VREF-

WKUP[4:1] Wake-up Wake-up event

VDDIO2
VDDIO3
pwr_pvd_wkup Wake-up event
VDDIO4 PVD and PVM
VDDIO5 pwr_pvm_x_wkup[5:0] Wake-up event

VDD33USB

MSv70447V3

13.3.1 PWR pins and internal signals

Table 51 lists the PWR inputs and output signals connected to package pins or balls, while
Table 52 shows the internal PWR signals.

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Table 51. PWR input/output signals connected to package pins or balls

Pin name Signal type Description

VDD Input Main I/O and VDD domain supply input

VDDA18AON Input Main analog supply input
VBAT Input Backup battery supply input
VDDA18PMU Input Step-down converter analog supply input
VDDSMPS Input Step-down converter supply input
VLXSMPS Output Step-down converter supply output
VFBSMPS Input Step-down converter feedback voltage sense
VSSSMPS Input Step-down converter ground
V08CAP Input/output Digital backup domain supply
VDDCORE Input Core domain supply
VDDA18ADC Input ADC analog supply
VREF+, VREF- Input/output External reference voltage for ADCs
VDDIO2 Input Independent I/O supply 2 (PO[5:0] and PP[15:0]), usually for XSPI1M_P1 (XSPI)
VDDIO3 Input Independent I/O supply 3 (PN[12:0])., usually for XSPI1M_P2 (XSPI)
VDDIO4 Input Independent I/O supply 4 (PC[1], PC[12:6] and PH[2,9]), usually for eMMC
VDDIO5 Input Independent I/O supply 5 (PC[0], PC[5:2] and PE[4]), usually for SD-Card.
VDD33USB Input USB HS PHYs and USB Type C PHY 3V3 supply input
VDDA18USB Input USB HS PHYs analog supply input
VDDA18PLL Input PLL analog supply
VDDCSI Input CSI PHY digital supply input
VDDA18CSI Input CSI PHY analog 1v8 supply input
VSS Input Main ground
VSSA Input Analog ground
PWR_ON Output Step-down converter or core supply enable output
NRST Input/output System reset, can be used to provide reset to external devices
PDR_ON Input Power-down reset enable
WKUPx Input Wake-up pins
PWR_CSLEEP Output MCU in Sleep mode
PWR_CSTOP Output MCU in Stop modes

Table 52. PWR internal input/output signals

Signal name Signal type Description

AHB Input/output AHB register interface

pwr_pvd_wkup Output Programmable voltage detector output

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Table 52. PWR internal input/output signals (continued)

Signal name Signal type Description

pwr_pvm_x_wkup[5:0] Output Peripheral voltage monitor output

pwr_por_rstn Output Power-on reset
pwr_bor_rstn Output Brownout reset
exti_wkup Input Wake-up request
pwr_wkup Output Bus matrix clock wake-up request (system clock)

Each of the four wake-up events, WKUPx, can be generated from four pins or internal
events.

Table 53. Wake-up source selection

Port Wake-up event

PA0 WKUP1
PA2 WKUP2
PC13 WKUP3
PD2 WKUP4

13.4 Power supplies

The system requires supply on VDD, VDDA18AON, VDDA18PMU, VDDSMPS, and
VDDCORE to start, and allows independent supplies for VDDA18ADC, VBAT, VDD33USB,
VDDIO2, VDDIO3, VDDIO4, and VDDIO5.
• VDD: external power supply for I/Os (can be 1.8 V or 3.3 V typical)
• VBAT: optional external power supply for backup domain when VDD is not present
(VBAT mode)
This power supply must be connected to VDD when no battery is used.
• VDDA18AON: external power supply for system analog such as reset, power
management, oscillators, and OTP
• VDDSMPS: external power supply for the SMPS step-down converter
This power supply must be tied to VSS when the SMPS is not used.
• VDDA18PMU: external analog power supply for the SMPS step-down converter
This power supply can be connected to VDDSMPS through an inductor-based filter.
It must be tied to VSS when the SMPS is not used.
• VLXSMPS: step-down converter supply output
• VFBSMPS: step-down converter sense feedback
• VSSSMPS: separate step-down converter ground
• VDDCORE: digital core domain supply, dependent on VDD supply
VDD must be present before VDDCORE. The VCORE is delivered by an external power
supply through VDDCORE pin, or by the SMPS step-down converter.
VDDCSI must usually be connected to VDDCORE.

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• VDDA18ADC: external analog power supply for ADCs and voltage reference buffers,
independent from any other supply
• VREF+: external reference voltage for ADCs, independent from any other supply
– When the voltage reference buffer is enabled, VREF+ and VREF- are delivered
by the internal voltage reference buffer.
– When the voltage reference buffer is disabled, VREF+ is delivered
by an independent external reference supply.
• VSSA: separate analog and reference voltage ground
• VDDIO2: external power supply for 22 I/Os (PO[5:0] and PP[15:0]), independent from
any other supply
• VDDIO3: external power supply for 13 I/Os (PN[12:0]), independent from any other
supply
• VDDIO4: external power supply for 10 I/Os (PC[1], PC[12:6], and PH[9,2]), independent
from any other supply
• VDDIO5: external power supply for six I/Os (PC[0], PC[5:2], and PE[4]), independent
from any other supply
• VDD33USB: external power supply for USB2 HS PHYs and USB Type-C® (CC1 and
CC2 pins), independent from any other supply
• VDDA18USB: external analog power supply for USB2 HS PHYs
• VDDA18CSI: external analog power supply for CSI D-PHY
• VDDA18PLL: external analog power supplies for PLLs
• VSS: common ground for all supplies except for step-down converter and analog
peripherals.
Note: Depending upon the operating power supply range, some peripherals can be used with
limited features and performance. For more details, refer to General operating conditions in
the datasheet.

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Figure 15. Power supply overview

VDDA18USB

VDDA18CSI
VDD33USB
VDDIO2
VDDIO4

VDDIO5

VDDIO3

VDDCSI
PC[1] PC[0] Port 1 Port 2
USB HS UCPD CSI
PC[12:6] PC[5:2] PO[5:0] PN[12:0]
PHYs I/Os PHY
PH[2,9] PE[4] PP[15:0]
I/Os I/Os
XSPIM I/Os VSS VSS VSS
VSS VSS VSS
Core domain (VCORE)
VDDCORE
VSS

I/O (CPU, system logic,

I/Os logic EXTI, peripherals, RAM)

VDD
VDDA18PMU
Retention domain
VDDSMPS
Step-down ITCM
VLXSMPS
converter
VFBSMPS DTCM

VSSSMPS
ITCM FLEX
VDD

LSI, WKUP, VRET

RET I/O
IWDG, BSEC,
I/Os logic
RIFSC
VSS
VDDA18AON OTP, HSE, HSI, MSI VSS

VDDA18PLL PLLs Backup domain

Power
V08CAP switch

VDD VSW Backup VBKP

VBAT regulator
Power switch

Backup
LSE, RTC, RAM
BKUP I/O
I/Os TAMP, backup
logic
registers, reset

VSS
VSS
VDDA18ADC Analog domain

VREFBUF ADCs
VREF+ VREF+
VREF- VREF-
VSSA
MSv70448V3

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By configuring the SMPS step-down converter, the supply configurations shown in

Figure 16 are supported for the VCORE domain.

Figure 16. System supply configurations

VDDA18PMU VDDA18PMU

VDD18 VDDSMPS VDDSMPS

VLXSMPS SMPS VLXSMPS SMPS

(on) (off)
VFBSMPS VFBSMPS

VSSSMPS VSSSMPS

VDDCORE
VCORE External supply VDDCORE
VCORE

VSS VSS

SMPS supply External supply (bypass)

MSv70449V2

The different supply configurations are controlled through SDEN in PWR_CR1 according to
Table 54. When the internal SMPS step-down converter is disabled, write SDEN bit in
PWR_CR1 to 0 as soon as possible

Table 54. Supply configuration control

SDEN

Supply
Description
configuration

Startup VCORE power domains are supplied from external source.

1
configuration SMPS step-down converter enabled at 0.8 V can be used to supply the VCORE.
SMPS step-down VCORE power domains are supplied from SMPS step-down converter according to VOS.
1
converter supply SMPS step-down converter power mode (MR, LP, off) follows system low-power modes.

SMPS step-down VCORE supplied from external source.

0
converter disabled SMPS step-down converter disabled, voltage monitoring still active.

13.4.1 System supply startup

The system startup sequence from power-on in different supply configurations is the
following (see Figure 16 for direct SMPS supply and external supply, respectively):

VCORE directly supplied from the SMPS step-down converter

1. When the system is powered on, the POR monitors VDD and VDDA18AON supplies.
Once the supplies are above the POR threshold level, the external voltage regulator
providing VDDA18PMU and VDDSMPS supplies is enabled via the PWR_ON signal.
2. The SMPS step-down converter is kept in reset as long as VDDA18PMU and VDDSMPS
are not stable.
3. Once VDDA18PMU and VDDSMPS supplies are above the Vdda18pmu_ok threshold level,
the SMPS step-down converter is taken out of reset, and the output level is set by
default at 0.8 V (VOS low). The system is kept in reset mode as long as VDDCORE is
stable.

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4. Once VDDCORE supply is above the Vddcore_ok threshold level, the system is taken
out of reset, and the HSI oscillator is enabled.
5. Once the oscillator is stable, the system is initialized: option bytes are loaded, and the
CPU starts in Run mode.

Figure 17. Device startup (VCORE supplied directly from SMPS step-down converter)

VDD
POR threshold

VDDA18AON
POR threshold

pwr_por_rstn

PWR_ON

VDDA18PMU / vdda18pmu_ok threshold

VDDSMPS

Vdda18pmu_ok
VOS low
VFBSMPS

VOS low vddcore_ok threshold

VCORE
tempo

Vcore_ok

Operating mode Power Wait

Reset Hardware system init Run
down oscillator

ck_sys

Direct
Supply configuration Default configuration SD
supply

SDEN X
(1) (2) (3) (4) (5)
MSv70450V3

When exiting Standby mode, the supply configuration is known by the system, as the
PWR_CR1 content is retained.

VCORE supplied in bypass mode (SMPS off)

The devices that feature the SMPS can be used in bypass mode.

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1. When the system is powered on, the POR monitors VDD and VDDA18AON supplies.
Once the supplies are above the POR threshold level, the external voltage regulator
providing the VDDCORE supply is enabled via the PWR_ON signal.
2. The system is kept in reset mode as long as VDDCORE is not stable.
3. Once VDDCORE supply is above the Vddcore_ok threshold level, the system is taken
out of reset, and the HSI oscillator is enabled.
4. Once the oscillator is stable, the system is initialized: option bytes are loaded, and the
CPU starts in Run mode. The software must disable SMPS bit clearing SDEN in
PWR_CR1.
Note: In SMPS off mode or bypass mode, reading SDEN returns 0. The SW must write 0 to SDEN
in PWR_CR1 register for the low power features to work properly.

Figure 18. Device startup (VCORE supplied from an external regulator)

VDD

POR threshold

VDDA18AON

POR threshold

pwr_por_rstn

PWR_ON

Vddcore_ok threshold
VDDCORE

tempo

Vcore_ok

Power Wait Hardware system

Operating mode down
Reset
oscillator init
Run

ck_sys

Supply configuration Default configuration Bypass mode

SDEN X
(1) (2) (3) (4)
MSv70451V2

13.4.2 Core domain

The VCORE core domain supply can be provided by the SMPS step-down converter, or by
an external supply (VDDCORE). VCORE supplies all the digital circuitries, except for the
backup domain and the retention domain in Standby mode. When a system reset occurs,

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the SMPS step-down converter is enabled to deliver 0.8 V. This allows the system to start
up in any supply configuration (see Figure 16).
After a power-on reset, the software must configure the used supply configuration in
PWR_CR1 before changing VOS in PWR_VOSCR, or the RCC sys_ck frequency. The
different system supply configurations are controlled as shown in Table 54.

SMPS step-down converter regulator

The SMPS requires an external coil to be connected between the VLXSMPS pin and (via a
capacitor) VSS. The converter can be used to supply directly the VCORE domain. It works in
three different power modes: main (MR), low-power (LP), or off.
The converter operating modes depend upon the system modes (Run, Stop, or Standby
mode), and are configured through the associated VOS and SVOS levels:
• Run mode
The SMPS step-down converter operates in MR mode, and provides full power to
the VCORE domain (core, memories, and digital peripherals). PWR_ON is set high.
The regulator output voltage can be scaled by software to different voltage levels
(VOS low and VOS high) that are configured through VOS in PWR_VOSCR . The
VOS voltage scaling is used to optimize the power consumption when the system is
clocked below the maximum frequency. By default, VOS low is selected after a system
reset. VOS can be changed on-the-fly to adapt to the required system performance.
• Stop mode
The SMPS step-down converter supplies the VCORE domain to retain the content of
registers and internal memories, and must be set in low-power mode. The voltage
regulator mode is selected through SVOS in PWR_CPUCR. In low-power mode, only
SVOS low and SVOS high scaling are allowed. Due to a lower voltage level for the
SVOS low, the Stop mode consumption can be further reduced.
• Standby mode
The SMPS step-down converter is off, and VCORE domains are powered down.
The content of registers and memories are lost except for the retention domain, and
the backup domain.
The PWR_ON signal is set low. The external regulator supplying VDDA18PMU and
VDDSMPS can be switched off.

13.4.3 PWR external supply

When VCORE is supplied from an external source (bypass mode), different operating modes
can be used, depending upon the system operating modes:
• In Run mode
The external source supplies full power to the VCORE domain. PWR_ON is set high.
The external source output voltage is scalable through different voltage levels
(VOS low and VOS high). Setting VOS in PWR_VOSCR has no effect on the external
supply. The application can use the register value to track the status of the external
supplied voltage, it is responsible to set properly the external supply voltage. Other
PWR_VOSCR register fields have default settings, and are "don't care" in external
supply.
• In Stop mode
The external source supplies VCORE domain to retain the content of registers and
internal memories. In low-power mode, only SVOS high scaling is allowed.

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• In Standby mode
The PWR_ON signal is set low, the external regulator is switched off, and the VCORE
domain is powered down. The content of registers and memories is lost except for the
retention domain and the backup domain.

13.4.4 Backup domain

To retain the content of the backup domain (RTC, backup registers, and backup RAM) when
VDD is turned off, the VBAT pin can be connected to an optional voltage supplied from a
battery or from another source.
The switching to VBAT is controlled by the power-down reset (PDR) embedded in the reset
block that monitors the VDD supply.

Warning: During tRSTTEMPO (temporization at VDD startup), or after a

PDR is detected, the power switch between VBAT and VDD
remains connected to VBAT.
During the startup phase, if VDD is established in less than
tRSTTEMPO (see the datasheet for the value of tRSTTEMPO), and
VDD > VBAT + 0.6 V, a current may be injected into VBAT
through an internal diode connected between VDD and the
power switch (VBAT).
If the power supply/battery connected to the VBAT pin cannot
support this current injection, it is strongly recommended to
connect an external low-drop diode between this power
supply and the VBAT pin.

When the VDD supply is present, the backup domain is supplied from VDD, to save VBAT
power supply battery life time. If no external battery is used in the application, it is
recommended to connect VBAT externally to VDD, and add a 100 nF external ceramic
capacitor between VBAT and VSS.
When the backup domain is supplied by VBAT (analog switch connected to VBAT),
the following pins are available:
• PC13, PC14, and PC15, which can be configured by RTC or LSE (see Section 61.3:
RTC functional description).
• PC13, PQ7 (TAMP_IN/OUT), and PD8, PH4 (only TAMP_IN) when they are configured
by the TAMP peripheral as tamper pins.

Accessing the backup domain

After reset, the backup domain (RCC_BDCR, RCC_RTC, TAMP registers, backup
registers, and backup RAM) is protected against possible unwanted write accesses.
To enable access to the backup domain, set DBP in PWR_DBPCR.
For more detail on RTC and backup RAM access, refer to Section 14: Reset and clock
control (RCC).

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Backup RAM (BKPSRAM)

The backup domain includes 8 Kbytes of BKPSRAM accessible in 32-, 16-, or 8-bit data
mode.
• In Run and Stop (SVOS high) modes, the BKPSRAM is supplied from VCORE supply.
• In Stop (SVOS low) mode, the BKPSRAM is supplied through the backup regulator in
VSW domain.
• In Standby and VBAT modes, the BKPSRAM can be supplied through the backup
regulator in VSW domain.
When the backup supply is enabled through BKPRBSEN in PWR_BDCR2, the BKPSRAM
content is retained even in Standby and/or VBAT mode.

Figure 19. Backup domain

VBAT
VSW
VDD
Backup domain
V08CAP

VDDCORE VBKP Backup

Backup I/Os
regulator

VCORE domain

Backup
RAM
interface
Backup

RTC LSE

MSv70452V1

13.4.5 Retention domain

The retention domain includes boot, OTP controller (BSEC), independent watchdog
(IWDG), resource isolation framework controller (RIFSC), I-TCM, D-TCM, and I-TCM
FLEXRAMs.
• In Run and Stop (SVOS high) modes, the retention domain is supplied from the
VCORE supply.
• In Stop (SVOS low) and Standby modes, the retention domain is supplied through the
backup regulator.
The content of the domain is retained in Standby mode (not powered in VBAT mode).

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Figure 20. Retention domain

VDD Retention domain

Backup supply
from backup
VDDCORE regulator

VCORE

Retention I/Os
VRET

Retention
interface
RIFSC LSI
BSEC IWDG
I-TCM/
D-TCM I-TCM
RAMs FLEX
MEM

VDDA18AON OTP

MSv70453V1

I-TCM and D-TCM RAMs

The retention domain includes 64 + 128 K bytes (instruction/data) of TCM for Cortex-M55.
• In Run and Stop (SVOS high) modes, I-TCM, and D-TCM memories are supplied from
the VCORE supply.
• In Stop (SVOS low) mode, I-TCM, and D-TCM memories are supplied through the
backup regulator in the VSW domain.
• In Standby mode, I-TCM and D-TCM memories can be supplied through the backup
regulator in the VSW domain.
When the backup supply is enabled by TCMRBSEN in PWR_CR4, the content of these
memories is retained even in Standby mode.

I-TCM FLEXMEM
The retention domain includes 64 Kbytes of extended TCMs for the Cortex-M55 (the I-TCM
FLEXMEM extension). This memory can be allocated to I-TCM or to system AXI RAM (see
Section 10: SRAM configuration controller (RAMCFG) for details
• In Run and Stop (SVOS high) modes, the I-TCM FLEXMEM is supplied from the
VCORE supply.
• In Stop (SVOS low) mode, the I-TCM FLEXMEM is supplied through the backup
regulator in the VSW domain.
• In Standby mode, the I-TCM FLEXMEM can be supplied through the backup regulator
in the VSW domain.
When the backup supply is enabled by t TCMFLXRBSEN in PWR_CR4, the content of
these memories is retained even in Standby mode.

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13.4.6 Analog supply

Separate VDDA18ADC analog supply
The analog supply domain is powered by dedicated VDDA18ADC and VSSA pins that allow
the supply to be filtered and shielded from noise on the PCB, thus improving ADC
conversion accuracy:
• The analog supply voltage input is available on a separate VDDA18ADC pin.
• An isolated supply ground connection is provided on VSSA pin.

Analog reference voltage VREF+/VREF-

To achieve better accuracy low-voltage signals, the ADC has a separate reference voltage,
available on VREF+ pin. The user can connect a separate external reference voltage
on VREF+.
VREF+ controls the highest voltage, represented by the full scale value. The lower voltage
reference (VREF-) must be connected to VSSA.
When enabled by ENVR in VREFBUF_CSR, VREF+ is provided from the internal voltage
reference buffer, which can also deliver a reference voltage to external components through
VREF+/VREF- pins.
When the internal voltage reference buffer is disabled by ENVR, VREF+ is delivered by an
independent external reference supply voltage.

13.5 Power supply supervision

Power supply level monitoring is available on the following supplies:
• VDD/VDDA18AON via POR/PDR (see Section 13.5.1), BOR (see Section 13.5.2), and
PVD monitor (see Section 13.5.6)
– The POR/PDR monitoring flag is available from PORRSTF in the RCC.
– The BOR monitoring flag is available from BORRSTF in the RCC.
– The PVD monitoring flag is available from PVDO in PWR_CR2. In addition, an
interrupt and wake-up can be generated via the EXTI.
• VDDA18PMU via Vdda18pmu_ok, which keeps in reset the SMPS, as long as the level is
not correct.
– The VDDA18PMU monitoring has no flags.
• VBAT via VBAT threshold (see Section 13.5.8)
– The V08CAP monitoring flags are available from V08CAPH and V08CAPL in
PWR_BDCR1. In addition, an interrupt and wake-up can be generated via EXTI.
• VDDCORE via Vcore_ok, which keeps the VCORE domain in reset as long as the level is
not correct (see Section 13.5.3).
– The VDDCORE ok monitoring flag is available from SBF in PWR_CPUCR when
exiting the Standby mode.
• VDDCORE via VCORE threshold (see Section 13.5.5)
– The VDDCORE monitoring flags are available from VCOREH and VCOREL in
PWR_CR3. In addition, an interrupt and wake-up can be generated via EXTI.
• VDDIO2, VDDIO3, VDDIO4, VDDIO5, VDD33USB, VDDA18ADC via peripheral voltage monitor
(see Section 13.5.7)

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• VSW via rst_vsw, which keeps VSW domain in reset mode as long as the level is not the
correct one
– The VSW monitoring has no flag. VSW registers reset value can be used.
• VFBSMPS can be monitored via VOSRDY in PWR_VOSCR.

13.5.1 Power-on reset (POR)/power-down reset (PDR)

The system has an integrated POR/PDR circuitry that ensures proper start-up operation.
The system remains in reset mode when VDD and VDDA18AON are below a specified VPOR
threshold, without the need for an external reset circuit. Once these supply levels are above
the VPOR threshold, the system is taken out of reset (see Figure 21). For more details
concerning these thresholds, refer to the electrical characteristics in the datasheet.
The POR/PDR generate also an application reset (NRST).
The PDR can be enabled/disabled by the device PDR_ON input pin.

Figure 21. POR/PDR waveform

VDD / VDDA18AON

POR

Hysteresis PDR

Temporisation TRSTTEMPO

pwr_por_rstn
MSv70454V1

1. For thresholds and hysteresis values, refer to the datasheets.

13.5.2 Brownout reset (BOR)

During power-on, the brownout reset (BOR) keeps the system under reset until the VDD
supply voltage reaches the specified VBOR threshold.
The VBOR threshold is configured through system option bytes. By default, the BOR is off.
The selection of another BOR threshold takes effect only after the device has loaded the
option bytes. The following programmable VBOR thresholds can be selected:
• BOR off (VBOR0): reset threshold level above 1.67 V
• BOR level 1 (VBOR1): reset threshold level above 2.7 V
For more details on these thresholds, refer to the electrical characteristics in the datasheet.
When the BOR is enabled and the VDD supply voltage drops below the selected VBOR
threshold, an application reset (NRST) is generated.

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The BOR can be disabled by programming the system option bytes. To disable it, VDD must
have been higher than VBOR0 to start the system option byte programming sequence. The
power-down is then monitored by the PDR (see Section 13.5.1).

Figure 22. BOR thresholds

VDD

BORrise

Hysteresis
BORfall

pwr_bor_rstn
MSv70455V1

1. For thresholds and hysteresis values, refer to the datasheets.

13.5.3 Vdda18pmu_ok reset

The system integrates a circuit for proper startup of the integrated SMPS.
The SMPS remains in reset mode when VDDA18PMU is below the threshold Vdda18pmu_ok.
Once the VDDA18PMU supply level is above Vdda18pmu_ok, the SMPS is taken out of reset,
and the output level is set by default at 0.8 V (VOS low). For more details concerning this
reset threshold, refer to the electrical characteristics in the datasheet.

Figure 23. Vdda18pmu_ok reset threshold

VDDA18PMU

VDDA18PMURise

Hysteresis
VDDA18PMUFall

Vdda18pmu_ok
MSv70456V1

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13.5.4 Vddcore_ok reset

The system has in integrated circuit for proper startup of the VCORE domain.
The VCORE domain remains in reset mode when VDDCORE is below the operation threshold
Vddcore_ok. Once the VDDCORE supply level is above Vddcore_ok, the VCORE domain is
taken out of reset. For more details concerning this reset threshold, refer to the electrical
characteristics in the datasheet.
When SVOS is cleared in PWR_CPUCR, the VDDCORE supply level can be lowered
in Stop mode (SVOS low).

Figure 24. Vddcore_ok reset thresholds

VDDCORE

VDDCORERise
Hysteresis
VDDCOREFall

T
Temporisation

Vddcore_ok
MSv70457V1

13.5.5 VDDCORE monitoring

The system has a detection circuitry that detects if the VDDCORE supply voltage is below or
above the operating range. The detection is done by comparing the VDDCORE with two
thresholds (high and low threshold). The level of the low threshold can be selected by
VCORELLS in PWR_CR3. The high level is fixed.
VCOREH and VCOREL flags are available in PWR_CR3, to indicate if VDDCORE is higher or
lower than the thresholds. VCOREH and VCOREL flags are available on tamper signals but
also connected to the EXTI, and can generate an interrupt if enabled through
EXTI registers.
The detection is enabled by setting VCOREMONEN in PWR_CR3.
The VDDCORE voltage thresholds, when enabled, are not available in Stop, Standby, and
VBAT modes. For more details concerning vcore_thr_high and vcore_thr_low thresholds,
refer to the electrical characteristics in the datasheet.

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Figure 25. VDDCORE monitoring

VDDCORE

vcore_thr_high

Vcore_thr_low

T
VCOREL

VCOREH
MSv70458V1

13.5.6 Programmable voltage detector (PVD)

The PVD can be used to monitor a voltage level on PVD_IN pin. The voltage level on
PVD_IN is compared to the internal VREFINT level. The PVD is enabled by setting PVDEN
in PWR_CR2. The PVD is not available in Standby mode.
A PVDO flag is available in PWR_CR2 to indicate if the voltage level on PVD_IN is higher or
lower than the PVD threshold. This event is internally connected to the EXTI, and can
generate an interrupt if enabled through the EXTI registers.
The PVDO output interrupt can be generated when the voltage level on PVD_IN drops
below the PVD threshold, and/or when the voltage level on PVD_IN rises above the PVD
threshold depending on EXTI rising/falling edge configuration. As an example, the service
routine can perform emergency shutdown tasks.

Figure 26. PVD thresholds

PVD_IN

PVDrise

Hysteresis PVDfall

PVDO

PVDEN

Software enable PDR reset

MSv70459V1

1. For thresholds and hysteresis values, refer to the datasheets.

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13.5.7 Peripheral voltage monitoring (PVM)

Only VDD is monitored by default, as it is the only supply required for all system-related
functions. The other supplies (VDDIO2, VDDIO3, VDDIO4, VDDIO5, VDD33USB, and
VDDA18ADC) can be independent from VDD, and can be monitored with six peripheral
voltages (PVM):
• VDDIO2VM monitors the PO[5:0] and PP[15:0] I/Os supply VDDIO2. VDDIO2RDY
indicates if VDDIO2 is higher or lower than the VIO2VM threshold.
• VDDIO3VM monitors the PN[12:0] I/Os supply VDDIO3. VDDIO3RDY indicates if
VDDIO3 is higher or lower than the VIO3VM threshold.
• VDDIO4VM monitors PC[1], PC[12:6], and PH[9,2] I/Os supply VDDIO4. VDDIO4RDY
indicates if VDDIO4 is higher or lower than the VIO4VM threshold.
• VDDIO5VM monitors the PC[0], PC[5:2] and PE[4] I/Os supply VDDIO5. VDDIO5RDY
indicates if VDDIO5 is higher or lower than the VIO5VM threshold.
• USB33VM monitors the USB supply VDD33USB. USB33RDY indicates if VDD33USB is
higher or lower than the VUSB33VM threshold.
• AVM monitors the ADC supply VDDA18ADC. ARDY indicates if VDDA18ADC is higher or
lower than the VAVM threshold.
For thresholds and hysteresis, refer to the datasheet.
Each PVM output is connected to an EXTI line, and can generate an interrupt if enabled
through the EXTI registers. The EXTI_PVM_x output interrupt is generated when
the independent power supply drops below the PVM threshold, and/or when it rises above
the PVM threshold, depending on EXTI line rising/falling edge configuration.
The PVM is not available in Standby mode.
The independent supplies (VDDIO2, VDDIO3, VDDIO4, VDDIO5, VDD33USB, and VDDA18ADC) are
not considered as present by default, and a logical and electrical isolation is applied to
ignore any information coming from the peripherals supplied by these dedicated supplies.
• If these supplies are shorted externally to VDD, the application must assume they are
available without enabling any peripheral voltage monitoring, and the power isolation
can be removed by setting the corresponding supply valid bits.
• If these supplies are independent from VDD, the PVM can be enabled to confirm
whether the supply is present or not.
The following sequence must be done before using the USB HS PHYs:
1. If VDD33USB is independent from VDD:
a) Enable the USB33VM by setting USB33VMEN in PWR_SVMCR3.
b) Wait for the USB33VM wake-up time.
c) Wait until USB33RDY is set in PWR_SVMCR3.
d) Optional: Disable the USB33VM for consumption saving.
2. Set USB33SV in PWR_SVMCR3 to remove the VDD33USB power isolation.
The following sequence must be done before using the analog-to-digital converters:
1. If VDDA18ADC is independent from VDD:
a) Enable the AVM by setting AVMEN in PWR_SVMCR3.
b) Wait for the AVM wake-up time.
c) Wait until ARDY is set in PWR_SVMCR3.
d) Optional: Disable the AVM for consumption saving.

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2. Set ASV in PWR_SVMCR3 to remove the VDDA18ADC power isolation.

GPIOs can work in the 1.8 V or 3.3 V power supply ranges. It is needed to select the supply
range of the I/Os before using them (the 3.3 V range is selected by default). The voltage
range configuration for VDD, VDDIO2, and VDDIO3 is retained in Standby mode.
The configuration can be retained for VDDIO4 and VDDIO5 in Standby mode when
VDDIO4VRSTBY is set in PWR_SVMCR1(and VDDIO5VRSTBY in PWR_SVMCR2). The
voltage range must not be retained if the supply range may change when exiting Standby
mode (SD card).
The following sequence must be done before using VDDIO4 I/Os:
1. If VDDIO4 is independent from VDD:
a) Enable the VDDIO4VM by setting VDDIO4VMEN in PWR_SVMCR1.
b) Wait for the VDDIO4VM wake-up time.
c) Wait until VDDIO4RDY is set in PWR_SVMCR1.
d) Optional: Disable the VDDIO4VM for consumption saving.
e) If VDDIO4 is in 1.8 V range: Set the VDDIO4 voltage range by setting
VDDIO4VRSEL in PWR_SVMCR1.
f) Optional: Retain VDDIO4VRSEL configuration by setting VDDIO4VRSTBY
in PWR_SVMCR1.
2. Set VDDIO4SV in PWR_SVMCR1 to remove the VDDIO4 power isolation.
Same sequence must be done for VDDIO5 I/Os.
The following sequence must be done before using VDDIO2 I/Os:
1. If VDDIO2 is independent from VDD:
a) Enable the VDDIO2VM by setting VDDIO2VMEN in PWR_SVMCR3.
b) Wait for the VDDIO2VM wake-up time.
c) Wait until VDDIO2RDY is set in PWR_SVMCR3.
d) Optional: Disable the VDDIO2VM for consumption saving.
e) If VDDIO2 is in 1.8 V range: Set the VDDIO2 voltage range by setting
VDDIO2VRSEL in PWR_SVMCR3.
2. Set VDDIO2SV in PWR_SVMCR3 to remove the VDDIO2 power isolation.
Same sequence must be done for the VDDIO3 I/Os.

13.5.8 Battery voltage thresholds

The battery voltage VBAT supply can be monitored by comparing it with two threshold levels:
V08CAPhigh and V08CAPlow. V08CAPH and V08CAPL flags in PWR_BDCR1 indicate if VSW
is higher or lower than the thresholds.
The VBAT supply monitoring can be enabled/disabled via MONEN in the PWR_BDCR1.
When V08CAP monitoring is enabled, the battery voltage thresholds increase the power
consumption. As an example, VSW levels monitoring can be used to trigger a tamper event
for an over or under voltage of the RTC power supply domain (available in VBAT mode).
The battery voltage thresholds, when enabled, are also available in Standby and
VBAT modes.
V08CAPH and V08CAPL are connected to RTC tamper signals (see Section 61: Real-time
clock (RTC).

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Note: When the device does not operate in VBAT mode, the battery voltage monitoring checks the
VDD level. When VDD is available, VSW is connected to VDD through the internal power
switch (see Section 13.4.4).

Figure 27. V08CAP thresholds

VBAT

V08CAPhigh

V08CAPlow

V08CAPH

V08CAPL
MSv70460V2

1. For thresholds and hysteresis values, refer to the datasheets.

13.5.9 Temperature thresholds

The junction temperature can be monitored by comparing it with two threshold levels,
TEMPhigh and TEMPlow. TEMPH and TEMPL flags in PWR_BDRC1 indicate whether the
device temperature is higher or lower than the thresholds. The temperature monitoring can
be enabled/disabled via MONEN in PWR_BDRC1. When the temperature monitoring
is enabled, the temperature thresholds increase the power consumption. As an example,
threshold levels can be used to trigger a routine to perform temperature control tasks.
The temperature thresholds, when the monitoring is enabled, are also available in Standby
and VBAT modes.
TEMPH and TEMPL wake-up interrupts are available on the RTC tamper signals
(see Section 61: Real-time clock (RTC)).

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Figure 28. Temperature thresholds

Temperature

TEMPhigh

TEMPlow

TEMPH

TEMPL
MSv70461V1

1. For thresholds and hysteresis values, refer to the datasheets.

13.6 Power management

The power management block controls the VCORE supply in accordance with the system
operation modes (see Section 13.6.1).
The device power domains can operate in one of the following operating modes:
• Run (power on, clock on)
• Sleep (power on, core clock stopped, peripherals kept running)
• Stop (power on, clock off)
• Standby (power off, clock off)
The VCORE supply level follows the system operating mode (Run, Stop, or Standby mode).
The following voltage scaling features allow the power to be controlled with respect to the
required system performance (see Table 55):
• To obtain a given system performance, the corresponding voltage scaling must be set
in accordance with the system clock frequency. To do this, configure VOS bits to the
Run mode voltage scaling.
• To obtain the best trade-off between power consumption and latency when exiting Stop
mode, configure SVOS bit to Stop mode voltage scaling.

13.6.1 Operating modes

Several system operating modes are available to tune the system according to the
performance required (when the CPU does not need to execute code, and waits for an
external event). The user must select the operating mode that gives the best compromise
between low power consumption, short start-up time, and available wake-up sources.
The operating modes are used to control the clock distribution to the different system
blocks, and to power them.
In Run mode, the power consumption can be reduced by one of the following means:

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• Lower the system performance by slowing down the system clocks, and reducing
the VCORE supply level through VOS voltage scaling bit.
• Gate the clocks to APBx and AHBx peripherals when they are not used,
through PERxEN bits.

Table 55. Operating mode summary

System oscillator

ON (SVOS low) ON (SVOS high) ON (VOS low/high) Voltage regulator

Peripheral clock
System clock

CPU clock

PWR_ON
System Entry Wake-up

ON
Run - -

ON(1)
ON

ON
WFI or return
Sleep
from ISR or WFE(2)

ON/OFF(3)
SVOS + SLEEPDEEP +

ON/OFF(5)
Stop SVOS WFI or return from ISR, 1
high WFE, or wake-up source See Table 56
cleared(4)

OFF

OFF
SLEEPDEEP + WFI or
Stop SVOS return from ISR, WFE, or
OFF

OFF
low wake-up source
cleared(3)

WKUP pins rising or falling edge, RTC

PDDS + SLEEPDEEP +
alarm (alarm A or alarm B), RTC
WFI or return from ISR,
OFF

OFF

OFF

OFF

OFF
Standby wake-up event, RTC tamper events, 0(6)
WFE, or wake-up source
RTC timestamp event, external reset in
cleared(3)
NRST pin, IWDG reset
1. The clock is gated in the core in Sleep mode.
2. WFI = wait for interrupt, ISR = interrupt service routine, WFE = wait for event.
3. The CPU subsystem peripherals that have a PERxLPEN bit, operate accordingly.
4. When the CPU is in Stop mode, the last EXTI wake-up source must be cleared by software.
5. When HSI or MSI is used, the state is controlled by HSISTOPEN and MSISTOPEN, otherwise the system oscillator is off.
6. A guaranteed minimum PWR_ON pulse low time can be defined by POPL bits in PWR_CR1.

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Table 56. Functionalities depending on system operating mode

Stop mode Stop mode Standby
SVOS high SVOS low mode

Wake-up capability

Wake-up capability

Wake-up capability

VBAT mode
Run mode
Peripheral(1)
- - -

CPU Y R - R - - - -
NPU O O - R - - - -
Debug O O O R - - - -
ROM memory Y R - R - - - -
RAMCFG O R - R - - - -
I-TCM O R - R - R - -
I-TCM FLEXMEM O R - R - R - -
D-TCM O R - R - R - -
AXISRAM1 O R - R - R(2) - -
AXISRAMx (x = 2, 3, 4) O O - R - - - -
I-TCM FLEXMEM extension O O - R - R(3) - -
D-TCM FLEXMEM extension O O - R - - - -
CACHEAXI O O - R - - - -
VENCRAM O O - R - - - -
GPU RAM O O - R - - - -
BKPSRAM O R - R - O - O
AHBSRAMx (x = 1, 2) O O - R - - - -
XSPIx (x = 1, 2, 3) O R - R - - - -
XSPIM O R - R - - - -
MCEx (x = 1, 2, 3, 4) O R - R - - - -
FMC O R - R - - - -
Backup registers Y R - R - R - R
Brownout reset (BOR) Y Y Y Y Y Y Y -
Programmable voltage detector (PVD) O O O O O - - -
Peripheral voltage monitor (PVM) O O O O O - - -
V08CAPH/V08CAPL monitoring O O O O O O O O
TEMPH/TEMPL monitoring O O O O O O O O
GPDMA1 O R - R - - - -
HPDMA1 O R - R - - - -

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Table 56. Functionalities depending on system operating mode (continued)

Stop mode Stop mode Standby
SVOS high SVOS low mode

Wake-up capability

Wake-up capability

Wake-up capability

VBAT mode
Run mode
Peripheral(1)
- - -

High-speed internal (HSI) O O - - - - - -

High-speed external (HSE) O - - - - - - -
Low-speed internal (LSI) O O - O - O - -
Low-speed external (LSE) O O - O - O - O
Multi-speed internal (MSI) O O - - - - - -
HSE CSS (clock security system) O - - - - - - -
LSE CSS O O O O O O O O
RTC/auto wake-up O O O O O O O O
TAMP, number of tamper pins 7 7 O 4 O 4 O 4
USB1HS O R O R - - - -
USB2HS O R O R - - - -
UCPD1 O R O R - - - -
SDMMCx (x = 1, 2) O R - R - - - -
FDCAN O R - R - - - -
MDIOS O R O R - - - -
ETH1 O R O R - - - -
LPUART1 O O O R - - - -
U(S)ARTx (x = 1 to 10) O O O R - - - -
I2Cx (x = 1 to 4) O O O R - - - -
I3Cx (x = 1, 2) O O O R - - - -
SPIx (x = 1 to 6) O O O R - - - -
SAIx (x = 1, 2) O R - R - - - -
ADF1 O O O R - - - -
MDF1 O O O R - - - -
DCMI O R - R - - - -
PSSI O R - R - - - -
DCMIPP O R - R - - - -
GPU O R - R - - - -
DMA2D O R - R - - - -

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Table 56. Functionalities depending on system operating mode (continued)

Stop mode Stop mode Standby
SVOS high SVOS low mode

Wake-up capability

Wake-up capability

Wake-up capability

VBAT mode
Run mode
Peripheral(1)
- - -

GFXTIM O R - R - - - -
GFXMMU O R - R - - - -
JPEG O R - R - - - -
VENC O R - R - - - -
LTDC O R - R - - - -
ADCx (x = 1, 2) O R - R - - - -
VREFBUF O R - R - - - -
DTS O R O R - - - -
TIMx (x = 1 to 18) O R - R - - - -
LPTIMx (x = 1 to 5) O O O R - - - -
IWDG O O O O O O O -
WWDG O R - R - - - -
RNG O R - R - - - -
SAES O R - R - - - -
CRYP O R - R - - - -
HASH O R - R - - - -
CRC O R - R - - - -
O O
GPIOs O O O O O -
4 pins 4 pins
1. Legend: Y = Yes (enable). O = Optional (disable by default. Can be enabled by software). R = data/state retained.
-= not available.
2. Only the first 80 Kbytes can optionally be retained (see Section 10: SRAM configuration controller (RAMCFG) for details).
3. Only the first 64 Kbytes can optionally be retained (see Section 10: SRAM configuration controller (RAMCFG) for details).

Debug mode
By default, the debug connection is lost if the application puts the MCU in Stop or Standby
mode while debug features are used (the Cortex-M55 core is no longer clocked or
powered).
However, by setting some configuration bits in DBGMCU control registers, the software can
be debugged even when using the low-power modes extensively. For more details, refer to
Debug and low-power modes.

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13.6.2 Voltage scaling

The VCORE domain is supplied from a single voltage regulator that supports voltage scaling
with the following features:
• Run mode voltage scaling
– VOS low
– VOS high
• Stop mode voltage scaling
– SVOS low
– SVOS high
For more details on voltage scaling values, refer to the product datasheets.
When using the internal SMPS step-down converter, after reset, the system starts on the
lowest Run mode voltage scaling (VOS low). The voltage scaling can be changed on-the-fly
by programming VOS in PWR_VOSCR, according to the required system performance.
Before entering Stop mode, the software can preselect the SVOS level in PWR_CPUCR.
The Stop mode voltage scaling for SVOS low and SVOS high also sets the voltage regulator
in low-power mode, to further reduce power consumption.
When exiting Stop mode, the MCU is in Run mode same range as before entering Stop
mode. When exiting Standby mode, the Run mode voltage scaling is reset to the default
VOS low value.
In Standby mode, the VCORE supply is switched off.

Figure 29. VCORE voltage scaling versus system power modes

Reset
Wake-up reset

Main VOS low Main VOS high

Wake-up Wake-up
Wake-up
Run

Stop Stop Stop Stop Software Run mode

Stop mode
LP SVOS low LP SVOS high
Standby mode
Stop

Standby Standby

Power down

Standby
MSv70462V1

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13.6.3 Power management examples

Example of VCORE voltage scaling behavior in Run mode
Figure 30 illustrates the following system operation sequence example:
1. After reset, the system starts from HSI with VOS low.
2. The system performance is then increased to a high-speed clock from the PLL
with voltage scaling VOS high. To do this:
a) Program the voltage scaling to VOS high.
b) Once the VCORE supply has reached the required level indicated by VOSRDY,
increase the clock frequency by enabling the PLL.
c) Once the PLL is locked, switch the system clock.
3. Reduce the system performance to HSI clock with voltage scaling VOS low. To do this:
a) Switch the clock to HSI.
b) Disable the PLL.
c) Decrease the voltage scaling to VOS low.
4. The system performance can then be increased to high-speed clock from the PLL.
To do this:
a) Program the voltage scaling to VOS high.
b) Once the VCORE supply has reached the required level indicated by VOSRDY,
increase the clock frequency by enabling the PLL.
c) Once the PLL is locked, switch the system clock.
When the system performance (clock frequency) is changed, VOS must be set accordingly.

Figure 30. Dynamic voltage scaling in Run mode

VOS high
VCORE
VOS low

VOS Low High Low High

VOSRDY

PLLxON

ck_sys

ck_hclk

Wait Wait Wait Wait Wait

Run Run Run Run
VOSRDY PLL VOSRDY VOSRDY PLL

Run from HSI Run from PLL Run from HSI Run from PLL

MSv70463V1

1. The status of the register bits at each step is shown in blue.

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Example of VCORE voltage scaling behavior in Stop mode

Figure 31 illustrates the following system operation sequence example:
1. The system runs from the PLL in high-performance mode (VOS high voltage scaling).
2. The CPU subsystem enters Stop mode, and the system enters Stop mode. The system
clock is stopped, and the hardware lowers the voltage scaling to the software
preselected SVOS low.
3. The CPU subsystem is then woken up. The system exits Stop mode, and the CPU
subsystem exits Stop mode. The hardware always sets the same voltage range as
before entering Stop mode, and waits for the requested supply level to be reached
before enabling the HSI clock. Once the HSI clock is stable, the system clock is
enabled and switch in Run mode under HSI clock.
4. The clock frequency can be increased by enabling the PLL. Once the PLL is locked,
the system clock can be switched.

Figure 31. Dynamic voltage scaling behavior in Stop mode

VOS high

VOS low
VCORE
SVOS low
VOS VOS high SVOS low VOS high

VOSRDY

exti_c_wkup

PLLnON

ck_sys

ck_hclk

Wait Wait
Run Stop Run Run
VOSRDY Wait PLL
HSI
Run from PLL Clock stopped Run from HSI Run from PLL

MSv70464V1

1. The status of the register bits at each step is shown in blue.

Example of VCORE voltage regulator and voltage scaling behavior

in Standby mode
Figure 32 illustrates the following system operation sequence example:
1. The system runs from the PLL in high-performance mode (VOS high voltage scaling).
2. The CPU subsystem deallocates all the peripherals, and the VCORE supply is
switched off. The system enters Standby mode. The PWR_ON signal request
VDDA18PMU and VDDSMPS supplies to be powered off. If needed, a guarantee minimum
PWR_ON pulse low time can be defined by POPL bits in PWR_CR1.
3. On a wake-up event, the external regulator suppling VDDA18PMU and VDDSMPS is
requested, via the PWR_ON signal. The system exits Standby mode. The hardware
sets the voltage scaling to the default VOS low, and waits for the requested supply level

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to be reached before enabling the default HSI oscillator. Once the HSI clock is stable,
the system clock is enabled.
4. In a next step, increase the system performance with the following:
a) The software first increases the voltage scaling to VOS high.
b) Before enabling the PLL, the software waits for the requested supply level to be
reached by monitoring VOSRDY.
c) Once the PLL is locked, the system clock can be switched.

Figure 32. Dynamic Voltage Scaling from Standby mode

PWR_ON

VCORE
VOS high

VOS low

SVOS low
0V

VOS VOS high Off VOS low VOS high

VOSRDY

exti_c_wkup

PLLxON

ck_sys

ck_hclk

Wait Wait
Run Standby Run Run
Wait VOSRDY PLL
Reset
HSI
Run from PLL Power down Run from HSI Run from PLL

MSv70465V1

1. The status of the register bits at each step is shown in blue.

13.7 Low-power modes

Several low-power modes are available to save power when the CPU does not need to
execute code (when waiting for an external event). The user must select the mode that
gives the best compromise between low power consumption, short start-up time, and
available wake-up sources:
• slowing down system clocks (see Section 14.6.6: System clocks)
• controlling individual peripheral clocks (see Section 14.6.11: Peripheral clock-gating
control)
• low-power modes
– Sleep (CPU clock stopped and still in Run mode)
– Stop (system clock stopped)
– Standby (system powered down)

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13.7.1 Slowing down system clocks

In Run mode, the speed of the system clocks sys[a,b,c,d]_ck can be reduced. For more
details, refer to Section 14.6.6: System clocks.

13.7.2 Controlling peripheral clocks

In Run mode, the peripherals bus clock can be stopped by configuring at any time PERxEN
in RCC_xxxxENR to reduce power consumption.
To reduce power consumption in Sleep mode, the individual peripheral clocks can be
disabled by configuring PERxLPEN bit in RCC_xxxxLPENR. For the peripherals still
receiving a clock in Sleep mode, their clock can be slowed down before entering
Sleep mode.
Example: For APB2 peripherals, the RCC register is RCC_APB2ENR, which contains bits
like SPI4EN or SAI1EN.

13.7.3 Entering low-power modes

CPU subsystem Sleep and Stop modes are entered by the device when executing WFI or
WFE instructions, or when SLEEPONEXIT is set on return-from-ISR in the Cortex-M55
System Control register.
The system can enter Stop or Standby mode when all EXTI wake-up sources are cleared.

13.7.4 Exiting low-power modes

The CPU subsystem exits Sleep mode through any interrupt or event; depending on how
the low-power mode was entered:
• If the WFI instruction or return from ISR was used to enter the low-power mode,
any peripheral interrupt acknowledged by the NVIC can wake up the system.
• If the WFE instruction is used to enter the low-power mode, the CPU exits the
low-power mode as soon as an event occurs. The wake-up event can be generated by:
– an NVIC IRQ interrupt
When SEVONPEND = 0 in the Cortex-M55 System Control register, the interrupt
must be enabled in the peripheral control register, and in the NVIC.
When the MCU resumes from WFE, the peripheral interrupt pending bit and the
NVIC peripheral IRQ channel pending bit in the NVIC interrupt clear pending
register, have to be cleared. Only NVIC interrupts with sufficient priority wake up
and interrupt the MCU.
When SEVONPEND = 1 in the Cortex-M55 System Control register, the interrupt
must be enabled in the peripheral control register and optionally in the NVIC.
When the MCU resumes from WFE, the peripheral interrupt pending bit and, when
enabled, the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear
pending register) have to be cleared.
All NVIC interrupts wake up the MCU, even the disabled ones.
Only enabled NVIC interrupts with sufficient priority wake-up and interrupt
the MCU.
– an event
An EXTI line must be configured in event mode. When the CPU resumes from
WFE, it is not necessary to clear the EXTI interrupt pending bit or the NVIC IRQ

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channel pending bit, as pending bit corresponding to the event line is not set.
The interrupt flag may have to be cleared in the peripheral.
The CPU subsystem exits Stop mode by enabling an EXTI interrupt or event depending on
how the low-power mode was entered (see above).
The CPU subsystem exits Standby mode by enabling an external reset (NRST pin), an
IWDG reset, an enabled WKUPx pin, or an RTC event.
Program execution restarts as after a system reset by fetching the vector tables in
SYSCFG_INITSVTORCR and SYSCFG_INITNSVTORCR registers.
The default boot address can be changed to allow a fast restart on TCM when exiting a low
power mode. The content of the vector table registers is maintained in Standby mode.

13.7.5 Sleep mode

The Sleep mode applies only to the CPU subsystem. In Sleep mode, the CPU clock
is stopped. The CPU subsystem peripheral clocks operate according to the values of
PERxLPEN bits in RCC_xxxxLPENR.

Entering Sleep mode

This mode is entered according to Section 13.7.3, when SLEEPDEEP bit in Cortex-M55
System Control register is cleared. Refer to Table 57 for details on how to enter Sleep
mode.

Exiting Sleep mode

The Sleep mode is exited according to Section 13.7.4. Refer to the table below for more
details on how to exit Sleep mode.

Table 57. Sleep mode

Sleep mode Description

WFI or WFE while:

– SLEEPDEEP = 0 (refer to the Cortex-M55 System Control register)
– CPU NVIC interrupts and events cleared
Mode entry On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1 (refer to the Cortex-M55 System Control register)
– CPU NVIC interrupts and events cleared
If WFI or return from ISR was used for entry:
– any interrupt enabled in NVIC (see Table 135: STM32N6x7xx vector table)
If WFE was used for entry and SEVONPEND = 0:
Mode exit – any event (see Section 25: Extended interrupts and event controller (EXTI))
If WFE was used for entry and SEVONPEND = 1:
– any interrupt even when disabled in NVIC (see Table 135: STM32N6x7xx vector table) or any
event (see Section 25: Extended interrupts and event controller (EXTI)
Wake-up
None
latency

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13.7.6 Stop mode

The Stop mode applies to the MCU. In Stop mode, the CPU clock is stopped. All CPU
subsystem peripheral clocks are stopped too, and only the CPU subsystem peripherals
having a PERxLPEN bit operate accordingly.
In Stop mode, CPU subsystem peripherals having a kernel clock request can still request
their kernel clock. For the peripheral having a PERxLPEN bit, this bit must be set to be able
to request the kernel clock.
HSI or MSI can remain enabled in system Stop mode (HSISTOPEN and MSISTOPEN set in
RCC_STOPCR). After exiting Stop mode, the clock is quickly available as kernel clock for
peripherals. Other system oscillator sources are stopped in Stop mode, and require
a starting time after exiting Stop mode.
In Stop mode and SVOS high, peripherals using the LSI or LSE clock, and peripherals
having a kernel clock request, are still able to operate.
In system Stop mode, the following features can be selected to remain active by
programming individual control bits:
• independent watchdog (IWDG)
The IWDG is started by writing to its key register or by hardware option. Once started, it
cannot be stopped except by a reset (see Section 59: Independent watchdog (IWDG).
• real-time clock (RTC) that is configured via RTCEN in RCC_BDCR
• internal RC oscillator (LSI RC) that is configured via LSION in RCC_CSR
• external 32.768 kHz oscillator (LSE OSC) that is configured via LSEON in RCC_CSR.
• peripherals capable of running on the LSI or LSE clock
• peripherals having a kernel clock request
• internal RC oscillators (HSI and MSI) that are configured via HSISTOPEN and
MSISTOPEN in RCC_STOPCR
• The ADCs can also consume power during Stop mode, unless they are disabled before
entering this mode. To disable them, ADON bit in ADC_CR2 must be written to 0.
The selected SVOS low levels add an additional start-up delay when exiting from system
Stop mode.

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Entering Stop mode

The Stop mode is entered according to Section 13.7.3, when SLEEPDEEP bit in the
Cortex-M55 System Control register is set.
The low-power mode security filter must be disabled by system option bytes (NRST_STOP)
to enter Stop mode. Refer to Section 14.5.4: Low-power mode security reset (lpwr_rst) for
details.
Refer to the tables below for details on how to enter to Stop mode.

Table 58. Stop mode SVOS high

Stop mode Description

WFI or WFE while:

SLEEPDEEP = 1 (refer to the Cortex-M55 System Control register)
CPU NVIC interrupts and events cleared
All CPU EXTI wake-up sources cleared
Mode entry On return from ISR while:
SLEEPDEEP = 1 and
SLEEPONEXIT = 1 (refer to the Cortex-M55 System Control register)
CPU NVIC interrupts and events cleared
All CPU EXTI wake-up sources cleared
If WFI or return from ISR was used for entry:
EXTI interrupt enabled in NVIC (see Table 135: STM32N6x7xx vector table, for peripheral that are
not stopped or powered down)
If WFE was used for entry and SEVONPEND = 0:
Mode exit EXTI event: Refer to Section 25: Extended interrupts and event controller (EXTI) for peripheral that
are not stopped or powered down.
If WFE was used for entry and SEVONPEND = 1:
EXTI Interrupt even when disabled in NVIC: refer to Table 135: STM32N6x7xx vector table or EXTI
event: refer to Section 25: Extended interrupts and event controller (EXTI) for peripheral that are not
stopped or powered down.
Wake-up SMPS wake-up time from low-power mode (Run mode operating supply level to restore) +
latency EXTI and RCC wake-up synchronization (see Section 14: Reset and clock control (RCC))

Table 59. Stop mode SVOS low

Stop mode Description

WFI or WFE while:

SLEEPDEEP = 1 (refer to the Cortex-M55 System Control register)
CPU NVIC interrupts and events cleared
All CPU EXTI wake-up sources cleared
Mode entry
On return from ISR while:
SLEEPDEEP = 1 and SLEEPONEXIT = 1 (refer to the Cortex-M55 System Control register)
CPU NVIC interrupts and events cleared
All CPU EXTI wake-up sources cleared

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Table 59. Stop mode SVOS low (continued)

Stop mode Description

WKUP pins rising or falling edge, RTC alarm (alarm A and alarm B), RTC wake-up, tamper event,
Mode exit
timestamp event, external reset in NRST pin, IWDG reset
Wake-up SMPS wake-up time from low-power mode (Run mode operating supply level to restore) +
latency EXTI and RCC wake-up synchronization (see Section 14.5.12: Power-on and wake-up sequences)

To allow peripherals having a kernel clock request to operate in Stop mode, the system must
use SVOS high.
Note: Use a DSB instruction to ensure that outstanding memory transactions complete before
entering Stop mode.
Exiting Stop mode
The Stop mode is exited according to Section 13.7.4.
Refer to Table 58 and Table 59 for more details on how to exit Stop mode.
When exiting Stop mode, the MCU is in Run mode same range as before entering
Stop mode. The system starts on HSI or MSI.
STOPF status flag in PWR_CPUCR indicates that the system exited Stop mode.

I/O states in Stop mode

I/O pin configuration remains unchanged in Stop mode.

13.7.7 Standby mode

The Standby mode is used to achieve the lowest power consumption. Like Stop mode,
it is based on CPU subsystem Stop mode. However, the VCORE supply regulator is
powered off.
When the system enters Standby mode, the voltage regulator is disabled. The complete
VCORE domain is consequently powered off. PLLs, HSI oscillator, MSI oscillator, and HSE
oscillator are also switched off. SRAM and register contents are lost except for backup
domain registers (RTC registers, RTC backup register, and backup RAM), and the retention
domain (see Section 13.4.4 and Section 13.4.5).
In system Standby mode, the following features can be selected by programming individual
control bits:
• independent watchdog (IWDG)
The IWDG is started by programming its key register or by hardware option.
Once started, it cannot be stopped except by a reset (see Section 42.3 in IDWG).
• real-time clock (RTC) that is configured via RTCEN in RCC_BDCR
• internal RC oscillator (LSI RC) that is configured by LSION in RCC_CSR
• External 32.768 kHz oscillator (LSE OSC) that is configured by LSEON in RCC_CSR

Entering Standby mode

The Standby mode is entered according to Section 13.7.3, when PDDS is set to one
in PWR_CPUCR.

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The low-power mode security filter must be disabled by system option bytes
(nRST_STDBY) to enter in Standby mode. Refer to Section 14.5.4: Low-power mode
security reset (lpwr_rst) for details.
Refer to Table 61 for more details on how to enter Standby mode.

Exiting Standby mode

The Standby mode is exited according to Section 13.7.4.
The system exits Standby mode when an external reset (NRST pin), an IWDG reset, a
WKUP pin event, an RTC alarm, a tamper event, or a timestamp event is detected.
All registers are reset after waking up from Standby except for power control and status
registers:
• PWR_CR1, PWR_CR4, PWR_BDCR1, PWR_BDCR2
• SBF and PDDS in PWR_CPUCR
• VDDIO4VRSTBY and VDDIO4VRSEL in PWR_SVMCR1
• VDDIO5VRSTBY and VDDIO5VRSEL in PWR_SVMCR2
• VDDIOxVRSEL in PWR_SVMCR3
• PWR_WKUPCR, PWR_WKUPSR, PWR_WKUPEPR
A pad or watchdog reset during Standby mode causes the program execution to start as
after an application reset (rerun the boot ROM).
An enabled WKUP pin or an RTC event during Standby mode causes the program
execution to start as after a system reset (fetch from SYSCFG_INITSVTORCR)
The default boot address can be changed to allow a fast restart on TCM when exiting a low
power mode.
Refer to Table 61 for more details on how to exit Standby mode.
SBF in PWR_CPUCR indicates that the system has exited Standby mode.

Table 60. Standby and Stop flags

STOPF
SBF

Description

0 1 System has been in Stop mode.

1 0 System has been in Standby mode.

Table 61. Standby mode

Standby mode Description

The CPU subsystem is in Stop mode, and there is no active EXTI wake-up source.
Mode entry PDDS bit for select Standby
All WKUPF bits in PWR_WKUPSR cleared
WKUP pins rising or falling edge, RTC alarm (alarm A and alarm B), RTC wake-up, tamper
Mode exit
event, timestamp event, external reset in NRST pin, IWDG reset
Wake-up latency System reset phase (see Section 14.5.2: System and application resets (sys_rst, nreset_rstn))

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I/O states in Standby mode

In Standby mode, all I/O pins are high impedance without pull, except for:
• RESET and PWR_ON pins (still available)
• RTC_AF1 pin if configured for tamper, time stamp, RTC alarm out, or RTC clock
calibration out
• WKUP pins (if enabled): WKUP pin pull configuration can be defined through
WKUPPUPD bits in PWR_WKUPEPR

13.7.8 Power mode output pins

To help the debug, the following signals are available as alternate functions:
• PWR_CSLEEP
When set, PWR_CSLEEP indicates that the CPU is in Sleep mode:
– WFI or WFE has been executed, and CPU stops execution.
When cleared, PWR_CSLEEP indicates that the CPU is in Run mode.
• PWR_CSTOP
When set, PWR_CSTOP indicates that the device is in Stop mode, meaning that
the following conditions are true:
– WFI or WFE has been executed with CPU SLEEPDEEP = 1.
When cleared, PWR_CSTOP indicates that the device is in Run mode.

Table 62. Power mode output states versus MCU power modes
PWR_CSTOP PWR_CSLEEP MCU power modes(1)

X 0 Run mode (CPU executing)

0 1 Sleep mode (CPU sleep)
1 1 Stop mode (CPU SleepDeep)
1. PWR_CSLEEP and PWR_CSTOP are generated in the core domain, then they are not driven in
Standby mode.

13.8 PWR security and privileged protection

After any application reset or system reset, the PWR does not filter any access (default
configuration: nonsecure, any privileged) until the trusted agent has programmed the
security and privileged protection.
The PWR is able to protect register bits from being modified by nonsecure and unprivileged
accesses. The protection can be activated for the following features through
PWR_SECCFGR and PWR_PRIVCFGR:
• system supply configuration
• voltage scaling
• low-power mode
• wake-up (WKUP) pins
• voltage detection and monitoring
• VBAT mode

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Table 63 summarizes the security and privilege configuration bits.

Table 63. PWR register security overview

Secure/privilege Access
PWR register Description
configuration bit type(1)

PWR_SECCFGR.SEC[0]
PWR_CR1 RW/RWO System supply configuration
PWR_PRIVCFGR.PRIV[0]
PWR_SECCFGR.SEC[1]
PWR_CR2 RW Programmable voltage detector
PWR_PRIVCFGR.PRIV[1]
PWR_SECCFGR.SEC[2]
PWR_CR3 RW VDDCORE monitor
PWR_PRIVCFGR.PRIV[2]
PWR_SECCFGR.SEC[3] I-TCM, D-TCM, and I-TCM FLEX MEM
PWR_CR4 RW
PWR_PRIVCFGR.PRIV[3] low-power control

PWR_SECCFGR.SEC[4]
PWR_VOSCR RW Voltage scaling selection
PWR_PRIVCFGR.PRIV[4]
PWR_BDCR1 RW VBAT and temperature monitor
PWR_SECCFGR.SEC[5]
PWR_BDCR2 RW BKPSRAM low-power control
PWR_PRIVCFGR.PRIV[5]
PWR_DBPCR RW Disable backup domain write protection
PWR_SECCFGR.SEC[6]
PWR_CPUCR RW CPU power control
PWR_PRIVCFGR.PRIV[6]
PWR_SVMCR1 RW VDDIO4 peripheral voltage monitor
PWR_SVMCR2 PWR_SECCFGR.SEC[7] RW VDDIO5 peripheral voltage monitor
PWR_PRIVCFGR.PRIV[7]
VDDIO2, VDDIO3, VDD33USB, and VDDA18ADC
PWR_SVMCR3 RW
peripheral voltage monitor

PWR_WKUPCR W Wake-up pin x (x = 1 to 4) clear register

PWR_SECCFGR.WKUPSEC[x]
PWR_WKUPSR R Wake-up pin x (x = 1 to 4) status register
PWR_PRIVCFGR.WKUPPRIV[x]
(X = 1 to 4) Wake-up pin x (x = 1 to 4) enable and polarity
PWR_WKUPEPR RW
register
1. RW: read or write, R: read, W: write, RWO: read or write once.
RC_W0: read or clear by writing 0. Writing 1 has no effect on the bit value.

13.8.1 Secure/nonsecure access filtering

To enable the filtering access based on this attribute, the authorized master agent must set
SECx in PWR_SECCFGR related to the PWR feature.
When a register is configured as secure, read and write operations are allowed only by a
secure access. Nonsecure read or write accesses are denied (RAZ/WI).
An illegal secure access event is generated to the IAC (illegal access controller). There is no
bus error generated.
When a register is configured as nonsecure, read and write operations are allowed by both
secure and nonsecure accesses.

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13.8.2 Privileged/unprivileged access filtering

To enable the filtering access based on this attribute, the authorized master agent has to set
PRIVx in PWR_PRIVCFGR related to the PWR feature.
When a register is configured as privileged, read and write operations are only allowed
by a privileged access. Unprivileged read or write accesses are denied (RAZ/WI). An illegal
privileged access event is generated to the IAC. There is no bus error generated.
When a register is configured as unprivileged, read and write operations are allowed by both
privileged and unprivileged accesses.

13.9 PWR registers

The PWR registers can be accessed in word, half-word and byte format, unless otherwise
specified.

13.9.1 PWR control register 1 (PWR_CR1)

Address offset: 0x000
Reset value: 0x0000 002X
This register is not reset by wake-up from Standby mode and application reset (such as
NRST or IWDG), but only reset by VDD POR.
Secure restriction is defined by SEC0 in PWR_SECCFGR. Privileged restriction is defined
by PRIV0 in PWR_PRIVCFGR.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. POPL[4:0]
rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPDS0 MODE
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SDEN Res. Res.
8V _PDN
rw rw rwo

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:16 POPL[4:0]: pwr_on pulse low configuration.
These bits are set and cleared by software. They define the minimum guaranteed duration of
the pwr_on low pulse in Standby mode. The LSI oscillator is automatically enabled when
needed by the POPL pulse low configuration.
00000: No guaranteed minimum low time
00001: ~ 1 ms guaranteed minimum low time (1 x 32 LSI cycles)
00010: ~ 2 ms guaranteed minimum low time (2 x 32 LSI cycles)
...
11111: ~ 31 ms guaranteed minimum low time (31 x 32 LSI cycles)
Bits 15:6 Reserved, must be kept at reset value.
Bit 5 LPDS08V: SMPS low-power mode enable (SVOS high only)
This bit is used to keep the SMPS in PWM mode (MR) in Stop SVOS high.
0: SMPS low-power mode disabled
1: SMPS low-power mode enabled (high-efficiency mode) (default)

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Bit 4 MODE_PDN: Enables the pull down on output voltage during power-down mode
0: Pull-down disabled. The output is in high impedance during the shutdown (default).
1: Pull-down enabled
Bit 3 Reserved, must be kept at reset value.
Bit 2 SDEN: SMPS step-down converter enable
0: SMPS step-down converter disabled
1: SMPS step-down converter enabled (default)
This bit must be written as soon as possible after device start, and it can be written only once
after POR.
When in bypass mode, SMPS is off, reading this bit returns 0, Write it to 0 as soon as
possible after POR, or it will be impossible to enter low power modes. When SMPS is on,
reading this bit returns 1 (default).
Bits 1:0 Reserved, must be kept at reset value.

13.9.2 PWR control register 2 (PWR_CR2)

Address offset: 0x004
Reset value: 0x0000 0000
Reset on any system reset.
Secure restriction is defined by SEC1 in PWR_SECCFGR. Privilege restriction is defined
by PRIV1 in PWR_PRIVCFGR.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. PVDO Res. Res. Res. Res. Res. Res. Res. PVDEN
r rw

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 PVDO: Programmable voltage detect output
This bit is set and cleared by hardware. It is valid only if PVD is enabled by PVDEN.
0: Voltage level on PVD_IN is equal or higher than the internal VREFINT.
1: Voltage level on PVD_IN is lower than the internal VREFINT.
Note: The PVD is disabled in Standby mode, and after a system reset. For this reason, this bit
is equal to 0 after Standby and system reset.
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 PVDEN: Programmable voltage detector enable
This bit is read only when PVDL is set in SYSCFG_CBR (when PVDL is set, there is no bus
errors generated when writing this register).
0: PVD disabled
1: PVD enabled

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13.9.3 PWR control register 3 (PWR_CR3)

Address offset: 0x008
Reset value: 0x0000 0000
Reset on any system reset.
Secure restriction is defined by SEC2 in PWR_SECCFGR. Privilege restriction is defined
by PRIV2 in PWR_PRIVCFGR.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VCORE VCORE VCORE VCORE
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
H L LLS MONEN
r r rw rw

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 VCOREH: Monitored VDDCORE level above high threshold
0: VDDCORE level below high threshold level, or monitor disabled
1: VDDCORE level equal or above high threshold level
Bit 8 VCOREL: Monitored VDDCORE level above low threshold
0: VDDCORE level above low threshold level, or monitor disabled
1: VDDCORE level equal or below low threshold level
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 VCORELLS: VDDCORE voltage detector low-level selection
This bit selects the low-voltage threshold detected by the monitoring.
0: VDDCORE low-voltage threshold 1 selected (VOS low)
1: VDDCORE low-voltage threshold 2 selected (VOS high)
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 VCOREMONEN: VDDCORE monitoring enable
When this bit is set, the VDDCORE supply monitoring is enabled.
0: VDDCORE monitoring disabled
1: VDDCORE monitoring enabled

13.9.4 PWR control register 4 (PWR_CR4)

Address offset: 0x00C
Reset value: 0x0000 0000
This register is not reset by wake-up from Standby mode, but by any application reset
(such as NRST or IWDG). Access 6 wait states when writing this register.
When a system reset occurs during the register write cycle, the written data are not
guaranteed.
Secure restriction is defined by SEC3 in PWR_SECCFGR. Privilege restriction is defined
by PRIV3 in PWR_PRIVCFGR.

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCMFL
TCMR
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. XRBSE Res. Res. Res.
BSEN
N
rw rw

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 TCMFLXRBSEN: I-TCM FLEXMEM backup supply enable (used to maintain I-TCM FLEX
MEM content in Standby mode)
When this bit is set, the I-TCM FLEXMEM is supplied from backup regulator in Standby
mode. When this bit is reset, the I-TCM FLEXMEM can still be used in Run and Stop modes,
but its content is lost in Standby mode.
0: I-TCM FLEXMEM backup supply disabled
1: I-TCM FLEXMEM backup supply enabled in Standby mode
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 TCMRBSEN: I-TCM and D-TCM RAMs backup supply enable (used to maintain TCM RAMs
content in Standby mode)
When this bit is set, I-TCM and D-TCM RAMs are supplied from backup regulator in Standby
mode. When this bit is reset, I-TCM and D-TCM RAMs can still be used in Run and Stop
modes, but their content is lost in Standby mode.
0: I-TCM and D-TCM RAMs backup supply disabled
1: I-TCM and D-TCM RAMs backup supply enabled in Standby mode

13.9.5 PWR voltage scaling control register (PWR_VOSCR)

Address offset: 0x020
Reset value: 0x0002 0002
Reset on any system reset.
Secure restriction is defined by SEC4 bit in PWR_SECCFGR. Privilege restriction is defined
by PRIV4 bit in PWR_PRIVCFGR.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTVOS ACT
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RDY VOS
r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VOS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VOS
RDY
r rw

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Bits 31:18 Reserved, must be kept at reset value.

Bit 17 ACTVOSRDY: Voltage level ready bit for currently used ACTVOS
This bit is set to 1 by hardware when the SMPS step-down converter is disabled
in PWR_CR1.
0: Voltage level invalid, above or below current ACTVOS
1: Voltage level valid, at current ACTVOS
Bit 16 ACTVOS: VOS currently applied for VCORE voltage scaling selection
When the SMPS step-down converter is disabled, this bit is tied to 0, when the converter is
enabled, this bit reflects the last VOS value applied to the PMU.
0: VOS low
1: VOS high
Bits 15:2 Reserved, must be kept at reset value.
Bit 1 VOSRDY: VOS ready bit for VCORE voltage scaling output selection
When the internal SMPS step-down converter is used, this bit indicates that all features
allowed by the selected VOS can be used.
This bit is set to 1 by hardware when the SMPS step-down converter is disabled
in PWR_CR1.
0: Not ready, voltage level below VOS selected level
1: Ready, voltage level at or above VOS selected level
Bit 0 VOS: Voltage scaling selection according to performance
When the SMPS step-down converter is disabled, this bit has no impact on the external
supply voltage. It can be read/written to keep track of the external supply voltage setting.
When the SMPS step-down converter is enabled this bit controls the VCORE voltage level,
and is used to obtain the best trade-off between power consumption and performance:
– When increasing the performance, the voltage scaling must be changed before increasing
the system frequency.
– When decreasing performance, the system frequency must be decreased before changing
the voltage scaling.
0: VOS low level (default)
1: VOS high level
Note: Refer to electrical characteristics in the datasheet for more details.

13.9.6 PWR backup domain control register 1 (PWR_BDCR1)

Address offset: 0x024
Reset value: 0x0000 0000
This register is not reset by wake-up from Standby mode, application reset (such as NRST
or IWDG), or VDD POR, but it only by VSW POR and VSWRST.
This register must not be accessed when VSWRST in RCC_BDCR resets the VSW domain.
After reset, PWR_BDCR1 is write-protected. Prior to modifying its content, DBP must be set
in PWR_DBPCR to disable the write protection.
Secure restriction is defined by SEC5 in PWR_SECCFGR. Privilege restriction is defined
by PRIV5 in PWR_PRIVCFGR.

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
V08CA V08CA
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TEMPH TEMPL
PH PL
r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MONE
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
N
rw

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 TEMPH: Temperature level monitoring versus high threshold
0: Temperature below high threshold level
1: Temperature equal or above high threshold level
Bit 18 TEMPL: Temperature level monitoring versus low threshold
0: Temperature above low threshold level
1: Temperature equal or below low threshold level
Bit 17 V08CAPH: V08CAP level monitoring versus high threshold
0: VBAT level below high threshold level.
1: VBAT level equal or above high threshold level
Bit 16 V08CAPL: V08CAP level monitoring versus low threshold
0: VBAT level above low threshold level
1: VBAT level equal or below low threshold level
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 MONEN: VBAT and temperature monitoring enable
When this bit is set, the VBAT supply and temperature monitoring are enabled.
0: VBAT and temperature monitoring disabled
1: VBAT and temperature monitoring enabled

13.9.7 PWR backup domain control register 2 (PWR_BDCR2)

Address offset: 0x028
Reset value: 0x0000 0000
This register is not reset by wake-up from Standby mode, application reset (such as NRST
or IWDG), or VDD POR, but it is only reset by VSW POR and VSWRST.
This register must not be accessed when VSWRST in RCC_BDCR resets the VSW domain.
After reset, PWR_BDCR2 is write-protected. Prior to modifying its content, DBP must be set
in PWR_DBPCR register to disable the write protection.
Secure restriction is defined by SEC5 in PWR_SECCFGR. Privilege restriction is defined
by PRIV5 in PWR_PRIVCFGR.

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RM0486 Power control (PWR)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKPRB
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SEN
rw

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 BKPRBSEN: BKPSRAM backup supply enable (used to maintain BKPSRAM content
in Standby and VBAT modes).
When this bit is set, the backup ram is supplied from backup regulator in Standby and
VBAT modes. When this bit is reset, the backup ram can still be used in Run and Stop modes,
but its content is lost in Standby and VBAT modes.
0: BKPSRAM backup supply disabled
1: BKPSRAM backup supply enabled

13.9.8 PWR disable backup protection control register (PWR_DBPCR)

Address offset: 0x02C
Reset value: 0x0000 0000
Reset on any system reset
Secure restriction is defined by SEC5 in PWR_SECCFGR. Privilege restriction is defined
by PRIV5 in PWR_PRIVCFGR.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DBP
rw

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 DBP: Disable backup domain write protection
In reset state, all registers and SRAM in backup domain are protected against parasitic write
access. This bit must be set to enable write access to these registers.
0: Write access to backup domain disabled
1: Write access to backup domain enabled

13.9.9 PWR CPU control register (PWR_CPUCR)

Address offset: 0x030
Reset value: 0x0001 0000
See individual bits for reset condition. Access six wait states when writing this register.
When a system reset occurs during the register write cycle, the written data are not
guaranteed.

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Secure restriction is defined by SEC6 in PWR_SECCFGR. Privilege restriction is defined

by PRIV6 in PWR_PRIVCFGR.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SVOS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. SBF STOPF Res. Res. Res. Res. Res. Res. CSSF PDDS
r r rc_w1 rw

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 SVOS: System Stop mode voltage scaling selection
This bit is reset on any system reset.
0: SVOS low
1: SVOS high (default)
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 SBF: Standby flag
This bit is set by hardware and cleared only by a POR or by setting the CSSF bit.
0: System has not been in Standby mode.
1: System has been in Standby mode.
Bit 8 STOPF: Stop flag
This bit is set by hardware and cleared by any reset, or by setting the CSSF bit.
0: System has not been in Stop mode.
1: System has been in Stop mode.
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 CSSF: Clear Standby and Stop flags (always read as 0)
This bit is reset on any system reset.
0: No effect
1: When written, clears the CPU flags (STOPF, SBF).
Note: This bit is cleared to 0 by hardware.
Bit 0 PDDS: Power-down deepsleep selection
This bit is reset only by a VDD POR reset (not reset when exit standby mode). It allows the
CPU to define the deepsleep mode for the system.
0: Stop mode when device enters deepsleep
1: Standby mode when device enters deepsleep

13.9.10 PWR supply voltage monitoring control register 1 (PWR_SVMCR1)

Address offset: 0x034
Reset value: 0x0000 0000
See individual bits for reset condition. Access six wait states when writing this register.
When a system reset occurs during the register write cycle, the written data are not
guaranteed.
Secure restriction is defined by SEC7 in PWR_SECCFGR. Privilege restriction is defined
by PRIV7 in PWR_PRIVCFGR.

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VDDIO4 VDDIO4 VDDIO4
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
VRSTBY VRSEL RDY
rw rw r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VDDIO4 VDDIO4
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SV VMEN
rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 VDDIO4VRSTBY: VDDIO4 I/O voltage range Standby mode
When this bit is set, the VDDIO4VRSEL configuration is retained in Standby mode.
This bit must be set if the VDDIO4 is in 1v8 range in Standby mode, and when exiting Standby
mode. It must not be set when VDDIO4 is in 3v3 range in Standby mode, or when exiting
Standby mode. This bit is not reset by wake-up from Standby mode, but by any application
reset (such as NRST or IWDG).
0: VDDIO4VRSEL not retained in Standby mode
1: VDDIO4VRSEL retained in Standby mode
Bit 24 VDDIO4VRSEL: VDDIO4 I/O voltage range selection
This bit is used to select the voltage range supported by I/Os supplied by VDDIO4. It is not
reset by wake-up from Standby mode, but by any application reset (such as NRST or IWDG),
when VDDIO4VRSTBY is set, otherwise this bit is reset on any system reset.
0: 3v3 voltage range selected. If VDDIO4 is in 1v8 range with this setting, I/Os work
in degraded mode.
1: 1v8 voltage range selected. HSLV_VDDIO4 option bit must be set to allow 1v8 voltage
range operation. Setting this configuration while VDDIO4 is in 3v3 range damages the device.
Bits 23:17 Reserved, must be kept at reset value.
Bit 16 VDDIO4RDY: VDDIO4 ready
0: VDDIO4 is below the threshold of the VDDIO4 voltage monitor.
1: VDDIO4 is equal or above the threshold of the VDDIO4 voltage monitor.
Bits 15:9 Reserved, must be kept at reset value.
Bit 8 VDDIO4SV: VDDIO4 independent I/O supply valid.
This bit is used to validate the VDDIO4 supply for electrical and logical isolation purpose.
Setting this bit is mandatory to use PC[1], PC[12:6], and PH[9:2] I/Os. If VDDIO4 is not always
present in the application, the VDDIO4 voltage monitor can be used to determine whether
this supply is ready or not. This bit is reset on any system reset.
0: VDDIO4 is not present. Logical and electrical isolation is applied to ignore this supply.
1: VDDIO4 is valid.
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 VDDIO4VMEN: VDDIO4 independent I/O voltage monitor enable
This bit is reset on any system reset.
0: VDDIO4 voltage monitor disabled
1: VDDIO4 voltage monitor enabled

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13.9.11 PWR supply voltage monitoring control register 2 (PWR_SVMCR2)

Address offset: 0x038
Reset value: 0x0000 0000
See individual bits for reset condition. Access six wait states when writing this register.
When a system reset occurs during the register write cycle, the written data are not
guaranteed.
Secure restriction is defined by SEC7 in PWR_SECCFGR. Privilege restriction is defined
by PRIV7 in PWR_PRIVCFGR.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VDDIO5 VDDIO5 VDDIO5
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
VRSTBY VRSEL RDY
rw rw r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VDDIO5 VDDIO5
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SV VMEN
rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 VDDIO5VRSTBY: VDDIO5 I/O voltage range Standby mode
When this bits is set, VDDIO5VRSEL configuration is retained in Standby mode.
This bit must be set if the VDDIO5 is in 1v8 range in Standby mode, and when exiting Standby
mode. It must not be set when VDDIO5 is in 3v3 range in Standby mode, or when exiting
Standby mode. This bit is not reset by wake-up from Standby mode, but by any application
reset (such as NRST or IWDG).
0: VDDIO5VRSEL not retained in Standby mode
1: VDDIO5VRSEL retained in Standby mode.
Bit 24 VDDIO5VRSEL: VDDIO5 I/O voltage range selection
This bit is used to select the voltage range supported by I/Os supplied by VDDIO5. It is not
reset by wake-up from Standby mode, but by any application reset (such as NRST or IWDG),
when VDDIO5VRSTBY bit is set, otherwise this bit is reset on any system reset.
0: 3v3 voltage range selected. If VDDIO5 is in 1v8 range with this setting, I/Os work
in degraded mode.
1: 1v8 voltage range selected. HSLV_VDDIO5 option bit must be set to allow 1v8 voltage
range operation. Setting this configuration while VDDIO5 is in 3v3 range damages the device.
Bits 23:17 Reserved, must be kept at reset value.
Bit 16 VDDIO5RDY: VDDIO5 ready
0: VDDIO5 is below the threshold of the VDDIO5 voltage monitor.
1: VDDIO5 is equal or above the threshold of the VDDIO5 voltage monitor.
Bits 15:9 Reserved, must be kept at reset value.
Bit 8 VDDIO5SV: VDDIO5 independent supply valid
This bit is used to validate the VDDIO5 supply for electrical and logical isolation purpose.
Setting this bit is mandatory to use PC[0], PC[5:2] and PE[4] I/Os. If VDDIO5 is not always
present in the application, the VDDIO5 voltage monitor can be used to determine whether this
supply is ready or not. This bit is reset on any system reset.
0: VDDIO5 is not present. Logical and electrical isolation is applied to ignore this supply.
1: VDDIO5 is valid.

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Bits 7:1 Reserved, must be kept at reset value.

Bit 0 VDDIO5VMEN: VDDIO5 independent voltage monitor enable
This bit is reset on any system reset.
0: VDDIO5 voltage monitor disabled
1: VDDIO5 voltage monitor enabled

13.9.12 PWR supply voltage monitoring control register 3 (PWR_SVMCR3)

Address offset: 0x03C
Reset value: 0x0000 0000
See individual bits for reset condition. Access six wait states when writing this register.
When a system reset occurs during the register write cycle, the written data are not
guaranteed.
Secure restriction is defined by SEC7 in PWR_SECCFGR. Privilege restriction is defined
by PRIV7 in PWR_PRIVCFGR.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VDDIO VDDIO
VDDIO USB33 VDDIO VDDIO
Res. Res. Res. Res. Res. 3VRSE 2VRSE Res. Res. Res. ARDY Res.
VRSEL RDY 3RDY 2RDY
L L
rw rw rw r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USB33 VDDIO VDDIO USB33 VDDIO VDDIO
Res. Res. Res. ASV Res. Res. Res. Res. AVMEN Res.
SV 3SV 2SV VMEN 3VMEN 2VMEN
rw rw rw rw rw rw rw rw

Bits 31:27 Reserved, must be kept at reset value.

Bit 26 VDDIO3VRSEL: VDDIO3 I/O voltage range selection
This bit is used to select the voltage range supported by I/Os supplied by VDDIO3. it is not
reset by wake-up from Standby mode, but by any application reset (such as NRST or IWDG).
0: 3v3 voltage range selected. If VDDIO3 is in 1v8 range with this setting, I/Os work
in degraded mode.
1: 1v8 voltage range selected. HSLV_VDDIO3 option bit must be set to allow 1v8 voltage
range operation. Setting this configuration while VDDIO3 is in 3v3 range damages the device.
Bit 25 VDDIO2VRSEL: VDDIO2 I/O voltage range selection
This bit is used to select the voltage range supported by I/Os supplied by VDDIO2. It is not
reset by wake-up from Standby mode, but by any application reset (such as NRST or IWDG).
0: 3v3 voltage range selected. If VDDIO2 is in 1v8 range with this setting, I/Os work
in degraded mode.
1: 1v8 voltage range selected. HSLV_VDDIO2 option bit must be set to allow 1v8 voltage
range operation. Setting this configuration while VDDIO2 is in 3v3 range damages the device.
Bit 24 VDDIOVRSEL: VDD I/O voltage range selection
This bit is used to select the voltage range supported by I/Os supplied by VDD. It is not reset
by wake-up from Standby mode, but by any application reset (such as NRST or IWDG).
0: 3v3 voltage range selected. If VDD is in 1v8 range with this setting, I/Os work in degraded
mode.
1: 1v8 voltage range selected. HSLV_VDD option bit must be set to allow 1v8 voltage range
operation. Setting this configuration while VDD is in 3v3 range damages the device.

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Bits 23:21 Reserved, must be kept at reset value.

Bit 20 ARDY: VDDA18ADC ready
0: VDDA18ADC is below the threshold of the VDDA18ADC voltage monitor.
1: VDDA18ADC is equal or above the threshold of the VDDA18ADC voltage monitor.
Bit 19 Reserved, must be kept at reset value.
Bit 18 USB33RDY: VDD33USB ready
0: VDD33USB is below the threshold of the USB33 voltage monitor.
1: VDD33USB is equal or above the threshold of the USB33 voltage monitor.
Bit 17 VDDIO3RDY: VDDIO3 ready
0: VDDIO3 is below the threshold of the VDDIO3 voltage monitor.
1: VDDIO3 is equal or above the threshold of the VDDIO3 voltage monitor.
Bit 16 VDDIO2RDY: VDDIO2 ready
0: VDDIO2 is below the threshold of the VDDIO2 voltage monitor.
1: VDDIO2 is equal or above the threshold of the VDDIO2 voltage monitor.
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 ASV: VDDA18ADC independent supply valid
This bit is used to validate the VDDA18ADC supply for electrical and logical isolation purpose.
Setting this bit is mandatory to use the analog to digital converters. If VDDA18ADC is not
always present in the application, the VDDA18ADC voltage monitor can be used to determine
whether this supply is ready or not. This bit is reset on any system reset.
0: VDDA18ADC is not present. Logical and electrical isolation is applied to ignore this supply.
1: VDDA18ADC is valid.
Bit 11 Reserved, must be kept at reset value.
Bit 10 USB33SV: VDD33USB independent supply valid
This bit is used to validate the VDD33USB supply for electrical and logical isolation purpose.
Setting this bit is mandatory to use the USB2 HS PHYs. If VDD33USB is not always present in
the application, the VDD33USB voltage monitor can be used to determine whether this supply
is ready or not. This bit is reset on any system reset.
0: VDD33USB is not present. Logical and electrical isolation is applied to ignore this supply.
1: VDD33USB is valid.
Bit 9 VDDIO3SV: VDDIO3 independent supply valid
This bit is used to validate the VDDIO3 supply for electrical and logical isolation purpose.
Setting this bit is mandatory to use PN[12:0] I/Os. If VDDIO3 is not always present in the
application, the VDDIO3 voltage monitor can be used to determine whether this supply is
ready or not. This bit is reset on any system reset.
0: VDDIO3 is not present. Logical and electrical isolation is applied to ignore this supply.
1: VDDIO3 is valid.
Bit 8 VDDIO2SV: VDDIO2 independent supply valid.
This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose.
Setting this bit is mandatory to use PO[5:0] and PP[15:0] I/Os. If VDDIO2 is not always present
in the application, the VDDIO2 voltage monitor can be used to determine whether this supply
is ready or not. This bit is reset on any system reset.
0: VDDIO2 is not present. Logical and electrical isolation is applied to ignore this supply.
1: VDDIO2 is valid.
Bits 7:5 Reserved, must be kept at reset value.

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Bit 4 AVMEN: VDDA18ADC independent ADC voltage monitor enable

This bit is reset on any system reset.
0: VDDA18ADC voltage monitor disabled
1: VDDA18ADC voltage monitor enabled
Bit 3 Reserved, must be kept at reset value.
Bit 2 USB33VMEN: VDD33USB independent USB 33 voltage monitor enable.
This bit is reset on any system reset.
0: VDD33USB voltage monitor disabled
1: VDD33USB voltage monitor enabled
Bit 1 VDDIO3VMEN: VDDIO3 independent voltage monitor enable
This bit is reset on any system reset.
0: VDDIO3 voltage monitor disabled
1: VDDIO3 voltage monitor enabled
Bit 0 VDDIO2VMEN: VDDIO2 independent voltage monitor enable
This bit is reset on any system reset.
0: VDDIO2 voltage monitor disabled
1: VDDIO2 voltage monitor enabled

13.9.13 PWR wake-up clear register (PWR_WKUPCR)

Address offset: 0x050
Reset value: 0x0000 0000
This register is not reset on any system reset. Access six wait states when writing this
register.
When a system reset occurs during the register write cycle, the written data are not
guaranteed.
Secure restriction of each it WKUPCx (x = 1 to 4) is defined by WUPxSEC
in PWR_SECCFGR. Privilege restriction of each WKUPCx (x = 1 to 4) is defined by
WUPxPRIV in PWR_PRIVCFGR.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKUP WKUP WKUP WKUP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
C4 C3 C2 C1
w w w w

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 WKUPC4: Clear wake-up flag for WKUP4 pin
These bits are always read as 0.
0: No effect
1: Writing 1 clears WKUPF4 in PWR_WKUPSR.
Note: This bit is cleared to 0 by hardware.

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Bit 2 WKUPC3: Clear wake-up flag for WKUP3 pin

These bits are always read as 0.
0: No effect
1: Writing 1 clears WKUPF3 in PWR_WKUPSR.
Note: This bit is cleared to 0 by hardware.
Bit 1 WKUPC2: Clear wake-up flag for WKUP2 pin
These bits are always read as 0.
0: No effect
1: Writing 1 clears WKUPF2 in PWR_WKUPSR.
Note: This bit is cleared to 0 by hardware.
Bit 0 WKUPC1: Clear wake-up flag for WKUP1 pin
These bits are always read as 0.
0: No effect
1: Writing 1 clears WKUPF1 in PWR_WKUPSR.
Note: This bit is cleared to 0 by hardware.

13.9.14 PWR wake-up status register (PWR_WKUPSR)

Address offset: 0x054
Reset value: 0x0000 0000
This register is not reset by wake-up from Standby mode, but by any application reset (such
as NRST or IWDG).
When clearing a WKUPFx, the AHB write access completes after the WKUPFx has been
cleared.
When a system reset occurs during the register write cycle, the written data are not
guaranteed.
Secure restriction of each WKUPFx (x = 1 to 4) is defined by WUPxSEC
in PWR_SECCFGR. Privilege restriction of each WKUPFx (x = 1 to 4) is defined
by WUPxPRIV in PWR_PRIVCFGR.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKUP WKUP WKUP WKUP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
F4 F3 F2 F1
r r r r

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 WKUPF4: Wake-up flag for WKUP4 pin before enable
This bit is set by hardware and cleared only by a NRST reset, or by setting the WKUPC4 bit.
0: No wake-up event occurred
1: A wake-up event was received from WKUP4 pin.

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RM0486 Power control (PWR)

Bit 2 WKUPF3: Wake-up flag for WKUP3 pin before enable

This bit is set by hardware and cleared only by a NRST reset, or by setting the WKUPC3 bit.
0: No wake-up event occurred
1: A wake-up event was received from WKUP3 pin.
Bit 1 WKUPF2: Wake-up flag for WKUP2 pin before enable
This bit is set by hardware and cleared only by a NRST reset, or by setting the WKUPC2 bit.
0: No wake-up event occurred
1: A wake-up event was received from WKUP2 pin.
Bit 0 WKUPF1: Wake-up flag for WKUP1 pin before enable
This bit is set by hardware and cleared only by a NRST reset, or by setting the WKUPC1 bit.
0: No wake-up event occurred
1: A wake-up event was received from WKUP1 pin.

13.9.15 PWR wake-up enable and polarity register (PWR_WKUPEPR)

Address offset: 0x058
Reset value: 0x0000 0000
This register is not reset by wake-up from Standby mode, but by any application reset
(such as NRST or IWDG). Access six wait states when writing this register.
When a system reset occurs during the register write cycle, the written data are not
guaranteed.
Secure restriction of each WKUPENx, WKUPPx, and WKUPPUPDx (x = 1 to 4) is defined
by WUPxSEC in PWR_SECCFGR. Privilege restriction of each WKUPENx, WKUPPx, and
WKUPPUPDx (x = 1 to 4) is defined by WUPxPRIV in PWR_PRIVCFGR.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUPPUPD4[1: WKUPPUPD3[1: WKUPPUPD2[1: WKUPPUPD1[1:
Res. Res. Res. Res. Res. Res. Res. Res.
0] 0] 0] 0]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKUP WKUP WKUP WKUP WKUP WKUP WKUP WKUP
Res. Res. Res. Res. Res. Res. Res. Res.
P4 P3 P2 P1 EN4 EN3 EN2 EN1
rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:22 WKUPPUPD4[1:0]: Wake-up pull configuration for WKUP4 pin
These bits define the I/O pad pull configuration used when WKUPEN4 = 1 (the associated
GPIO port pull configuration must be set to the same value or 00). The WKUP pin pull
configuration is maintained in Standby mode.
00: No pulls
01: Pull-up
10: Pull-down
11: Reserved

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Bits 21:20 WKUPPUPD3[1:0]: Wake-up pull configuration for WKUP3 pin

These bits define the I/O pad pull configuration used when WKUPEN3 = 1 (the associated
GPIO port pull configuration must be set to the same value or 00). The WKUP pin pull
configuration is maintained in Standby mode.
00: No pulls
01: Pull-up
10: Pull-down
11: Reserved
Bits 19:18 WKUPPUPD2[1:0]: Wake-up pull configuration for WKUP2 pin
These bits define the I/O pad pull configuration used when WKUPEN2 = 1 (the associated
GPIO port pull configuration must be set to the same value or 00). The WKUP pin pull
configuration is maintained in Standby mode.
00: No pulls
01: Pull-up
10: Pull-down
11: Reserved
Bits 17:16 WKUPPUPD1[1:0]: Wake-up pull configuration for WKUP1 pin
These bits define the I/O pad pull configuration used when WKUPEN1 = 1 (the associated
GPIO port pull configuration must be set to the same value or 00). The WKUP pin pull
configuration is maintained in Standby mode.
00: No pulls
01: Pull-up
10: Pull-down
11: Reserved
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 WKUPP4: Wake-up polarity bit for WKUP4 pin
This bit defines the polarity used for event detection on external WKUP4 pin.
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bit 10 WKUPP3: Wake-up polarity bit for WKUP3 pin
This bit defines the polarity used for event detection on external WKUP3 pin.
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bit 9 WKUPP2: Wake-up polarity bit for WKUP2 pin
This bit defines the polarity used for event detection on external WKUP2 pin.
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bit 8 WKUPP1: Wake-up polarity bit for WKUP1 pin
This bit defines the polarity used for event detection on external WKUP1 pin.
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 WKUPEN4: Enable WKUP4 pin
0: An event on WKUP4 pin does not wake up the system from Standby and Stop modes.
1: A rising or falling edge on WKUP4 pin wakes up the system from Standby and Stop
modes.

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RM0486 Power control (PWR)

Bit 2 WKUPEN3: Enable WKUP3 pin

0: An event on WKUP3 pin does not wake up the system from Standby and Stop modes.
1: A rising or falling edge on WKUP3 pin wakes up the system from Standby and Stop
modes.
Bit 1 WKUPEN2: Enable WKUP2 pin
0: An event on WKUP2 pin does not wake up the system from Standby and Stop modes.
1: A rising or falling edge on WKUP2 pin wakes up the system from Standby and Stop
modes.
Bit 0 WKUPEN1: Enable WKUP1 pin
0: An event on WKUP1 pin does not wake up the system from Standby and Stop modes.
1: A rising or falling edge on WKUP1 pin wakes up the system from Standby and Stop
modes.

13.9.16 PWR security configuration register (PWR_SECCFGR)

Address offset: 0x070
Reset value: 0x0000 0000
Reset on any system reset.
Nonsecure or unprivileged writes to this register are ignored, while any read is allowed.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUP WKUP WKUP WKUP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SEC4 SEC3 SEC2 SEC1
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. SEC7 SEC6 SEC5 SEC4 SEC3 SEC2 SEC1 SEC0
rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 WKUPSEC4: WKUP4 pin secure protection
0: Bits related to WKUP4 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR
can be read and written with secure or nonsecure access.
1: Bits related to WKUP4 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR
can be read and written only with secure access.
Bit 18 WKUPSEC3: WKUP3 pin secure protection
0: Bits related to WKUP3 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR
can be read and written with secure or nonsecure access.
1: Bits related to WKUP3 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR
can be read and written only with secure access.
Bit 17 WKUPSEC2: WKUP2 pin secure protection
0: Bits related to WKUP2 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR
can be read and written with secure or nonsecure access.
1: Bits related to WKUP2 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR
can be read and written only with secure access.

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Power control (PWR) RM0486

Bit 16 WKUPSEC1: WKUP1 pin secure protection

0: Bits related to WKUP1 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR
can be read and written with secure or nonsecure access.
1: Bits related to WKUP1 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR
can be read and written only with secure access.
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 SEC7: Peripheral voltage monitor secure protection
0: PWR_SVMCR1, PWR_SVMCR2, and PWR_SVMCR3 can be read and written with
secure or nonsecure access.
1: PWR_SVMCR1, PWR_SVMCR2, and PWR_SVMCR3 can be read and written only with
secure access.
Bit 6 SEC6: CPU power control secure protection
0: PWR_CPUCR can be read and written with secure or nonsecure access.
1: PWR_CPUCR can be read and written only with secure access.
Bit 5 SEC5: Backup domain secure protection
0: PWR_BDCR1, PWR_BDCR2, and PWR_DBPCR can be read and written with secure or
nonsecure access.
1: PWR_BDCR1, PWR_BDCR2, and PWR_DBPCR can be read and written only with
secure access.
Bit 4 SEC4: Voltage scaling selection secure protection
0: PWR_VOSCR can be read and written with secure or nonsecure access.
1: PWR_VOSCR can be read and written only with secure access.
Bit 3 SEC3: I-TCM, D-TCM, and I-TCM FLEXMEM low power control secure protection
0: PWR_CR4 can be read and written with secure or nonsecure access.
1: PWR_CR4 can be read and written only with secure access.
Bit 2 SEC2: VDDCORE monitor secure protection
0: PWR_CR3 can be read and written with secure or nonsecure access.
1: PWR_CR3 can be read and written only with secure access.
Bit 1 SEC1: Programmable voltage detector secure protection
0: PWR_CR2 can be read and written with secure or nonsecure access.
1: PWR_CR2 can be read and written only with secure access.
Bit 0 SEC0: System supply configuration secure protection
0: PWR_CR1 can be read and written with secure or nonsecure access.
1: PWR_CR1 can be read and written only with secure access.

13.9.17 PWR privilege configuration register (PWR_PRIVCFGR)

Address offset: 0x074
Reset value: 0x0000 0000
Reset on any system reset.
Write access to this register is privileged only. Any read access is allowed on this register.

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RM0486 Power control (PWR)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUP WKUP WKUP WKUP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
PRIV4 PRIV3 PRIV2 PRIV1
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. PRIV7 PRIV6 PRIV5 PRIV4 PRIV3 PRIV2 PRIV1 PRIV0
rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 WKUPPRIV4: WKUP4 pin privileged protection
0: Bits related to WKUP4 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR
can be read and written with privileged or unprivileged access.
1: Bits related to WKUP4 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR
can be read and written only with privileged access.
This bit can only be written by privileged application. If corresponding WKUPSEC4 is set
in PWR_SECCFGR, this bit can only be written by secure privileged application.
Bit 18 WKUPPRIV3: WKUP3 pin privileged protection
0: Bits related to WKUP3 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR
can be read and written with privileged or unprivileged access.
1: Bits related to WKUP3 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR
can be read and written only with privileged access.
This bit can only be written by privileged application. If corresponding WKUPSEC3 is set
in PWR_SECCFGR, this bit can only be written by secure privileged application.
Bit 17 WKUPPRIV2: WKUP2 pin privileged protection
0: Bits related to WKUP2 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR
can be read and written with privileged or unprivileged access.
1: Bits related to WKUP2 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR
can be read and written only with privileged access.
This bit can only be written by privileged application. If corresponding WKUPSEC2 is set
in PWR_SECCFGR, this bit can only be written by secure privileged application.
Bit 16 WKUPPRIV1: WKUP1 pin privileged protection
0: Bits related to WKUP1 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR
can be read and written with privileged or unprivileged access.
1: Bits related to WKUP1 pin in PWR_WKUPCR, PWR_WKUPSR, and PWR_WKUPEPR
can be read and written only with privileged access.
This bit can only be written by privileged application. If corresponding WKUPSEC1 is set
in PWR_SECCFGR, this bit can only be written by secure privileged application.
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 PRIV7: Peripheral voltage monitor privileged protection
0: PWR_SVMCR1, PWR_SVMCR2, and PWR_SVMCR3 can be read and written with
privileged or unprivileged access.
1: PWR_SVMCR1, PWR_SVMCR2, and PWR_SVMCR3 can be read and written only with
privileged access.
This bit can only be written by privileged application. If corresponding SEC7 is set
in PWR_SECCFGR, this bit can only be written by secure privileged application.

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Power control (PWR) RM0486

Bit 6 PRIV6: CPU power control privileged protection

0: PWR_CPUCR can be read and written with privileged or unprivileged access.
1: PWR_CPUCR can be read and written only with privileged access.
This bit can only be written by privileged application. If corresponding SEC6 is set
in PWR_SECCFGR, this bit can only be written by secure privileged application.
Bit 5 PRIV5: Backup domain privileged protection
0: PWR_BDCR1, PWR_BDCR2, and PWR_DBPCR can be read and written with privileged
or unprivileged access.
1: PWR_BDCR1, PWR_BDCR2, and PWR_DBPCR can be read and written only with
privileged access.
This bit can only be written by privileged application. If corresponding SEC5 is set
in PWR_SECCFGR, this bit can only be written by secure privileged application.
Bit 4 PRIV4: Voltage scaling selection privileged protection
0: PWR_VOSCR can be read and written with privileged or unprivileged access.
1: PWR_VOSCR can be read and written only with privileged access.
This bit can only be written by privileged application. If corresponding SEC4 is set
in PWR_SECCFGR, this bit can only be written by secure privileged application.
Bit 3 PRIV3: I-TCM, D-TCM, and I-TCM FLEX MEM low power control privileged protection
0: PWR_CR4 can be read and written with privileged or unprivileged access.
1: PWR_CR4 can be read and written only with privileged access.
This bit can only be written by privileged application. If corresponding SEC3 is set
in PWR_SECCFGR, this bit can only be written by secure privileged application.
Bit 2 PRIV2: VDDCORE monitor privileged protection
0: PWR_CR3 can be read and written with privileged or unprivileged access.
1: PWR_CR3 can be read and written only with privileged access.
This bit can only be written by privileged application. If corresponding SEC2 is set
in PWR_SECCFGR ,his bit can only be written by secure privileged application.
Bit 1 PRIV1: Programmable voltage detector privileged protection
0: PWR_CR2 can be read and written with privileged or unprivileged access.
1: PWR_CR2 can be read and written only with privileged access.
This bit can only be written by privileged application. If corresponding SEC1 is set
in PWR_SECCFGR, this bit can only be written by secure privileged application.
Bit 0 PRIV0: System supply configuration privileged protection
0: PWR_CR1 can be read and written with privileged or unprivileged access.
1: PWR_CR1 can be read and written only with privileged access.
This bit can only be written by privileged application. If corresponding SEC0 is set
in PWR_SECCFGR, this bit can only be written by secure privileged application.

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RM0486 Power control (PWR)

13.9.18 PWR debug control register 1 (PWR_CRCFG1)

Address offset: 0x080
Reset value: 0xD000 0000
Bits [15:0] are not reset by wake-up from STANDBY mode, application reset (such as NRST,
IWDG) and VDD POR, but only by VSW POR and VSWRST. Bits [31:16] are reset by system
reset and when waking up from STANDBY mode.
Write access is protected and software must write a KEY (0XCAFECAFE) as a word access
in this register to unlock a single write access. Once unlocked, the register accepts a single
written access (byte, half word, or word), after it relocks.
Secure privileged write access only. Any read access is allowed on this register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SD_VS VDDA1
SD_OK SD_LP MODE SYNC_
_READ 8PMUR SD_STATUS_SPARE[3:0] Res. Res. Res. RLPSN Res. Res.
START M _DVS ADC
Y DY
r r r r r r r r rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MERG
SLOPE_SFST SDFP SDDISI UNLOC
Res. Res. Res. Res. Res. SEL_DLY_NOVL[2:0] SEL_LC[1:0] E_CLK
[1:0] WMEN LM KED
_FSM
rw rw rw rw rw rw rw rw rw rw rw

Bit 31 SD_OKSTART: Step down converter start up phase status

Bit 30 SD_VS_READY: Step down converter voltage scaling status
Bit 29 SD_LPM: Step down converter low power mode status
Bit 28 VDDA18PMURDY: VDDA18PMU ready.
0: VDDA18PMU is below the threshold of the VDDA18PMU voltage monitor.
1: VDDA18PMU is equal or above the threshold of the VDDA18PMU voltage monitor.
Bits 27:24 SD_STATUS_SPARE[3:0]: Step down converter spare status bits
Bits 23:21 Reserved, must be kept at reset value.
Bit 20 RLPSN: RAM low power mode disable in STOP.
When set the RAMs does not enter low power mode when the system enters STOP
0: RAM enters low power mode when system enters STOP
1: RAM remains in normal mode when system enters STOP
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 MODE_DVS: Mode selection during voltage scaling of the SD converter
Bit 16 SYNC_ADC:
0: SD_Converter clock free running
1: SD_Converter clock synchronized to ADC
Bits 15:11 Reserved, must be kept at reset value.
Bits 10:8 SEL_DLY_NOVL[2:0]: NOVL delay selection
Bits 7:6 SEL_LC[1:0]: External inductor/capacitor selection for SD converter
Bits 5:4 SLOPE_SFST[1:0]: Set slope of the voltage ramp during the startup.

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Power control (PWR) RM0486

Bit 3 SDFPWMEN: Step down converter force PWM mode

0: SD_Converter Normal mode
1: SD_Converter forced PWM mode
Bit 2 SDDISILM: Step down converter current limitation disabling
0: Current limitation disabled
1: Current limitation enabled
Bit 1 MERGE_CLK_FSM: Synchronous clk in Ramp and Mos FSM
Bit 0 UNLOCKED: Debug register unlocked
0: accessed locked: key was not written and after each register write access
1: after key 0xCAFECAFE was written in this register

13.9.19 PWR debug control register 2 (PWR_CRCFG2)

Address offset: 0x084
Reset value: 0x0000 0000
Reset on any system reset.
Write access is protected and software must write a KEY (0XCAFECAFE) as a word access
in this register to unlock a single write access. Once unlocked, the register accepts a single
written access (byte, half word, or word), after it relocks.
Secure privileged write access only. Any read access is allowed on this register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. DBG_FSM[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_O DBG_I UNLOC
SEL_DLY_FSM[11:0] Res.
UT_EN N_EN KED
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 DBG_FSM[11:0]:
Bits 15:4 SEL_DLY_FSM[11:0]: Various delay in the asynchronous FSM
Bit 3 Reserved, must be kept at reset value.
Bit 2 DBG_OUT_EN: Enable SD debug status outputs
Bit 1 DBG_IN_EN: Enable SD debug control inputs
Bit 0 UNLOCKED: Debug register unlocked
0: accessed locked: key was not written and after each register write access
1: after key 0xCAFECAFE was written in this register

13.9.20 PWR Debug control register 3 (PWR_CRCFG3)

Address offset: 0x088
Reset value: 0x0000 0000
Reset on any system reset.

404/4691 RM0486 Rev 2

RM0486 Power control (PWR)

Write access is protected and software must write a KEY (0XCAFECAFE) as a word access
in this register to unlock a single write access. Once unlocked, the register accepts a single
written access (byte, half word, or word), after it relocks.
Secure privileged write access only. Any read access is allowed on this register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNLOC
Res. Res. Res. DBG_CFG_BIT[11:0]
KED
rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:13 Reserved, must be kept at reset value.

Bits 12:1 DBG_CFG_BIT[11:0]: Spare configuration bits
Bit 0 UNLOCKED: Debug register unlocked
0: accessed locked: key was not written and after each register write access
1: after key 0xCAFECAFE was written in this register

RM0486 Rev 2 405/4691

408
 0x034
0x030
0x028
0x024
0x020
0x008
0x004
0x000

0x02C
0x01C
0x00C

0x010 -

406/4691
13.9.21

Reserved
PWR_CR4
PWR_CR3
PWR_CR2
PWR_CR1

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

PWR_BDCR2
PWR_BDCR1

PWR_DBPCR

PWR_CPUCR
PWR_VOSCR

PWR_SVMCR1
Offset Register name
Power control (PWR)

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
PWR register map

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
VDDIO4VRSTBY Res. Res. Res. Res. Res. Res. Res. Res. Res.

0
25
VDDIO4VRSEL Res. Res. Res. Res. Res. Res. Res. Res. Res.

0
24
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res.
0

20
Res. Res. Res. Res. TEMPH Res. Res. Res. Res.

0
0

19
Res. Res. Res. Res. TEMPL Res. Res. Res. Res.

0
0

18

RM0486 Rev 2
Res. Res. Res. Res. V08CAPH ACTVOSRDY Res. Res. Res.

0
1
0
POPL[4:0]

17
VDDIO4RDY SVOS Res. Res. V08CAPL ACTVOS Res. Res. Res.

0
1
0
0
0

16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15

Reserved
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Table 64. PWR register map and reset values

11
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 10
Res. SBF Res. Res. Res. Res. Res. VCOREH Res. Res.

0
0

9
VDDIO4SV STOPF Res. Res. Res. Res. Res. VCOREL PVDO Res.

0
0
0
0

8
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 7
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 6
Res. Res. Res. Res. Res. Res. Res. Res. Res. LPDS08V
1

5
Res. Res. Res. Res. Res. Res. TCMFLXRBSEN VCORELLS Res. MODE_PDN
0

0
0

4
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 3
Res. Res. Res. Res. Res. Res. Res. Res. Res. SDEN
1

2
Res. CSSF Res. Res. Res. VOSRDY Res. Res. Res. Res.

0
1

1
VDDIO4VMEN PDDS DBP BKPRBSEN MONEN VOS TCMRBSEN VCOREMONEN PVDEN Res.

0
0
0
0
0
0
0
0
0

0
RM0486
 0x080
0x074
0x070
0x058
0x054
0x050
0x038

0x06C
0x04C
0x03C

0x040 -

0x05C -
RM0486

Reserved
Reserved

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

PWR_CRCFG1
PWR_SVMCR3
PWR_SVMCR2

PWR_WKUPSR
PWR_WKUPCR

PWR_SECCFGR
PWR_WKUPEPR

PWR_PRIVCFGR
Offset Register name

SD_OKSTART Res. Res. Res. Res. Res. Res. Res.

1
31
SD_VS_READY Res. Res. Res. Res. Res. Res. Res.

1
30
SD_PLM Res. Res. Res. Res. Res. Res. Res.

0
29
VDDA18PMURDY Res. Res. Res. Res. Res. Res. Res.

1
28
Res. Res. Res. Res. Res. Res. Res.

0
27
Res. Res. Res. Res. Res. VDDIO3VRSEL Res.

0
0
SD_STATUS_SPARE 26
[3:0] Res. Res. Res. Res. Res. VDDIO2VRSEL VDDIO5VRSTBY

0
0
0

25
Res. Res. Res. Res. Res. VDDIOVRSEL VDDIO5VRSEL

0
0
0

24
Res. Res. Res. Res. Res. Res. Res.

0
WKUPPUPD4[1:0] 23
Res. Res. Res. Res. Res. Res. Res.

0
22
Res. Res. Res. Res. Res. Res. Res.

0
WKUPPUPD3[1:0] 21
RLPSN Res. Res. Res. Res. ARDY Res.

0
0
0

20
Res. WKUPPRIV4 WKUPSEC4 Res. Res. Res. Res.

0
0
0
WKUPPUPD2[1:0] 19
Res. WKUPPRIV3 WKUPSEC3 Res. Res. USB33RDY Res.

0
0
0
0

18

RM0486 Rev 2
MODE_DVS WKUPPRIV2 WKUPSEC2 Res. Res. VDDIO3RDY Res.

0
0
0
0
0

WKUPPUPD1[1:0] 17
SYNC_ADC WKUPPRIV1 WKUPSEC1 Res. Res. VDDIO2RDY VDDIO5RDY

0
0
0
0
0
0

16
Res. Res. Res. Res. Res. Res. Res. Res. 15

Reserved
Reserved

Res. Res. Res. Res. Res. Res. Res. Res. 14

Res. Res. Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. ASV Res.
0

12
Res. Res. Res. WKUPP4 Res. Res. Res. Res.

0
11
Res. Res. WKUPP3 Res. Res. USB33SV Res.

0
0

SEL_DLY_NOVL 10
Res. Res. WKUPP2 Res. Res. VDDIO3SV Res.

0
0
0

[2:0] 9
Table 64. PWR register map and reset values (continued)

Res. Res. WKUPP1 Res. Res. VDDIO2SV VDDIO5SV

0
0
0
0

8
PRIV7 SEC7 Res. Res. Res. Res. Res.

0
0
0
SEL_LC[1:0] 7
PRIV6 SEC6 Res. Res. Res. Res. Res.

0
0
0
6
PRIV5 SEC5 Res. Res. Res. Res. Res.

0
0
0
SLOPE_SFST 5
[1:0] PRIV4 SEC4 Res. Res. Res. AVMEN Res.

0
0
0
0

4
SDFPWMEN PRIV3 SEC3 WKUPEN4 WKUPF4 WKUPC4 Res. Res.

0
0
0
0
0
0

3
SDDISILM PRIV2 SEC2 WKUPEN3 WKUPF3 WKUPC3 USB33VMEN Res.

0
0
0
0
0

0
0

2
MERGE_CLK_FSM PRIV1 SEC1 WKUPEN2 WKUPF2 WKUPC2 VDDIO3VMEN Res.

0
0
0
0
0

0
0

1
UNLOCKED PRIV0 SEC0 WKUPEN1 WKUPF1 WKUPC1 VDDIO2VMEN VDDIO5VMEN

0
0
0
0
0

0
0
0

0
Power control (PWR)

407/4691
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Power control (PWR) RM0486

Table 64. PWR register map and reset values (continued)

Offset Register name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
DBG_OUT_EN
DBG_IN_EN
UNLOCKED
PWR_CRCFG2
Res.
Res.
Res.
Res.
DBG_FSM[11:0] SEL_DLY_FSM[11:0]

Res.
0x084

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

UNLOCKED
PWR_CRCFG3
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DBG_CFG_BIT[11:0]
0x088

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.3 for the register boundary addresses.

408/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

14 Reset and clock control (RCC)

The RCC manages the clock and reset generation for the whole microcontroller.
The operating modes to whom this section refers are defined in Section 13.6.1: Operating
modes of the PWR.

14.1 RCC main features

• AHB-Lite bus interface
• RIF (resource isolation framework) aware
• Reset part:
– Generation of local and system reset
– Bidirectional pin to reset the microcontroller and/or external devices
– WWDG and IWDG reset supported
– Power-on (POR) and brownout (BOR) resets initiated by the PWR
• Clock generation:
– Generation and dispatching of clocks for the complete device
– Four separate PLLs using integer or fractional ratios
– Clock gating to reduce power dissipation
– Two external oscillators:
> High-speed external oscillator (HSE) supporting a wide range of crystals from
8 to 48 MHz (when the USBHSPHY is used, the HSE frequency must be
19.2, 20, or 24 MHz)
> Low-speed external oscillator (LSE) for a 32.768 kHz crystal
– Four internal oscillators:
> High-speed internal oscillator (HSI)
> Low-power internal oscillator (MSI)
> Low-speed internal oscillator (LSI)
> High-speed internal secure oscillator (HSIS)
– Buffered clock outputs for external devices
– Generation of two types of interrupt lines:
> Dedicated interrupt lines for clock failure management
> General interrupt line for other events (separated into secure and
nonsecure)
– Clock generation handling in Stop and Standby modes

14.2 RCC power domains

RCC interfaces with four power domains, namely core (VDDCORE), retention (VDD, VRET),
backup (VSW, VBKP), and analog (VDDA18ADC).

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14.3 RCC block diagram

Figure 33. RCC block diagram

RCC
NRST nreset_rstn

rcc_sft_rst
sys_rst
iwdg_out_rst bsec_rst, bsec_srst, bsec_nrst
IWDG
option bytes, fuse_ok BSEC
wwdg_out_rst
WWDG System
pwr_bor_rst reset rcc_vcore_rst
control
pwr_por_rst rcc_perx_rst
pwr_vcore_ok
rcc_vsw_rst
pwr_vsw_rst
PWR dbg_stdby_rstn rcc_dbg_rst

cpu_sleep
pwr_wkup
cpu_deepsleep CPU
rcc_pwrds Clock manager
VSW domain lse_ck (CMU)
OSC32_IN lsi_ck M perx_ker_ckreq
LSE /CSS lse_ck hse_ck
U To RTC/AWU PERx
OSC32_OUT X
rcc_lsecss_fail
TAMP DIV To core and busses
hse_ck

System clock
rcc_hsecss_fail System

enabling
(SCEU)
TIM1, 8, hsi_ck rcc_bus_ck
clock
En
15, 16, 17 msi_ck rcc_cpu_ck
OSC_IN HSE / generation
hse_ck (SCGU) rcc_bus2_dbg_ck
CSS
OSC_OUT
PLL1
VDD domain hse_ck

Peripheral clock
To peripherals
Dividers

lsi_ck hsi_ck PLL2

M

enabling
LSI

(PKEU)
msi_ck U PLL3 Peripheral rcc_perx_ker_ck
i2s_ckin X
hsi_ck PLL4 kernel rcc_perx_bus_ck
HSI
clock
AHB Bus

selection
MSI msi_ck (PKSU)
i2s_ckin
To BSEC AUDIOCLK
HSIS
hsis_ck

M
RIFSC U
Dividers

rcc_it X MCO1
rcc_s_it Register interface and control E MCO2
S
NVIC rcc_hsecss_it
rcc_lsecss_it

MSv70466V2

14.4 RCC pins and internal signals

Table 65. RCC input/output signals connected to package pins or balls
Name Type Description

NRST I/O System reset, can be used to provide reset to external devices
OSC32_IN I 32 kHz oscillator input
OSC32_OUT O 32 kHz oscillator output
OSC_IN I System oscillator input
OSC_OUT O System oscillator output
MCO1 O Output clock 1 for external devices

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Table 65. RCC input/output signals connected to package pins or balls (continued)
Name Type Description

MCO2 O Output clock 2 for external devices

AUDIOCLK I External kernel clock input for digital audio interfaces: SPI/I2S, SAI, MDF, ADF

The RCC exchanges signals with all components of the product. Table 66 shows only the
most significant internal signals.

Table 66. RCC internal input/output signals

Name Type Description

rcc_it O General interrupt request line (nonsecure)

rcc_s_it O General interrupt request line (secure)
rcc_hsecss_it O HSE clock security failure interrupt
rcc_lsecss_it O LSE clock security failure interrupt
rcc_hsecss_fail O Event indicating that an HSE clock security failure is detected
rcc_lsecss_fail O Event indicating that an LSE clock security failure is detected
nreset_rstn I/O Application reset
sys_rst I/O System reset
bsec_rstn O BSEC warm reset
bsec_srstn O BSEC scratch (cold) reset
bsec_hrstn O BSEC hot reset
BSEC has finished loading the OTP (one-time programmable, which contains the
fuse_ok I
option bytes)
option bytes I Configuration bits from BSEC, affecting RCC behavior (reset, clock, osc)
iwdg_out_rst I Reset line driven by the IWDG, indicating that a timeout occurred
wwdg_out_rst I Reset line driven by the WWDG, indicating that a timeout occurred
pwr_bor_rst I Brownout reset generated by the PWR
pwr_por_rst I Power-on reset generated by the PWR
pwr_vsw_rst I Power-on reset of the VSW domain generated by the PWR
dbg_stdby_rstn I Standby emulation mode reset generated by the PWR
rcc_perx_rst O Reset generated by the RCC for the peripherals
pwr_wkup I Wake-up request generated by the PWR, and used to restore the clocks
Informs the PWR that the RCC has stopped all clocks (PWR can then go to Stop
rcc_pwrds O
or Standby mode)
cpu_sleep I
Signals generated by the CPU, indicating if it is in Run, Sleep, or Stop mode
cpu_deepsleep I
When this signal is asserted, the CPU does not advance in execution, and does
cpu_SLEEPHOLDACKn I
not perform any memory operation

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Table 66. RCC internal input/output signals (continued)

Name Type Description

Request to extend the CPU sleep state regardless of wake-up events. If the CPU
rcc_SLEEPHOLDREQn O acknowledges this request (SLEEPHOLDACKn asserted), the CPU remains idle
even when it receives a wake-up event.
perx_ker_ckreq I Generated by some peripherals to request the activation of their kernel clock
rcc_perx_ker_ck O Kernel clock signals generated by the RCC for some peripherals
rcc_perx_bus_ck O Bus interface clock signals generated by the RCC for peripherals
rcc_bus_ck O Clocks generated by the RCC for APB, AHB, and AXI bridges
rcc_cpu_ck O
Clocks generated by the RCC for the CPU
ck_cpu_dbg O
rcc_bus2_dbg_ck O Debug components clock
ck_cpu_tsgen O TSGEN clock (timestamp generator)
ck_cpu_tpiu O TPIU clock (double data rate)

14.5 Functional description of RCC reset

The RCC handles the reset generation for the complete product, using events coming from
different sources:
• assertion of the NRST pin from an external device
• a failure on the supply voltage applied to VDD or VBAT
• an exit from Standby mode
• a watchdog timeout
• a software command
The reset scope depends on the source that generates it.

14.5.1 Reset from the PWR

The PWR provides several reset signals to the RCC:
• power-on/off reset signal (pwr_por_rstn): asserted when the VDD supply is lower than
the VPOR threshold
• brownout reset signal (pwr_bor_rstn): asserted when the VDD supply is lower than
the VBOR threshold
• core reset signal (pwr_okin_vcore_rstn): asserted when the VDDCORE supply is not
valid or available
Note: VDDCORE is switched off when the product is in Standby mode. When the system exits
Standby mode, pwr_okin_vcore_rstn is asserted while VDDCORE from the regulator is not
valid. pwr_okin_vcore_rstn is also asserted when the VDD supply is not valid.
• VSW domain reset signal (pwr_vsw_rstn): asserted when the VSW supply is lower than
the expected threshold
Refer to Table 67 for more details.

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Figure 34. Simplified reset circuit

RCC – Reset control VDD domain

VDDCORE domain
Pad VDD
LCKRESET VDD domain
RPU
SFTRESET

RPCTL
lpwr_rst cmd_pad_rst rcc_pad_rst Pulse
iwdg_out_rst Stretcher
IWDG

OR
wwdg_out_rst
WWDG Filter
pwr_bor_rstn
pwr_por_rstn
NRST
nreset_rstn (external
reset)
(application reset)
CR
app_rstn

RST logic
rcc_vcore_rst
sys_rst (system reset)
Hardware system init done
VDD domain
Hardware bsec_rstn
NAND

system pwr_por_rstn bsec_srstn

PWR init fuse_ok bsec_hrstn
BSEC
pwr_okin_ control
Option bytes, fuse_ok
vcore_rstn

mrepair_req
mrepair_ack MREPAIR

VSWRST
RCC_BDCR
Logic

pwr_vsw_rstn rcc_vsw_rst

VSW domain

RCC_xxxRSTR ... Logic rcc_perx_rst

...

TAMP tamp_rst

rcc_vcore_rst rcc_vcore_rst

RCC_MISCRSTR

dbgrst
Logic

cdbgrstreq/ack rcc_dbg_rst
DAP Logic

MSv70467V2

14.5.2 System and application resets (sys_rst, nreset_rstn)

A system reset (sys_rst) resets most of the registers to their default values, unless
otherwise specified in the register description (summary in Table 67).
A system reset can be generated from one of the following sources:
• an assertion of the NRST pin (external reset)

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• a reset from the power-on/off reset block (pwr_por_rstn)

• a reset from the brownout reset block (pwr_bor_rstn), see Section 13.5.2: Brownout
reset (BOR) for a detailed description of the BOR function
• a reset from the independent watchdogs (iwdg_out_rst)
• an exit from Standby mode (rcc_vcore_rst)
• a reset from the window watchdogs depending on WWDG configuration
(wwdg_out_rst)
• a software reset (SFTRESET) signal, connected to SYSRESETREQ from the
Cortex-M55 core
• a lockup reset (LCKRESET) signal, connected to LOCKUP from the Cortex-M55 core
• a reset from the low-power mode security reset, depending on the option byte
configuration (lpwr_rst)
The application reset (nreset_rstn) is similar to the system reset, but it is not asserted when
the system exits Standby mode.
Note: The sys_rst is actually a combination the native internal reset signal (int_sys_rstn) and the
debug Standby reset signal (dbg_stdby_rstn). Some registers are reset by int_sys_rstn only.
See Section 14.6.13 for more details about dbg_stdby_rstn.
The SYSRESETREQ bit in Cortex-M55 must be set to force a software reset on the device.
Refer to the Cortex-M55 with FPU Technical Reference Manual for more details. There is
also a SYSCFG register, which affects SYSRESETREQ.

14.5.3 NRST reset

The NRST is active low. A pulse stretcher guarantees a minimum reset pulse duration of
20 μs (see the datasheet for details). The NRST assertion can also be extended by adding
the CR capacitor.
It is not recommended to leave the NRST pin unconnected. When not used, connect this pin
to ground via a 10 to 100 nF capacitor (CR in Figure 34). As shown in Figure 34, a filter is
present to suppress spurious coming from the NRST pin.

14.5.4 Low-power mode security reset (lpwr_rst)

To prevent critical applications from mistakenly entering a low-power mode, two low-power
mode security resets are available. When enabled through RST_STOP and RST_STDBY
option bytes, a system reset (sys_rst) is generated if the following conditions are met:
• The CPU mistakenly enters Stop mode.
This type of reset is enabled by setting RST_STOP user option byte. If a Stop mode
entry sequence is successfully executed, a system reset is generated.
• The system mistakenly enters Standby mode.
This type of reset is enabled by setting RST_STDBY user option byte. If a Standby
mode entry sequence is successfully executed, a system reset is generated.
LPWRRSTF bit in RCC_RSR indicates that a low-power mode security reset occurred
(see row 8 in Table 68).
The lpwr_rst input is activated when a low-power mode security reset is required.
This signal is generated by the PWR.

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See Section 5: OTP mapping (OTP) for additional information, and Table 55: Operating
mode summary for the overview of existing power modes.

14.5.5 Backup domain reset

A backup domain reset (rcc_vsw_rst) is generated when one of the following occurs:
• a software reset, triggered by setting VSWRST in RCC_BDCR: the BKPSRAM is not
affected.
• VSW voltage outside the operating range: the BKPSRAM content is no longer valid.
The RCC_BDCR register and all bitfields in the backup domain (including RTC) return to
their reset values: these include RTCEN, RTCLPEN, RTCPRE, RTCSEL, LSECSSRA,
LSECSSD, LSECSSON, LSERDY, LSERDYF, LSEON, LSEDRV, LSEEXT, LSEBYP,
LSEGFON.
See Section 13.4.4: Backup domain and Section 3: System security for additional
information.

14.5.6 CoreSight debug reset

CoreSight debug components can be reset in three different ways:
• using the DAP by setting CDBGRSTREQ in DP_CTRLSTAT
This asserts the debug reset request signal (cdbgrstreq) connected to the RCC. The
RCC then asserts the debug reset (rcc_dbg_rst), and a handshake signal cdbgrstack
acknowledges the DAP request. The debug reset remains asserted while cdbgrstreq is
asserted (see Figure 34 for details).
• when the application sets DBGRST in RCC_MISCRSTR
This asserts the rcc_dbg_rst reset, which is deasserted when DBGRST is cleared to 0.
• when a VDDCORE power-on reset occurs (rcc_vcore_rst)
This reset is asserted after a POR, or when the product exits Standby mode.
Refer to Section 14.5.6 for details.

14.5.7 Option-byte loading

As shown in Figure 36, the option-byte loading (OBL via OTP_LD) sequence happens after
a POR or a pin reset.
The system reset (sys_rst) is released only after the OBL has completed.
The BSEC manages an OTP array of fuse words, which hold the option-byte configuration
for the device. This configuration must be set every time an app_rstn is asserted, and the
system stays in reset until this configuration has been properly loaded (fuse_ok signal is
received from the BSEC module).
The BSEC handles the following reset sources:
• a main reset (bsec_rstn) asserted when an app_rstn is asserted
• a scratch reset (bsec_srstn) asserted when a pwr_por_rstn is asserted
• a hot reset (bsec_hrstn) asserted when fuse_ok is low

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14.5.8 Reset of peripherals

The application can reset individually any peripheral, whenever requested. This can be
done via registers named RCC_xxxxRSTR (xxxx is the bus name on which the peripheral is
connected).
To reset a peripheral, the corresponding reset bit must be set to 1 (peripheral clock not
required), and then set back to 0 (peripheral clock must be enabled and running in
advance). There is no need to enable a peripheral clock to reset a peripheral.
Caution: PKA, CRYP, SAES, and HASH may be reset directly in hardware upon a tamper event.

14.5.9 Reset pulse control (RPCTL)

The RPCTL allows the application to control the minimum activation time of the NRST pad.
This feature is particularly helpful because some external devices may require a specific
reset duration. In addition, the internal reset pulse, for example from IWDG, may be too
short for external devices.
The RPCTL is located in the VDD domain, and is reset only after a power-on reset.
The RPCTL is controlled by MRD[4:0] in RCC_RDCR.
If MRD is 0, then the RPCTL is bypassed. The minimum activation time in this case is given
by the pulse stretcher embedded in the reset pad (typically 20 μs).
If MRD is non-0, then the rising edge of cmd_pad_rst causes NRST to be immediately
driven low, for at least the duration set by MRD[4:0]. The duration of the reset is unchanged
if the cmd_pad_rst signal is active for longer than the duration set by MRD[4:0]. The
minimum activation time is between 1 and 31 ms.
The RPCTL uses the LSI clock to measure time. When the cmd_pad_rst goes high, the
RPCTL requests the LSI clock to control the reset duration. If the LSI was not enabled by
another function, it may take some microseconds before obtaining LSI ready (TLSI_SU).
Figure 35 shows two scenarios.

Figure 35. NRST reset pulse control

cmd_pad_rst
TLSI_SU
RPCTL_lsi_ck

RPCTL_cnt 0 MRD MRD-1 MRD-2 0

NRST

TLSI_SU + MRD x 1ms

cmd_pad_rst
TLSI_SU
RPCTL_lsi_ck

RPCTL_cnt 0 MRD MRD-1 MRD-2 0

NRST
MSv71163V1

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14.5.10 Reset coverage summary

Table 67 gives a detailed view of the coverage of the most important reset sources.
Note: When VDD is not valid, VDDCORE is not valid as well.

Table 67. Reset coverage summary (1)

Main reset lines

rcc_vcore_rst(3)
pwr_por_rstn(2)

nreset_rstn(4)

rcc_vsw_rstn
rcc_perx_rst
rcc_dbg_rst
Reset functions

sys_rst
VDD domain X - - - - - -
MCU X X X - - - -
WWDG X X X - - - -
IWDG X - - X - - -
AXI/AHB interconnections X X X - - - -
Debug components (including DBGMCU): reset all the debug parts except the
X X - - X - -
SWJ-DP function, which is reset by the NJTRST or rcc_vcore_rst resets.
Hardware system init: includes the memory repair. X X - - - - -
RCC reset register (RCC_RSR) X - - - - - -
RCC control register (RCC_CR) and RCC APB5 Sleep enable register
X - - - - - -
RCC (RCC_RDCR)
RCC bitfields in the backup domain - - - - - - X
Other RCC registers X X X - - - -
PWR_CSR1 - - - - - - X
PWR_CSR2 X - - - - - -
PWR_CSR3: individual bits of this register do not have the same reset
PWR X X X - - - -
condition (see Section 13: Power control (PWR) for details).
PWR_WKUPCR, PWR_WKUPFR, and PWR_WKUPEPR X - - X - - -
Other registers X X X - - - -
Peripheral (except APB) - - - - - - X
RTC
Peripheral APB X X X - - X -
BKPSRAM: after a reset of the VSW domain, the BKPSRAM backup regulator is
disabled. This function is controlled via BKPRBSEN (in PWR_BDCR2). If the - - - - - - X
rcc_vsw_rst reset is due to a too low VSW voltage, the BKPSRAM content is lost.
Other peripherals X X X - - X -
1. ‘X’ means that the function is reset by the corresponding reset line. ‘-’ means that the function is not reset by the
corresponding reset line.
2. pwr_por_rstn is asserted when the voltage applied to VDD is not valid. When pwr_por_rstn is asserted, the rcc_vcore_rst,
NRST, sys_rst, and nreset_rstn are asserted as well.

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3. rcc_vcore_rst is asserted when the voltage applied to VDD is not valid, or when the system exits Standby mode (because
VDDCORE is switched off). When rcc_vcore_rst is asserted, sys_rst and pwr_dbg_rst are asserted as well.
4. When nreset_rstn is asserted, sys_rst is asserted as well.

14.5.11 Reset source identification

The CPU can identify the reset source by checking reset flags in RCC_RSR or PWR_CSR3
registers.
The CPU can clear flags in RCC_RSR by setting RMVF bit in this register.
Table 68 shows how the status bits behave according to the situation that generated the
reset. For example, when an IWDG timeout occurs (row 7), if the CPU reads RCC_RSR
during the boot phase, both PINRSTF and IWDGRSTF bits are set, indicating that the
IWDG also generated a pin reset.

Table 68. Reset source identification(1)

LPWRRSTF

WWDGRST
IWDGRSTF

BORRSTF

PORRSTF
LCKRSTF

SFTRSTF

PINRSTF
SBF (2)
# Situation generating a reset

1 Power-on reset (pwr_por_rstn) 0 0 0 0 0 0 1 1 1

2 Pin reset (NRST) 0 0 0 0 0 0 0 1 0
3 Brownout reset (pwr_bor_rstn) 0 0 0 0 0 0 1 1 0
4 System reset generated by the CPU (SFTRESET) 0 0 0 0 0 1 0 1 0
5 System reset generated by the CPU (LCKRESET) 0 0 0 0 1 0 0 1 0
6 WWDG reset (wwdg_out_rst) 0 0 0 1 0 0 0 1 0
7 IWDG reset (iwdg_out_rst) 0 0 1 0 0 0 0 1 0
8 CPU erroneously enters Stop or Standby mode 0 1 0 0 0 0 0 1 0
9 The product exits Standby mode 1 0 0 0 0 0 0 1 0
1. Grayed cells highlight the register bits that are set.
2. The SBF bit is located in PWR_CSR3 register.

14.5.12 Power-on and wake-up sequences

For detailed diagrams, refer to Section 13.4.1: System supply startup in the PWR.
The time interval between the event that exits the device from a low-power, and the moment
where the CPU is able to execute code, depends on the system state and on its
configuration. Figure 36 shows the most usual examples.

Power-on wake-up sequence

The sequence shown in Figure 36 gives the most significant phases of the power-on
wake-up. It is the longest sequence since the circuit was not powered.
Note: This sequence remains unchanged whatever VBAT is present or not.

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Boot from pin reset (NRST)

When a pin reset occurs, VDD is still present. As a result:
• the regulator settling time is faster since the reference voltage is already stable
• the HSI restart delay may be needed if the HSI was not enabled when the NRST
occurred, otherwise this restart delay phase is skipped.

Boot from system standby

When waking up from system standby, the reference voltage is stable since VDD has not
been removed. As a result, the regulator settling time is fast. Since VDDCORE was not
present, the restart delay for the HSI and HSIS cannot be skipped.
sys_rst remains asserted until HSIS runs and the memory repair completes.

Restart from system stop

When restarting from system stop, VDD is still present. As a result, the sequence is mainly
composed of two steps:
1. The regulator settling time reaches VOS1 (default voltage).
2. HSI/MSI restart delay. This step can be skipped if HSISTOPEN = MSISTOPEN = 1 in
RCC_STOPCR.
sys_rst remains asserted until HSIS runs.

Figure 36. Boot sequences versus system states

Power-on wake-up (with or without VBAT)

VDD > POR
HSIS OTP_LD
REG + bandgap HSI MEM BR RUN
Time

NRST goes high Pin reset (internal or external)

(HSIS) OTP_LD
REG (HSI) BR RUN
Time

Wake-up event Wake-up from system Standby mode

HSIS
REG HSI MEM RUN
Time

Wake-up event
Wake-up from system Stop mode
HSIS
REG_VOS1 (HSI/MSI) RUN
Time

REG + bandgap Bandgap and regulator settling time OTP_LD Option-bytes loading RUN CPU fetch

REG_VOS1 REG settling time to reach the VOS1 MEM Memory repair delay HSI/MSI HSI or MSI restart delay

REG REG settling time BR Boot ROM code

MSv70468V2

14.6 Functional description of RCC clocks

The RCC provides a wide choice of clock generators:
• HSI (high-speed internal oscillator) clock: ~ 8, 16, 32, or 64 MHz

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• HSE (high-speed external oscillator) clock: 8 to 48 MHz

• LSE (low-speed external oscillator) clock: 32 kHz
• LSI (low-speed internal oscillator) clock: ~ 32 kHz
• MSI (low-power internal oscillator) clock: ~ 4 or 16 MHz
The RCC offers a high flexibility for the application to select the appropriate clock
for the CPU and peripherals (in particular for peripherals that require a specific clock, such
as SPI/I2S and SAI).
To optimize the power consumption, each clock source can be switched ON or OFF
independently.
The RCC provides up to four PLLs; each of them can be configured in integer mode (with or
without SSCG - spread spectrum clock generation), or fractional mode.
As shown in the Figure 37, the RCC offers two clock outputs (MCO1 and MCO2), with
flexibility on the clock selection and frequency adjustment.
The SCGU (system clock generation unit) contains several prescalers to configure the CPU
and bus matrix clock frequencies.
The PKSU (peripheral kernel clock selection unit) provides several dynamic switches, which
give a large choice of kernel clock distribution to peripherals.
The PKEU (peripheral kernel clock enable unit) performs the peripheral kernel clock gating.
The SCEU (system clock enable unit) performs the clock gating for the bus interface, cores,
and the bus matrix.

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Figure 37. Top-level clock tree

VDD domain RCC

LSIEN or IWDG activated
lsi_ck
LSI tempo To IWDG

RTCSEL

LSEON VSW (Backup) 0

OSC32_IN 0 RTCEN
lse_ck lse_ck
OSC32_OUT LSE tempo 1 rcc_rtc_ck
lsi_ck 2 To RTC/AWU
CSS hse_rtc_ck
3

hsi_div_ck MCO1SEL
HSE PERSEL 0
hse_div2_osc_ck CSS lse_ck 1
RTCPRE hsi_ck
FAIL 0 msi_ck 2 MCO1PRE
HSEON hse_osc_ck ÷2 to 63 msi_ck 1 lsi_ck 3 ÷1 to 16
OSC_IN 0 MCO1
HSE tempo hse_ck hse_ck 2 hse_ck 4
OSC_OUT 1 ic19_ck 3 per_ck
CSS ÷2 hse_div2_ck ic5_ck 5
ic5_ck 4 ic10_ck 6
HSECSSBPRE ÷1,2,,16 ic10_ck 5
÷1024 hsi_cal_ck sysa_ck 7
HSION hsi_osc_ck ic15_ck 6
HSIDIV MCO2SEL
HSI tempo ÷1,2,4,8 hsi_div_ck ic20_ck 7
hsi_div_ck 0
hsi_ck
lse_ck 1
÷4 hsi_div4_ck CPUSW
msi_ck 2 MCO2PRE
MSION msi_osc_ck hsi_ck lsi_ck 3
0 ÷1 to 16 MCO2
MSI tempo msi_ck msi_ck 1 sysa_ck hse_ck 4
÷128 msi_cal_ck hse_ck 2 ic15_ck 5
for BSEC hsis_osc_ck ic1_ck 3 ic20_ck 6
HSIS tempo hsis_ck sysb_ck 7
SYSSW
hsi_ck 0
msi_ck 1 sys[b,c,d]_ck
hse_ck 2
PLL1SEL ic[2,6,11]_ck 3

SCGU (system clock generation)

sysa_ck

SCEU (system clock enabling)

hsi_ck PLL1 sysb_ck
0 0 ic1_ck
pll1_ck ref1_ck 2
1 IC1 sysc_ck
3
msi_ck 1 ÷ DIVM1 VCO 0 ic2_ck sysd_ck
2 2
1 IC2
3
hse_ck DIVN1 0 ic3_ck
3 2
1 IC3
i2s_ckin 3 To CPU,
FRACN1
0 ic4_ck
2
1 IC4 busses, and
3
SSCG1 0 ic5_ck peripherals
2
1 IC5
PLL2SEL 3

hsi_ck 0 PLL2 0 ic6_ck

pll2_ck 1 IC6
2
3
msi_ck 1 ÷ DIVM2 VCO 0 ic7_ck
1 IC7
2 2
3 ic[20:2]_ck
hse_ck DIVN2 0 ic8_ck
1 IC8
3 2
3
i2s_ckin 0 ic9_ck
FRACN2 2
1 IC9
3
PKSU (peripheral kernel clock selection)

SSCG2 0 ic10_ck
2
1 IC10
PLL3SEL
PKEU (peripheral clock enabling)

hsi_ck 0 PLL3 0 ic11_ck

pll3_ck 1 IC11
2 To
3
msi_ck 1 ÷ DIVM3 VCO 0 ic12_ck
2
1 IC12 peripherals
2 3
hse_ck DIVN3 0 ic13_ck lsi_ck
1 IC13
3 2
3
i2s_ckin 0 ic14_ck lse_ck
FRACN3 2
1 IC14
3 msi_ck
SSCG3 0 ic15_ck
2
1 IC15
PLL4SEL 3 hsi_div_ck
hsi_ck PLL4 hsi_div4_ck
0 0 ic16_ck
pll4_ck 2
1 IC16 hse_ck
1 3
msi_ck ÷ DIVM4 VCO 0 ic17_ck hse_div2_ck
2 2
1 IC17
3
hse_ck DIVN4 0 ic18_ck sys[b,c,d]_ck
3 2
1 IC18 per_ck
3
i2s_ckin 0 ic19_ck
FRACN4 2
1 IC19
3
SSCG4 0 ic20_ck
2
1 IC20 AUDIOCLK
3 i2s_ckin
to ETH1_CLK_SEL
to
ETH1_REF_CLK_SEL
to ETH1_SEL(2:0)
x Represents the selected mux input after a system reset.
MSv70469V5

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14.6.1 Clock naming convention

The RCC provides clocks to the complete circuit. To avoid misunderstandings, the following
terms are used in this document:
• Peripheral clocks provided by the RCC to the peripherals
Two kinds of clock are available:
– bus interface clocks
– kernel clocks
A peripheral receives from the RCC a bus interface clock to access its registers, and
thus control the peripheral operation. This clock is generally the AHB, APB, or AXI
clock, depending on which bus the peripheral is connected to. Some peripherals need
only a bus interface clock.
Some peripherals require also a dedicated clock (named kernel clock) to handle the
interface function. As an example, SAI must generate specific and accurate master
clock frequencies, which require dedicated kernel clock frequencies.
An advantage of decoupling the bus interface clock from the kernel clock is that the bus
clock can be changed without reprogramming the peripheral.
• CPU clock: derived from a dedicated system clock (sysa_ck), is asynchronous to the
bus clocks.
• Bus matrix clocks: provided to the different bridges (APB, AHB, AXI, or NoC), are
derived from a system clock (sysb_ck).
• NPU and NPU AXI clocks: the NPU clock is derived from a dedicated system clock,
sysc_ck, also used for the AXI matrix close to the NPU.
• AXISRAM1/2 clocks: derived from sysb_ck.
• AXISRAM3/4/5/6 clocks: derived from sysd_ck.

14.6.2 Oscillator description

Table 69 shows the oscillator states versus system modes, when the oscillators are enabled
via registers. Available means that the resource can be used if activated via registers.

Table 69. Oscillator states versus system modes

VDDCORE domain VDD domain VSW domain
System modes
HSIS HSE HSI MSI LSI LSE

Exit from system reset On Off On Off Available Available

Exit from system stop On Off On(1) On(2) Available Available
In Run/Sleep mode On Available Available Available Available Available
In Stop mode Off Off Available(3) Available (4)
Available Available
In Standby mode Off Off Off Off Available Available
In VBAT mode Off Off Off Off Off Available
1. If STOPWUCK = 0.
2. If STOPWUCK = 1.
3. HSI can remain activated in Stop mode if HSISTOPEN = 1, or if a peripheral selecting HSI generates a kernel clock
request. Caution: HSI must be off if the PWR is programmed to use SVOS low.
4. MSI can remain activated in Stop mode if MSISTOPEN = 1, or if the peripheral selecting MSI generates a kernel clock
request. Caution: MSI must be off if the PWR is programmed to use SVOS low.

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HSE oscillator
The HSE allows the application to provide a very accurate high-speed clock for the device.
The HSE can generate an internal clock from two sources:
• external clock source (analog or digital)
• external crystal/ceramic resonator
Refer to the datasheet for the values of CL1, CL2, and R1.

Figure 38. HSE clock source

Digital external clock Analog external clock Crystal/ceramic resonator configuration

OSC_IN OSC_OUT OSC_IN OSC_OUT OSC_IN OSC_OUT

VDD

R1
R1

External digital clock External analog clock

CL1 CL2
source source Load
capacitors

MSv70470V2

External clock source (HSE bypass)

In this mode, the oscillator is not used, and an external clock source must be provided
to the OSC_IN pin. The external clock can be low swing (analog) or digital.
In order to allow the boot ROM to detect in which configuration the HSE is used, a resistor
(R1) must be connected to GND or VDD (see Figure 38).
The resistor must be connected to GND when the HSE uses an external digital clock, and
to VDD when the HSE is using an external analog clock. The resistor must be removed
if a crystal or ceramic resonator is used.
The external clock signal can be digital or analog (square, sinus, or triangle). An analog
clock signal with a reduced amplitude is supported thanks to an internal clock squarer.
The input signal must have a duty cycle close to 50% (refer to the datasheet for additional
information).
This mode is selected when HSEBYP = 1 in RCC_HSECFGR and HSEON = 1 in RCC_CR.
In case of an analog clock input (low swing) HSEEXT must be set to 0 in RCC_HSECFGR.
For a digital clock input, HSEEXT must be set to 1.

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Figure 39. HSE clock generation

HSEON HSEEXT HSEBYP HSERDY

hse_ck

clock squarer
HSEDIV2SEL
0
1 1 Tempo and
1
ready logic HSE_DIV2 hse_div2_osc_ck
OSC_IN HSE 0
0
OSC hse_osc_ck
OSC_OUT
HSE_CSS

HSE

rcc_hsecss_fail
RCC
MSv70471V3

External crystal/ceramic resonator

A crystal/resonator can be connected as shown in Figure 38: the crystal/resonator and the
load capacitors must be placed as close as possible to the oscillator pins in order to
minimize the output distortion and startup stabilization time. The loading capacitance values
must be adjusted according to the selected crystal or ceramic resonator. Refer to the
electrical characteristics section of the datasheet for more details.
The oscillator mode is enabled by setting HSEBYP = 0 and HSEON = 1.

HSE ready logic

The HSERDY flag indicates when a valid clock is available at HSE output (hse_ck). When
the HSE is enabled (HSEON = 1), the HSERDY flag goes to 1 when 1024 valid cycles of
HSE have been detected. The hse_ck clock is not released until HSERDY goes to 1.
An interrupt can be generated if enabled in RCC_CIER.

HSE controls
The HSE can be switched on and off through HSEON.
The HSE is automatically disabled by hardware when the system enters Stop or Standby
mode (see Table 69).
The HSE clock can also be driven to MCO1 and MCO2 outputs, and used as clock source
for other application components.
HSE programming sequence
In order to initialize the HSE, the application must follow this sequence:
1. Make sure the HSE is not directly or indirectly used as system clock. If it is, switch to
the HSI or MSI as clock source for system clock.
2. Disable the HSE by writing 0 to HSEON.
3. Check that the HSE is disabled by waiting HSERDY = 0.
4. If the oscillator mode is needed, select the oscillator mode with HSEBYP = 0.
5. If an external clock is connected to OSC_IN:
– Select the bypass mode by setting HSEBYP = 1.

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– If the input clock is a full-swing digital signal, set HSEEXT = 1.

– If the input clock is a low-swing signal, set HSEEXT = 0.
6. Enable again the HSE by writing 1 to HSEON.
7. Wait for HSERDY = 1, then the HSE is ready for use.

LSE oscillator
The LSE allows the application to provide a very accurate low-frequency clock for the
device. The LSE can generate an internal clock from two possible sources:
• external user clock
• external crystal/ceramic resonator

External clock source (LSE bypass)

In this mode, the oscillator is not used, and an external clock source must be provided to
the OSC32_IN pin. The OSC32_OUT pin must be left high-Z.
The external clock signal can have a frequency up to 32.768 kHz, and can be digital or
analog (square, sinus, or triangle). An analog clock signal with a reduced amplitude is
supported thanks to an internal clock squarer. The input signal must have a duty cycle close
to 50%. Refer to the datasheet for additional information.
This mode is selected by setting LSEBYP = 1 in RCC_LSECFGR, and LSEON = 1
in RCC_CR. In case of an analog clock input (low swing), LSEEXT must be set to 0
in RCC_LSECFGR. For a digital clock input, LSEEXT must be set to 1.

Figure 40. LSE clock generation

RCC LSEON
LSEEXT LSEBYP
clock squarer
LSE
VSW domain
0
1 LSERDY
1 Tempo and
ready logic lse_ck
OSC32_IN LSE 0
OSC
OSC32_OUT LSEDRV[1:0]

LSEGFON LSE_CSS
rcc_lsecss_fail

MSv70472V1

External crystal/ceramic resonator source (LSE crystal)

The LSE clock is generated from a 32.768 kHz crystal or ceramic resonator. It provides a
low-power highly accurate clock source to the RTC for clock/calendar, or other timing
functions. A crystal/resonator can be connected as shown in Figure 38. The
crystal/resonator and the load capacitors must be placed as close as possible to the
oscillator pins to minimize output distortion and startup stabilization time. The loading
capacitance values must be adjusted according to the selected crystal or ceramic resonator.
Refer to the electrical characteristics section of the datasheet for more details.
The oscillator mode is selected by setting LSEBYP bit to 0 and LSEON bit to 1.

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The LSE offers a programmable driving capability (LSEDRV in RCC_LSECFGR) to

modulate the amplifier driving capability. This driving capability is chosen according to the
external crystal/ceramic component requirement to ensure a stable oscillation.
The driving capability must be set before enabling the LSE oscillator.

Warning: The driving capability must not be changed when the LSE is
enabled. The LSE behavior is not guaranteed in that case.

LSE ready logic

The LSE offers an LSERDY flag, which indicates whether the LSE clock is available or not.
When the LSE is enabled (LSEON = 1), LSERDY goes to 1 in RCC_SR when a certain
number of valid LSE clock cycles has been detected. The lse_ck clock is not released until
LSERDY goes to 1.
When LSEBYP = 0, the RCC waits 4096 clocks cycles before activating the LSERDY flag.
When LSEBYP = 1, the RCC waits 16 clocks cycles.
An interrupt can be generated if enabled in RCC_CIER.

LSE controls
LSEBYP, LSEEXT, LSEDRV, and LSEON are write-protected by DBP in PWR_DBPCR.
In order to modify the bits, DBP must be set 1.
The LSE oscillator is switched on and off using the LSEON bit.
The LSE remains enabled when the system enters Stop, Standby, or VBAT mode (see
Table 69).
The LSE clock can also be driven to MCOx outputs, and used as clock source for external
components.

LSE programming sequence

To initialize the LSE, the application must follow the sequence hereafter:
1. Set DBP = 1 in PWR_DBPCR in order to allow write access.
2. Disable the LSE by writing to 0 to LSEON.
3. Check that the LSE is disabled by waiting LSERDY = 0.
4. If the oscillator mode is needed:
– Select the oscillator mode by setting LSEBYP = 0.
– Configure LSEDRV (if needed).
5. If an external clock is connected to OSC32_IN:
– Select the bypass mode by setting LSEBYP = 1.
– If the input clock is a full-swing digital signal, set LSEEXT = 1.
– If the input clock is a low-swing signal, set LSEEXT = 0.
6. enable again the LSE by writing 1 to LSEON.
7. Wait for LSERDY = 1, then the LSE is ready for use.
8. If no further changes are needed, set DBP = 0 in PWR_DBPCR to write-protect the
settings.

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If the RTC is used, the LSE bypass must not be configured in digital mode, but in low-swing
analog mode (default value after reset).

HSI oscillator
The HSI block provides the default clock to the device. It is a high-speed internal RC
oscillator that can be used directly as system clock, peripheral clock, or as PLL input.
A predivider allows the application to select an HSI output frequency of 8, 16, 32, or
64 MHz. This predivider is controlled by the HSIDIV in RCC_HSICFGR.
The HSI advantages are the following:
• low-cost clock source (no external crystals required)
• faster startup time than HSE (a few microseconds)
• reduced power consumption
The HSI frequency, even with frequency calibration, is less accurate than an external crystal
oscillator or ceramic resonator.

HSI controls
The HSI can be switched on and off using HSION in RCC_CR. The HSIRDY flag
in RCC_SR indicates if the HSI is stable or not. At startup, the HSI output clock is not
released until HSIRDY is set to 1 by hardware.
The HSI clock can also be used as a backup source (auxiliary clock) if the HSE fails
(see CSS on HSE).
The HSI can be disabled or not when the system enters Stop mode (see Table 69).
The HSI clock can also be driven to MCOx outputs, and used as clock source for other
application components.
Care must be taken when the HSI is used as kernel clock for communication peripherals.
The application must take into account the following parameters:
• the time interval between the moment where the peripheral generates a kernel clock
request, and the moment where the clock is really available
• the frequency accuracy

HSI calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations. That is why each device is factory calibrated by STMicroelectronics to achieve
an ACCHSI accuracy (refer to the product datasheet for more information).
After a power-on reset or pin reset, the factory calibration value is loaded in HSICAL[8:0]
in RCC_HSICFGR.
If the application is subject to voltage or temperature variations, this may affect the RC
oscillator frequency. The user application can trim the HSI frequency using HSITRIM[6:0]
in RCC_HSICFGR.

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Figure 41. HSI calibration flow

RCC
HSI
Engineering bsec_hsi_cal[8:0] hsi_cal[8:0]
option bytes CAL[8:0]
(factory calibration)
HSITRIM[6:0] HSICAL[8:0]
(signed) (unsigned)
RCC_HSICFGR

MSv70473V1

Note: The HSI clock divided by eight is also used for PAD compensation mechanism, and must be
enabled if the PAD compensation mechanism is activated. Refer to Section 16: System
configuration controller (SYSCFG) for additional details.

MSI oscillator
The MSI is a low-power RC oscillator that can be used directly as system clock, peripheral
clock, or PLL input.
However, the following point must be considered: If the MSI clock is currently used as kernel
clock for some peripherals, the application must ensure that the MSI frequency change
does not disturb these peripherals.
The MSI advantages are the following:
• low-cost clock source (no external crystals required)
• faster startup time than HSE (a few microseconds)
• very low-power consumption
The MSI provides a clock frequency of 4 MHz (default MSIFREQSEL) or 16 MHz, while the
HSI is able to provide a clock up to 64 MHz.
The MSI frequency, even with frequency calibration, is less accurate than an external crystal
oscillator or ceramic resonator.

MSI controls
The MSI can be switched on and off through the MSION in RCC_CR. The MSIRDY flag
in RCC_SR indicates whether the MSI is stable or not. At startup, the MSI output clock is not
released until MSIRDY is set by hardware.
The MSI can be disabled or not when the system enters Stop mode (see Table 69).
The MSI clock can also be driven to MCOx outputs, and used as clock source for other
application components.
Even if the MSI settling time is faster than the HSI, care must be taken when the MSI is used
as kernel clock for communication peripherals: the application must take into account the
following parameters:
• the interval between the moment when the peripheral generates a kernel clock request,
and the moment when the clock is really available
• the frequency precision

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RM0486 Reset and clock control (RCC)

MSI calibration
RC oscillator frequencies can vary because of manufacturing process variations. Each
device is factory calibrated by ST to achieve the specified ACCMSI accuracy (refer to the
product datasheet for more information).
After a power-on or pin reset, the factory calibration value for 4 MHz is loaded
in MSICAL[7:0] in RCC_MSICFGR.
If MSIFREQSEL is set to 16 MHz in RCC_MSICFGR, a different calibration value is
provided by the BSEC.
Voltage or temperature variations can affect the RC oscillator frequency. The user
application can trim the MSI frequency using MSITRIM[4:0] in RCC_MSICFGR.

Figure 42. MSI calibration flow

MSIFREQSEL
BSEC
MSI
Engineering msi_trim_4mhz[7:0]
0 msi_cal[7:0]
option bytes 1
CAL[7:0]
(factory calibration) msi_trim_16mhz[7:0]

MSITRIM[4:0] MSICAL[7:0]
(signed) (unsigned)
RCC_MSICFGR
RCC
MSv70474V2

HSIS oscillator
The HSIS is a 64 MHz RC oscillator to clock only the BSEC. It is always activated after
pwr_por_rstn or app_rstn reset.
When the system goes into Stop or Standby mode, the HSIS clock is disabled by hardware.
Refer to Section 14.6.7 for additional information.

HSIS calibration
RC oscillator frequencies can vary from one device to another, due to manufacturing
process variations. To compensate for this, there is an HSISCAL[8:0] input on the oscillator.
The BSEC provides two calibration values (ambient and not ambient). The RCC selects
between these two values using a select signal from the BSEC.
After a power-on reset, or pad reset, the factory calibration value is loaded in HSISCAL[8:0].

LSI oscillator
The LSI acts as a very low-power clock source that can be kept running when the system
is in Stop or Standby mode for the IWDG and the auto-wake-up unit (AWU). The clock
frequency is around 32 kHz. For more details, refer to the electrical characteristics section
of the datasheet.
The LSI can be switched on and off using LSION. The LSIRDY flag indicates whether the
LSI oscillator is stable or not. If an independent watchdog is started either by hardware or
software, the LSI is forced on, and cannot be disabled.

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The LSI remains enabled when the system enters Stop or Standby mode (see Table 69).
At LSI startup, the clock is not provided until the hardware sets LSIRDY. An interrupt can be
generated if enabled in RCC_CIER.
Te LSI clock can also be driven to MCOx outputs, and used as a clock source for other
application components.

14.6.3 Clock security system (CSS)

The CSS can detect a failure of either (or both) LSE and HSE oscillators. There are signals
that can be connected to the TAMP (rcc_lsecss_fail and rcc_hsecss_fail), and signals for
the interrupt controller (rcc_lsecss_it, rcc_hsecss_it, and rcc_it).

CSS on HSE
The CSS can be enabled by software via HSECSSON. This bit can be enabled even when
HSEON = 0.
The CSS on HSE is activated when the HSE is enabled and ready, and when the software
sets HSECSSON = 1. The CSS on HSE does no longer work when the HSE is disabled.
For example, this function does not work when the system is in Stop mode.
HSECSSON cannot be cleared directly by software. It is cleared by hardware when a
system reset occurs, or when the system enters Standby mode (see Section 14.5.2).
On an HSE failure, an HSI injection feature can automatically inject a divided HSI clock in
replacement at the root of the HSE tree. Users of the failed HSE keep running, but
potentially at a slightly lower frequency. The HSI injected clock is adapted to the HSE
frequency by an integer division. The PLLs relocks, but at the same or lower speed.
To enable the automatic HSI injection, first configure HSECSSBPRE in RCC_HSECFGR,
then set HSECSSBYP = 1.
The HSI division ratio is configured with HSECSSBPRE. For instance, with the HSI
at 64 MHz and an HSE at 48 MHz, the division ratio must be configured to 2x
(HSECSSBPRE = 1): a failed HSE is replaced by a clock at 64 / 2 = 32 MHz.
When the CSS on HSE is enabled, the following actions are done by the RCC if a failure is
detected:
• If the HSI injection feature is enabled, the HSI oscillator is forced active, and the HSE
clock is replaced by hsi_css_ck.
• rcc_hsecss_fail is asserted.
• The clock failure event (rcc_hsecss_fail) is also sent to the break inputs of
advanced-control timers (TIM1/8/15/16/17).
• An NMI interrupt is generated to inform the software about the failure (rcc_hsecss_it).
This allows the MCU to perform rescue operations. The NMI interrupt is asserted until
HSECSSF = 0 in RCC_CICR. The HSECSSF flag can be cleared by setting
HSECSSC = 1.
• A tamper event can also be triggered to clear content of backup registers and
BKPSRAM.

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CSS on LSE
A CSS on the LSE oscillator can be enabled by software by programming LSECSSON. This
bit is disabled by hardware if one of the following conditions is met:
• after a VSW hardware reset (pwr_vsw_rst)
• after a VSW software reset via VSWRST bit
The software can also disable the CSS after an LSE failure detection.
The CSS on LSE works in all modes (Run, Stop, and Standby modes) including VBAT mode.
The LSECSS provides a re-arm feature, offering the possibility to the software to re-arm
the LSECSS, and to re-enable the LSE clock when a failure has been detected. This feature
allows the application to decide if the LSE must be provided again to the RTC even
if a failure occurred, or if another action must be performed. For example, the application
can decide to reset the VSW domain only if a certain number of consecutive LSE failures
occurred, within a time window.
The LSECSS offers two flag signals:
• the LSECSSD able to retain an LSE failure even in VBAT mode
• the LSECSSF used to generate an interrupt in case of LSE failure (flag not affected
by a failure detected when the product is in VBAT mode)
The sequence hereafter describes the LSE that enables sequence with the CSS enabled:
1. Follow the LSE enable procedure given in LSE programming sequence, except
the last step.
2. Select the LSE clock via RTCSEL[1:0].
3. Set the LSECSSON bit to 1.
4. If no further changes are needed, clear DBP to 0 in PWR_DBPCR to write-protect
accesses.
Note: The LSECSSON bit must be enabled after the LSE is enabled (LSEON set by software) and
ready (LSERDY set by hardware), and after the RTC clock has been selected
through RTCSEL.
If a failure is detected on the LSE, the hardware does the following:
• The LSE clock is no more delivered to the RTC.
• RTCSEL, LSECSSON, and LSEON are not changed by the hardware.
• A failure event is generated (rcc_lsecss_fail). This event allows the system to wake up
from Standby mode, but also to protect the backup registers and BKPSRAM via TAMP.
This event is also generated in VBAT mode.
• The LSECSSF is activated (except in VBAT mode) in order to generate an interrupt
(rcc_lsecss_it, enabled by LSECSSIE).
• The LSECSSD is activated as well, retaining the first LSE failure even in VBAT mode.
On the software side, different actions can be taken according to the application
requirements. Three different cases are described hereafter in order to illustrate the
hardware behavior, they can also be combined. The application can also decide to handle
LSE failure differently.
Case A
The application no longer wants to use LSE when a failure is detected:
1. Unlock registers by setting DBP in PWR_DBPCR to 1.

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2. Disable the CSS function (this step is mandatory):

a) Clear LSECSSF if the interrupt was enabled for this event.
b) Clear LSECSSON to 0.
c) Clear LSEON to 0 in order to disable the LSE.
3. Change the clock source for the RTC if needed:
a) Clear RTCEN to 0 to disable the RTC clock.
b) Enable the new clock source for the RTC.
c) Set RTCPRE if HSE is a new clock source.
d) Select the proper clock source via RTCSEL.
e) Set RTCEN to 1 to enable the RTC clock.
4. The application must perform specific actions for TAMP events if enabled
(see Section 4: Boot and security control (BSEC) and Section 61: Real-time clock
(RTC)).
• Lock registers by clearing DBP to 0 in PWR_DBPCR
Case B
The application wants to re-initialize the VSW domain:
1. Unlock registers by setting the DBP bit of PWR_DBPCR to 1
2. Perform a VSW reset by setting VSWRST bit to 1, then back to 0.
3. The application must perform specific actions for TAMP events if enabled
(see Section 4: Boot and security control (BSEC) and Section 61: Real-time clock
(RTC)).
4. Re-initialize all components of the VSW domain.
5. Lock registers by clearing DBP to 0 in PWR_DBPCR.
Case C
The application tries to reuse LSE when a failure is detected:
1. If the number of failures in a given time window is higher than a given threshold then
go to case A or B. Otherwise, continue to next step.
2. Unlock registers by setting DBP to 1 in PWR_DBPCR.
3. Clear LSECSSF if interrupt was enabled for this event.
4. The application must perform specific actions for TAMP events if enabled
(see Section 4: Boot and security control (BSEC) and Section 61: Real-time clock
(RTC)).
5. Clear LSECSSON to 0.
6. Rearm the LSECSS function by writing 1 to LSECSSRA, then back to 0.
7. Wait for LSERDY = 1. The LSERDY flag must go to 1 after the oscillator settling time
delay plus, 4096 periods of LSE clock. If it is not the case, it probably means that
the LSE failure is permanent. LSECSSON cannot be set to 1. It is recommended
to execute case A or B.
8. Set LSECSSON to 1.
9. When LSECSSON = 1, the LSE is enabled, and protected by LSECSS.
10. Lock registers by clearing DBP to 0 in PWR_DBPCR.

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14.6.4 Clock output generation (MCO1/MCO2)

There are two MCO1 and MCO2 microcontroller clock output pins. A clock source can be
selected for each [Link] selected clock can be divided thanks to a configurable
prescaler (refer to Figure 37 for additional information on signal selection).
MCO1 and MCO2 are enabled using MCO1EN and MCO2EN in RCC_MISCENR.
The GPIO port corresponding to each MCO pin must be programmed in alternate
function mode.
MCO1 and MCO2 are controlled via MCO1PRE[3:0], MCO1SEL[2:0], MCO2PRE[3:0], and
MCO2SEL[2:0] located in RCC_CCIPR5.
MCO1PRE and MCO2PRE dividers provide a clock with a duty cycle of 50% for even
divisions values, and around 53% for odd division values.
Note: MCO1 and MCO2 are available in Run, Stop, and Sleep modes.
Caution: The clock provided to the MCOx outputs must not exceed the maximum pin speed (refer to
the product datasheet for information about the supported pin speed).
Table 70 shows the signals available on each MCO output.

Table 70. Clock output selection

MCO1SEL MCO2SEL

Position Clock source Position Clock source

0 hsi_div_ck 0 hsi_div_ck
1 lse_ck 1 lse_ck
2 msi_ck 2 msi_ck
3 lsi_ck 3 lsi_ck
4 hse_ck 4 hse_ck
5 ic5_ck 5 ic15_ck
6 ic10_ck 6 ic20_ck
7 sysa_ck 7 sysb_ck

14.6.5 PLL description

The RCC features four PLLs with the same features.
A typical allocation is:
• PLL1, clocks to the CPU, buses, and storage (XSPI, SDMMC)
• PLL2, clocks to NPU and audio peripherals
• PLL3, clocks to CACHEAXI RAM and Ethernet
• PLL4, clocks to display, camera, FDCAN, and other peripherals
Each PLL has the following features:
• FREF frequency range:
– 5 to 1200 MHz in integer mode
– 10 to 1200 MHz in fractional mode
• VCO frequency range from 800 to 3200 MHz
• Three working modes:

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– fractional mode, using a 24-bit delta-sigma modulator (DSM)

– integer mode
– spread spectrum mode to reduce EMI. The fully digital spread spectrum clock
generator (SSCG) is used in that case.
The internal post-dividers (POSTDIV1, POSTDIV2) are powered-off by default. They must
be powered-on when the PLL is in use (PLLxPDIVEN).
The active post-dividers (ICx) are outside the PLL design. Each post-divider has a 4-way
multiplexer before it, which can select any PLL output as input.
The DIVMx divider in RCC_PLLxCFGR1 must be properly programmed to keep the PFD
input frequency below 50 MHz.

Figure 43. PLL block diagram

VDDA0V8 VDDA1V8

PLLON PLL
FOUTPOSTDIVEN
Lock detect LOCK
DACEN
MODDSEN
800 to 3200 MHz BYP
5 to 1200 MHz
FREF ÷1..63
PFD CP LPF VCO ÷ 1-7 ÷ 1-7 0
FOUTPOSTDIV
DIVM[5:0] FREF 1
DAC POSTDIV1[2:0]=1
FBDIV[11:0] POSTDIV2[2:0]=1
MODDIV[3:0] SSCG ǻȈmodulator
MODSPR[4:0] FRAC[23:0]
(DSM)
MODSPRDW
÷1..15
DIVN[11:0] [11:0]
DIVNFRAC[23:0]
÷16..640 integer
MODSSDIS ÷20..320 fractional
CLKSSCG
MODSSRST
MSv70475V2

The PLL is enabled by setting PLLxON to 1 in RCC_CR. PLLxRDY in RCC_SR indicates

that the PLL is ready (locked).
The DIVNx loop divider must be programmed to achieve the expected VCO output
frequency before enabling the PLL. Changing the value on-the-fly can result in a spike on
the VCO output proportional to the PFD frequency step. A frequency step of more than
0.01% per PFD clock period must be avoided. The SSCG typically steps the frequency by
less than 0.005% per PFD clock period, so does not generate spikes.
The VCO output range must be respected.
The clock from FOUTPOSTDIV has a 50% duty-cycle (± 3%).
The ICx post-dividers provide clocks with 50% duty-cycle when dividing by an even value.
If an ICx post-divider enable is set to 0, its value can be changed without disabling any PLL.
The PLLs are disabled by hardware when the system enters Stop or Standby mode.
PLLs using HSE as reference clock are also disabled by hardware if an HSE failure is
detected.

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PLL programming recommendations

• Before enabling the PLLs, the user must ensure that the reference frequency (FREF)
provided to the PLL is stable and in the correct range.
• POSTDIV1 and POSTDIV2 must be set to 1.
• PLLxPDIVEN must be set to 1 to output the clock FOUTPOSTDIV.
• When a PLL output is used, PLLxON and PLLxRDY must be set to 1. The application
can then set any connected post-divider enable bits to 1 (in RCC_DIVEN).
• When a PLL output is not used, PLLxON must be cleared to 0. The application must
also set any connected post-divider enable bits to 0 (in RCC_DIVEN).
Caution: The 4 MHz setting for the MSI oscillator cannot be used as FREF.
The PLLs can work in three different modes:
• integer
• fractional
• spread spectrum

Using PLLs in integer mode

The PLLx works in integer mode when the delta-sigma modulator (DSM) is loaded
with a 0 value, and PLLxMODSSDIS = 1.
To load 0 into the DSM and to set DIVN, use the following sequence:
1. Clear PLLxON to 0.
2. Set DIVN value (valid range 16 to 640).
3. Clear DIVNFRAC (in RCC_PLLxCFGR2) and PLLxMODDSEN to 0.
4. Set PLLxMODSSRST to 1.
5. Set PLLxON to 1.
Caution: Do not update DIVN after the PLL has been enabled.
The VCO frequency (FVCO) and output frequency expressions are the following:

DIVN
F VCO = F REF × ----------------
DIVM

F VCO
F OUTPOSTDIV = ----------------------------------------------------------------
-
POSTDIV1 × POSTDIV2
Using the PLLs in fractional mode
This mode is enabled when DSM ≠ 0, PLLxMODDSEN = 1, and PLLxMODSSDIS = 1.
To load the value into the DSM perform the following sequence:
1. Clear PLLxON to 0.
2. Set DIVN value (valid range 20 to 320).
3. Set DIVNFRAC (in RCC_PLLxCFGR2) to the required value, and set
PLLxMODDSEN = DACEN 1.
4. Set PLLxMODSSRST to 1.
5. Set PLLxON to 1.

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Caution: Do not update DIVN and DIVNFRAC after the PLL has been enabled.
The minimum FREF is 10 MHz in fractional mode.
The VCO frequency (FVCO) and output frequency expressions are the following:

⎛ DIVNFRAC⎞
⎜ DIVN + ------------------------------------⎟
⎝ 24 ⎠
2
F
VCO
= F REF × ------------------------------------------------------
DIVM

F VCO
F OUTPOSTDIV = -----------------------------------------------------------------
-
POSTDIV1 × POSTDIV2

Using PLLs in spread spectrum mode

The spread spectrum mode is activated when the DSM is loaded with 0, and
PLLxMODSSDIS is cleared to 0. This feature is available for all PLLs.
The spread spectrum method is to modulate the VCO frequency with a low-frequency
triangular signal, in order to spread the clock energy into a wider frequency band.
The amount of emitted EMI is then reduced.
The spread spectrum modulation is adjusted using the following fields:
• MODDIV[3:0] to adjust the modulation frequency
• MODSPR[4:0] to adjust the modulation depth (or modulation index)
• MODSPRDW to define if the modulation is centered around the VCO frequency
(center-spread), or lowered with respect to VCO frequency (down-spread)
MODDIV[3:0], MODSPR[4:0] and MODSPRDW are in RCC_PLLxCFGR3.
Figure 44 shows the SSCG modulating the nominal frequency (FN), when MODSPRDW = 0
(center-spread), and MODSPRDW = 1 (down-spread). The nominal frequency is that output
by the PLL in integer mode, when no clock spreading is applied.
Down-spread guarantees that the PLL output frequency does not exceed the programmed
frequency value when SSCG is enabled.

Figure 44. Spread spectrum modulation

Frequency FMOD Frequency FMOD

FN

MD

FN t
MD
t

MD

Center-spread Down-spread
MSv70476V1

The peak modulation depth (in percentage) is given by the formula MD (%) = MODSPR /10.

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Note: Modulation is turned off when MODSPR = 0.

The modulation frequency (FMOD) is given by:
F CLKSSCG
F MOD = --------------------------------------
-
128 × MODDIV

where 128 is the number of points in the internal wave table.

Note: When the PLL is locked, FCLKSSCG = FPFD. The upper limit of the frequency of modulation
(FMOD) is set by the PLL bandwidth. The PLL bandwidth limits the maximum modulation to
FCLKSSCG / 200, where FCLKSSCG = FREF / DIVM or 50 MHz, whichever is lower.
To use the spread spectrum feature, to do the following:
1. Program the PLL to the nominal frequency (FN) using the FOUTPOSTDIV formula
from Using PLLs in integer mode
2. Compute the MODDIV value according to the desired modulation frequency (FMOD):
⎛ F CLKSSCG ⎞
MODDIV = ROUND ⎜ ------------------------------⎟
⎝ 128 × F MOD⎠

3. Compute the MODSPR value according to the desired modulation depth (MD).
4. Set the MODSPRDW value according to the desired modulation type (center-spread or
down-spread).
5. Compute DIVN accordingly (DIVNFRAC=0):
⎛ F N × DIVM⎞
DIVN = ROUND ⎜ ---------------------------⎟
⎝ F REF ⎠

6. Clear PLLxMODSSDIS, PLLxMODDSEN, and DACEN to 0.

7. Set PLLxMODSSRST to 1, and clear PLLxON to 0. PLLxON must be held at 0 for 1 μs
to make sure the PLL is fully reset.
8. Set PLLxON, PLLxMODDSEN, and DACEN to 1 (see Note:).
9. Wait until the first edge of CLKSSCG, and then clear PLLxMODSSRST to 0 (this can be
done before or after the PLL is locked).
Note: The spread spectrum accuracy relies on the PLL fractional-N capability, so MODDSEN and
DACEN must be set to 1.
The user can check FMIN, FMAX as follows:
• Calculate FN as above.
• If MODSPRDW = 0 (center-spread):
FMIN = FN x (1 - MD / 100) and FMAX = FN x (1 + MD / 100)
• If MODSPRDW = 1 (down-spread):
FMIN = FN x (1 - MD / 100) and FMAX = FN

Programming sequence for spread spectrum mode

The programming sequence to enable SSCG and the PLL is:
1. Deassert PLLxMODSSRST.
2. Set PLLxDIVN, PLLxDIVNFRAC, and PLLxMODSSDIS to 0.

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3. Assert PLLxMODDSEN and PLLxDACEN.

4. Assert PLLxMODSSRST and deassert PLLxON.
5. PLLxON must be deasserted for 1µs to make sure PLL is fully reset.
Then assert PLLxON.
6. Wait until PLLxRDY is asserted, then deassert PLLxMODSSRST.

14.6.6 System clocks

System clock selection
After a system reset, the HSI is selected as system clock (sys[a,b,c,d]_ck), and all PLLs are
switched off.
The system clock can be stopped by hardware when the system enters Stop or
Standby mode.
When the system runs, the user can select system clocks (sys[a,b,c,d]_ck) from the four
following sources:
• HSE
• HSI
• MSI
• ic[1,2,6,11]_ck
This function is controlled by programming RCC_CFGR1. A switch from one clock source
to another occurs only if the target clock source is ready (clock stable after startup delay or
PLL locked). If a clock source that is not yet ready is selected, the switch occurs when
the clock source is ready.
The SYSSW only selects the ic[2,6,11]_ck if all three IC dividers are enabled.
SWS bits in RCC_CFGR1 indicate which clock sources are currently selected. Other status
bits in RCC_CR indicate which clock(s) is (are) ready.

System clock generation

Figure 45 shows a simplified view of the clock distribution for the CPU and buses. All the
dividers shown in the block diagram can be changed on-the-fly, without generating timing
violations. This feature is a very simple solution to adapt bus frequencies to application
needs, thus optimizing the power consumption.
The AXI sys_bus_ck is divided by HPRE to generate the AHB clock. HPRE is controlled
by RCC_CFGR2.
In addition to the divide values shown, PPRE1, PPRE2, PPRE4, and PPRE5 can divide
by 32, 64, and 128.
There is almost no clock protection, so the software must avoid configurations that can
block the system.
Note: The application must respect the maximum allowed frequencies: FCPUmax and FBUsmax.
FBUS represents the maximum allowed frequency for AHB and AXI buses (refer to
the datasheet for the maximum values).
The trace clock (ck_cpu_tpiu) is generated from sys_cpu_ck clock, divided by eight. For
additional information, refer to Clock distribution for trace and debug.

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Figure 45. Core and bus clock generation

RCC System clock generation (SCGU)

÷8 ck_cpu_tpiu (50% duty cycle)

÷8 ck_cpu_systck (enable 1/8)

CPUSW FCPUmax CPU

÷ 12 ck_cpu_tsgen
DEEP
hsi_ck 0 SLEEP ck_cpu_dbg
msi_ck 1 sysa_ck sys_cpu_ck
D CT ck_cpu
hse_ck 2
ic1_ck 3 aclkc
AXI CPU

aclks
CT AXI domain CPU/GPU

aclka
sys_bus_ck

SYSSW CT AXI domain cam/disp/VENC

aclkn AXI domain NPU cache

hsi_ck 0 CT
FBUSmax and TCM
msi_ck 1 sysb_ck
D CPU S-AHB (TCM)
hse_ck 2 TIMPRE
3 ck_timg1
ic2_ck CT ÷ 1,2,4,8 Timer group1

ck_timg2
Timer group2

SCEU (system cLock enabling)

ck_bus2_dbg
HPRE CT System debug clock (dbg, dap)
hclk

hclkm
÷ 1,2,4,8,16 AHBM main matrix
sys_bus2_ck hclk[5:0]
AHB0/1/2/3/4/5 peripheral clocks

CPU P-AHB (peripheral bus)

PPRE1

pclk1
÷ 1,2,4,8,16 APB1 peripheral clocks

FBUSmax / 2 PPRE2
pclk2
÷ 1,2,4,8,16 APB2 peripheral clocks

PPRE4
pclk4
hsi_ck 0 ÷ 1,2,4,8,16 APB4 peripheral clocks
msi_ck 1 sysc_ck sys_npu_ck
D PPRE5
hse_ck 2 pclk5
÷ 1,2,4,8,16 APB5 peripheral clocks
ic6_ck 3
hclku
CT USB/SDMMC peripheral clocks

hclke
CT Ethernet peripheral clocks
hsi_ck 0
msi_ck 1 sysd_ck sys_npur_ck
D CT NPU
hse_ck 2

ic11_ck 3 AXI domain NPU

AXISRAM3/4/5/6 clocks
(close to NPU)
MSv70477V2

x Represents the selected value after a system reset. D The switch is dynamic: the transition between two inputs is glitch-free.
CT Represents a cLock tree balancing, with an alignment of the downstream synchronous logic.

1. Dividers values can be changed on-the-fly. All dividers have 50% duty-cycles.

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14.6.7 Clock generation in Stop and Standby modes

When the system enters Stop mode, all clocks (system and kernel) are stopped, and
the following clock sources are disabled as well:
• MSI, HSI
• HSE
• PLL1, PLL2, PLL3, PLL4
Note: The MSI and HSI stay active based on xxxSTOPEN bits in RCC_STOPCR.
HSIS is also disabled.
The content of the RCC registers is not altered, except CPUSW and SYSSW, forced to HSI
or MSI (depending on STOPWUCK value), and PLLxON and HSEON, set to 0.
HSION and MSION are also modified, depending on STOPWUCK (see Table 71).
When the CPU requests to go in Stop mode, the RCC first stops all requested clocks, and
informs the PWR that all clocks have been properly stopped. As shown in Figure 46,
three main signals are used to control power transitions:
• rcc_pwrds: used to indicate to the PWR that the RCC stopped all clocks. The PWR can
then go to Stop or Standby mode.
• pwr_wkup is used to indicate to the RCC to re-enable the clocks.
• The exti_wkup is used to indicate to the PWR that an event requests to exit the system
from Stop mode.

Figure 46. Key signals controlling low-power modes

exti_wkup pwr_wkup
EXTI PWR RCC
Wake-up
events ...
rcc_pwrds

sys_ck
MSv70478V1

Exiting Stop mode

When the device exits system Stop mode via a wake-up event, HSIS is started
automatically.
Note: sys_rst is only deasserted after HSIS has successfully started.
The application can select which other oscillator (HSI and/or MSI) is used to restart
the system. STOPWUCK in RCC_CFGR1 selects the oscillator used as system clock.
Table 71 describes their behavior.

Table 71. STOPWUCK description

Distributed clocks when system exits Stop mode
Activated oscillator when
STOPWUCK -
system exits Stop mode
System clock Kernel clock

0 → HSI HSI HSI

1 → MSI MSI MSI

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During Stop mode

There are two specific cases where the HSI or MSI can be enabled during system Stop
mode:
• When a dedicated peripheral requests the kernel clock, the peripheral receives the HSI
or MSI according to the kernel clock source selected for this peripheral (via PERxSEL).
• When HSISTOPEN or MSISTOPEN are set in RCC_STOPCR, the HSI and MSI are
kept running during Stop mode but the outputs are gated. The clock is then available
immediately when the system exits Stop mode, or when a peripheral requests
the kernel clock (see Table 72 for details).
Caution: HSI and MSI are always off in Stop mode when the PWR is set to SVOS low.

Table 72. HSISTOPEN and MSISTOPEN behavior

HSISTOPEN (MSISTOPEN) - HSI (MSI) state during Stop mode HSI (MSI) setting time

0 → Off tsu(HSI) (tsu(MSI)) (1)

1 → Running and gated Immediate
1. tsu(HSI) and tsu(MSI) are the startup times of the HSI and MSI oscillators (see the datasheet for their values).

When the microcontroller exits Standby mode, the HSI is selected as system and kernel
clock. RCC registers are reset to their initial values except for the backup domain
configurations (LSE in RCC_CR/RCC_LSECFGR, RTC in RCC_CCIPR7, RCC_BDCR),
and the reset cause (RCC_RSR, RCC_HWRSR).
Caution: When leaving Stop mode without reset (but not from Standby mode), the RCC returns in the
same state as before, except for the software that has been forced to select the
STOPWUCK source. When leaving Standby mode, the application can restore previous
CPU clock settings, if needed.
Caution: If the system clock switch selection (SYSSW) is HSI or MSI oscillator, STOPWUCK (system
clock selection after a wake-up from system Stop) must select the same oscillator.

14.6.8 Peripheral clock distribution

Some peripherals are designed to work with two different clock domains, operating
asynchronously:
• a domain synchronous with the register and bus interface (ckg_bus_perx clock)
• a domain generally synchronous with the peripheral (kernel clock)
Other peripherals only need a bus interface clock, hence the user application has more
freedom to choose an optimized clock frequency for the CPU, bus matrix, and for the kernel
part of the peripheral. The user can change the bus frequency without reprogramming
peripherals (example: an ongoing transfer with UART is not disturbed if its APB clock is
changed on-the-fly).
Table 73 summarizes the clocks from RCC to the peripherals. The clock named per_ck is
the output of a mux (see Figure 37).

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Table 73. Peripheral clock distribution summary

Kernel clock MUX Max kernel
Clock Type
Peripherals Clock source clock frequency (1)(2)
type
Position Control field (in MHz)

hclk2 0(3)
per_ck 1
ic7_ck 2
ic8_ck 3
Kernel ADF1SEL 200 A
ADF1 msi_ck 4
hsi_div_ck 5
I2S_CKIN 6
timg_ck 7
Bus hclk2 - - 200 -
hclk1 0(3)
per_ck 1
ic7_ck 2
ic8_ck 3
Kernel ADC12SEL 125 A
ADC12 msi_ck 4
hsi_div_ck 5
I2S_CKIN 6
timg_ck 7
Bus hclk1 - - 200 -
sys_bus_ck - - 400 -
CACHEAXI Bus
hclk5 - - 200 -
CRC Bus hclk4 - - 200 -
CRYP Bus hclk3 - - 200 -
Kernel sys_cpu_ck - - 800 A
DBG
Bus ck_bus2_dbg - - 200 -
Kernel hsi_div8_ck - - 10 A
DTS
Bus pclk4 - - 100 -
Kernel as DCMIPP - DCMIPPSEL - A
CSI
Bus pclk5 - - 200 -
Kernel ic18_ck - - 27 A
CSIPHY
Bus pclk5 - - 200 -

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Table 73. Peripheral clock distribution summary (continued)

Kernel clock MUX Max kernel
Clock Type
Peripherals Clock source clock frequency (1)(2)
type
Position Control field (in MHz)

pclk5 0
per_ck 1
Kernel DCMIPPSEL 333 A
ic17_ck 2
DCMIPP
hsi_div_ck 3
sys_busa_ck - - 400 -
Bus
pclk5 - 200
GPDMA1 Bus hclk1 - - 200 -

HPDMA1 Bus hclk5 - - 200 -

hclk5
DMA2D Bus - - 200 -
aclk
Kernel hsi_div8_ck - - 10 A
DTS
Bus pclk4 - - 200 -
ETH1_TX_CLK - - 25 A
ETH1_RX_CLK/ETH1
0(3)
_REF_CLK
ETH1REFCLKSEL 125 A
eth1_clk_fb 1

sys_bus2_ck 0(3)
per_ck 1
Kernel ETH1CLKSEL 125 A
ETH1 ic12_ck 2
hse_ck 3
sys_bus2_ck 0
per_ck 1
ETH1PTPSEL 200 A
ic13_ck 2
hse_ck 3
Bus hclk1 - - 200 -
EXTI Bus pclk4 - - 125 -
pclk1 0(3)
per_ck 1
Kernel FDCANSEL 150 A
FDCAN ic19_ck 2
hse_ck 3
Bus pclk1 - - 200 -

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Table 73. Peripheral clock distribution summary (continued)

Kernel clock MUX Max kernel
Clock Type
Peripherals Clock source clock frequency (1)(2)
type
Position Control field (in MHz)

hclk5 0(3)
per_ck 1
Kernel FMCSEL 200 A
ic3_ck 2
FMC
ic4_ck 3
sys_buss_ck -
Bus - 400 -
hclk5
GPIOA-H, GPION-Q Bus hclk4 - - 200 -

GPU2D Bus sys_buss_ck - - 400 -

sys_buss_ck
GFXMMU Bus - - 400 -
hclk5
GFXTIM Bus pclk5 - - 200 -
HASH Bus hclk3 - - 200 -
pclk1 0(3)
per_ck 1
ic10_ck 2 I2C1SEL, I2C2SEL,
I2C1, I2C2, Kernel 100 A
ic15_ck 3 I2C3SEL
I2C3
msi_ck 4
hsi_div_ck 5
Bus pclk1 - - 100 -
(3)
pclk1 0
per_ck 1
ic10_ck 2
Kernel I2C4SEL 100 A
I2C4 ic15_ck 3
msi_ck 4
hsi_div_ck 5
Bus pclk4 - - 100 -
pclk1 0(3)
per_ck 1
ic10_ck 2
Kernel I3C1SEL, I3C2SEL 100 A
I3C1, I3C2 ic15_ck 3
msi_ck
hsi_div_ck
Bus pclk1 - - 100 -

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Table 73. Peripheral clock distribution summary (continued)

Kernel clock MUX Max kernel
Clock Type
Peripherals Clock source clock frequency (1)(2)
type
Position Control field (in MHz)

Kernel lsi_ck - - 1 A
IWDG
Bus pclk4 - - 100 -
JPEG Bus hclk5 - - 200 -
pclk1 0(3)
per_ck 1
ic15_ck 2
Kernel LPTIM1SEL 200 A
LPTIM1 lse_ck 3
lsi_ck 4
timg_ck 5
Bus pclk1 - - 200 -
(3)
pclk4 0
per_ck 1
LPTIM2SEL.
ic15_ck 2 LPTIM3SEL.
LPTIM2, LPTIM3, Kernel 200 A
lse_ck 3 LPTIM4SEL,
LPTIM4, LPTIM5 LPTIM5SEL
lsi_ck 4
timg_ck 5
Bus pclk4 - - 200 -
(3)
pclk4 0
per_ck 1
ic9_ck 2
Kernel ic14_ck 3 LPUART1SEL 100 A
LPUART1
lse_ck 4
msi_ck 5
hsi_div_ck 6
Bus pclk4 - - 100 -
pclk5 0
per_ck 1
Kernel LTDCSEL 86 A
ic16_ck 2
LTDC
hsi_div_ck 3
pclk5 - - 200
Bus -
sys_busa_ck - - 400
As XSPI1, XSPI2,
aclk -
MCE1, MCE2, MCE3 Bus XSPI3 200 -
hclk5 -

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Table 73. Peripheral clock distribution summary (continued)

Kernel clock MUX Max kernel
Clock Type
Peripherals Clock source clock frequency (1)(2)
type
Position Control field (in MHz)

aclk - As FMC
MCE4 Bus 200 -
hclk5 -
hclk2 0(4)
per_ck 1
ic7_ck 2
ic8_ck 3
Kernel MDF1SEL 200 A
MDF1 msi_ck 4
hsi_div_ck 5
I2S_CKIN 6
timg_ck 7
Bus hclk2 - - 200 -
MDIOS Bus pclk1 - - 200 -
sys_npu_ck - - 1000 A
Kernel
sys_npur_ck - - 900 A
NPU
sys_bus_ck - - 400
Bus
sys_bus2_ck - - 200 -
hse_div2_ck 0(3)
per_ck 1 OTGPHY1SEL,
Kernel 48 A
ic15_ck 2 OTGPHY2SEL
OTGPHY1,
hse_div2_osc_ck 3
OTGPHY2
otgphy1_ker_ck, OTGPHY1CK
0
otgphy2_ker_ck REFSEL,
Kernel 200 -
OTGPHY2CK
hse_div2_osc_ck 1 REFSEL,
Kernel phyclock - - 60 A
OTG1, OTG2
Bus hclku - - 200 -
PKA Bus hclk3 - - 200 -
PWR Bus hclk4 - - 200 -
(3)
hclk5 0 -
per_ck 1 -
Kernel PSSISEL 40
PSSI ic20_ck 2
hsi_div_ck 3
Bus hclk5 - - 200 -
RCC Bus hclk - - 200 -

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Table 73. Peripheral clock distribution summary (continued)

Kernel clock MUX Max kernel
Clock Type
Peripherals Clock source clock frequency (1)(2)
type
Position Control field (in MHz)

Kernel hsis_osc_ck - - 64 A
RNG
Bus hclk3 - - 200 -
no clock 0(3)
lse_ck 1
Kernel lsi_ck 2 RTCSEL 4 A
RTC(5)
hse_ker_ck /
3
(RTCDIV+1)
Bus pclk4 - - 100 -
Kernel hclk3 - - 200 A
SAES
Bus hclk3 - - 200 -
(3)
pclk2 0
per_ck 1
ic7_ck 2
ic8_ck 3
Kernel SAI1SEL, SAI2SEL 200 A
SAI1, SAI2 msi_ck 4
hsi_div_ck 5
I2S_CKIN 6
spdif_symb_ck 7
Bus pclk2 - - 200 -
(3)
sys_bus2_ck 0
per_ck 1
Kernel SDMMC1SEL 208 A
SDMMC1 ic4_ck 2
ic5_ck 3
Bus sys_bus2_ck - - 200 -
(3)
sys_bus2_ck 0
per_ck 1
Kernel SDMMC2SEL 208 A
SDMMC2 ic4_ck 2
ic5_ck 3
Bus sys_bus2_ck - - 200 -

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Table 73. Peripheral clock distribution summary (continued)

Kernel clock MUX Max kernel
Clock Type
Peripherals Clock source clock frequency (1)(2)
type
Position Control field (in MHz)

pclk1 0(3)
per_ck 1
ic7_ck 2
Kernel ic8_ck 3 SPDIFRX1SEL 200 A
SPDIFRX1
msi_ck 4
hsi_div_ck 5
I2S_CKIN 6
Bus pclk1 - - 200 -
(3)
pclk2 0
per_ck 1
ic8_ck 2
Kernel ic9_ck 3 SPI1SEL 200 A
SPI1
msi_ck 4
hsi_div_ck 5
I2S_CKIN 6
Bus pclk2 - - 200 -
(3)
pclk1 0
per_ck 1
ic8_ck 2
Kernel ic9_ck 3 SPI2SEL, SPI3SEL 200 A
SPI2, SPI3
msi_ck 4
hsi_div_ck 5
I2S_CKIN 6
Bus pclk1 - - 200 -
pclk2 0(3)
per_ck 1
ic9_ck 2
Kernel ic14_ck 3 SPI4SEL, SPI5SEL 133 A
SPI4, SPI5
msi_ck 4
hsi_div_ck 5
hse_ck 6
Bus pclk2 - - 200 -

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RM0486 Reset and clock control (RCC)

Table 73. Peripheral clock distribution summary (continued)

Kernel clock MUX Max kernel
Clock Type
Peripherals Clock source clock frequency (1)(2)
type
Position Control field (in MHz)

pclk4 0(3)
per_ck 1
ic8_ck 2
Kernel ic9_ck 3 SPI1SEL 200 A
SPI6
msi_ck 4
hsi_div_ck 5
I2S_CKIN 6
Bus pclk4 - - 200 -
TIM2, TIM3, TIM4, Kernel timg1_ck - - 400 S
TIM5, TIM6, TIM7,
TIM10, TIM11, Bus pclk1 - - 200 -
TIM12, TIM13, TIM14
TIM1, TIM8, TIM9, Kernel timg2_ck - - 400 S
TIM15, TIM16,
TIM17, TIM18 Bus pclk2 - - 200 -

pclk2 0(3)
per_ck 1
ic9_ck 2
Kernel ic14_ck 3 USART1SEL 100 A
USART1
lse_ck 4
msi_ck 5
hsi_div_cl 6
Bus pclk2 - - 100 -
(3)
pclk1 0
per_ck 1
USART2SEL,
ic9_ck 2 USART3SEL,
USART2, USART3, UART4SEL,
Kernel ic14_ck 3 100 A
UART4, UART5, UART5SEL,
UART7, UART8 lse_ck 4 UART7SEL,
UART8SEL
msi_ck 5
hsi_div_ck 6
Bus pclk1 - - 100 -

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Table 73. Peripheral clock distribution summary (continued)

Kernel clock MUX Max kernel
Clock Type
Peripherals Clock source clock frequency (1)(2)
type
Position Control field (in MHz)

pclk2 0(3)
per_ck 1
ic9_ck 2
USART6SEL,
USART6, UART9, Kernel ic14_ck 3 UART9SEL, 100 A
USART10 USART10SEL
lse_ck 4
msi_ck 5
hsi_div_ck 6
Bus pclk2 - - 100 -
Kernel hsi_div4_ck - - 25 A
UCPD1
Bus pclk1 - - 100 -
sys_busa_ck - - 400 -
VENC Bus
pclk5 - - 200 -
VENCRAM Bus sys_buss_ck - - 400 -
VREFBUF Bus pclk4 - - 200 -
WWDG1 Bus pclk1 - - 200 -
hclk5 0(3)
per_ck 1 XSPI1SEL,
Kernel XSPI2SEL, 200 A
XSPI1, XSPI2, XSPI3 ic3_ck 2 XSPI3SEL
ic4_ck 3

Bus sys_buss_ck - - 200 -

XSPIM Bus hclk5 - - 200 -

1. 'A' means that the kernel clock is asynchronous with respect to bus interface clock.
2. ‘S’ means that the kernel clock is synchronous with respect to bus interface clock.
3. Reset value.
4. Reset value.
5. The RTC switch is in the VSW voltage domain.

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Clock distribution for the NPU

Figure 47. Clock distribution for the NPU

RCC RAMCTRLSS
SCGU SCEU axisram3_en AXISRAM3

AXISRAM3EN
Logic
AXISRAM3LPEN

axisram4_en
AXISRAM4

AXISRAM4EN

NPU_NIC
Logic
AXISRAM4LPEN

axisram5_en AXISRAM5

AXISRAM5EN
Logic
AXISRAM5LPEN
axisram6_en
AXISRAM6
AXISRAM6EN
Logic
sys_npur_ck AXISRAM6LPEN

sys_npu_ck

NPU_NOC
Sleep/ noc_en ck_noc_npu
Stop
logic
aclkn_en ck_icn_npu

ACLKNEN Logic
ACLKNLPEN
npu_en NPU
NPUEN
Logic
NPULPEN
ck_icn_m_npu

sys_bus_ck
ck_icn_s_cacheaxi CACHEAXI
CACHEAXIRAMEN CACHEAXI
Logic
CACHEAXIRAMLPEN
NPU_NIC

RAM
sys_bus_ck ck_icn_m_cacheaxi

CACHEAXIEN
Logic
CACHEAXILPEN
sys_bus2_ck ck_icn_p_cacheaxi

aclknc_en ck_icn_npuc
sys_bus_ck
ACLKNCEN
ACLKNCLPEN Logic

NPUSS
MSv70479V2

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Clock distribution for graphic blocks (GPU, LTDC, DCMIPP, and PSSI)

Figure 48. Clock distribution for PSSI, CSI, and DCMIPP

RCC PSSI
PKSU PKEU
hclk5 ck_icn_p_pssi
hclk pixclk
PSSISEL PSSIEN
Logic feedback
hclk5 0 PSSILPEN
per_ck 1 ck_ker_pssi PSSI_PXCLK
D
ic20_ck 2
hsi_div_ck 3 DCMI

pclk pixclk

pclk5 ck_icn_p_dcmipp
pclk
DCMIPP

aclk ck_icn_m_dcmipp
aclk
DCMIPPSEL pxclk DCMIPP_PXCLK
DCMIEN
Logic
pclk5 0 DCMILPEN
per_ck 1 ck_ker_dcmipp
clk_proc
ic17_ck 2 D
hsi_div_ck 3
CSI2Host
clk_proc

pclk5 ck_icn_p_csi
pclk
CSIEN
Logic clk_byte
CSILPEN

CSIPHY
clk_byte

pclk clkp CSI_CLKP

ck_ker_csitxesc clkn CSI_CLKN
ic18_ck clk_txesc

ck_ker_csiphy
clk_cfg

Bus interface clocks

D The switch is dynamic: the transition between two inputs is glitch-free.
Kernel clocks
X represents the selected switch input after a system reset.
MSv70481V1

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Figure 49. Clock distribution for GPU, ICACHE, and GFXMMU

RCC PKEU
GPU
hclk5 ck_icn_p_gpu
hclk

aclk ck_icn_m_gpu
aclk
GPUEN
Logic
GPULPEN
ICACHE
hclk
ck_icn_p_icache

aclk
ck_icn_m_icache

GFXMMU
hclk5 ck_icn_p_gfxmmu
hclk

aclk ck_icn_m_gfxmmu
aclk
GFXMMUEN
Logic
GFXMMULPEN Bus interface clocks
Kernel clocks
MSv70480V2

The PSSI receives an AHB clock and a kernel clock (pxclk). The pxclk can be provided
either by an external device via PSSI_PIXCK pin, or by the RCC.
Note: The clock generated by the RCC is provided to pxclk input by the feedback path of the
PSSI_PIXCK pin. The drive of the PSSI_PIXCK is controlled by the PSSI.

Figure 50. Clock distribution for LTDC

RCC
PKSU PKEU LTDC
pclk5 ck_icn_p_ltdc
pclk

aclk ck_icn_m_ltdc
aclk
LTDCSEL LTDCEN ltdc_en
Logic pll_lock
pclk5 0 LTDCLPEN
per_ck 1 ck_ker_ltdc
pixel_ck
ic16_ck 2 D
hsi_div_ck 3

Bus interface clocks

D The switch is dynamic: the transition between two inputs is glitch-free.

X represents the selected switch input after a system reset. Kernel clocks
MSv70482V1

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Figure 51. Clock distribution for VENC

RCC VENC
PKEU

pclk5 ck_icn_p_venc
pclk

aclka ck_icn_m_venc
aclk

VENCEN Bus interface clocks

Logic
VENCLPEN
Kernel clocks
VENCRAM
aclks
aclk

VENCRAMEN
Logic
VENCRAMLPEN

MSv70483V2

Clock distribution for OTG1, OTG2, and UCPD1

Figure 52 shows the clock distribution for:
• USB Type-C Power Delivery block (UCPD1): uses ucpd1_ker_ck as kernel clock.
ucpd1_ker_ck is directly generated from the HSI output divided by four.
• OTGPHYx: embeds a PLL that accepts a reference input frequency of 19.2, 20, or
24 MHz. The reference clock can be selected among one of the following:
– hse_div2_osc_ck
– hse_div2_ck
– ic15_ck
– per_ck
hse_div2_osc_ck is direct from the HSE oscillator, without the tempo delay. It can be
selected to be HSE or HSE/2.
The OTGPHYx provides a 60 MHz clock (phyclock) to the OTGx.
• OTGx: uses the phyclock when working in HS or FS mode.
The reference clock selection for the OTGPHYx is performed by a simple multiplexer. To
change the clock source, the application must use the following sequence:
1. Disable the OTGPHYx clock by clearing OTGPHYxEN to 0.
2. Change the clock source selector (OTGPHYxSEL) to the desired value.
3. Enable the OTGPHYx clock by setting OTGPHYxEN to 1.
Clocks provided by the RCC are controlled by enable bits in RCC_AHB5ENR.
Note: Before programming OTG1PHYCTL_CR, OTG1EN must be asserted (the
OTG1PHYCTL_CR logic requires the clock enabled by OTG1EN).

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Figure 52. Clock distribution for OTG1, OTG2, and UCPD1

RCC PKSU PKEU

ck_icn_p_ucpd1
UCPD1
pclk1 pclk
ucpd1_ker_ck
hsi_osc_ck ÷4 ck_ker_ucpd1
usbpdclk
6 MHz min

UCPD1EN ucpd1_ck_ker_req
Logic clkreq
UCPD1LPEN

OTG1
hclku ck_icn_m_otg1
hclk

otg1_cg_en
utmi_clk
(for utmi+, 8 bit itf)
OTG1EN
Logic
OTG1LPEN

UTMI+
phyclock
OTG1PHYCTL
_CR
OTGPHY1
OTGHSPHYFSEL[2:0]
OTGHSPHYCMN 480 MHz
OTGPHY1EN
Logic
hse_div2_ck 0 OTGPHY1LPEN
otgphy1_cg_en PLL
per_ck 1 CLKCORE
otgphy1_ker_ck
D 0
ic15_ck 2 Allowed freq:
19.2, 20, 24 MHz hse_div2_osc_ck 1
hse_div2_osc_ck 3
FSEL[2:0]

OTGPHY1SEL OTGPHY1CKREFSEL COMMONONN

10 REFCLKSEL[1:0]

hclku ck_icn_m_otg2 OTG2

hclk

otg2_cg_en utmi_clk
(for utmi+, 8 bit itf)
OTG2EN
Logic
OTG2LPEN

UTMI+
phyclock
phyclock

OTG2PHYCTL
_CR
OTGPHY2
OTGHSPHYFSEL[2:0]
OTGHSPHYCMN 480 MHz
OTGPHY2EN
Logic
hse_div2_ck 0 OTGPHY2LPEN
otgphy2_cg_en PLL
per_ck 1 CLKCORE
otgphy2_ker_ck
D 0
ic15_ck 2 Allowed freq:
19.2, 20, 24 MHz hse_div2_osc_ck 1
hse_div2_osc_ck 3
FSEL[2:0]

OTGPHY2SEL OTGPHY2CKREFSEL COMMONONN

10 REFCLKSEL[1:0]
D The switch is dynamic: the transition between two inputs is glitch-free.

X represents the selected switch input after a system reset.

Bus interface clocks Kernel clocks MSv70484V3

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Clock distribution for ETH1

Kernel Ethernet clocks are provided by the RCC, who provides also clock selectors
(CLK_SEL, REF_CLK_SEL, SEL), and clock enables for TX and RX used in the ETHSS.
Note: Bus and PTP clocks are gated via ETH1MACEN and ETH1MACLPEN bits.

Figure 53. Clock distribution for ETH1

RCC ETH1GTXCLKSEL ETH1_CLK_SEL ETH1_CLK

RCC_CCIPR2 ETH1REFCLKSEL ETH1_REF_CLK_SEL
ETH1SEL(2:0) ETH1_SEL(2:0)
GTX1_CLK
ETH1
RCC_AHB5RSTR RESETn

ETH1_MDC
PKSU PKEU
ETH1CLKSEL
ETH1EN
Logic
sys_bus2_ck 0 ETH1LPEN
per_ck 1 ck_ker_eth1
D
ic12_ck 2
hse_ck 3
ETH1TXEN Logic ck_eth1_tx_en
ETH1TXLPEN

ETH1RXEN Logic ck_eth1_rx_en

ETH1RXLPEN
sys_bus_ck ETH1_TX_CLK
aclk
ck_icn_m_eth1

ETH1MACEN Logic ck_eth1_mac_en ETH1_CLK125

ETH1MACLPEN

ETH1PTPSEL
sys_bus2_ck hclk ETH1_RX_CLK/
sys_bus2_ck 0 ck_icn_p_eth1
ETHPTPDIV ETH1_REF_CLK
per_ck 1 clk_ptp_ref
D ÷ 1 to 16 ck_ker_eth1ptp
ic13_ck 2
hse_ck 3

D The switch is dynamic: the transition between two inputs is glitch-free. Bus interface clocks

X represents the selected switch input after a system reset. Kernel clocks
MSv70485V1

The ETH1 can generate a reference clock to the external PHY via the ETH1_CLK pin. The
ETH1_CLK is generated only if all the following conditions are met:
• ETH1EN is enabled.
• The system is in Run or Sleep mode.
• The clock source for ck_ker_eth1 is available.

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RM0486 Reset and clock control (RCC)

The clock management for ETH is very flexible and based on the PHY interface mode (MII,
RMII, or RGMII). All clock signals (enables, selection, and pins) are shown in Figure 54.

Figure 54. Clock management for ETH1

125 MHz (rgmii) 50 MHz (rmii) 25 MHz (mii) ETH1_CLK

ck_ker_eth1
(rmii)
eth_clk_fb

GTX1_CLK
ETH1_TX_CLK 2.5 or 25 MHz
(rgmii)
(mii)

1
ETH1_MDC
ETH1_CLK125
(rgmii) 0

mii gmii_mdc_o
0,1 0 ck_eth1_tx_en ETH1
ETH1_CLK_SEL
rgmii clk_tx
div 50 2 1

rmii clk_tx_180
div 5 3 4

phy_intf_sel

ETH1_SEL(2:0)
mac_speed(1)
mac_speed(0) mac_speed(1:0)

ETH1_REF_CLK_SEL

ETH1_SEL(2)
eth_clk_fb
1
div 20 1 ck_eth1_rx_en
ETH1_RX_CLK rmii 1
(mii,rgmii) 0
clk_rx
ETH1_REF_CLK div 2 0
(rmii) rgmii 0
mii clk_rx_180
ck_eth1_mac_en
clk_rmii

1 csysreq

ck_icn_m_eth1 aclk

ck_icn_p_eth1 hclk

ck_ker_eth1ptp clk_ptp_ref

64'b0 ptp_timestamp_i(63:0)

MSv70486V1

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Clock distribution for MDIOS

MDIOS (MDIO slave) clocks are provided by the RCC.

Figure 55. Clock distribution for MDIOS

RCC
PKEU
MDIOS
RCC_APB1RSTR RESETn

mdios_mdc
mdc
MDC
(from pin)
MDIOSEN Logic mdio
MDIOSLPEN
MDIO

ck_icn_s_mdio pclk

MSv70487V1

Clock distribution for FMC, XSPIs, and SDMMCs

The FMC kernel clock can be chosen between four different sources. For each XSPI, a
clock switch can be used to select between four different sources. Each XSPI can be
enabled independently.
The following steps are needed to correctly configure XSPI switches:
1. Switch on the desired clock source.
2. Ensure the clock source is ready, and conditions described above are met.
3. Set XSPIxSEL to the desired position.
4. Enable the XSPI clock (XSPIxEN = 1).
The XSPIs provide a clock to the external memory with a duty-cycle distortion lower than
5%. To this end, the kernel clock provided to the XSPIs has a typical duty cycle of 50%. In
addition, the XSPIs embed a prescaler allowing clock division by even ratios.

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RM0486 Reset and clock control (RCC)

Figure 56. Clock distribution for FMC and MCE4

FMCRST
RCC
sys_rstn FMC
RISUPhclk MCE4 RISUP
hclk
ck_icn_p_mce4
hclk

MCE4EN RISAF4

fmc_ker_ck
Logic aresetn
MCE4LPEN ck_icn_p_risaf hresetn
hclk

aclk

aclk

aclk

hclk
RISAFEN
Logic
RISAFLPEN
ck_icn_s_fmc

FMCEN
Logic
FMCLPEN ck_icn_p_fmc
FMCSEL

hclk5 0 ck_ker_fmc
per_ck 1
D
ic3_ck 2
ic4_ck 3

D The switch is dynamic: the transition between two inputs is glitch-free. Bus interface clocks

X represents the selected switch input after a system reset. Kernel clocks
MSv70488V2

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Figure 57. Clock distribution for XSPIs and MCE1/2/3

RCC XSPIPHY1RST

XSPIMRST hresetn
hclk
XSPIMEN hclk
Logic
XSPIMLPEN RISUPXSPIM

XPI1RST

sys_rstn
RISUP MCE1 RISUP XSPI1
hclk hclk
ck_icn_p_mce1
hclk

MCE1EN RISAF1

xspi_ker_ck
Logic aresetn
MCE1LPEN
ck_icn_p_risaf hresetn
hclk

aclk

aclk

aclk

hclk
RISAFEN
Logic XSPI-PHY1
RISAFLPEN
DLL_XSPI1
ck_icn_s_xspi1
XSPI1SEL
XSPI1EN
Logic
XSPI1LPEN
hclk5 0 X
ck_ker_xspi1
per_ck 1
D S
ic3_ck 2
ic4_ck
P
3 XSPI2RST
I
M
RISUP MCE2 RISUP XSPI2
hclk hclk
ck_icn_p_mce2
hclk

MCE2EN RISAF2

xspi_ker_ck
Logic aresetn
MCE2LPEN
hresetn
hclk
aclk

aclk

aclk

hclk
XSPI-PHY2
ck_icn_s_xspi2
XSPI2SEL DLL_XSPI2
XSPI2EN
Logic
hclk5 XSPI2LPEN
0
per_ck ck_ker_xspi2
1
D
ic3_ck 2
ic4_ck 3
XSPI3RST

RISUP MCE3 RISUP XSPI3

hclk hclk
ck_icn_p_mce3
hclk

MCE3EN RISAF3
xspi_ker_ck

Logic Kernel clocks

MCE3LPEN aresetn
hresetn
hclk
aclk

aclk

aclk

hclk

ck_icn_s_xspi3
XSPI3SEL
XSPI3EN
Logic
hclk5 XSPI3LPEN
0
per_ck ck_ker_xspi3
1
D
ic3_ck 2 XSPIPHY2RST
ic4_ck 3

Bus interface clocks

D The switch is dynamic: the transition between two inputs is glitch-free. X represents the selected switch input after a system reset. Kernel clocks

MSv70489V2

The SDMMC1 and SDMMC2 have separate kernel clocks. A clock switch allows the
selection between four different sources. Each SDMMC can be enabled independently.
When an SDMMC is enabled via its SDMMCxEN bit, the associated SDMMC_SYSCONF
is also enabled.
The application must configure the SDMMC to match the duty-cycle constraint of the
interface clock.

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Table 74. SDMMC interface clock constraints

SDMMC mode Mode name Interface clock frequency Duty cycle constraint

SDR12 25 MHz or less 30 - 70%

SDR25 50 MHz or less 30 - 70%
SDIO
DDR50 50 MHz or less 45 - 55%
SDR50 100 MHz or less 30 - 70%
Backward compatible 26 MHz or less 30 - 70%
[Link] High-speed SDR 52 MHz or less 30 - 70%
High-speed DDR 52 MHz or less 45 - 55%

For example, if the SDMMC works in SDR50, a kernel clock of 50 MHz, with a duty cycle
better than 30-70% is enough. If the SDMMC works in DDR50, it is recommended to
provide a kernel clock of 100 MHz, and to divide the frequency of the kernel clock by two,
using the SDMMC divider, to ensure a duty-cycle very close to 50% for the SDMMC_CK.

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Figure 58. Clock distribution for SDMMCx and companions

RCC SDMMC1RST SDMMC1_SYSCONF

RISUP
hclk hclk
SDMMC1DLLRST

SDMMC1_DLL
SDMMC1EN
Logic hresetn
SDMMC1LPEN

SDMMC1
SDMMC1SEL RISUP hresetn
hresetn
hclk
sys_bus2_ck 0
per_ck sdmmc_hclk
1D
ic4_ck 2 RIMU
ic5_ck 3 hresetn
hclk
sdmmc_ker_ck

SDMMC2RST RISUP SDMMC2_SYSCONF

hclk hclk
SDMMC2DLLRST

SDMMC2_DLL
SDMMC2EN
Logic hresetn
SDMMC2LPEN

SDMMC2
SDMMC2SEL RISUP hresetn
hresetn
hclk
sys_bus2_ck 0
per_ck sdmmc_hclk
1 D
ic4_ck 2 RIMU
ic5_ck 3 hresetn
hclk
sdmmc_ker_ck

D The switch is dynamic: the transition between two inputs is glitch-free. Bus interface clocks

X represents the selected switch input after a system reset. Kernel clocks
MSv70490V1

Clock distribution for ADC1/2

If the application requires that the ADC is precisely triggered by a TIMx timer without any
uncertainty (fixed trigger latency), ck_timg1 must be selected as the kernel clock source.
The other clock sources are asynchronous to TIMx, which results in an uncertain trigger
instant due to the resynchronization between the two clock domains. The LPTIMx timers are
also asynchronous.
The ADCPRE[7:0] divide value is set in RCC_CCIPR1.
clk_adc_sync is generated by Pulse-gen, one ck_timg1 cycle before the adc_ck rising edge.

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Figure 59. Clock distribution for ADCs

RCC ADC1-2
PKSU PKEU
ADC12SEL[2:0]
hclk1 adc_hclk
hclk1 0 == 7 ADC12EN
per_ck 1 Logic
ADCPRE[7:0] ADC12LPEN
ic7_ck 2
adc_ck
ic8_ck 3 D ÷ 1 to 256
msi_ck 4
hsi_div_ck 5
TIMx
i2s_ckin 6
ck_timg1 Pulse-gen clk_adc_sync
ck_timg1 7

D The switch is dynamic: the transition between two inputs is glitch-free. Bus interface clocks

X represents the selected switch input after a system reset. Kernel clocks
MSv70491V2

Clock distribution for RTC/AWU clock

The rtc_ck clock source can be one of the following:
• hse_rtc_ck (hse_ker_ck divided by a programmable prescaler)
• lse_ck
• lsi_ck clock
The source clock is selected by programming RTCSEL and RTCPRE in RCC_CCIPR7.
RTCSEL and RTCPRE are write-protected by DBP bit in PWR_DBPCR. In order to modify
the bits, DBP must be set 1.
This selection cannot be modified without resetting the backup domain.

Figure 60. Clock distribution for RTC

RCC RTCAPBEN
Logic
RTCAPBLPEN RTC
RTCSEL rtc_pclk
pclk4

rtc_ker_ck
0 0 RTCEN
lse_ck 1
D
lsi_ck 2
hse_rtc_ck 3
RTCPRE

hse_ck ÷ 2 to 63
PKSU PKEU

D The switch is dynamic: the transition between two inputs is glitch-free. Bus interface clocks

X represents the selected switch input after a system reset. Kernel clocks
MSv70492V1

If the LSE is selected as RTC clock, the RTC works normally even if the backup or the VDD
supply disappears.

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The LSE clock is in the backup domain, whereas the other oscillators are not, with the
following consequences:
• If LSE is selected as RTC clock, the RTC continues to work even if the VDD supply
is switched off, provided the VBAT supply is maintained.
• If LSI is selected as the RTC clock, the AWU state is not guaranteed if the VDD supply
is powered off.
• If the HSE clock is used as RTC clock, the RTC state is not guaranteed if the VDD
supply is powered off, or if the VVDDCORE supply is powered off. In addition, the HSE
is not available if the system goes to Stop mode.
rtc_ker_ck is enabled through RTCEN in RCC_APB4ENR.
The RTC bus interface clock (APB clock) is enabled through RTCAPBEN
in RCC_APB4ENR, and RTCAPBLPEN in RCC_APB4LLPENR.
Note: To read the RTC calendar register when the APB clock frequency is less than seven times
the RTC clock frequency (FAPB < 7 x FRTCLCK), the software must read the calendar time
and date registers twice. Data are correct if the second read access to RTC_TR gives the
same result of the first one. Otherwise, a third read access must be performed.

Clock distribution for watchdogs

The RCC provides the clock for the two watchdogs: the independent watchdog (IWDG),
connected to the LSI, and the window watchdog (WWDG), connected to the APB clock.
If an IWDG is started by either hardware option or software access, the LSI is forced on, and
cannot be disabled. After the LSI oscillator setup delay, the clock is provided to the IWDG.
The WWDG clock (pclk1) can be enabled by setting WWDGEN in RCC_APB1LENR.
The software cannot stop WWDG down-counting by clearing WWDGEN to 0. The WWDG is
frozen when the device goes to Stop mode.

Figure 61. Clock distribution for IWDG and WWDG

RCC WWDGEN
Logic WWDG
WWDGLPEN
pclk
pclk1

IWDG OTP_IWDG_HW
OTP logic

RCC_CR pclk4 pclk OTP_IWDG_FZ_STANDBY

LSION
PKEU OTP_IWDG_FZ_STOP
iwdg_ker_req Debug function
iwdg_ker_clk

lsi_enable lsi_ck Bus interface clocks

LSI
Kernel clocks

MSv70493V1

Clock distribution for trace and debug

The clock generation for the trace and debug is controlled by the DBGMCU.
DBGCLKEN in DBGMCU_CR allows the application to provide a clock to the debug
components. This clock can also be enabled via the debug access port.
The trace clock generation is controlled via TRACECLKEN in DBGMCU_CR.

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Figure 62. Clock distribution for trace and debug

RCC Trace and debug

DBGCLKEN
from DBGMCU ACK CDBGPWRUPREQ
logic CDBGPWRUPACK
sys_cpu_ck

ck_sys_dbg
ck_cpu_tpiu
TRACECLKEN ck_trace (traceclkin)
from DBGMCU

MSv70494V2

14.6.9 General clock concept overview

The RCC handles the distribution of the CPU, bus interface, and peripheral clocks for the
system, according to the CPU operating mode (refer to Section 14.6.1 for details on clock
definitions).
For each peripheral, the application can control the activation/deactivation of its kernel and
bus interface clocks. Before using a peripheral, the CPU must enable it (by setting PERxEN
to 1), and define if it remains active in Sleep mode (by setting PERxLPEN to 1). This is
called allocation of a peripheral by the CPU (refer to Section 14.6.10 for more details).
The peripheral allocation is used:
• by the RCC to automatically control the clock gating according to the CPU modes
• by the PWR to control VDDCORE supply voltages

Memory handling
The CPU can access all memory areas available in the device:
• AXISRAM1 to AXISRAM6, CACHEAXI RAM, and FLEXRAM
• AHBSRAM1 and AHBSRAM2
• BKPSRAM
CACHEAXI RAM, and VENCRAM are disabled by default, see RCC embedded memories
enable register (RCC_MEMENR). The CPU must enable them before using these
memories.
Read or write accesses to a peripheral register or memory, without the clocks enabled in the
RCC registers, result in a system freeze. A system reset is required to unlock this.
If the access is performed by a debug interface (as an example, from a debug session
inside an IDE), then a power-on reset is required to unlock the device, as the debug
interface is not affected by a system reset.
Note: The memory interface clocks (flash memory and RAM interfaces) can be stopped by
software during Sleep mode (via SRAMyLPEN bits).
Refer to Section 14.6.11 and Section 14.6.12 for details on clock enabling.

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14.6.10 Peripheral allocation

The CPU can allocate a peripheral (and hence control its kernel and bus interface clock) by
setting the dedicated PERxEN bit to 1. The CPU can control the peripheral clock gating
when it is in Sleep mode via PERxLPEN bits.
The peripheral allocation bits (PERxEN bits) are used by the hardware to provide the kernel
and bus interface clocks to the peripherals. Theses bits are also used to link peripherals to
the CPU. The hardware can then safely gate peripheral clocks and bus matrix clocks,
according to CPU states.

Clock switches and gating

• Clock switching delays
The input selected by the clock switches can be changed dynamically without
generating spurs or timing violation. For example, if PERxSEL (in Figure 63) goes
from 0 to 1, the switch first disables the clock output using the currently selected clock
(in0_ck), and enables again the clock output using the new selected clock (in1_ck).
Disable and enable commands are re-synchronized to their respective clocks. If one
of the two clocks are not present, the sequence cannot be completed, and no clock is
output. To recover from this situation, the user must either provide a valid clock to
in1_ck input, or set back PERxSEL to 0.
During the transition from one input to another, the kernel clock provided to the
peripheral is gated, in the worst case, during two or three clock cycles of the new
selected clock.
As shown in Figure 63, both input clocks must be present during transition time.

Figure 63. Kernel clock switching

Transition time

PERxSEL ...
1 2
in0_ck ...
PERxSEL
1 2
in1_ck ... in0_ck 0
D
in1_ck 1

rcc_perx_ker_ck ...
(Kernel clock provided to PERx) rcc_perx_ker_ck
In this area, ck_in0 clock can be
disabled
D The switch is dynamic: the transition between two inputs is glitch-free.
MSv70495V1

• Clock enabling delays

In the same way, the clock gating logic synchronizes the enable command (coming
generally from a kernel clock request, or PERxEN bits) with the selected clock, in order
to avoid generation of spurious:
– A maximum delay of two periods of the enabled clock can occur between the
enable command and the first rising edge of the clock. The enable command can

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be the rising edge of PERxEN in RCC_xxxxENR, or a kernel clock request

asserted by a peripheral.
– A maximum delay of 1.5 periods of the disabled clock can occur between the
disable command and the last falling edge of the clock. The disable command can
be the falling edge of PERxEN in RCC_xxxxENR, or a kernel clock request
released by a peripheral.
Note: Both kernel and bus interface clocks are affected by this re-synchronization delay.

14.6.11 Peripheral clock-gating control

As mentioned previously, each peripheral requires one or several bus interface clocks,
named rcc_perx_bus_ck (for peripheral ‘x’). These clocks can be an APB, AHB, or AXI
clock, according to which bus(ses) the peripheral is connected.
The clocks used as bus interface for peripherals can be aclk[s,a,n], hclk[m,u,e], hclk[5:1],
pclk[5:4], pclk[2:1], or ck_timg[1,2], depending on the bus connected to each peripheral.
Some peripherals also require dedicated clocks for their communication interface.
These clocks are generally asynchronous with respect to the bus interface clock. They are
named kernel clocks (perx_ker_ck). Both bus interface and kernel clocks can be gated
according to several conditions detailed hereafter.
As shown in Figure 64, enabling kernel and bus interface clocks of each peripheral depends
on several input signals:
• PERxEN and PERxLPEN bits
PERxEN represents the peripheral enable (allocation) bit for the CPU. The CPU can
write these bits to 1 via RCC_xxxxENR.
• CPU state (cpu_sleep and cpu_deepsleep signals)
• kernel clock request (perx_ker_ckreq) of the peripheral itself, when the feature is
available
Refer to Section 14.6.10 for more details.

Figure 64. Enable logic details for peripheral kernel clock

RCC
SCEU
SCGU (system clock enabling unit)
(system rcc_bus_ck rcc_perx_bus_ck
clock generation)

sync
PERxEN
busif
PERxLPEN
control
CPU_state logic rcc_perx_bus_en
PKSU perx_ker_ckreq PERx
(peripheral kernel clock
selection) When the peripheral
rcc_perx_ker_en offers the feature
Kernel
PERxSEL control
logic sync
rcc_perx_ker_ck
….

PKEU
(peripheral kernel clock enabling)

D The switch is dynamic: the transition between two inputs is glitch-free.

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The clocks for all AHB and APB buses (AHBM, AHB1/2/3/4/5, APB1/2/4/5) are
automatically enabled when a dependent peripheral is active. This may induce a chain:
a peripheral activation activates the APB that activates the AHB, and activates the AHBM.
For instance, the manual UART4 activation induces the automatic APB1 activation (APB1
is used to configure the UART4). This induces the automatic AHB1 bus activation (AHB1 is
needed to drive the APB1). This induces the activation of the central AHBM matrix (AHBM is
needed to drive the AHB1).

High-bandwidth interconnect
The NoC and the two NPU AXI bus clocks (ck_icn_npu and ck_icn_npuc, see Figure 47)
are permanently enabled in Run and Sleep modes, and permanently disabled in Stop and
Standby modes.
An internal automatic clock-gating optimizes the NoC power consumption: when no
transaction is ongoing in a bus section, an automatic clock-gating clocks and gates this bus.
The NPU interconnect clock (ck_icn_npu) can be disabled by setting ACLKNEN = 0
(disabled in Run and Sleep modes), or ACLKNLPEN = 0 (disabled in Sleep mode only).
If the clock is disabled, the NPU cannot work (no interconnect downstream), and the CPU
cannot access AXISRAM3/4/5/6, the CACHEAXI RAM, or the FLEXRAM.
The clock of the NPU interconnect (ck_icn_npuc) can be disabled by setting
ACLKNCEN = 0 (disabled in Run and Sleep modes), or ACLKNCLPEN = 0 (disabled in
Sleep mode only). If the clock is disabled, neither the CPU or NPU can access
AXISRAM3/4/5/6, the CACHEAXI, the CACHEAXI RAM, or the FLEXRAM.
Table 75 gives a detailed description of the enabling logic of the peripheral clocks
for peripherals located in the CPU domain and allocated by the CPU.

Table 75. Peripheral clock enabling

rcc_perx_bus_ck
rcc_perx_ker_ck
perx_ker_ckreq
PERxLPEN

CPU state
PERxSEL
PERxEN

Comments

0 X X X X - - No clock provided to the peripheral (PERxEN = 0)

Kernel and bus interface clocks are provided to the peripheral (CPU
1 X X X Run CK CK
in Run mode, and PERxEN = 1)
No clock provided to the peripheral (CPU is in Sleep mode and
1 0 - -
PERxLPEN = 0)
X X Sleep
Kernel and bus interface clocks are provided to the peripheral (CPU
1 1 CK CK
in Sleep mode and PERxLPEN = 1)

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Table 75. Peripheral clock enabling (continued)

rcc_perx_bus_ck
rcc_perx_ker_ck
perx_ker_ckreq
PERxLPEN

CPU state
PERxSEL
PERxEN

Comments

1 0 X X - - No clock provided to the peripheral (PERxLPEN = 0)

no lsi_ck
and
no lse_ck
No clock provided to the peripheral (CPU in Stop mode, and lse_ck
1 1 and no X - -
or lsi_ck or hsi_ker_ck or msi_ker_ck not selected as kernel clock)
hsi_ker_ck
and no
msi_ker_ck

Stop Kernel clock provided to the peripheral (PERxEN = PERxLPEN = 1,

lsi_ck or
1 1 X CK - and lsi_ck or lse_ck selected and enabled)
lse_ck
Bus interface clock not provided as the CPU is in Stop mode
Kernel clock provided to the peripheral (req_ker_perx = 1,
hsi_ker_ck or PERxEN = PERxLPEN = 1, and hsi_ker_ck or msi_ker_ck selected
1 1 1 CK - and enabled)
msi_ker_ck
Bus interface clock not provided as the CPU is in Stop mode
hsi_ker_ck or No clock provided to the peripheral (CPU in Stop mode, and no
1 1 0 - -
msi_ker_ck kernel clock request pending)

The kernel clock is provided to the peripherals when one of the following conditions is met:
1. The CPU is in Run mode and the peripheral is enabled.
2. The CPU is in Sleep mode and the peripheral is enabled with PERxLPEN = 1.
3. The CPU is in Stop mode, the peripheral is enabled with PERxLPEN = 1, the peripheral
generates a kernel clock request, and the selected clock is hsi_ker_ck or msi_ker_ck.
4. The CPU is in Stop mode, the peripheral is enabled with PERxLPEN = 1, and the
kernel source clock of the peripheral is lse_ck or lsi_ck.
The bus interface clock is provided to the peripherals only when conditions 1 or 2 are met.

14.6.12 CPU and bus matrix clock-gating control

The clocks of the CPU, AHB/AXI bridges, and APB buses are enabled as follows:
• The CPU clock (rcc_cpu_ck) is enabled when the CPU is in Run or Sleep mode.
• The AXI bridge clock is enabled when the CPU is in Run or Sleep mode.
• The AHB bus matrix clock is enabled if one of the following conditions is met:
– The CPU is in Run mode.
– The CPU is in Sleep mode, and at least one peripheral connected to this bridge
has both its PERxEN and PERxLPEN set to 1.
– The CPU is in Sleep mode, and AHB1, 2, 3, 4, or 5 has its clock enabled.
• The clocks of AHB1/2/3/4/5 bridges are enabled when one of the following conditions is
met:

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– The CPU is in Run mode.

– The CPU is in Sleep mode, and at least one peripheral connected to this bus has
both its PERxEN and PERxLPEN set to 1.
– The CPU is in Sleep mode, and the APB bus connected to the AHB bridge has its
clock enabled.
• The APB1/2/4/5 clock buses are enabled when one of the following conditions is met:
– The CPU is in Run mode.
– The CPU is in Sleep mode, and at least one peripheral connected to this bus has
both its PERxEN and PERxLPEN set to 1.
Refer to Section 14.6.11 for details on the automatic clock-gating for AHBMEN, and all
AHB/APB buses.

14.6.13 Low-power emulation modes

To ease the device debug, the RCC is able to handle an emulation mode for Stop and
Standby modes.

Sleep emulation mode

The Sleep emulation mode is controlled by DBGSLEEP in DBGMCU_CR. When the
processor goes to Sleep mode with DBGSLEEP = 1, the processor clock, the clocks of all
enabled peripherals, debug parts, and interconnect are maintained activated.

Stop emulation mode

The Stop emulation mode is controlled by DBGSTOP in DBGMCU_CR. When the
processor goes to Stop mode with DBGSTOP = 1:
• The processor, peripheral, and interconnect clocks remain active.
• The debug clock is active (ck_bus2_dbg, see Figure 45), and all debug parts remain
clocked. All PLLs and OSCs remain active.
When a wake-up event occurs:
• The peripheral waking up the system sends the interrupt to the NVIC via the EXTI.
• If the PWR asserts the pwr_wkup signal, the RCC exits Stop mode. The RCC selects
HSI or MSI as system clock, depending on STOPWUCK. The CPU exits Stop mode.

Standby emulation mode

The Standby emulation mode is controlled by DBGSTBY in DBGMCU_CR.
When the system goes to Standby mode with DBGSTBY = 1 and dbg_stdby_rstn = 0:
• the VDDCORE voltage is not switched-off
• all CPU, interconnect, and peripherals are under reset except the debug part
• all PLLs and OSCs remain active
• the debug part is clocked
• peripherals on VSW or VDD domains are not reset
The system exits Standby mode when dbg_stdby_rstn is deasserted:
• the RCC deasserts the rcc_pwrds signal
• all peripherals are removed from reset
• the RCC enters Run state

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14.7 RCC interrupts

The RCC provides the following interrupt lines:
• rcc_it: general interrupt line that provides events when PLLs or oscillators are ready
(for nonsecure bits)
• rcc_s_it: general interrupt line that provides events when PLLs or oscillators are ready
(for secure bits)
• rcc_hsecss_it: interrupt line dedicated to the failure detection of the HSE CSS
• rcc_lsecss_it: interrupt line dedicated to the failure detection of the LSE CSS
The interrupt enable is controlled via RCC_CIER, except for the HSE CSS failure.
When the HSE CSS feature is enabled, the interrupt generation cannot be masked.
The interrupt flags can be checked via RCC_CIFR, and these flags can be cleared
via RCC_CICR.
Note: The interrupt flags are not relevant if the corresponding interrupt enable bit is not set.
Table 76 gives a summary of the interrupt sources and the way to control them.

Table 76. Interrupt sources and control

Interrupt source Description Interrupt enable Action to clear interrupt Interrupt line

LSIRDYF LSI ready LSIRDYIE Set LSIRDYC to 1

LSERDYF LSE ready LSERDYIE Set LSERDYC to 1
HSIDRYF HSI ready HSIDRYIE Set HSIRDYC to 1
HSERDYF HSE ready HSERDYIE Set HSERDYC to 1
MSIRDYF MSI ready MSIRDYIE Set MSIRDYC to 1 rcc_it, rcc_s_it
PLL1RDYF PLL1 ready PLL1RDYIE Set PLL1RDYC to 1
PLL2RDYF PLL2 ready PLL2RDYIE Set PLL2RDYC to 1
PLL3RDYF PLL3 ready PLL3RDYIE Set PLL3RDYC to 1
PLL4RDYF PLL4 ready PLL4RDYIE Set PLL4RDYC to 1
LSECSSF LSE CSS failure LSECSSIE (1)
Set LSECSSC to 1 rcc_lsecss_it
HSECSSF HSE CSS failure -(2) Set HSECSSC to 1 rcc_hsecss_it
1. The security system feature must be enabled (LSECSSON = 1) to generate interrupts.
2. This interrupt cannot be masked when the security system feature is enabled (HSECSSON = 1).

14.8 RCC application information

14.8.1 HSE crystal auto-detection

The software can detect the frequency of the crystal connected to the HSE. The crystal
choices are 19.2, 20.0, 24.0, 38.4, 40.0, 48.0 MHz. The closest crystal frequencies are 19.2
and 20 MHz (differing ~4%).
Measurement uses a timer clocked by a fast clock, triggered by the slower clock. Using the
PWM input mode of input capture, it is possible to measure the full period of the slow clock.

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LSE reference
If available, the LSE can trigger TIM16 to count hse_ck ticks. This is crystal accurate (better
than using HSI).
Configure a PLL to generate (HSE * 8) MHz. Then set SYSSW to select ic2_ck for
sysb_ck = ck_timg (TIMPRE = 1). This means sys_bus_ck relates to the HSE frequency.
LSE is connected to TIM16 - TI1_2.
Example: the multiplication by eight of hse_ck gives
(40 × 1000 × 8) / 32.768 = 9765 counts, and (38.4 × 1000 × 8) / 32.768 = 9375 counts.
19.2, 20, 24, 38.4, 40, 48 = 4687, 4882, 5859, 9375, 9765, 11718 counts
sys_bus_ck = 153.6, 160, 192, 307.2, 320, 384 MHz

HSI reference
HSI can be used when LSE is not available. A trimmed HSI can vary by ±4% (at 3 σ) across
the full temperature range. This means that 19.2 and 20 MHz cannot be differentiated
reliably.
If the DTS is available, the user can measure the temperature to compensate for
the HSI drift.
The RCC generates an hse_cal_ck signal, which is HSE divided by 1024. This signal is
connected to TIM17 - TI1_2.
hse_cal_ck has an expected frequency between 19.2 to 50 kHz. The HSI is about 64 MHz.
To get 300 MHz, select HSI as input to a PLL, then ic2_ck for sysb_ck = ck_timg
(TIMPRE = 1).
Example: The division by 1024 of hse_ck gives 300 × 1024 / 40 = 7680 counts, and
300 × 1024 / 38.4 = 8000 counts.
19.2, 20, 24, 38.4, 40, 48 = 16000, 15360, 12800, 8000, 7680, 6400 counts
A less accurate method is to use hse_ck output on MCO divided by 16. This gives, for
example: 300 × 16 / 40 = 120 counts, and 300 × 16 / 38.4 = 125 counts.
19.2, 20, 24, 38.4, 40, 48 = 250, 240, 200, 125, 120, 100 counts

14.8.2 Calibration and clock frequency measurement using TIMx

Most of the clock source generator frequencies can be measured by means of the input
capture of TIMx.

Calibrating HSI or MSI with the LSE

The main purpose of connecting the LSE to a TIMx input capture is to accurately measure
the HSI or MSI. This requires to use the HSI or MSI as sys_bus_ck either directly, or via a
PLL. The number of system clock counts between consecutive edges of the LSE signal
gives a measurement of the internal clock period. Taking advantage of the high precision of
LSE crystals (typically a few tens of ppm), the user can determine the internal clock
frequency with the same resolution, and trim the source to compensate for variations due to
manufacturing, temperature, or voltage.
The ratio between the two clock frequencies affects the measurement precision. The
greater the ratio, the more accurate the calculation.

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HSI and MSI oscillators have dedicated user-accessible calibration bits for this purpose
(see RCC_HSICFGR and RCC_MSICFGR). When the HSI or MSI is used via a PLL, it is
also possible to fine-tune the sys_bus_ck using the fractional divider of the PLL.

Calibrating LSI with HSI

The LSI frequency can also be measured. This is useful for applications that do not have a
crystal. The ultra-low-power LSI oscillator has a large manufacturing process variation. The
LSI clock frequency can be measured using the more precise HSI clock source. Using this
measurement, the user can obtain a more accurate RTC timebase timeout (when LSI is
used as RTC clock source), and/or a more accurate IWDG timeout.

14.8.3 Clock monitoring

Monitoring HSI with LSE
The purpose is to assist the software calibration procedure when the HSI frequency drifts
out of a predefined range because of environmental variation (for example, temperature).
This monitoring can be enabled in all system modes where HSI is used, except Standby and
VBAT modes. When enabled, the number of HSI clock ticks between consecutive edges of
the LSE clock is counted.
The HSI monitoring control is based on RCC_HSIMCR and RCC_HSIMSR.
The following steps can be used to enable the monitoring:
1. Enable LSE signal:
a) Set DBP = 1 in PWR_DBPCR.
b) Write 1 to LSEON.
c) Wait for LSERDY = 1.
d) Set DBP = 0 in PWR_DBPCR.
2. Set up HSI clock period monitoring:
a) Write 1 to HSIMONEN in RCC_HSIMCR to start the monitoring.

14.8.4 Clock frequency limits

The maximum frequencies that can be set for each peripheral are detailed in Table 77.

Table 77. Maximum peripheral clock frequencies

Peripheral Maximum kernel clock frequency (MHz)

PWR 200
RNG 64
RTC 4
SAES 200
SAI1 200
SAI2 200
SDMMC1 208
SDMMC2 208

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Table 77. Maximum peripheral clock frequencies (continued)

Peripheral Maximum kernel clock frequency (MHz)

SPDIFRX1 200
SPI1 200
SPI2 200
SPI3 200
SPI4 133
SPI5 133
SPI6 200
SYSCFG 200
TIMx 400
LPTIMx 200
DTS 10
USART1 100
USART2 100
USART3 100
UART4 100
UART5 100
USART6 100
UART7 100
UART8 100
UART9 100
USART10 100
LPUART1 100
UCPD1 25
VENC 400
VREFBUF 200
WWDG 200
MREPAIR 64

As an example, the PLL configuration to achieve these frequencies would use HSI as
reference clock (64 MHz), and program the VCO of PLL1, 2, 3, and 4, to respectively, 800,
993.52, 875, and 514.5 MHz.

14.9 RCC security

The system RIF protects bus accesses to the RCC and peripheral registers.

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The RIFSC indicates if an access to the RCC or other peripherals is secure and/or
privileged. Signals are connected from the RIFSC to the RCC to communicate this
information. The notation for these signals is S, P.
The RCC is able to protect register bits from being modified by nonsecure and unprivileged
accesses.
If a peripheral RISUP is programmed as secure (or privileged), the peripheral clock and
reset bits become secure (or privileged).
If the peripheral is TrustZone-aware, the peripheral clock and reset bits become secure (or
privileged) as soon as at least one function is configured as secure (or privileged) by RIFSC.
Peripheral configuration registers inside the RCC can be also be made secure (or
privileged) via a global override bit (PERSEC in RCC_SECCFGR3, PERPRIV in
RCC_PRIVCFGR3).
After an application reset or system reset, the RCC does not filter any access until the
trusted agent has configured the system.

14.9.1 Internal register protection

The following can be made secure and/or privileged (via RCC_SECCFGRx and
RCC_PRIVCFGRx):
• internal and external oscillators (HSE, LSE, HSI, MSI, LSI)
• PLLs and AHB prescalers
• system clock-source selection
• MCO clock outputs
• reset flags
• automatic internal oscillator wake-up configuration
There are four access controls for RCC registers:
• SEC (secure)
• PRIV (privileged)
• LOCK (locked SEC and PRIV)
• PUB (public)

SEC (in RCC_SECCFGRx)

xxxSEC defines the secure status required for a write to the xxx configuration registers
(for example, HSISEC for the HSI oscillator). When this bit is set, configuration register bits
are writable by secure software only. This bit can be locked (cannot be changed) with the
xxxLOCK bit, and is readable by all. Write access to RCC_SECCFGRx is controlled by S, P.

PRIV (in RCC_PRIVCFGRx)

xxxPRIV defines the privileged status required for a write to the xxx configuration registers
(such as HSIPRIV for the HSI oscillator). When this bit is set, the configuration register bits
are writable only by privileged software. This bit can be locked (cannot be changed) with the
xxxLOCK bit, and is readable by all. Write access to RCC_PRIVCFGRx is controlled by
xxxSEC, P. xxxPRIV can be set/cleared by write to 1 registers.

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LOCK (in RCC_LOCKCFGRx)

xxxLOCK, when set, locks definitively xxxSEC and xxxPRIV settings: xxxLOCK is readable
by all. Write access to RCC_LOCKCFGRx is controlled by S, P. xxxLOCK is a set-once bit.

PUB (in RCC_PUBCFGRx)

xxxPUB grants read access to configuration/status bits, regardless of security or privilege.
For example, if HSIPUB bit is set, any software can read the HSI oscillator configuration and
status. If not set then normal access controls are enforced.
xxxPUB is readable by all. Write access to RCC_PUBCFGRx is controlled by xxxSEC and
xxxPRIV. xxxPUB can be set/cleared by write-to-1 registers.

14.9.2 Internal register write-protection

There are different controls for write-protecting a register bit.
• xxxLOCK bits (described above)
• other internal protection logic (controlled from internal or external signals)
Only protection logic using the pwr_lock_backup signal is implemented.

14.10 RCC registers

14.10.1 RCC control register (RCC_CR)

Address offset: 0x0
Reset value: 0x0000 0008
This register is used to enable the RCC oscillators and PLLs in Run or Sleep mode.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4 PLL3 PLL2 PLL1 HSE HSI MSI LSE LSI
Res. Res. Res. Res. Res. Res. Res.
ON ON ON ON ON ON ON ON ON
rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 PLL4ON: PLL4 enable
This bit is reset by int_sys_rstn. It is security-protected by PLL4SEC or PLL4PRIV, and is
publicly readable if PLL4PUB = 1. It can be set with PLL4ONS, and cleared with PLL4ONC.
This bit is set and reset by software. It cannot be cleared if PLL4 is currently used to generate
the CPU or system clock.
0: PLL4 is OFF (default after reset)
1: PLL4 is ON

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Bit 10 PLL3ON: PLL3 enable

This bit is reset by int_sys_rstn. It is security-protected by PLL3SEC or PLL3PRIV, and is
publicly readable if PLL3PUB = 1. It can be set with PLL3ONS, and cleared with PLL3ONC.
This bit is set and reset by software. It cannot be cleared if PLL3 is currently used to generate
the CPU or system clock.
0: PLL3 is OFF (default after reset)
1: PLL3 is ON
Bit 9 PLL2ON: PLL2 enable
This bit is reset by int_sys_rstn. It is security-protected by PLL2SEC or PLL2PRIV, and is
publicly readable if PLL2PUB = 1. It can be set with PLL2ONS, and cleared with PLL2ONC.
This bit is set and reset by software. It cannot be cleared if PLL2 is currently used to generate
the CPU or system clock.
0: PLL2 is OFF (default after reset)
1: PLL2 is ON
Bit 8 PLL1ON: PLL1 enable
This bit is reset by int_sys_rstn. It is security-protected by PLL1SEC or PLL1PRIV, and is
publicly readable if PLL1PUB = 1. It can be set with PLL1ONS, and cleared with PLL1ONC.
This bit is set and reset by software. It cannot be cleared if PLL1 is currently used to generate
the CPU or system clock.
0: PLL1 is OFF (default after reset)
1: PLL1 is ON
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 HSEON: HSE oscillator enable
This bit is reset by int_sys_rstn. It is security-protected by HSESEC or HSEPRIV, and is
publicly readable if HSEPUB = 1. It can be set with HSEONS, and cleared with HSEONC.
This bit is set and reset by software.
0: HSE is OFF (default after reset)
1: HSE is ON
Bit 3 HSION: HSI oscillator enable
This bit is reset by int_sys_rstn. It is security-protected by HSISEC or HSIPRIV, and is
publicly readable if HSIPUB = 1. It can be set with HSIONS, and cleared with HSIONC. This
bit is set and reset by software.
0: HSI is OFF
1: HSI is ON (default after reset)
Bit 2 MSION: MSI oscillator enable
This bit is reset by int_sys_rstn. It is security-protected by MSISEC or MSIPRIV, and is
publicly readable if MSIPUB = 1. It can be set with MSIONS, and cleared with MSIONC. This
bit is set and reset by software.
0: MSI is OFF (default after reset)
1: MSI is ON
Bit 1 LSEON: LSE oscillator enable
This bit is reset by rcc_vsw_rstn. It is in the VBKP voltage domain. It is write-protected by the
pwr_lock_backup_n signal. It is security-protected by LSESEC, LSEPRIV, and is publicly
readable if LSEPUB = 1. It can be set with LSEONS, and cleared with LSEONC. This bit is
set and reset by software.
0: LSE is OFF (default after reset)
1: LSE is ON

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Bit 0 LSION: LSI oscillator enable

This bit is reset by nreset_rstn. It is in the VRET voltage domain. This bit is security-protected
by LSISEC or LSIPRIV, and is publicly readable if LSIPUB = 1. It can be set with LSIONS,
and cleared with LSIONC. This bit is set and reset by software.
0: LSI is OFF (default after reset)
1: LSI is ON

14.10.2 RCC status register (RCC_SR)

Address offset: 0x4
Reset value: 0x0000 0000
This register is used to retrieve the status the RCC oscillators and PLLs.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4 PLL3 PLL2 PLL1 HSE HSI MSI LSE LSI
Res. Res. Res. Res. Res. Res. Res.
RDY RDY RDY RDY RDY RDY RDY RDY RDY
r r r r r r r r r

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 PLL4RDY: PLL4 clock ready flag
This bit is security-protected by PLL4SEC or PLL4PRIV, and is publicly readable if
PLL4PUB = 1. It is set by hardware to indicate that the PLL4 is locked.
0: PLL4 unlocked (default after reset)
1: PLL4 locked
Bit 10 PLL3RDY: PLL3 clock ready flag
This bit is security-protected by PLL3SEC or PLL3PRIV, and is publicly readable if
PLL3PUB = 1. It is set by hardware to indicate that the PLL3 is locked.
0: PLL3 unlocked (default after reset)
1: PLL3 locked
Bit 9 PLL2RDY: PLL2 clock ready flag
This bit is security-protected by PLL2SEC or PLL2PRIV, and is publicly readable if
PLL2PUB = 1. it is set by hardware to indicate that the PLL2 is locked.
0: PLL2 unlocked (default after reset)
1: PLL2 locked
Bit 8 PLL1RDY: PLL1 clock ready flag
This bit is security-protected by PLL1SEC or PLL1PRIV, and is publicly readable if
PLL1PUB = 1. It is set by hardware to indicate that the PLL1 is locked.
0: PLL1 unlocked (default after reset)
1: PLL1 locked
Bits 7:5 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

Bit 4 HSERDY: HSE clock ready flag

This bit is security-protected by HSESEC or HSEPRIV, and is publicly readable if
HSEPUB = 1.
It is set by hardware to indicate that the HSE oscillator is stable.
0: HSE not ready (default after reset)
1: HSE ready
Bit 3 HSIRDY: HSI clock ready flag
This bit is security-protected by HSISEC or HSIPRIV, and is publicly readable if HSIPUB = 1.
It is set by hardware to indicate that the HSI oscillator is stable.
0: HSI not ready (default after reset)
1: HSI ready
Bit 2 MSIRDY: MSI clock ready flag
This bit is security-protected by MSISEC or MSIPRIV, and is publicly readable if MSIPUB = 1.
It is set and reset by hardware to indicate that the MSI oscillator is stable.
0: MSI not ready (default after reset)
1: MSI ready
Bit 1 LSERDY: LSE clock ready flag
This bit is security-protected by LSESEC or LSEPRIV, and is publicly readable if
LSEPUB = 1. It is set and reset by hardware to indicate that the LSE oscillator is stable. This
bit requires 6 cycles of lse_ck before it is deasserted.
0: LSE not ready (default after reset)
1: LSE ready
Bit 0 LSIRDY: LSI clock ready flag
This bit is security-protected by LSISEC or LSIPRIV, and is publicly readable if LSIPUB = 1. It
is set by hardware to indicate that the LSI oscillator is stable.
0: LSI not ready (default after reset)
1: LSI ready

14.10.3 RCC Stop mode control register (RCC_STOPCR)

Address offset: 0x8
Reset value: 0x0000 0002
This register is used to enable the RCC oscillators in Stop mode.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSIST MSIST
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
OPEN OPEN
rw rw

Bits 31:2 Reserved, must be kept at reset value.

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Bit 1 HSISTOPEN: HSI oscillator enable

This bit is reset by int_sys_rstn. It is security-protected by HSISEC or HSIPRIV, and is
publicly readable if HSIPUB = 1. It can be set with HSISTOPENS, and cleared with
HSISTOPENC. This bit is set and reset by software.
0: HSI is OFF
1: HSI is ON (default after reset)
Bit 0 MSISTOPEN: MSI oscillator enable
This bit is reset by int_sys_rstn. It is security-protected by MSISEC or MSIPRIV, and is
publicly readable if MSIPUB = 1. It can be set with MSISTOPENS, and cleared with
MSISTOPENC. This bit is set and reset by software.
0: MSI is OFF (default after reset)
1: MSI is ON

14.10.4 RCC configuration register 1 (RCC_CFGR1)

Address offset: 0x20
Reset value: 0x0000 0000
This register controls the selection of the CPU and system clocks, and their status (see
Figure 45 for various SYSSW inputs). The register is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. SYSSWS[1:0] Res. Res. SYSSW[1:0] Res. Res. CPUSWS[1:0] Res. Res. CPUSW[1:0]
r r rw rw r r rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STOP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
WUCK
rw

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 SYSSWS[1:0]: System clock switch status
This bitfield is security-protected by SYSSEC, SYSPRIV, and is publicly readable if
SYSPUB = 1. It is set and reset by hardware to show the source of the system bus clocks
(sys_bus_ck).
00: hsi_ck selected as sysb_ck, sysc_ck, sysd_ck system clocks (default after reset)
01: msi_ck selected as sysb_ck, sysc_ck, sysd_ck system clocks
10: hse_ck selected as sysb_ck, sysc_ck, sysd_ck system clocks
11: ic2_ck selected as sysb_ck, ic6_ck selected as sysc_ck, ic11_ck as sysd_ck system
clocks
Bits 27:26 Reserved, must be kept at reset value.
Bits 25:24 SYSSW[1:0]: System clock switch selection
This bitfield is security-protected by SYSSEC, SYSPRIV, and is publicly readable if
SYSPUB = 1. It is set by the software to select the source of the system bus clocks
(sys_bus_ck).
00: hsi_ck selected as system clock (default after reset)
01: msi_ck selected as system clock
10: hse_ck selected as system clock
11: ic2_ck selected as system clock
Bits 23:22 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

Bits 21:20 CPUSWS[1:0]: CPU clock switch status

This bitfield is security-protected by SYSSEC, SYSPRIV, and is publicly readable if
SYSPUB = 1. It is set and reset by hardware to show the source of the CPU clock
(sys_cpu_ck).
00: hsi_ck selected as system clock (default after reset)
01: msi_ck selected as system clock
10: hse_ck selected as system clock
11: ic1_ck selected as system clock
Bits 19:18 Reserved, must be kept at reset value.
Bits 17:16 CPUSW[1:0]: CPU clock switch selection
This bitfield is security-protected by SYSSEC, SYSPRIV, and is publicly readable if
SYSPUB = 1. It is set by the software to select the source of the CPU clock (sys_cpu_ck).
00: hsi_ck selected as system clock (default after reset)
01: msi_ck selected as system clock
10: hse_ck selected as system clock
11: ic1_ck selected as system clock
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 STOPWUCK: System clock selection after a wake up from system stop
This bit is security-protected by SYSSEC, SYSPRIV, and is publicly readable if SYSPUB = 1.
It is set and reset by software to select the system wake-up clock from system stop.
0: HSI selected as wake-up clock from system stop (default after reset)
1: MSI selected as wake-up clock from system stop

14.10.5 RCC configuration register 2 (RCC_CFGR2)

Address offset: 0x24
Reset value: 0x0010 0000
This register controls the division factors of the central clocks: AHB, APB, and timer. It is
reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. TIMPRE[1:0] Res. HPRE[2:0] Res. PPRE5[2:0]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. PPRE4[2:0] Res. Res. Res. Res. Res. PPRE2[2:0] Res. PPRE1[2:0]
rw rw rw rw rw rw rw rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:24 TIMPRE[1:0]: Timer clock prescaler selection
This bitfield is security-protected by a SEC signal from RIFSC, the SYSSEC bit, a PRIV
signal from RIFSC, or the SYSPRIV bit, and is publicly readable if SYSPUB = 1. It is set and
reset by software to control the clock frequency of all the timers connected to APB1 and
APB2 domains.
00: timg_ck = sys_bus_ck (default after reset)
01: timg_ck = sys_bus_ck / 2
10: timg_ck = sys_bus_ck / 4
11: timg_ck = sys_bus_ck / 8
Bit 23 Reserved, must be kept at reset value.

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Bits 22:20 HPRE[2:0]: AHB clock prescaler

This bitfield is security-protected by SYSSEC or SYSPRIV, and is publicly readable if
SYSPUB = 1. It is set and reset by software to control the division factor of the clocks
between the system AXI bus and the configuration AHB bus. The AXI sys_bus_ck source
clock is divided in function of HPRE, to generate the AHB clock.
The division ratio is as follows:
000: sys_bus2_ck= sys_bus_ck
001: sys_bus2_ck = sys_bus_ck / 2 (default after reset)
010: sys_bus2_ck= sys_bus_ck / 4
011: sys_bus2_ck = sys_bus_ck / 8
100: sys_bus2_ck = sys_bus_ck / 16
101: sys_bus2_ck = sys_bus_ck / 32
110: sys_bus2_ck = sys_bus_ck / 64
111: sys_bus2_ck = sys_bus_ck / 128
Bit 19 Reserved, must be kept at reset value.
Bits 18:16 PPRE5[2:0]: CPU domain APB5 prescaler
This bitfield is security-protected by SYSSEC or SYSPRIV, and is publicly readable if
SYSPUB = 1. It is set and reset by software to control the division factor of rcc_pclk5.
000: rcc_pclk5 = sys_bus2_ck (default after reset)
001: rcc_pclk5 = sys_bus2_ck / 2
010: rcc_pclk5 = sys_bus2_ck / 4
011: rcc_pclk5 = sys_bus2_ck / 8
100: rcc_pclk5 = sys_bus2_ck / 16
101: rcc_pclk5 = sys_bus2_ck / 32
110: rcc_pclk5 = sys_bus2_ck / 64
111: rcc_pclk5 = sys_bus2_ck / 128
Bit 15 Reserved, must be kept at reset value.
Bits 14:12 PPRE4[2:0]: CPU domain APB4 prescaler
This bitfield is security-protected by SYSSEC or SYSPRIV, and is publicly readable if
SYSPUB = 1. It is set and reset by software to control the division factor of rcc_pclk4.
000: rcc_pclk4 = sys_bus2_ck (default after reset)
001: rcc_pclk4 = sys_bus2_ck / 2
010: rcc_pclk4 = sys_bus2_ck / 4
011: rcc_pclk4 = sys_bus2_ck / 8
100: rcc_pclk4 = sys_bus2_ck / 16
101: rcc_pclk4 = sys_bus2_ck / 32
110: rcc_pclk4 = sys_bus2_ck / 64
111: rcc_pclk4 = sys_bus2_ck / 128
Bits 11:7 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

Bits 6:4 PPRE2[2:0]: CPU domain APB2 prescaler

This bitfield is security-protected by SYSSEC or SYSPRIV, and is publicly readable if
SYSPUB = 1. It is set and reset by software to control the division factor of rcc_pclk2.
000: rcc_pclk2 = sys_bus2_ck (default after reset)
001: rcc_pclk2 = sys_bus2_ck / 2
010: rcc_pclk2 = sys_bus2_ck / 4
011: rcc_pclk2 = sys_bus2_ck / 8
100: rcc_pclk2 = sys_bus2_ck / 16
101: rcc_pclk2 = sys_bus2_ck / 32
110: rcc_pclk2 = sys_bus2_ck / 64
111: rcc_pclk2 = sys_bus2_ck / 128
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 PPRE1[2:0]: CPU domain APB1 prescaler
This bitfield is security-protected by SYSSEC or SYSPRIV, and is publicly readable if
SYSPUB = 1. Is it set and reset by software to control the division factor of rcc_pclk1.
000: rcc_pclk1 = sys_bus2_ck (default after reset)
001: rcc_pclk1 = sys_bus2_ck / 2
010: rcc_pclk1 = sys_bus2_ck / 4
011: rcc_pclk1 = sys_bus2_ck / 8
100: rcc_pclk1 = sys_bus2_ck / 16
101: rcc_pclk1 = sys_bus2_ck / 32
110: rcc_pclk1 = sys_bus2_ck / 64
111: rcc_pclk1 = sys_bus2_ck / 128

14.10.6 RCC backup domain protection register (RCC_BDCR)

Address offset: 0x2C
Reset value: 0x0000 0000
This register controls the reset of the backup domain. It is reset by pwr_vsw_rstn, and is in
the VBKP voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VSW
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bit 31 VSWRST: Vswitch (VSW) domain software reset.

This bit is write-protected by the pwr_lock_backup_n signal. It is security-protected by a SEC
signal from RIFSC, the RSTSEC bit, a PRIV signal from RIFSC, or the RSTPRIV bit, and is
publicly readable if RSTPUB = 1. Writing 1 to this VSWRST bit by software generates a pulse
that resets the VSW domain.
0: VSW domain not reset (default after reset)
1: VSW domain reset
Bits 30:0 Reserved, must be kept at reset value.

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14.10.7 RCC reset status register for hardware (RCC_HWRSR)

Address offset: 0x30
Reset value: 0x00A0 0000
This register is used to monitor the resets that occurred. It is reset by pwr_por_rstn, and is in
the VBKP voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWR WWDG IWDGR SFTRS PORR PINRS BORR LCKRS
Res. Res. Res. Res. Res. Res. Res. RMVF
RSTF RSTF STF TF STF TF STF TF
r r r r r r r r w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bit 31 Reserved, must be kept at reset value.

Bit 30 LPWRRSTF: Illegal Stop or Standby flag
This bit is set by hardware when the CPU goes erroneously in Stop or Standby mode. It is
reset by software by writing HWRMVF.
0: No illegal reset occurred (default after power-on reset)
1: Illegal Stop or Standby reset occurred
Bit 29 Reserved, must be kept at reset value.
Bit 28 WWDGRSTF: Window watchdog reset flag
This bit is set by hardware when a window watchdog reset occurs. it is reset by software by
writing HWRMVF.
0: No window watchdog reset occurred from WWDG (default after power-on reset)
1: Window watchdog reset occurred from WWDG
Bit 27 Reserved, must be kept at reset value.
Bit 26 IWDGRSTF: Independent watchdog reset flag
This bit is set by hardware when an independent watchdog reset occurs. It is reset by
software by writing HWRMVF.
0: No independent watchdog reset occurred (default after power-on reset)
1: Independent watchdog reset occurred
Bit 25 Reserved, must be kept at reset value.
Bit 24 SFTRSTF: Software system reset flag
This bit is set by hardware when the software system reset is due to the [Link] CPU can
generate a software system reset by writing SYSRESETREQ in AIRCR register of the CPU.
This bit is reset by software by writing HWRMVF.
0: No software system reset occurred (default after power-on reset)
1: A software system reset has been generated by the CPU.
Bit 23 PORRSTF: POR/PDR reset flag
This bit is set by hardware when a POR/PDR occurs. it is reset by software by writing
HWRMVF.
0: No POR/PDR occurred
1: POR/PDR occurred (default after power-on reset)

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RM0486 Reset and clock control (RCC)

Bit 22 PINRSTF: Pin reset flag (NRST)

This bit is set by hardware when a reset from pin occurs. it is reset by software by writing
HWRMVF.
0: No reset from pin occurred
1: Reset from pin occurred (default after power-on reset)
Bit 21 BORRSTF: BOR reset flag
This bit is set by hardware when a BOR occurs (pwr_bor_rst). it is reset by software by
writing HWRMVF.
0: No BOR occurred
1: BOR occurred (default after power-on reset)
Bits 20:18 Reserved, must be kept at reset value.
Bit 17 LCKRSTF: CPU lockup reset flag
This bit is set by hardware when a reset from a CPU lockup occurs. Is it reset by software by
writing RMVF.
0: No reset from CPU lockup occurred
1: Reset from CPU lockup occurred
Bit 16 RMVF: Remove reset flag
This bit is write-protected by the security bit. It is security-protected by a SEC signal from
RIFSC, the RSTSEC bit, a PRIV signal from RIFSC, or the RSTPRIV bit, and is publicly
readable if RSTPUB = 1. This bit is written by software to clear the value of the reset flags in
this register.
0: Clear of the reset flags not activated (default after power-on reset)
1: Clear the value of the reset flags
Bits 15:0 Reserved, must be kept at reset value.

14.10.8 RCC reset register (RCC_RSR)

Address offset: 0x34
Reset value: 0x00A0 0000
This register is used to monitor the resets that occurred. It is reset by pwr_por_rstn, and is
in the VBKP voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWR WWDG IWDGR SFTRS PORR PINRS BORR LCKRS
Res. Res. Res. Res. Res. Res. Res. RMVF
RSTF RSTF STF TF STF TF STF TF
r r r r r r r r w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bit 31 Reserved, must be kept at reset value.

Bit 30 LPWRRSTF: Illegal Stop or Standby flag
This bit is set by hardware when the CPU goes erroneously in Stop or Standby mode. It is
reset by software by writing RMVF.
0: No illegal reset occurred (default after power-on reset)
1: Illegal Stop or Standby reset occurred
Bit 29 Reserved, must be kept at reset value.

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Bit 28 WWDGRSTF: Window watchdog reset flag

This bit is set by hardware when a window watchdog reset occurs. It is reset by software by
writing RMVF.
0: No window watchdog reset occurred from WWDG (default after power-on reset)
1: Window watchdog reset occurred from WWDG
Bit 27 Reserved, must be kept at reset value.
Bit 26 IWDGRSTF: Independent watchdog reset flag
This bit is set by hardware when an independent watchdog reset occurs. It is reset by
software by writing RMVF.
0: No independent watchdog reset occurred (default after power-on reset)
1: Independent watchdog reset occurred
Bit 25 Reserved, must be kept at reset value.
Bit 24 SFTRSTF: Software system reset flag
This bit is set by hardware when the software system reset is due to the [Link] CPU can
generate a software system reset by writing SYSRESETREQ in AIRCR register of the CPU.
This bit is reset by software by writing RMVF.
0: No software system reset occurred (default after power-on reset)
1: A software system reset has been generated by the CPU.
Bit 23 PORRSTF: POR/PDR reset flag
This bit is set by hardware when a POR/PDR occurs. It is reset by software by writing RMVF.
0: No POR/PDR occurred
1: POR/PDR occurred (default after power-on reset)
Bit 22 PINRSTF: Pin reset flag (NRST)
This bit is set by hardware when a reset from pin occurs. It is reset by software by writing
RMVF.
0: No reset from pin occurred
1: Reset from pin occurred (default after power-on reset)
Bit 21 BORRSTF: BOR reset flag
This bit is set by hardware when a BOR occurs (pwr_bor_rst). It is reset by software by
writing RMVF.
0: No BOR occurred
1: BOR occurred (default after power-on reset)
Bits 20:18 Reserved, must be kept at reset value.
Bit 17 LCKRSTF: CPU lockup reset flag
This bit is set by hardware when a reset from a CPU lockup occurs. it is reset by software by
writing RMVF.
0: No reset from CPU lockup occurred
1: Reset from CPU lockup occurred
Bit 16 RMVF: Remove reset flag
This bit is write-protected by the security bit. It is security-protected by a SEC signal from
RIFSC, the SYSSEC bit, a PRIV signal from RIFSC, or the SYSPRIV bit, and is publicly
readable if SYSPUB = 1. This bit is written by software to clear the value of the reset flags in
this register.
0: Clear of the reset flags not activated (default after power-on reset)
1: Clear the value of the reset flags
Bits 15:0 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

14.10.9 RCC LSE configuration register (RCC_LSECFGR)

Address offset: 0x40
Reset value: 0x0000 0000
This register is used to configure the LSE oscillator. It is reset by rcc_vsw_rstn, and is in the
VBKP voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSE LSE
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LSEDRV[1:0]
GFON EXT
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSE LSE LSE LSE
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
BYP CSSD CSSRA CSSON
rw r rw w

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:18 LSEDRV[1:0]: LSE oscillator driving capability
This bitfield is write-protected by the pwr_lock_backup_n signal. It is security-protected by
LSESEC or LSEPRIV, and is publicly readable if LSEPUB = 1. it is set by software to select
the driving capability of the LSE oscillator.
00: Lowest drive (default after reset)
01: Medium-high drive
10: Medium-low drive
11: Highest drive
Bit 17 LSEGFON: LSE clock glitch filter enable
This bit is write-protected by the pwr_lock_backup_n signal. It is security-protected by
LSESEC or LSEPRIV, and is publicly readable if LSEPUB = 1. This bit is set and cleared by
software to enable the LSE clock glitch filter. it t can be written only when LSE is disabled
(LSE ACT = 0).
0: LSE clock glitch filter disabled (default after reset)
1: LSE clock glitch filter enabled
Bit 16 LSEEXT: LSE clock type in bypass mode
This bit is write-protected by the pwr_lock_backup_n signal. It is security-protected by
LSESEC or LSEPRIV, and is publicly readable if LSEPUB = 1. This bit is set and reset by
software to select the external clock type (analog or digital).
The external clock must be enabled with the LSE enable bit to be used by the device.
This LSEEXT bit can be written only if the LSE oscillator is disabled.
0: LSE in analog mode (default after reset)
1: LSE in digital mode
Bit 15 LSEBYP: LSE clock bypass
This bit is write-protected by the pwr_lock_backup_n signal. It is security-protected by
LSESEC or LSEPRIV, and is publicly readable if LSEPUB = 1. This bit is set and cleared by
software to bypass the oscillator with an external clock.
The external clock must be enabled with the LSE enable bit to be used by the device.
This LSEBYP bit can be written even if the LSE oscillator is disabled.
0: LSE oscillator not bypassed (default after reset)
1: LSE oscillator bypassed with an external clock
Bits 14:10 Reserved, must be kept at reset value.

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Bit 9 LSECSSD: LSE clock security system (CSS) failure detection

This bit is set by hardware to indicate when a failure has been detected by the CSS on the
external LSE oscillator.
0: No failure detected on the oscillator (default after reset)
1: Failure detected on the oscillator
Bit 8 LSECSSRA: LSE clock security system (CSS) rearm function
This bit is write-protected by the pwr_lock_backup_n signal. It is security-protected by
LSESEC or LSEPRIV, and is publicly readable if LSEPUB = 1. This bit is set by software.
After an LSE failure detection, the software can re-enable the LSECSS by writing this bit to 1.
Reading this bit returns the written value. Prior to set this bit to 1, LSECSSON must be set
to 0. Refer to CSS on LSE for details.
0: Writing 0 has no effect (default after reset).
1: Writing 1 generates a rearm pulse for the LSECSS function.
Bit 7 LSECSSON: LSE clock security system (CSS) enable
This bit is write-protected by the pwr_lock_backup_n signal. It is security-protected by
LSESEC or LSEPRIV, and is publicly readable if LSEPUB = 1. This bit is set by software to
enable the CSS on the LSE oscillator. Refer to LSE oscillator for details on the activation and
deactivation sequences. Once this LSECSSON bit is enabled, it cannot be disabled, except
after an LSE failure detection (LSECSSD = 1).
0: CSS on the LSE oscillator OFF (default after reset)
1: CSS on the LSE oscillator ON
Bits 6:0 Reserved, must be kept at reset value.

14.10.10 RCC MSI configuration register (RCC_MSICFGR)

Address offset: 0x44
Reset value: 0x0000 0000
This register is used to configure the MSI oscillator. It is reset by int_sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. MSICAL[7:0] Res. Res. MSITRIM[4:0]
r r r r r r r r rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSIFR
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EQSEL
rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:23 MSICAL[7:0]: MSI clock calibration
This bitfield is set by hardware by option-byte loading during a system reset. It is adjusted by
software through MSITRIM bitfield. This MSICAL bitfield represents the sum of the
engineering-option-byte calibration value and MSITRIM[4:0] value.
Bits 22:21 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

Bits 20:16 MSITRIM[4:0]: MSI clock trimming

This bitfield is set by software to adjust calibration. It is added to the engineering option bytes
(CAL_BSEC_Fuse[7:0]) loaded during the reset phase (bsec_msi_cal[7:0]), to form the
calibration trimming value.
MSICAL[7:0] = MSITRIM[4:0] + CAL_BSEC_Fuse[7:0].
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 MSIFREQSEL: MSI oscillator frequency selection
This bit is set and cleared by software.
0: MSI oscillator frequency is 4 MHz (default after backup domain reset).
1: MSI oscillator frequency is 16 MHz.
Bits 8:0 Reserved, must be kept at reset value.

14.10.11 RCC HSI configuration register (RCC_HSICFGR)

Address offset: 0x48
Reset value: 0x0000 0000
This register is used to configure the HSI oscillator. It is reset by pwr_okin_vcore_rstn, and
is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSICAL[8:0] HSITRIM[6:0]
r r r r r r r r r rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. HSIDIV[1:0] Res. Res. Res. Res. Res. Res. Res.
rw rw

Bits 31:23 HSICAL[8:0]: HSI clock calibration

This bitfield is set by hardware by option-byte loading during a system reset. It is adjusted by
software through HSITRIM bitfield. This HSICAL bitfield represents the sum of the
engineering option byte calibration value and HSITRIM[6:0] value.
Bits 22:16 HSITRIM[6:0]: HSI clock trimming
This bitfield is set by software to adjust calibration. It represents a signed value, added to the
engineering option bytes (bsec_hsi_cal[8:0]) loaded during the reset phase (bsec_hsi_cal), to
form the calibration trimming value: HSICAL[8:0] = HSITRIM[6:0] + bsec_hsi_cal[8:0].
0x1-0x3F: bsec_hsi_cal[8:0] + {V}
0x40-0x7F: bsec_hsi_cal[8:0] - 128 + {v}
0x00: bsec_hsi_cal[8:0] (default after reset)
Bits 15:9 Reserved, must be kept at reset value.
Bits 8:7 HSIDIV[1:0]: HSI clock divider
This bitfield is set and reset by software to control the hsi_ck frequency (see Figure 37).
00: hsi_div_ck = hsi_ck (default after reset)
01: hsi_div_ck = hsi_ck / 2
10: hsi_div_ck = hsi_ck / 4
11: hsi_div_ck = hsi_ck / 8
Bits 6:0 Reserved, must be kept at reset value.

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14.10.12 RCC HSI monitor control register (RCC_HSIMCR)

Address offset: 0x4C
Reset value: 0x001F 07A1
This register is used to monitor and trim of the HSI oscillator. It is reset by int_sys_rstn, and
is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSI
Res. Res. Res. Res. Res. Res. Res. Res. Res. HSIDEV[5:0]
MONEN
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. HSIREF[10:0]
rw rw rw rw rw rw rw rw rw rw rw

Bit 31 HSIMONEN: HSI clock period monitor enable

This bit is set and cleared by software.
0: Writing 0 disables the HSI clock period monitoring. Reading 0 means that the HSI clock
period monitoring is disabled.
1: Writing 1 enables the HSI clock period monitoring. Reading 1 means that the HSI clock
period monitoring is enabled.
Bits 30:22 Reserved, must be kept at reset value.
Bits 21:16 HSIDEV[5:0]: HSI clock count deviation value
This bitfield is set and cleared by software.
Bits 15:11 Reserved, must be kept at reset value.
Bits 10:0 HSIREF[10:0]: HSI clock-cycle counter reference value.
This bit contains the number of HSI clock cycles expected between two consecutive rising
edges of the LSE signal. It is set by hardware.

14.10.13 RCC HSI monitor status register (RCC_HSIMSR)

Address offset: 0x50
Reset value: 0x0000 0000
This register is used to monitor and trim of the HSI oscillator. It is reset by int_sys_rstn, and
is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. HSIVAL[10:0]
r r r r r r r r r r r

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:0 HSIVAL[10:0]: HSI clock-cycle counter measured value
This bitfield contains the number of HSI clock cycles measured between consecutive rising
edges of the LSE signal. it is set by hardware.

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14.10.14 RCC HSE configuration register (RCC_HSECFGR)

Address offset: 0x54
Reset value: 0x0000 0800
This register is used to configure the HSE oscillator. It is reset by int_sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSE
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EXT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSE HSE HSE HSE HSE
HSECSSBPRE[3:0] Res. Res. Res. Res. Res. Res. Res.
BYP CSSBYP CSSD CSSON DIV2SEL
rw rw rw rw rw rw r rs rw

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 HSEEXT: HSE clock type in bypass mode
This bit is set and reset by software to select the external clock type (analog or digital). The
external clock must be enabled with the HSE enable bit to be used by the device. This
HSEEXT bit can be written only if the HSE oscillator is disabled.
0: HSE in analog mode (default after reset)
1: HSE in digital mode
Bit 15 HSEBYP: HSE clock bypass
This bit is set and cleared by software to bypass the oscillator with an external clock. The
external clock must be enabled with the HSE enable bit to be used by the device. This
HSEBYP bit can be written even if the HSE oscillator is disabled.
0: HSE oscillator not bypassed (default after reset)
1: HSE oscillator bypassed with an external clock
Bits 14:11 HSECSSBPRE[3:0]: HSE CSS bypass divider
This bitfield is set and reset by software to divide the replacement internal HSI oscillator that
bypasses the HSE oscillator when a failure is detected. Refer to HSE oscillator for details on
the activation and deactivation sequences.
0000: HSI clock divided by 1
0001: HSI clock divided by 2
0010: HSI clock divided by 3
0011: HSI clock divided by 4
0100: HSI clock divided by 5
0101: HSI clock divided by 6
0110: HSI clock divided by 7
0111: HSI clock divided by 8
1000: HSI clock divided by 9
1001: HSI clock divided by 10
1010: HSI clock divided by 11
1011: HSI clock divided by 12
1100: HSI clock divided by 13
1101: HSI clock divided by 14
1110: HSI clock divided by 15
1111: HSI clock divided by 16

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Bit 10 HSECSSBYP: HSE CSS bypass enable

This bit is set and reset by software to enable the CSS to bypass the HSE oscillator when a
failure is detected, and to get a clock from the HSI oscillator. Refer to HSE oscillator for
details on the activation and deactivation sequences.
0: CSS bypass of the HSE oscillator OFF (default after reset)
1: CSS bypass on the HSE oscillator ON
Bit 9 HSECSSD: HSE CSS failure detection
This bit is set by hardware to indicate when a failure has been detected by the CSS on the
external HSE oscillator.
0: No failure detected on the oscillator (default after reset)
1: Failure detected on the oscillator
Bit 8 Reserved, must be kept at reset value.
Bit 7 HSECSSON: HSE CSS enable
This bit is set by software to enable the CSS on the HSE oscillator. Refer to HSE oscillator for
details on the activation and deactivation sequences. Once this HSECSSON bit is enabled, it
cannot be disabled, except after an HSE failure detection (HSECSSD = 1).
0: CSS on the HSE oscillator OFF (default after reset)
1: CSS on the HSE oscillator ON
Bit 6 HSEDIV2SEL: HSE div2 clock source select
This bit is set and reset by software to select the source of the div2 output clock.
0: HSE: hse_div2_osc_ck = hse_osc_ck (default after reset)
1: HSE: hse_div2_osc_ck = hse_osc_ck/2
Bits 5:0 Reserved, must be kept at reset value.

14.10.15 RCC PLL1 configuration register 1 (RCC_PLL1CFGR1)

Address offset: 0x80
Reset value: 0x0820 2500
This register is used to configure the main features of PLL1. It is reset by int_sys_rst,n and
is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL1B
Res. PLL1SEL[2:0] Res. PLL1DIVM[5:0] PLL1DIVN[11:8]
YP
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL1DIVN[7:0] Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw rw rw rw rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:28 PLL1SEL[2:0]: PLL1 source selection of the reference clock
This bitfield is set and reset by software to select system clock source (sys_ck).
000: hsi_ck selected as reference clock
001: msi_ck selected as reference clock
010: hse_ck selected as reference clock
011: I2S_CKIN selected as reference clock

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Bit 27 PLL1BYP: PLL1 bypass

This bit is set and cleared by software to bypass the VCO, and to feed the output with the PLL
reference clock.
0: PLL output is driven by the VCO, via the optional POSTDIV division.
1: PLL output is bypassed and driven by the PLL reference clock (default after reset).
Bit 26 Reserved, must be kept at reset value.
Bits 25:20 PLL1DIVM[5:0]: PLL1 reference input clock divide frequency ratio
This bitfield is set and cleared by software.
0x00: Not applicable when the PLL is enabled
0x01: Reference clock divided by 1 (min value)
0x2-0x3F: Reference clock divided by {v}. It is recommended to configure the maximum
divided reference clock frequency close to FVCO / 16.
Bits 19:8 PLL1DIVN[11:0]: PLL1 integer part for the VCO multiplication factor
This bitfield is set and cleared by software to control the multiplication factor of the VCO.
VCO output frequency = reference clock * DIVN / DIVM when FRACV = 0.
In integer mode, this value must be set between 0x10 (16) and 0x280 (640).
In fractional mode, this value must be set between 0x14 (20) and 0x140 (320).
Bits 7:0 Reserved, must be kept at reset value.

14.10.16 RCC PLL1 configuration register 2 (RCC_PLL1CFGR2)

Address offset: 0x84
Reset value: 0x0080 0000
This register is used to configure the optional fractional feedback division of PLL1. It is reset
by int_sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. PLL1DIVNFRAC[23:16]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL1DIVNFRAC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:0 PLL1DIVNFRAC[23:0]: PLL1 fractional part of the VCO multiplication factor
This bitfield is set and cleared by software to control the VCO fractional multiplication factor.
VCO output frequency = reference clock * (DIVN + DIVNFRAC / 224) / DIVM.

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14.10.17 RCC PLL1 configuration register 3 (RCC_PLL1CFGR3)

Address offset: 0x88
Reset value: 0x4900 000D
This register is used to configure the SSCG and optional inner features of PLL1. It is reset
by int_sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL1P
Res. PLL1PDIV1[2:0] PLL1PDIV2[2:0] Res. Res. Res. PLL1MODSPR[4:0]
DIVEN
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL1M PLL1M PLL1M PLL1M
PLL1D
Res. Res. Res. Res. PLL1MODDIV[3:0] Res. Res. Res. ODSP ODDS ODSS ODSS
ACEN
RDW EN DIS RST
rw rw rw rw rw rw rw rw rw

Bit 31 Reserved, must be kept at reset value.

Bit 30 PLL1PDIVEN: PLL1 post divider POSTDIV1, POSTDIV2, and PLL clock output enable
This bit is set and cleared by software to enable the post divider.
0: POSTDIV1 and POSTDIV2 powered down
1: POSTDIV1 and POSTDIV2 active (default after reset)
Bits 29:27 PLL1PDIV1[2:0]: PLL1 VCO frequency divider level 1
This bitfield is set and cleared by software to divide the VCO frequency output.
000: Not applicable
001: VCO output divided by 1 (minimum value) (default after reset)
010: VCO output divided by 2
011: VCO output divided by 3
100: VCO output divided by 4
101: VCO output divided by 5
110: VCO output divided by 6
111: VCO output divided by 7
Bits 26:24 PLL1PDIV2[2:0]: PLL1 VCO frequency divider level 2
This bitfield is set and cleared by software to divide the VCO frequency output.
000: Not applicable
001: VCO output divided by 1 (minimum value) (default after reset)
010: VCO output divided by 2
011: VCO output divided by 3
100: VCO output divided by 4
101: VCO output divided by 5
110: VCO output divided by 6
111: VCO output divided by 7
Bits 23:21 Reserved, must be kept at reset value.
Bits 20:16 PLL1MODSPR[4:0]: PLL1 modulation spread depth adjustment
This bitfield is set and cleared by software to adjust the modulation depth of the clock
spreading generator.
Bits 15:12 Reserved, must be kept at reset value.

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Bits 11:8 PLL1MODDIV[3:0]: PLL1 modulation division frequency adjustment

This bitfield is set and cleared by software to adjust the modulation frequency of the clock
spreading generator. Corresponds to DIVVAL in Figure 43).
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 PLL1MODSPRDW: PLL1 modulation spread spectrum down
This bit is set and cleared by software to select the clock spreading mode of PLL1.
0: Center-spread modulation selected (default after reset)
1: Down-spread modulation selected
Bit 3 PLL1MODDSEN: PLL1 modulation spread spectrum (and fractional divide) enable
This bit is set and cleared by software to enable the delta-sigma modulator.
0: Modulation spread spectrum and fractional divide not active
1: Modulation spread spectrum and fractional divide active (default after reset)
Bit 2 PLL1MODSSDIS: PLL1 modulation spread spectrum disable
This bit is set and cleared by software to enable the clock spreading generator of PLL1.
0: Modulation spread spectrum active (and fractional divide inactive)
1: Fractional divide active (and modulation spread spectrum inactive) (default after reset)
Bit 1 PLL1DACEN: PLL1 noise canceling DAC enable in fractional mode
This bit is set and cleared by software to enable the noise cancellation in fractional mode.
0: DAC not active (default after reset)
1: DAC active
Bit 0 PLL1MODSSRST: PLL1 modulation spread spectrum reset
This bit is set and cleared by software.
0: PLL1 modulation spread spectrum reset module released
1: PLL1 modulation spread spectrum reset module asserted (default after reset)

14.10.18 RCC PLL2 configuration register 1 (RCC_PLL2CFGR1)

Address offset: 0x90
Reset value: 0x0800 0000
This register is used to configure the main features of PLL2. It is reset by int_sys_rstn, and
is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL2B
Res. PLL2SEL[2:0] Res. PLL2DIVM[5:0] PLL2DIVN[11:8]
YP
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL2DIVN[7:0] Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw rw rw rw rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:28 PLL2SEL[2:0]: PLL2 source selection of the reference clock
This bitfield is set and reset by software to select system clock source (sys_ck).
000: hsi_ck selected as reference clock
001: msi_ck selected as reference clock
010: hse_ck selected as reference clock
011: I2S_CKIN selected as reference clock

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Bit 27 PLL2BYP: PLL2 bypass

This bit is set and cleared by software to bypass the VC,O and to feed the output with the PLL
reference clock.
0: PLL output is driven by the VCO, via the optional POSTDIV division.
1: PLL output is bypassed and driven by the PLL reference clock (default after reset).
Bit 26 Reserved, must be kept at reset value.
Bits 25:20 PLL2DIVM[5:0]: PLL2 reference input clock divide frequency ratio
This bitfield is set and cleared by software.
0x2-0x3F: Reference clock is divided by {v}. The maximum divided reference clock frequency
must be close to FVCO/16.
0x00: Not applicable when PLL is enabled
0x01: Reference clock is divided by 1 (min value).
Bits 19:8 PLL2DIVN[11:0]: PLL2 integer part for the VCO multiplication factor
This bitfield is set and cleared by software to control the multiplication factor of the VCO.
VCO output frequency = reference clock * DIVN / DIVM when FRACV = 0.
In integer mode, this value must be set between 0x10 (16) and 0x280 (640).
In fractional mode, this value must be set between 0x14 (20) and 0x140 (320).
Bits 7:0 Reserved, must be kept at reset value.

14.10.19 RCC PLL2 configuration register 2 (RCC_PLL2CFGR2)

Address offset: 0x94
Reset value: 0x0000 0000
This register is used to configure the optional fractional feedback division of PLL2. It is reset
by int_sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. PLL2DIVNFRAC[23:16]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL2DIVNFRAC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:0 PLL2DIVNFRAC[23:0]: PLL2 fractional part of the VCO multiplication factor
This bitfield is set and cleared by software to control the VCO fractional multiplication factor.
VCO output frequency = reference clock * (DIVN + DIVNFRAC / 224) / DIVM.

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14.10.20 RCC PLL2 configuration register 3 (RCC_PLL2CFGR3)

Address offset: 0x98
Reset value: 0x4900 0005
This register is used to configure the SSCG and optional inner features of PLL2. It is reset
by int_sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL2P
Res. PLL2PDIV1[2:0] PLL2PDIV2[2:0] Res. Res. Res. PLL2MODSPR[4:0]
DIVEN
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL2M PLL2M PLL2M PLL2M
PLL2D
Res. Res. Res. Res. PLL2MODDIV[3:0] Res. Res. Res. ODSP ODDS ODSS ODSS
ACEN
RDW EN DIS RST
rw rw rw rw rw rw rw rw rw

Bit 31 Reserved, must be kept at reset value.

Bit 30 PLL2PDIVEN: PLL2 post divider POSTDIV1, POSTDIV2, and PLL clock output enable
This bit is set and cleared by software to enable the post divider.
0: POSTDIV1 and POSTDIV2 powered down
1: POSTDIV1 and POSTDIV2 active (default after reset)
Bits 29:27 PLL2PDIV1[2:0]: PLL2 VCO frequency divider level 1
This bitfield is set and cleared by software to divide the VCO frequency output.
000: Not applicable
001: VCO output divided by 1 (minimum value) (default after reset)
010: VCO output divided by 2
011: VCO output divided by 3
100: VCO output divided by 4
101: VCO output divided by 5
110: VCO output divided by 6
111: VCO output divided by 7
Bits 26:24 PLL2PDIV2[2:0]: PLL2 VCO frequency divider level 2
This bitfield is set and cleared by software to divide the VCO frequency output.
000: Not applicable
001: VCO output divided by 1 (minimum value) (default after reset)
010: VCO output divided by 2
011: VCO output divided by 3
100: VCO output divided by 4
101: VCO output divided by 5
110: VCO output divided by 6
111: VCO output divided by 7
Bits 23:21 Reserved, must be kept at reset value.
Bits 20:16 PLL2MODSPR[4:0]: PLL2 modulation spread depth adjustment
This bitfield is set and cleared by software to adjust the modulation depth of the clock
spreading generator.
Bits 15:12 Reserved, must be kept at reset value.

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Bits 11:8 PLL2MODDIV[3:0]: PLL2 modulation division frequency adjustment

This bitfield is set and cleared by software to adjust the modulation frequency of the clock
spreading generator. It corresponds to DIVVAL in Figure 43.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 PLL2MODSPRDW: PLL2 modulation down spread
This bit is set and cleared by software to select the clock spreading mode of PLL2.
0: Center-spread modulation selected (default after reset)
1: Down-spread modulation selected
Bit 3 PLL2MODDSEN: PLL2 modulation spread spectrum (and fractional divide) enable
This bit is set and cleared by software to enable the delta-sigma modulator.
0: Modulation spread spectrum and fractional divide not active (default after reset)
1: Modulation spread spectrum and fractional divide active
Bit 2 PLL2MODSSDIS: PLL2 modulation spread spectrum disable
This bit is set and cleared by software to enable the clock spreading generator of PLL2.
0: Modulation spread spectrum active (and fractional divide inactive)
1: Fractional divide active (and the Modulation spread spectrum inactive) (default after reset)
Bit 1 PLL2DACEN: PLL2 noise canceling DAC enable in fractional mode
This bit is set and cleared by software to enable the noise cancellation in fractional mode.
0: DAC not active (default after reset)
1: DAC active
Bit 0 PLL2MODSSRST: PLL2 modulation spread spectrum reset
This bit is set and cleared by software.
0: PLL2 modulation spread spectrum reset module released
1: PLL2 modulation spread spectrum reset module asserted (default after reset)

14.10.21 RCC PLL3 configuration register 1 (RCC_PLL3CFGR1)

Address offset: 0xA0
Reset value: 0x0800 0000
This register is used to configure the main features of PLL3. It is reset by int_sys_rstn, and
is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL3B
Res. PLL3SEL[2:0] Res. PLL3DIVM[5:0] PLL3DIVN[11:8]
YP
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL3DIVN[7:0] Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw rw rw rw rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:28 PLL3SEL[2:0]: PLL3 source selection of the reference clock
This bitfield is set and reset by software to select system clock source (sys_ck).
000: hsi_ck selected as reference clock
001: msi_ck selected as reference clock
010: hse_ck selected as reference clock
011: I2S_CKIN selected as reference clock

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RM0486 Reset and clock control (RCC)

Bit 27 PLL3BYP: PLL3 bypass

This bit is set and cleared by software to bypass the VCO and feed the output with the PLL
reference clock.
0: PLL output is driven by the VCO, via the optional POSTDIV division.
1: PLL output is bypassed and driven by the PLL reference clock (default after reset).
Bit 26 Reserved, must be kept at reset value.
Bits 25:20 PLL3DIVM[5:0]: PLL3 reference input clock divide frequency ratio
This bitfield is set and cleared by software.
0x2-0x3F: Reference clock is divided by {v}. The maximum divided reference clock frequency
must be close to FVCO/16.
0x00: Not applicable when PLL is enabled
0x01: Reference clock is divided by 1 (min value)
Bits 19:8 PLL3DIVN[11:0]: PLL3 Integer part for the VCO multiplication factor
This bitfield is set and cleared by software to control the multiplication factor of the VCO.
VCO output frequency = reference clock * DIVN / DIVM when FRACV = 0.
In integer mode, this value must be set between 0x10 (16) and 0x280 (640).
In fractional mode, this value must be set between 0x14 (20) and 0x140 (320).
Bits 7:0 Reserved, must be kept at reset value.

14.10.22 RCC PLL3 configuration register 2 (RCC_PLL3CFGR2)

Address offset: 0xA4
Reset value: 0x0000 0000
This register is used to configure the optional fractional feedback division of PLL3. It is reset
by int_sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. PLL3DIVNFRAC[23:16]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL3DIVNFRAC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:0 PLL3DIVNFRAC[23:0]: PLL3 fractional part of the VCO multiplication factor
This bitfield is set and cleared by software to control the VCO fractional multiplication factor.
VCO output frequency = reference clock * (DIVN + DIVNFRAC / 224) / DIVM.

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14.10.23 RCC PLL3 configuration register 3 (RCC_PLL3CFGR3)

Address offset: 0xA8
Reset value: 0x4900 0005
This register is used to configure the SSCG and optional inner features of PLL3. It is reset
by int_sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL3P
Res. PLL3PDIV1[2:0] PLL3PDIV2[2:0] Res. Res. Res. PLL3MODSPR[4:0]
DIVEN
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL3M PLL3M PLL3M PLL3M
PLL3D
Res. Res. Res. Res. PLL3MODDIV[3:0] Res. Res. Res. ODSP ODDS ODSS ODSS
ACEN
RDW EN DIS RST
rw rw rw rw rw rw rw rw rw

Bit 31 Reserved, must be kept at reset value.

Bit 30 PLL3PDIVEN: PLL3 post divider POSTDIV1, POSTDIV2, and PLL clock output enable
This bit is set and cleared by software to enable the post divider.
0: POSTDIV1 and POSTDIV2 powered down
1: POSTDIV1 and POSTDIV2 active (default after reset)
Bits 29:27 PLL3PDIV1[2:0]: PLL3 VCO frequency divider level 1
This bitfield is set and cleared by software to divide the VCO frequency output.
000: Not applicable
001: VCO output divided by 1 (minimum value) (default after reset)
010: VCO output divided by 2
011: VCO output divided by 3
100: VCO output divided by 4
101: VCO output divided by 5
110: VCO output divided by 6
111: VCO output divided by 7
Bits 26:24 PLL3PDIV2[2:0]: PLL3 VCO frequency divider level 2
This bitfield is set and cleared by software to divide the VCO frequency output.
000: Not applicable
001: VCO output divided by 1 (minimum value) (default after reset)
010: VCO output divided by 2
011: VCO output divided by 3
100: VCO output divided by 4
101: VCO output divided by 5
110: VCO output divided by 6
111: VCO output divided by 7
Bits 23:21 Reserved, must be kept at reset value.
Bits 20:16 PLL3MODSPR[4:0]: PLL3 modulation spread depth adjustment
This bitfield is set and cleared by software to adjust the modulation depth of the clock
spreading generator.
Bits 15:12 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

Bits 11:8 PLL3MODDIV[3:0]: PLL3 modulation division frequency adjustment

This bitfield is set and cleared by software to adjust the modulation frequency of the clock
spreading generator. It corresponds to DIVVAL in Figure 43.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 PLL3MODSPRDW: PLL3 modulation down spread
This bit is set and cleared by software to select the clock spreading mode of PLL3.
0: Center-spread modulation selected (default after reset)
1: Down-spread modulation selected
Bit 3 PLL3MODDSEN: PLL3 modulation spread spectrum (and fractional divide) enable
This bit is set and cleared by software to enable the delta-sigma modulator.
0: Modulation spread spectrum and fractional divide not active (default after reset)
1: Modulation spread spectrum and fractional divide active
Bit 2 PLL3MODSSDIS: PLL3 modulation spread spectrum disable
This bit is set and cleared by software to enable the clock spreading generator of PLL3.
0: Modulation spread spectrum active (and fractional divide inactive)
1: Fractional divide active (and the modulation spread spectrum inactive) (default after reset)
Bit 1 PLL3DACEN: PLL3 noise canceling DAC enable in fractional mode
This bit is set and cleared by software to enable the noise cancellation in fractional mode.
0: DAC not active (default after reset)
1: DAC active
Bit 0 PLL3MODSSRST: PLL3 modulation spread spectrum reset
This bit is set and cleared by software.
0: PLL3 modulation spread spectrum reset module released
1: PLL3 modulation spread spectrum reset module asserted (default after reset)

14.10.24 RCC PLL4 configuration register 1 (RCC_PLL4CFGR1)

Address offset: 0xB0
Reset value: 0x0800 0000
This register is used to configure the main features of PLL4. It is reset by int_sys_rstn, and
is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL4B
Res. PLL4SEL[2:0] Res. PLL4DIVM[5:0] PLL4DIVN[11:8]
YP
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4DIVN[7:0] Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw rw rw rw rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:28 PLL4SEL[2:0]: PLL4 source selection of the reference clock
This bitfield is set and reset by software to select system clock source (sys_ck).
000: hsi_ck selected as reference clock
001: msi_ck selected as reference clock
010: hse_ck selected as reference clock
011: I2S_CKIN selected as reference clock

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Bit 27 PLL4BYP: PLL4 bypass

This bit is set and cleared by software to bypass the VCO, and to feed the output with the PLL
reference clock.
0: PLL output is driven by the VCO, via the optional POSTDIV division.
1: PLL output is bypassed and driven by the PLL reference clock (default after reset).
Bit 26 Reserved, must be kept at reset value.
Bits 25:20 PLL4DIVM[5:0]: PLL4 reference input clock divide frequency ratio
This bitfield is set and cleared by software.
0x2-0x3F: Reference clock is divided by {v}. The maximum divided reference clock frequency
must be close to FVCO/16.
0x00: Not applicable when PLL is enabled
0x01: Reference clock is divided by 1 (min value).
Bits 19:8 PLL4DIVN[11:0]: PLL4 integer part for the VCO multiplication factor
This bitfield is set and cleared by software to control the multiplication factor of the VCO.
VCO output frequency = reference clock * DIVN / DIVM when FRACV = 0.
In integer mode, this value must be set between 0x10 (16) and 0x280 (640).
In fractional mode, this value must be set between 0x14 (20) and 0x140 (320).
Bits 7:0 Reserved, must be kept at reset value.

14.10.25 RCC PLL4 configuration register 2 (RCC_PLL4CFGR2)

Address offset: 0xB4
Reset value: 0x0000 0000
This register is used to configure the optional fractional feedback division of PLL4. It is reset
by int_sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. PLL4DIVNFRAC[23:16]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4DIVNFRAC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:0 PLL4DIVNFRAC[23:0]: PLL4 fractional part of the VCO multiplication factor
This bitfield is set and cleared by software to control the VCO fractional multiplication factor.
VCO output frequency = reference clock * (DIVN + DIVNFRAC / 224) / DIVM.

14.10.26 RCC PLL4 configuration register 3 (RCC_PLL4CFGR3)

Address offset: 0xB8
Reset value: 0x4900 0005
This register is used to configure the SSCG and optional inner features of PLL4. It is reset
by int_sys_rstn, and is in the VCORE voltage domain.

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RM0486 Reset and clock control (RCC)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL4P
Res. PLL4PDIV1[2:0] PLL4PDIV2[2:0] Res. Res. Res. PLL4MODSPR[4:0]
DIVEN
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4M PLL4M PLL4M PLL4M
PLL4D
Res. Res. Res. Res. PLL4MODDIV[3:0] Res. Res. Res. ODSP ODDS ODSS ODSS
ACEN
RDW EN DIS RST
rw rw rw rw rw rw rw rw rw

Bit 31 Reserved, must be kept at reset value.

Bit 30 PLL4PDIVEN: PLL4 post divider POSTDIV1, POSTDIV2, and PLL clock output enable
This bit is set and cleared by software to enable the post divider.
0: POSTDIV1 and POSTDIV2 powered down
1: POSTDIV1 and POSTDIV2 active (default after reset)
Bits 29:27 PLL4PDIV1[2:0]: PLL4 VCO frequency divider level 1
This bitfield is set and cleared by software to divide the VCO frequency output.
000: Not applicable
001: VCO output divided by 1 (minimum value) (default after reset)
010: VCO output divided by 2
011: VCO output divided by 3
100: VCO output divided by 4
101: VCO output divided by 5
110: VCO output divided by 6
111: VCO output divided by 7
Bits 26:24 PLL4PDIV2[2:0]: PLL4 VCO frequency divider level 2
This bitfield is set and cleared by software to divide the VCO frequency output.
000: Not applicable
001: VCO output divided by 1 (minimum value) (default after reset)
010: VCO output divided by 2
011: VCO output divided by 3
100: VCO output divided by 4
101: VCO output divided by 5
110: VCO output divided by 6
111: VCO output divided by 7
Bits 23:21 Reserved, must be kept at reset value.
Bits 20:16 PLL4MODSPR[4:0]: PLL4 modulation spread depth adjustment
This bitfield is set and cleared by software to adjust the modulation depth of the clock
spreading generator.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:8 PLL4MODDIV[3:0]: PLL4 modulation division frequency adjustment
This bitfield is set and cleared by software to adjust the modulation frequency of the clock
spreading generator. It corresponds to DIVVAL in Figure 43.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 PLL4MODSPRDW: PLL4 modulation down spread
This bit is set and cleared by software to select the clock spreading mode of PLL4.
0: Center-spread modulation selected (default after reset)
1: Down-spread modulation selected

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Bit 3 PLL4MODDSEN: PLL4 modulation spread spectrum (and fractional divide) enable
This bitfield is set and cleared by software to enable the delta-sigma modulator.
0: Modulation spread spectrum and fractional divide not active (default after reset)
1: Modulation spread spectrum and fractional divide active
Bit 2 PLL4MODSSDIS: PLL4 modulation spread spectrum disable
This bit is set and cleared by software to enable the clock spreading generator of PLL4.
0: Modulation spread spectrum active (and fractional divide inactive)
1: Fractional divide active (and modulation spread spectrum inactive) (default after reset)
Bit 1 PLL4DACEN: PLL4 noise canceling DAC enable in fractional mode
This bit is set and cleared by software to enable the noise cancellation in fractional mode.
0: DAC not active (default after reset)
1: DAC active
Bit 0 PLL4MODSSRST: PLL4 modulation spread spectrum reset
This bit is set and cleared by software.
0: PLL4 modulation spread spectrum reset module released
1: PLL4 modulation spread spectrum reset module asserted (default after reset)

14.10.27 RCC IC1 configuration register (RCC_IC1CFGR)

Address offset: 0xC4
Reset value: 0x0002 0000
This register is used to configure the IC1 divider. It is reset by int_sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IC1SEL[1:0] Res. Res. Res. Res. IC1INT[7:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 IC1SEL[1:0]: Divider IC1 source selection
This bitfield is set and reset by software to select the PLL output to feed for the channel IC1.
00: pll1_ck selected (default after reset)
01: pll2_ck selected
10: pll3_ck selected
11: pll4_ck selected
Bits 27:24 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

Bits 23:16 IC1INT[7:0]: Divider IC1 integer division factor

This bitfield is set and reset by software to control the frequency of the IC1 clock. The
frequency is divided by the value IC1INT + 1: {v}: IC1 = pllx_ck / {v + 1}.
0x00: IC1 = pllx_ck
0x01: IC1 = pllx_ck / 2
0x02: IC1 = pllx_ck / 3 (default after reset)
0x03: IC1 = pllx_ck / 4
...
0xFF: IC1 = pllx_ck / 256
Bits 15:0 Reserved, must be kept at reset value.

14.10.28 RCC IC2 configuration register (RCC_IC2CFGR)

Address offset: 0xC8
Reset value: 0x0003 0000
This register is used to configure the IC2 divider. It is reset by int_sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IC2SEL[1:0] Res. Res. Res. Res. IC2INT[7:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 IC2SEL[1:0]: Divider IC2 source selection
This bitfield is set and reset by software to select the PLL output to feed for the channel IC2.
00: pll1_ck selected (default after reset)
01: pll2_ck selected
10: pll3_ck selected
11: pll4_ck selected
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:16 IC2INT[7:0]: Divider IC2 integer division factor
This bitfield is set and reset by software to control the frequency of the IC2 clock. The
frequency is divided by the value IC2INT + 1: {v}: IC2 = pllx_ck / {v + 1}.
0x00: IC2 = pllx_ck
0x01: IC2 = pllx_ck / 2
0x02: IC2 = pllx_ck / 3
0x03: IC2 = pllx_ck / 4 (default after reset)
...
0xFF: IC2 = pllx_ck / 256
Bits 15:0 Reserved, must be kept at reset value.

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14.10.29 RCC IC3 configuration register (RCC_IC3CFGR)

Address offset: 0xCC
Reset value: 0x0000 0000
This register is used to configure the IC3 divider. It is reset by int_sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IC3SEL[1:0] Res. Res. Res. Res. IC3INT[7:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 IC3SEL[1:0]: Divider IC3 source selection
This bitfield is set and reset by software to select the PLL output to feed for the channel IC3.
00: pll1_ck selected (default after reset)
01: pll2_ck selected
10: pll3_ck selected
11: pll4_ck selected
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:16 IC3INT[7:0]: Divider IC3 integer division factor
This bitfield is set and reset by software to control the frequency of the IC3 clock. The
frequency is divided by the value IC3INT + 1: {v}: IC3 = pllx_ck / {v + 1}.
0x00: IC3 = pllx_ck (default after reset)
0x01: IC3 = pllx_ck / 2
0x02: IC3 = pllx_ck / 3
0x03: IC3 = pllx_ck / 4
...
0xFF: IC3 = pllx_ck / 256
Bits 15:0 Reserved, must be kept at reset value.

14.10.30 RCC IC4 configuration register (RCC_IC4CFGR)

Address offset: 0xD0
Reset value: 0x0000 0000
This register is used to configure the IC4 divider. It is reset by int_sys_rstn and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IC4SEL[1:0] Res. Res. Res. Res. IC4INT[7:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

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RM0486 Reset and clock control (RCC)

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 IC4SEL[1:0]: Divider IC4 source selection
This bitfield is set and reset by software to select the PLL output to feed for the channel IC4.
00: pll1_ck selected (default after reset)
01: pll2_ck selected
10: pll3_ck selected
11: pll4_ck selected
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:16 IC4INT[7:0]: Divider IC4 integer division factor
This bitfield is set and reset by software to control the frequency of the IC4 clock. The
frequency is divided by the value IC4INT+1: {v}: IC4 = pllx_ck / {v + 1}.
0x00: IC4 = pllx_ck (default after reset)
0x01: IC4 = pllx_ck / 2
0x02: IC4 = pllx_ck / 3
0x03: IC4 = pllx_ck / 4
...
0xFF: IC4 = pllx_ck / 256
Bits 15:0 Reserved, must be kept at reset value.

14.10.31 RCC IC5 configuration register (RCC_IC5CFGR)

Address offset: 0xD4
Reset value: 0x0000 0000
This register is used to configure the IC5 divider. It is reset by int_sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IC5SEL[1:0] Res. Res. Res. Res. IC5INT[7:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 IC5SEL[1:0]: Divider IC5 source selection
This bitfield is set and reset by software to select the PLL output to feed for the channel IC5.
00: pll1_ck selected (default after reset)
01: pll2_ck selected
10: pll3_ck selected
11: pll4_ck selected
Bits 27:24 Reserved, must be kept at reset value.

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Bits 23:16 IC5INT[7:0]: Divider IC5 integer division factor

This bitfield is set and reset by software to control the frequency of the IC5 clock. The
frequency is divided by the value IC5INT + 1: {v}: IC5 = pllx_ck / {v + 1}.
0x00: IC5 = pllx_ck (default after reset)
0x01: IC5 = pllx_ck / 2
0x02: IC5 = pllx_ck / 3
0x03: IC5 = pllx_ck / 4
...
0xFF: IC5 = pllx_ck / 256
Bits 15:0 Reserved, must be kept at reset value.

14.10.32 RCC IC6 configuration register (RCC_IC6CFGR)

Address offset: 0xD8
Reset value: 0x0003 0000
This register is used to configure the IC6 divider. It is reset by int_sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IC6SEL[1:0] Res. Res. Res. Res. IC6INT[7:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 IC6SEL[1:0]: Divider IC6 source selection
This bitfield is set and reset by software to select the PLL output to feed for the channel IC6.
00: pll1_ck selected (default after reset)
01: pll2_ck selected
10: pll3_ck selected
11: pll4_ck selected
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:16 IC6INT[7:0]: Divider IC6 integer division factor
This bitfield is set and reset by software to control the frequency of the IC6 clock. The
frequency is divided by the value IC6INT+1: {v}: IC6 = pllx_ck / {v + 1}.
0x00: IC6 = pllx_ck
0x01: IC6 = pllx_ck / 2
0x02: IC6 = pllx_ck / 3
0x03: IC6 = pllx_ck / 4 (default after reset)
...
0xFF: IC6 = pllx_ck / 256
Bits 15:0 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

14.10.33 RCC IC7 configuration register (RCC_IC7CFGR)

Address offset: 0xDC
Reset value: 0x1000 0000
This register is used to configure the IC7 divider. It is reset by int_sys_rstn, and is
in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IC7SEL[1:0] Res. Res. Res. Res. IC7INT[7:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 IC7SEL[1:0]: Divider IC7 source selection
This bitfield is set and reset by software to select the PLL output to feed for the channel IC7.
00: pll1_ck selected
01: pll2_ck selected (default after reset)
10: pll3_ck selected
11: pll4_ck selected
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:16 IC7INT[7:0]: Divider IC7 integer division factor
This bitfield is set and reset by software to control the frequency of the IC7 clock. The
frequency is divided by the value IC7INT + 1: {v}: IC7 = pllx_ck / {v + 1}.
0x00: IC7 = pllx_ck (default after reset)
0x01: IC7 = pllx_ck / 2
0x02: IC7 = pllx_ck / 3
0x03: IC7 = pllx_ck / 4
...
0xFF: IC7 = pllx_ck / 256
Bits 15:0 Reserved, must be kept at reset value.

14.10.34 RCC IC8 configuration register (RCC_IC8CFGR)

Address offset: 0xE0
Reset value: 0x1000 0000
This register is used to configure the IC8 divider. It is reset by int_sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IC8SEL[1:0] Res. Res. Res. Res. IC8INT[7:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

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Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 IC8SEL[1:0]: Divider IC8 source selection
This bitfield is set and reset by software to select the PLL output to feed for the channel IC8.
00: pll1_ck selected
01: pll2_ck selected (default after reset)
10: pll3_ck selected
11: pll4_ck selected
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:16 IC8INT[7:0]: Divider IC8 integer division factor
This bitfield is set and reset by software to control the frequency of the IC8 clock. The
frequency is divided by the value IC8INT + 1: {v}: IC8 = pllx_ck / {v + 1}.
0x00: IC8 = pllx_ck (default after reset)
0x01: IC8 = pllx_ck / 2
0x02: IC8 = pllx_ck / 3
0x03: IC8 = pllx_ck / 4
...
0xFF: IC8 = pllx_ck / 256
Bits 15:0 Reserved, must be kept at reset value.

14.10.35 RCC IC9 configuration register (RCC_IC9CFGR)

Address offset: 0xE4
Reset value: 0x1000 0000
This register is used to configure the IC9 divider. It is reset by int_sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IC9SEL[1:0] Res. Res. Res. Res. IC9INT[7:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 IC9SEL[1:0]: Divider IC9 source selection
This bitfield is set and reset by software to select the PLL output to feed for the channel IC9.
00: pll1_ck selected
01: pll2_ck selected (default after reset)
10: pll3_ck selected
11: pll4_ck selected
Bits 27:24 Reserved, must be kept at reset value.

510/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bits 23:16 IC9INT[7:0]: Divider IC9 integer division factor

This bitfield is set and reset by software to control the frequency of the IC9 clock. The
frequency is divided by the value IC9INT + 1: {v}: IC9 = pllx_ck / {v + 1}.
0x00: IC9 = pllx_ck (default after reset)
0x01: IC9 = pllx_ck / 2
0x02: IC9 = pllx_ck / 3
0x03: IC9 = pllx_ck / 4
...
0xFF: IC9 = pllx_ck / 256
Bits 15:0 Reserved, must be kept at reset value.

14.10.36 RCC IC10 configuration register (RCC_IC10CFGR)

Address offset: 0xE8
Reset value: 0x1000 0000
This register is used to configure the IC10 divider. It is reset by int_sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IC10SEL[1:0] Res. Res. Res. Res. IC10INT[7:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 IC10SEL[1:0]: Divider IC10 source selection
This bitfield is set and reset by software to select the PLL output to feed for the channel IC10.
00: pll1_ck selected
01: pll2_ck selected (default after reset)
10: pll3_ck selected
11: pll4_ck selected
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:16 IC10INT[7:0]: Divider IC10 integer division factor
This bitfield is set and reset by software to control the frequency of the IC10 clock. The
frequency is divided by the value IC10INT + 1. {v}: IC10 = pllx_ck / {v + 1}.
0x00: IC10 = pllx_ck (default after reset)
0x01: IC10 = pllx_ck / 2
0x02: IC10 = pllx_ck / 3
0x03: IC10 = pllx_ck / 4
...
0xFF: IC10 = pllx_ck / 256
Bits 15:0 Reserved, must be kept at reset value.

14.10.37 RCC IC11 configuration register (RCC_IC11CFGR)

Address offset: 0xEC
Reset value: 0x0003 0000

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This register is used to configure the IC11 divider. It is reset by int_sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IC11SEL[1:0] Res. Res. Res. Res. IC11INT[7:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 IC11SEL[1:0]: Divider IC11 source selection
This bitfield is set and reset by software to select the PLL output to feed for the channel IC11.
00: pll1_ck selected (default after reset)
01: pll2_ck selected
10: pll3_ck selected
11: pll4_ck selected
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:16 IC11INT[7:0]: Divider IC11 integer division factor
This bitfield is set and reset by software to control the frequency of the IC11 clock. The
frequency is divided by the value IC11INT + 1: {v}: IC11 = pllx_ck / {v + 1}.
0x00: IC11 = pllx_ck
0x01: IC11 = pllx_ck / 2
0x02: IC11 = pllx_ck / 3
0x03: IC11 = pllx_ck / 4 (default after reset)
...
0xFF: IC11 = pllx_ck / 256
Bits 15:0 Reserved, must be kept at reset value.

14.10.38 RCC IC12 configuration register (RCC_IC12CFGR)

Address offset: 0xF0
Reset value: 0x2000 0000
This register is used to configure the IC12 divider. It is reset by int_sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IC12SEL[1:0] Res. Res. Res. Res. IC12INT[7:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:30 Reserved, must be kept at reset value.

512/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bits 29:28 IC12SEL[1:0]: Divider IC12 source selection

This bitfield is set and reset by software to select the PLL output to feed for the channel IC12.
00: pll1_ck selected
01: pll2_ck selected
10: pll3_ck selected (default after reset)
11: pll4_ck selected
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:16 IC12INT[7:0]: Divider IC12 integer division factor
This bitfield is set and reset by software to control the frequency of the IC12 clock. The
frequency is divided by the value IC12INT + 1: {v}: IC12 = pllx_ck / {v + 1}.
0x00: IC12 = pllx_ck (default after reset)
0x01: IC12 = pllx_ck / 2
0x02: IC12 = pllx_ck / 3
0x03: IC12 = pllx_ck / 4
...
0xFF: IC12 = pllx_ck / 256
Bits 15:0 Reserved, must be kept at reset value.

14.10.39 RCC IC13 configuration register (RCC_IC13CFGR)

Address offset: 0xF4
Reset value: 0x2000 0000
This register is used to configure the IC13 divider. It is reset by int_sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IC13SEL[1:0] Res. Res. Res. Res. IC13INT[7:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 IC13SEL[1:0]: Divider IC13 source selection
This bitfield is set and reset by software to select the PLL output to feed for the channel IC13.
00: pll1_ck selected
01: pll2_ck selected
10: pll3_ck selected (default after reset)
11: pll4_ck selected
Bits 27:24 Reserved, must be kept at reset value.

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Bits 23:16 IC13INT[7:0]: Divider IC13 integer division factor

This bitfield is set and reset by software to control the frequency of the IC13 clock. The
frequency is divided by the value IC13INT + 1: {v}: IC13 = pllx_ck / {v + 1}.
0x00: IC13 = pllx_ck (default after reset)
0x01: IC13 = pllx_ck / 2
0x02: IC13 = pllx_ck / 3
0x03: IC13 = pllx_ck / 4
...
0xFF: IC13 = pllx_ck / 256
Bits 15:0 Reserved, must be kept at reset value.

14.10.40 RCC IC14 configuration register (RCC_IC14CFGR)

Address offset: 0xF8
Reset value: 0x2000 0000
This register is used to configure the IC14 divider. It is reset by int_sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IC14SEL[1:0] Res. Res. Res. Res. IC14INT[7:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 IC14SEL[1:0]: Divider IC14 source selection
This bitfield is set and reset by software to select the PLL output to feed for the channel IC14.
00: pll1_ck selected
01: pll2_ck selected
10: pll3_ck selected (default after reset)
11: pll4_ck selected
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:16 IC14INT[7:0]: Divider IC14 integer division factor
This bitfield is set and reset by software to control the frequency of the IC14 clock. The
frequency is divided by the value IC14INT + 1. {v}: IC14 = pllx_ck / {v + 1}.
0x00: IC14 = pllx_ck (default after reset)
0x01: IC14 = pllx_ck / 2
0x02: IC14 = pllx_ck / 3
0x03: IC14 = pllx_ck / 4
...
0xFF: IC14 = pllx_ck / 256
Bits 15:0 Reserved, must be kept at reset value.

514/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

14.10.41 RCC IC15 configuration register (RCC_IC15CFGR)

Address offset: 0xFC
Reset value: 0x2000 0000
This register is used to configure the IC15 divider. It is reset by int_sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IC15SEL[1:0] Res. Res. Res. Res. IC15INT[7:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 IC15SEL[1:0]: Divider IC15 source selection
This bitfield is set and reset by software to select the PLL output to feed for the channel IC15.
00: pll1_ck selected
01: pll2_ck selected
10: pll3_ck selected (default after reset)
11: pll4_ck selected
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:16 IC15INT[7:0]: Divider IC15 integer division factor
This bitfield is set and reset by software to control the frequency of the IC15 clock. The
frequency is divided by the value IC15INT + 1: {v}: IC15 = pllx_ck / {v + 1}.
0x00: IC15 = pllx_ck (default after reset)
0x01: IC15 = pllx_ck / 2
0x02: IC15 = pllx_ck / 3
0x03: IC15 = pllx_ck / 4
...
0xFF: IC15 = pllx_ck / 256
Bits 15:0 Reserved, must be kept at reset value.

14.10.42 RCC IC16 configuration register (RCC_IC16CFGR)

Address offset: 0x100
Reset value: 0x3000 0000
This register is used to configure the IC16 divider. It is reset by int_sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IC16SEL[1:0] Res. Res. Res. Res. IC16INT[7:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

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Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 IC16SEL[1:0]: Divider IC16 source selection
This bitfield is set and reset by software to select the PLL output to feed for the channel IC16.
00: pll1_ck i selected
01: pll2_ck selected
10: pll3_ck selected
11: pll4_ck selected (default after reset)
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:16 IC16INT[7:0]: Divider IC16 integer division factor
This bitfield is set and reset by software to control the frequency of the IC16 clock. The
frequency is divided by the value IC16INT + 1: {v}: IC16 = pllx_ck / {v + 1}.
0x00: IC16 = pllx_ck (default after reset)
0x01: IC16 = pllx_ck / 2
0x02: IC16 = pllx_ck / 3
0x03: IC16 = pllx_ck / 4
Bits 15:0 Reserved, must be kept at reset value.

14.10.43 RCC IC17 configuration register (RCC_IC17CFGR)

Address offset: 0x104
Reset value: 0x3000 0000
This register is used to configure the IC17 divider. It is reset by int_sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IC17SEL[1:0] Res. Res. Res. Res. IC17INT[7:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 IC17SEL[1:0]: Divider IC17 source selection
This bitfield is set and reset by software to select the PLL output to feed for the channel IC17.
00: pll1_ck selected
01: pll2_ck selected
10: pll3_ck selected
11: pll4_ck selected (default after reset)
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:16 IC17INT[7:0]: Divider IC17 integer division factor
This bitfield is set and reset by software to control the frequency of the IC17 clock. The
frequency is divided by the value IC17INT + 1: {v}: IC17 = pllx_ck / {v + 1}.
0x00: IC17 = pllx_ck (default after reset)
0x01: IC17 = pllx_ck / 2
0x02: IC17 = pllx_ck / 3
0x03: IC17 = pllx_ck / 4

516/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bits 15:0 Reserved, must be kept at reset value.

14.10.44 RCC IC18 configuration register (RCC_IC18CFGR)

Address offset: 0x108
Reset value: 0x3000 0000
This register is used to configure the IC18 divider. It is reset by int_sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IC18SEL[1:0] Res. Res. Res. Res. IC18INT[7:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 IC18SEL[1:0]: Divider IC18 source selection
This bitfield is set and reset by software to select the PLL output to feed for the channel IC18.
00: pll1_ck selected
01: pll2_ck selected
10: pll3_ck selected
11: pll4_ck selected (default after reset)
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:16 IC18INT[7:0]: Divider IC18 integer division factor
This bitfield is set and reset by software to control the frequency of the IC18 clock. The
frequency is divided by the value IC18INT + 1: {v}: IC18 = pllx_ck / {v + 1}.
0x00: IC18 = pllx_ck (default after reset)
0x01: IC18 = pllx_ck / 2
0x02: IC18 = pllx_ck / 3
0x03: IC18 = pllx_ck / 4
Bits 15:0 Reserved, must be kept at reset value.

14.10.45 RCC IC19 configuration register (RCC_IC19CFGR)

Address offset: 0x10C
Reset value: 0x3000 0000
This register is used to configure the IC19 divider. It is reset by int_sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IC19SEL[1:0] Res. Res. Res. Res. IC19INT[7:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

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Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 IC19SEL[1:0]: Divider IC19 source selection
This bitfield is set and reset by software to select the PLL output to feed for the channel IC19.
00: pll1_ck selected
01: pll2_ck selected
10: pll3_ck selected
11: pll4_ck selected (default after reset)
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:16 IC19INT[7:0]: Divider IC19 integer division factor
This bitfield is set and reset by software to control the frequency of the IC19 clock. The
frequency is divided by the value IC19INT + 1: {v}: IC19 = pllx_ck / {v + 1}.
0x00: IC19 = pllx_ck (default after reset)
0x01: IC19 = pllx_ck / 2
0x02: IC19 = pllx_ck / 3
0x03: IC19 = pllx_ck / 4
Bits 15:0 Reserved, must be kept at reset value.

14.10.46 RCC IC20 configuration register (RCC_IC20CFGR)

Address offset: 0x110
Reset value: 0x3000 0000
This register is used to configure the IC20 divider. It is reset by int_sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IC20SEL[1:0] Res. Res. Res. Res. IC20INT[7:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 IC20SEL[1:0]: Divider IC20 source selection
This bitfield is set and reset by software to select the PLL output to feed for the channel IC20.
00: pll1_ck selected
01: pll2_ck selected
10: pll3_ck selected
11: pll4_ck selected (default after reset)
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:16 IC20INT[7:0]: Divider IC20 integer division factor
This bitfield is set and reset by software to control the frequency of the IC20 clock. The
frequency is divided by the value IC20INT + 1. {v}: IC20 = pllx_ck / {v + 1}.
0x00: IC20 = pllx_ck (default after reset)
0x01: IC20 = pllx_ck / 2
0x02: IC20 = pllx_ck / 3
0x03: IC20 = pllx_ck / 4

518/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bits 15:0 Reserved, must be kept at reset value.

14.10.47 RCC clock-source interrupt enable register (RCC_CIER)

Address offset: 0x124
Reset value: 0x0002 0000
This register controls the enabling (unmasking) of the interrupts.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUPI HSECS LSECS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
E SIE SIE
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4R PLL3R PLL2R PLL1R HSERD HSIRD MSIRD LSERD LSIRD
Res. Res. Res. Res. Res. Res. Res.
DYIE DYIE DYIE DYIE YIE YIE YIE YIE YIE
rw rw rw rw rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 WKUPIE: CPU wake-up from Stop interrupt enable
This bit is set and reset by software to enable/disable interrupt caused by CPU wake-up from
Stop mode.
0: Wake-up interrupt disabled (default after reset)
1: Wake-up interrupt enabled
Bits 23:18 Reserved, must be kept at reset value.
Bit 17 HSECSSIE: HSE CSS interrupt enable
This bit is set and reset by software to enable/disable interrupt caused by the CSS on
external 32 kHz oscillator.
0: HSE CSS interrupt disabled
1: HSE CSS interrupt enabled (default after reset)
Bit 16 LSECSSIE: LSE CSS interrupt enable
This bit is set and reset by software to enable/disable interrupt caused by the CSS on
external 32 kHz oscillator.
0: LSE CSS interrupt disabled (default after reset)
1: LSE CSS interrupt enabled
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 PLL4RDYIE: PLL4 ready interrupt enable
This bit is set and reset by software to enable/disable interrupt caused by PLL4 lock.
0: PLL4 lock interrupt disabled (default after reset)
1: PLL4 lock interrupt enabled
Bit 10 PLL3RDYIE: PLL3 ready interrupt enable
This bit is set and reset by software to enable/disable interrupt caused by PLL3 lock.
0: PLL3 lock interrupt disabled (default after reset)
1: PLL3 lock interrupt enabled
Bit 9 PLL2RDYIE: PLL2 ready interrupt enable
This bit is set and reset by software to enable/disable interrupt caused by PLL2 lock.
0: PLL2 lock interrupt disabled (default after reset)
1: PLL2 lock interrupt enabled

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Bit 8 PLL1RDYIE: PLL1 ready interrupt enable

This bit is set and reset by software to enable/disable interrupt caused by PLL1 lock.
0: PLL1 lock interrupt disabled (default after reset)
1: PLL1 lock interrupt enabled
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 HSERDYIE: HSE ready interrupt enable
This bit is set and reset by software to enable/disable interrupt caused by the HSE oscillator
stabilization.
0: HSE ready interrupt disabled (default after reset)
1: HSE ready interrupt enabled
Bit 3 HSIRDYIE: HSI ready interrupt enable
This bit is set and reset by software to enable/disable interrupt caused by the HSI oscillator
stabilization.
0: HSI ready interrupt disabled (default after reset)
1: HSI ready interrupt enabled
Bit 2 MSIRDYIE: MSI ready interrupt enable
This bit is set and reset by software to enable/disable interrupt caused by the MSI oscillator
stabilization.
0: MSI ready interrupt disabled (default after reset)
1: MSI ready interrupt enabled
Bit 1 LSERDYIE: LSE ready interrupt enable
This bit is set and reset by software to enable/disable interrupt caused by the LSE oscillator
stabilization.
0: LSE ready interrupt disabled (default after reset)
1: LSE ready interrupt enabled
Bit 0 LSIRDYIE: LSI ready interrupt enable
This bit is set and reset by software to enable/disable interrupt caused by the LSI oscillator
stabilization.
0: LSI ready interrupt disabled (default after reset)
1: LSI ready interrupt enabled

14.10.48 RCC clock-source interrupt flag register (RCC_CIFR)

Address offset: 0x128
Reset value: 0x0000 0000
This register returns the triggered interrupts. It is reset by sys_rstn.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUP HSECS LSECS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
F SF SF
r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4R PLL3R PLL2R PLL1R HSERD HSIRD MSIRD LSERD LSIRD
Res. Res. Res. Res. Res. Res. Res.
DYF DYF DYF DYF YF YF YF YF YF
r r r r r r r r r

Bits 31:25 Reserved, must be kept at reset value.

520/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bit 24 WKUPF: CPU wake-up from Stop interrupt flag

This bit is reset by software by writing the WKUPFC bit. It is set by hardware when the CPU
needs to exit Stop mode.
0: No wake-up interrupt caused by the PWR (default after reset)
1: Wake-up interrupt caused by the PWR
Bits 23:18 Reserved, must be kept at reset value.
Bit 17 HSECSSF: HSE ready interrupt flag
This bit is reset by software by writing the HSECSSC bit. It is set by hardware when the HSE
clock becomes stable and HSECSSIE is set.
0: No clock ready interrupt caused by the HSE (default after reset)
1: Clock ready interrupt caused by the HSE
Bit 16 LSECSSF: LSE ready interrupt flag
This bit is reset by software by writing the LSECSSC bit. It is set by hardware when the LSE
clock becomes stable and LSECSSIE is set.
0: No clock ready interrupt caused by the LSE (default after reset)
1: Clock ready interrupt caused by the LSE
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 PLL4RDYF: PLL4 ready interrupt flag
This bit is reset by software by writing the PLL4RDYC bit. It is set by hardware when the
PLL4 clock becomes stable and PLL4RDYIE is set.
0: No clock ready interrupt caused by the PLL4 (default after reset)
1: Clock ready interrupt caused by the PLL4
Bit 10 PLL3RDYF: PLL3 ready interrupt flag
This bit is reset by software by writing the PLL3RDYC bit. It is set by hardware when the
PLL3 clock becomes stable and PLL3RDYIE is set.
0: No clock ready interrupt caused by the PLL3 (default after reset)
1: Clock ready interrupt caused by the PLL3
Bit 9 PLL2RDYF: PLL2 ready interrupt flag
This bit is reset by software by writing the PLL2RDYC bit. it is set by hardware when the
PLL2 clock becomes stable and PLL2RDYIE is set.
0: No clock ready interrupt caused by the PLL2 (default after reset)
1: Clock ready interrupt caused by the PLL2
Bit 8 PLL1RDYF: PLL1 ready interrupt flag
This bit is reset by software by writing the PLL1RDYC bit. It is set by hardware when the
PLL1 clock becomes stable and PLL1RDYIE is set.
0: No clock ready interrupt caused by the PLL1 (default after reset)
1: Clock ready interrupt caused by the PLL1
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 HSERDYF: HSE ready interrupt flag
This bit is reset by software by writing the HSERDYC bit. It is set by hardware when the HSE
clock becomes stable and HSERDYIE is set.
0: No clock ready interrupt caused by the HSE (default after reset)
1: Clock ready interrupt caused by the HSE

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Bit 3 HSIRDYF: HSI ready interrupt flag

This bit is reset by software by writing the HSIRDYC bit. It is set by hardware when the HSI
clock becomes stable and HSIRDYIE is set.
0: No clock ready interrupt caused by the HSI (default after reset)
1: Clock ready interrupt caused by the HSI
Bit 2 MSIRDYF: MSI ready interrupt flag
This bit is reset by software by writing the MSIRDYC bit. It is set by hardware when the MSI
clock becomes stable and MSIRDYIE is set.
0: No clock ready interrupt caused by the MSI (default after reset)
1: Clock ready interrupt caused by the MSI
Bit 1 LSERDYF: LSE ready interrupt flag
This bit is reset by software by writing the LSERDYC bit. It is set by hardware when the LSE
clock becomes stable and LSERDYIE is set.
0: No clock ready interrupt caused by the LSE (default after reset)
1: Clock ready interrupt caused by the LSE
Bit 0 LSIRDYF: LSI ready interrupt flag
This bit is reset by software by writing the LSIRDYC bit. It is set by hardware when the LSI
clock becomes stable and LSIRDYIE is set.
0: No clock ready interrupt caused by the LSI (default after reset)
1: Clock ready interrupt caused by the LSI

14.10.49 RCC clock-source interrupt clear register (RCC_CICR)

Address offset: 0x12C
Reset value: 0x0000 0000
This register clears the interrupts.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUP HSECS LSECS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
FC SC SC
w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4R PLL3R PLL2R PLL1R HSERD HSIRD MSIRD LSERD LSIRD
Res. Res. Res. Res. Res. Res. Res.
DYC DYC DYC DYC YC YC YC YC YC
w w w w w w w w w

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 WKUPFC: CPU wake-up ready interrupt clear
This bit is set by software to clear WKUPF. It is reset by hardware when clear done.
0: WKUPF not modified (default after reset)
1: WKUPF cleared
Bits 23:18 Reserved, must be kept at reset value.
Bit 17 HSECSSC: HSE ready interrupt clear
This bit is set by software to clear HSECSSF. it is reset by hardware when clear done.
0: HSECSSF not modified (default after reset)
1: HSECSSF cleared

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RM0486 Reset and clock control (RCC)

Bit 16 LSECSSC: LSE ready interrupt clear

This bit is set by software to clear LSECSSF. It is reset by hardware when clear done.
0: LSECSSF not modified (default after reset)
1: LSECSSF cleared
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 PLL4RDYC: PLL4 ready interrupt clear
This bit is set by software to clear PLL4RDYF. It is reset by hardware when clear done.
0: PLL4RDYF not modified (default after reset)
1: PLL4RDYF cleared
Bit 10 PLL3RDYC: PLL3 ready interrupt clear
This bit is set by software to clear PLL3RDYF. it is reset by hardware when clear done.
0: PLL3RDYF not modified (default after reset)
1: PLL3RDYF cleared
Bit 9 PLL2RDYC: PLL2 ready interrupt clear
This bit is set by software to clear PLL2RDYF. It is reset by hardware when clear done.
0: PLL2RDYF not modified (default after reset)
1: PLL2RDYF cleared
Bit 8 PLL1RDYC: PLL1 ready interrupt clear
This bit is set by software to clear PLL1RDYF. It is reset by hardware when clear done.
0: PLL1RDYF not modified (default after reset)
1: PLL1RDYF cleared
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 HSERDYC: HSE ready interrupt clear
This bit is set by software to clear HSERDYF. It is reset by hardware when clear done.
0: HSERDYF not modified (default after reset)
1: HSERDYF cleared
Bit 3 HSIRDYC: HSI ready interrupt clear
This bit is set by software to clear HSIRDYF. It is reset by hardware when clear done.
0: HSIRDYF not modified (default after reset)
1: HSIRDYF cleared
Bit 2 MSIRDYC: MSI ready interrupt clear
This bit is set by software to clear MSIRDYF. It is reset by hardware when clear done.
0: MSIRDYF not modified (default after reset)
1: MSIRDYF cleared
Bit 1 LSERDYC: LSE ready interrupt clear
This bit is set by software to clear LSERDYF. it is reset by hardware when clear done.
0: LSERDYF not modified (default after reset)
1: LSERDYF cleared
Bit 0 LSIRDYC: LSI ready interrupt clear
This bit is set by software to clear LSIRDYF. It is reset by hardware when clear done.
0: LSIRDYF not modified (default after reset)
1: LSIRDYF cleared

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Reset and clock control (RCC) RM0486

14.10.50 RCC clock configuration for independent peripheral register 1

(RCC_CCIPR1)
Address offset: 0x144
Reset value: 0x0000 0000
This register is used to configure various clocks. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DCMIPPSEL[1:0] Res. Res. Res. Res.
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCPRE[7:0] Res. ADC12SEL[2:0] Res. ADF1SEL[2:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:20 DCMIPPSEL[1:0]: Source selection for the DCMIPP kernel clock
This bitfield is set and reset by software.
00: pclk5 selected as reference clock
01: per_ck selected as reference clock
10: ic17_ck selected as reference clock
11: hsi_div_ck selected as reference clock
Bits 19:16 Reserved, must be kept at reset value.
Bits 15:8 ADCPRE[7:0]: ADC12 kernel clock divider selection (for clock ck_ker_adc12)
This bitfield is set and reset by software. The division ratio is linear: {v}: ck_ker_adc12 / {v+1}.
0x00: ck_ker_adc12 divided by 1
0x01: ck_ker_adc12 divided by 2
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 ADC12SEL[2:0]: Source selection for the ADC12 kernel clock
This bitfield is set and reset by software.
000: hclk1 selected as reference clock
001: per_ck selected as reference clock
010: ic7_ck selected as reference clock
011: ic8_ck selected as reference clock
100: msi_ck selected as reference clock
101: hsi_div_ck selected as reference clock
110: I2S_CKIN selected as reference clock
111: timg_ck selected as reference clock
Bit 3 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

Bits 2:0 ADF1SEL[2:0]: Source selection for the ADF1 kernel clock
This bitfield is set and reset by software.
000: hclk2 selected as reference clock
001: per_ck selected as reference clock
010: ic7_ck selected as reference clock
011: ic8_ck selected as reference clock
100: msi_ck selected as reference clock
101: hsi_div_ck selected as reference clock
110: I2S_CKIN selected as reference clock
111: timg_ck selected as reference clock

14.10.51 RCC clock configuration for independent peripheral register 2

(RCC_CCIPR2)
Address offset: 0x148
Reset value: 0x0000 0000
This register is used to configure various clocks. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETH1G ETH1R
Res. Res. Res. Res. Res. Res. Res. TXCLKS Res. Res. Res. EFCLK Res. ETH1SEL[2:0]
EL SEL
rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETH1P
ETH1CLKSEL ETH1PTPSEL
Res. Res. Res. Res. Res. WRDO ETH1PTPDIV[3:0] Res. Res.
[1:0] [1:0]
WNACK
rw rw r rw rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 ETH1GTXCLKSEL: Ethernet 1 reference Tx RGMII 125 MHz clock selection
This bit is set and reset by software.
0: External clock (ETH1_CLK125) is used. Need to program AFmux.
1: Internal clock from the RCC is used.
Bits 23:21 Reserved, must be kept at reset value.
Bit 20 ETH1REFCLKSEL: Ethernet 1 reference Rx clock selection
This bit is set and reset by software.
0: External clock (ETH_RX/REF_CLK) is used. This is RX clock for an RGMII or MII PHY, or
REF clock for an RMII PHY. Need to program AFmux.
1: Internal clock (ck_ker_eth1 from RCC) is used. To be used when the RMII 50 MHz (pad
ETH1_CLK) is generated to the RMII PHY.
Bit 19 Reserved, must be kept at reset value.

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Bits 18:16 ETH1SEL[2:0]: Ethernet 1 PHY interface selection

This bitfield is set and reset by software.
Note: Apply this configuration while the ETH1 is under reset, before enabling the ETH1 clocks.
000: MII
001: RGMII
100: RMII
Others: Reserved
Bits 15:14 Reserved, must be kept at reset value.
Bits 13:12 ETH1CLKSEL[1:0]: Source selection for the ETH1 kernel clock
This bitfield is set and reset by software.
00: hclke selected as reference clock
01: per_ck selected as reference clock
10: ic12_ck selected as reference clock
11: hse_ck selected as reference clock
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 ETH1PWRDOWNACK: Ethernet 1 Power-down status
This bit is set and reset by software. It is asserted when the power-down sequence start has
been acknowledged.
0: Power-down sequence start not yet acknowledged
1: Power-down sequence start acknowledged
Bits 7:4 ETH1PTPDIV[3:0]: ETH1 kernel clock divider selection (for clock ck_ker_eth1ptp)
This bitfield is set and reset by software. The division ratio is linear.
0000: ck_ker_eth1ptp divided by 1
0001: ck_ker_eth1ptp divided by 2
0010: ck_ker_eth1ptp divided by 3
0011: ck_ker_eth1ptp divided by 4
0100: ck_ker_eth1ptp divided by 5
0101: ck_ker_eth1ptp divided by 6
0110: ck_ker_eth1ptp divided by 7
0111: ck_ker_eth1ptp divided by 8
1000: ck_ker_eth1ptp divided by 9
1001: ck_ker_eth1ptp divided by 10
1010: ck_ker_eth1ptp divided by 11
1011: ck_ker_eth1ptp divided by 12
1100: ck_ker_eth1ptp divided by 13
1101: ck_ker_eth1ptp divided by 14
1110: ck_ker_eth1ptp divided by 15
1111: ck_ker_eth1ptp divided by 16
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 ETH1PTPSEL[1:0]: Source selection for the ETH1 kernel clock
This bitfield is set and reset by software.
00: hclke selected as reference clock
01: per_ck selected as reference clock
10: ic13_ck selected as reference clock
11: hse_ck selected as reference clock

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RM0486 Reset and clock control (RCC)

14.10.52 RCC clock configuration for independent peripheral register 3

(RCC_CCIPR3)
Address offset: 0x14C
Reset value: 0x0000 0003
This register is used to configure various clocks. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FMCSEL[1:0] Res. Res. FDCANSEL[1:0]
rw rw rw rw

Bits 31:6 Reserved, must be kept at reset value.

Bits 5:4 FMCSEL[1:0]: Source selection for the FMC kernel clock
This bitfield is set and reset by software.
00: hclk5 selected as reference clock
01: per_ck selected as reference clock
10: ic3_ck selected as reference clock
11: ic4_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 FDCANSEL[1:0]: Source selection for the FDCAN kernel clock
This bitfield is set and reset by software.
00: pclk1 selected as reference clock
01: per_ck selected as reference clock
10: ic19_ck selected as reference clock
11: hse_ck selected as reference clock
Others: Reserved, no clock provided as reference clock

14.10.53 RCC clock configuration for independent peripheral register 4

(RCC_CCIPR4)
Address offset: 0x150
Reset value: 0x0000 0000
This register is used to configure various clocks. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. LTDCSEL[1:0] Res. I3C2SEL[2:0] Res. I3C1SEL[2:0]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. I2C4SEL[2:0] Res. I2C3SEL[2:0] Res. I2C2SEL[2:0] Res. I2C1SEL[2:0]
rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:26 Reserved, must be kept at reset value.

Bits 25:24 LTDCSEL[1:0]: Source selection for the LTDC kernel clock
This bitfield is set and reset by software.
00: pclk5 selected as reference clock
01: per_ck selected as reference clock
10: ic16_ck selected as reference clock
11: hsi_div_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 23 Reserved, must be kept at reset value.
Bits 22:20 I3C2SEL[2:0]: Source selection for the I3C2 kernel clock
This bitfield is set and reset by software.
000: pclk1 selected as reference clock
001: per_ck selected as reference clock
010: ic10_ck selected as reference clock
011: ic15_ck selected as reference clock
100: msi_ck selected as reference clock
101: hsi_div_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 19 Reserved, must be kept at reset value.
Bits 18:16 I3C1SEL[2:0]: Source selection for the I3C1 kernel clock
This bitfield is set and reset by software.
000: pclk1 selected as reference clock
001: per_ck selected as reference clock
010: ic10_ck selected as reference clock
011: ic15_ck selected as reference clock
100: msi_ck selected as reference clock
101: hsi_div_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 15 Reserved, must be kept at reset value.
Bits 14:12 I2C4SEL[2:0]: Source selection for the I2C4 kernel clock
This bitfield is set and reset by software.
000: pclk1 selected as reference clock
001: per_ck selected as reference clock
010: ic10_ck selected as reference clock
011: ic15_ck selected as reference clock
100: msi_ck selected as reference clock
101: hsi_div_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 11 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

Bits 10:8 I2C3SEL[2:0]: Source selection for the I2C3 kernel clock
This bitfield is set and reset by software.
000: pclk1 selected as reference clock
001: per_ck selected as reference clock
010: ic10_ck selected as reference clock
011: ic15_ck selected as reference clock
100: msi_ck selected as reference clock
101: hsi_div_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 I2C2SEL[2:0]: Source selection for the I2C2 kernel clock
This bitfield is set and reset by software.
000: pclk1 selected as reference clock
001: per_ck selected as reference clock
010: ic10_ck selected as reference clock
011: ic15_ck selected as reference clock
100: msi_ck selected as reference clock
101: hsi_div_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 I2C1SEL[2:0]: Source selection for the I2C1 kernel clock
This bitfield is set and reset by software.
000: pclk1 selected as reference clock
001: per_ck selected as reference clock
010: ic10_ck selected as reference clock
011: ic15_ck selected as reference clock
100: msi_ck selected as reference clock
101: hsi_div_ck selected as reference clock
Others: Reserved, no clock provided as reference clock

14.10.54 RCC clock configuration for independent peripheral register 5

(RCC_CCIPR5)
Address offset: 0x154
Reset value: 0x0000 F0F0
This register is used to configure various clocks. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MDF1SEL[2:0]
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCO2PRE[3:0] Res. MCO2SEL[2:0] MCO1PRE[3:0] Res. MCO1SEL[2:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value.

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Bits 18:16 MDF1SEL[2:0]: Source selection for the MDF1 kernel clock
This bitfield is set and reset by software.
000: hclk2 selected as reference clock
001: per_ck selected as reference clock
010: ic7_ck selected as reference clock
011: ic8_ck selected as reference clock
100: msi_ck selected as reference clock
101: hsi_div_ck selected as reference clock
110: I2S_CKIN selected as reference clock
111: timg_ck selected as reference clock
Bits 15:12 MCO2PRE[3:0]: MCO2 Kernel clock divider selection (for clock MCO2)
This bitfield is set and reset by software. The division ratio is linear.
0000: MCO2 divided by 1
0001: MCO2 divided by 2
0010: MCO2 divided by 3
0011: MCO2 divided by 4
0100: MCO2 divided by 5
0101: MCO2 divided by 6
0110: MCO2 divided by 7
0111: MCO2 divided by 8
1000: MCO2 divided by 9
1001: MCO2 divided by 10
1010: MCO2 divided by 11
1011: MCO2 divided by 12
1100: MCO2 divided by 13
1101: MCO2 divided by 14
1110: MCO2 divided by 15
1111: MCO2 divided by 16
Bit 11 Reserved, must be kept at reset value.
Bits 10:8 MCO2SEL[2:0]: Source selection for the MCO2 kernel clock
This bitfield is set and reset by software.
000: hsi_div_ck selected as reference clock (default after reset)
001: lse_ck selected as reference clock
010: msi_ck selected as reference clock
011: lsi_ck selected as reference clock
100: hse_ck selected as reference clock
101: ic15_ck selected as reference clock
110: ic20_ck selected as reference clock
111: sysb_ck selected as reference clock

530/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bits 7:4 MCO1PRE[3:0]: MCO1 Kernel clock divider selection (for clock MCO1)
This bitfield is set and reset by software. The division ratio is linear.
0000: MCO1 divided by 1
0001: MCO1 divided by 2
0010: MCO1 divided by 3
0011: MCO1 divided by 4
0100: MCO1 divided by 5
0101: MCO1 divided by 6
0110: MCO1 divided by 7
0111: MCO1 divided by 8
1000: MCO1 divided by 9
1001: MCO1 divided by 10
1010: MCO1 divided by 11
1011: MCO1 divided by 12
1100: MCO1 divided by 13
1101: MCO1 divided by 14
1110: MCO1 divided by 15
1111: MCO1 divided by 16
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 MCO1SEL[2:0]: Source selection for the MCO1 kernel clock
This bitfield is set and reset by software.
000: hsi_div_ck selected as reference clock (default after reset)
001: lse_ck selected as reference clock
010: msi_ck selected as reference clock
011: lsi_ck selected as reference clock
100: hse_ck selected as reference clock
101: ic5_ck selected as reference clock
110: ic10_ck selected as reference clock
111: sysa_ck selected as reference clock

14.10.55 RCC clock configuration for independent peripheral register 6

(RCC_CCIPR6)
Address offset: 0x158
Reset value: 0x0000 0000
This register is used to configure various clocks. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTG OTG
PHY2CK OTGPHY2 PHY1CK
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
REF SEL[1:0] REF
SEL SEL
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. OTGPHY1SEL[1:0] Res. Res. XSPI3SEL[1:0] Res. Res. XSPI2SEL[1:0] Res. Res. XSPI1SEL[1:0]
rw rw rw rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

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Bit 24 OTGPHY2CKREFSEL:
This bitfield is set and reset by software.
0: otgphy2_ker_ck selected
1: hse_div2_osc_ck selected
Bits 23:22 Reserved, must be kept at reset value.
Bits 21:20 OTGPHY2SEL[1:0]: Source selection for the OTGPHY2 kernel clock
This bitfield is set and reset by software.
00: hse_div2_ck selected as reference clock
01: per_ck selected as reference clock
10: ic15_ck selected as reference clock
11: hse_div2_osc_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bits 19:17 Reserved, must be kept at reset value.
Bit 16 OTGPHY1CKREFSEL:
This bitfield is set and reset by software.
0: otgphy1_ker_ck selected
1: hse_div2_osc_ck selected
Bits 15:14 Reserved, must be kept at reset value.
Bits 13:12 OTGPHY1SEL[1:0]: Source selection for the OTGPHY1 kernel clock
This bitfield is set and reset by software.
00: hse_div2_ck selected as reference clock
01: per_ck selected as reference clock
10: ic15_ck selected as reference clock
11: hse_div2_osc_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bits 11:10 Reserved, must be kept at reset value.
Bits 9:8 XSPI3SEL[1:0]: Source selection for the XSPI3 kernel clock
This bitfield is set and reset by software.
00: hclk5 selected as reference clock
01: per_ck selected as reference clock
10: ic3_ck selected as reference clock
11: ic4_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 XSPI2SEL[1:0]: Source selection for the XSPI2 kernel clock
This bitfield is set and reset by software.
00: hclk5 selected as reference clock
01: per_ck selected as reference clock
10: ic3_ck selected as reference clock
11: ic4_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bits 3:2 Reserved, must be kept at reset value.

532/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bits 1:0 XSPI1SEL[1:0]: Source selection for the XSPI1 kernel clock
This bitfield is set and reset by software.
00: hclk5 selected as reference clock
01: per_ck selected as reference clock
10: ic3_ck selected as reference clock
11: ic4_ck selected as reference clock
Others: Reserved, no clock provided as reference clock

14.10.56 RCC clock configuration for independent peripheral register 7

(RCC_CCIPR7)
Address offset: 0x15C
Reset value: 0x0000 0200
This register is used to configure various clocks. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. SAI2SEL[2:0] Res. SAI1SEL[2:0] Res. Res. RTCPRE[5:4]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCPRE[3:0] Res. Res. RTCSEL[1:0] Res. Res. PSSISEL[1:0] Res. PERSEL[2:0]
rw rw rw rw rw rw rw rw rw rw rw

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:24 SAI2SEL[2:0]: Source selection for the SAI2 kernel clock
This bitfield is set and reset by software.
000: pclk2 selected as reference clock
001: per_ck selected as reference clock
010: ic7_ck selected as reference clock
011: ic8_ck selected as reference clock
100: msi_ck selected as reference clock
101: hsi_div_ck selected as reference clock
110: I2S_CKIN selected as reference clock
111: spdif_symb_ck selected as reference clock
Bit 23 Reserved, must be kept at reset value.
Bits 22:20 SAI1SEL[2:0]: Source selection for the SAI1 kernel clock
This bitfield is set and reset by software.
000: pclk2 selected as reference clock
001: per_ck selected as reference clock
010: ic7_ck selected as reference clock
011: ic8_ck selected as reference clock
100: msi_ck selected as reference clock
101: hsi_div_ck selected as reference clock
110: I2S_CKIN selected as reference clock
111: spdif_symb_ck selected as reference clock
Bits 19:18 Reserved, must be kept at reset value.

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Bits 17:12 RTCPRE[5:0]: RTC OSC clock divider selection (for clock hse_ck)
This bitfield is set and reset by software. The division ratio is linear: {v}: hse_ck / {v+1}.
0x00: hse_ck divided by 1
0x01: hse_ck divided by 2
Bits 11:10 Reserved, must be kept at reset value.
Bits 9:8 RTCSEL[1:0]: Source selection for the RTC kernel clock
This bitfield is write-protected by the pwr_lock_backup_n signal. It is security-protected by a
SEC signal from RIFSC, the PERSEC bit, a PRIV signal from RIFSC, or the PERPRIV bit.
This bitfield is set and reset by software.
01: lse_ck selected as reference clock
10: lsi_ck selected as reference clock
11: hse_rtc_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 PSSISEL[1:0]: Source selection for the PSSI kernel clock
This bitfield is set and reset by software.
00: hclk5 selected as reference clock
01: per_ck selected as reference clock
10: ic20_ck selected as reference clock
11: hsi_div_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 PERSEL[2:0]: Source selection for the PER kernel clock
This bitfield is set and reset by software.
000: hsi_ck selected as reference clock
001: msi_ck selected as reference clock
010: hse_ck selected as reference clock
011: ic19_ck selected as reference clock
100: ic5_ck selected as reference clock
101: ic10_ck selected as reference clock
110: ic15_ck selected as reference clock
111: ic20_ck selected as reference clock

14.10.57 RCC clock configuration for independent peripheral register 8

(RCC_CCIPR8)
Address offset: 0x160
Reset value: 0x0000 0000
This register is used to configure various clocks. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMMC2SEL SDMMC1SEL
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
[1:0] [1:0]
rw rw rw rw

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RM0486 Reset and clock control (RCC)

Bits 31:6 Reserved, must be kept at reset value.

Bits 5:4 SDMMC2SEL[1:0]: Source selection for the SDMMC2 kernel clock
This bitfield is set and reset by software.
00: hclku selected as reference clock
01: per_ck selected as reference clock
10: ic4_ck selected as reference clock
11: ic5_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 SDMMC1SEL[1:0]: Source selection for the SDMMC1 kernel clock
This bitfield is set and reset by software.
00: hclku selected as reference clock
01: per_ck selected as reference clock
10: ic4_ck selected as reference clock
11: ic5_ck selected as reference clock
Others: Reserved, no clock provided as reference clock

14.10.58 RCC clock configuration for independent peripheral register 9

(RCC_CCIPR9)
Address offset: 0x164
Reset value: 0x0000 0000
This register is used to configure various clocks. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. SPI6SEL[2:0] Res. SPI5SEL[2:0] Res. SPI4SEL[2:0]
rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. SPI3SEL[2:0] Res. SPI2SEL[2:0] Res. SPI1SEL[2:0] Res. SPDIFRX1SEL[2:0]
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:24 SPI6SEL[2:0]: Source selection for the SPI6 kernel clock
This bitfield is set and reset by software.
000: pclk4 selected as reference clock
001: per_ck selected as reference clock
010: ic8_ck selected as reference clock
011: ic9_ck selected as reference clock
100: msi_ck selected as reference clock
101: hsi_div_ck selected as reference clock
110: I2S_CKIN selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 23 Reserved, must be kept at reset value.

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Bits 22:20 SPI5SEL[2:0]: Source selection for the SPI5 kernel clock
This bitfield is set and reset by software.
000: pclk2 selected as reference clock
001: per_ck selected as reference clock
010: ic9_ck selected as reference clock
011: ic14_ck selected as reference clock
100: msi_ck selected as reference clock
101: hsi_div_ck selected as reference clock
110: hse_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 19 Reserved, must be kept at reset value.
Bits 18:16 SPI4SEL[2:0]: Source selection for the SPI4 kernel clock
This bitfield is set and reset by software.
000: pclk2 selected as reference clock
001: per_ck selected as reference clock
010: ic9_ck selected as reference clock
011: ic14_ck selected as reference clock
100: msi_ck selected as reference clock
101: hsi_div_ck selected as reference clock
110: hse_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 15 Reserved, must be kept at reset value.
Bits 14:12 SPI3SEL[2:0]: Source selection for the SPI3 kernel clock
This bitfield is set and reset by software.
000: pclk1 selected as reference clock
001: per_ck selected as reference clock
010: ic8_ck selected as reference clock
011: ic9_ck selected as reference clock
100: msi_ck selected as reference clock
101: hsi_div_ck selected as reference clock
110: I2S_CKIN selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 11 Reserved, must be kept at reset value.
Bits 10:8 SPI2SEL[2:0]: Source selection for the SPI2 kernel clock
This bitfield is set and reset by software.
000: pclk1 selected as reference clock
001: per_ck selected as reference clock
010: ic8_ck selected as reference clock
011: ic9_ck selected as reference clock
100: msi_ck selected as reference clock
101: hsi_div_ck selected as reference clock
110: I2S_CKIN selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 7 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

Bits 6:4 SPI1SEL[2:0]: Source selection for the SPI1 kernel clock
This bitfield is set and reset by software.
000: pclk2 selected as reference clock
001: per_ck selected as reference clock
010: ic8_ck selected as reference clock
011: ic9_ck selected as reference clock
100: msi_ck selected as reference clock
101: hsi_div_ck selected as reference clock
110: I2S_CKIN selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 SPDIFRX1SEL[2:0]: Source selection for the SPDIFRX1 kernel clock
This bitfield is set and reset by software.
000: pclk1 selected as reference clock
001: per_ck selected as reference clock
010: ic7_ck selected as reference clock
011: ic8_ck selected as reference clock
100: msi_ck selected as reference clock
101: hsi_div_ck selected as reference clock
110: I2S_CKIN selected as reference clock
Others: Reserved, no clock provided as reference clock

14.10.59 RCC clock configuration for independent peripheral register 12

(RCC_CCIPR12)
Address offset: 0x170
Reset value: 0x0000 0000
This register is used to configure various clocks. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. LPTIM5SEL[2:0] Res. LPTIM4SEL[2:0] Res. LPTIM3SEL[2:0]
rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. LPTIM2SEL[2:0] Res. LPTIM1SEL[2:0] Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw rw rw

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:24 LPTIM5SEL[2:0]: Source selection for the LPTIM5 kernel clock
This bitfield is set and reset by software.
000: pclk4 selected as reference clock
001: per_ck selected as reference clock
010: ic15_ck selected as reference clock
011: lse_ck selected as reference clock
100: lsi_ck selected as reference clock
101: timg_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 23 Reserved, must be kept at reset value.

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Bits 22:20 LPTIM4SEL[2:0]: Source selection for the LPTIM4 kernel clock
This bitfield is set and reset by software.
000: pclk4 selected as reference clock
001: per_ck selected as reference clock
010: ic15_ck selected as reference clock
011: lse_ck selected as reference clock
100: lsi_ck selected as reference clock
101: timg_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 19 Reserved, must be kept at reset value.
Bits 18:16 LPTIM3SEL[2:0]: Source selection for the LPTIM3 kernel clock
This bitfield is set and reset by software.
000: pclk4 selected as reference clock
001: per_ck selected as reference clock
010: ic15_ck selected as reference clock
011: lse_ck selected as reference clock
100: lsi_ck selected as reference clock
101: timg_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 15 Reserved, must be kept at reset value.
Bits 14:12 LPTIM2SEL[2:0]: Source selection for the LPTIM2 kernel clock
This bitfield is set and reset by software.
000: pclk4 selected as reference clock
001: per_ck selected as reference clock
010: ic15_ck selected as reference clock
011: lse_ck selected as reference clock
100: lsi_ck selected as reference clock
101: timg_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 11 Reserved, must be kept at reset value.
Bits 10:8 LPTIM1SEL[2:0]: Source selection for the LPTIM1 kernel clock
This bitfield is set and reset by software.
000: pclk1 selected as reference clock
001: per_ck selected as reference clock
010: ic15_ck selected as reference clock
011: lse_ck selected as reference clock
100: lsi_ck selected as reference clock
101: timg_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bits 7:0 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

14.10.60 RCC clock configuration for independent peripheral register 13

(RCC_CCIPR13)
Address offset: 0x174
Reset value: 0x0000 0000
This register is used to configure various clocks. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. UART8SEL[2:0] Res. UART7SEL[2:0] Res. USART6SEL[2:0] Res. UART5SEL[2:0]
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. UART4SEL[2:0] Res. USART3SEL[2:0] Res. USART2SEL[2:0] Res. USART1SEL[2:0]
rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:28 UART8SEL[2:0]: Source selection for the UART8 kernel clock
This bitfield is set and reset by software.
000: pclk1 selected as reference clock
001: per_ck selected as reference clock
010: ic9_ck selected as reference clock
011: ic14_ck selected as reference clock
100: lse_ck selected as reference clock
101: msi_ck selected as reference clock
110: hsi_div_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 27 Reserved, must be kept at reset value.
Bits 26:24 UART7SEL[2:0]: Source selection for the UART7 kernel clock
This bitfield is set and reset by software.
000: pclk1 selected as reference clock
001: per_ck selected as reference clock
010: ic9_ck selected as reference clock
011: ic14_ck selected as reference clock
100: lse_ck selected as reference clock
101: msi_ck selected as reference clock
110: hsi_div_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 23 Reserved, must be kept at reset value.
Bits 22:20 USART6SEL[2:0]: Source selection for the USART6 kernel clock
This bitfield is set and reset by software.
000: pclk2 selected as reference clock
001: per_ck selected as reference clock
010: ic9_ck selected as reference clock
011: ic14_ck selected as reference clock
100: lse_ck selected as reference clock
101: msi_ck selected as reference clock
110: hsi_div_ck selected as reference clock
Others: Reserved, no clock provided as reference clock

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Bit 19 Reserved, must be kept at reset value.

Bits 18:16 UART5SEL[2:0]: Source selection for the UART5 kernel clock
This bitfield is set and reset by software.
000: pclk1 selected as reference clock
001: per_ck selected as reference clock
010: ic9_ck selected as reference clock
011: ic14_ck selected as reference clock
100: lse_ck selected as reference clock
101: msi_ck selected as reference clock
110: hsi_div_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 15 Reserved, must be kept at reset value.
Bits 14:12 UART4SEL[2:0]: Source selection for the UART4 kernel clock
This bitfield is set and reset by software.
000: pclk1 selected as reference clock
001: per_ck selected as reference clock
010: ic9_ck selected as reference clock
011: ic14_ck selected as reference clock
100: lse_ck selected as reference clock
101: msi_ck selected as reference clock
110: hsi_div_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 11 Reserved, must be kept at reset value.
Bits 10:8 USART3SEL[2:0]: Source selection for the USART3 kernel clock
This bitfield is set and reset by software.
000: pclk1 selected as reference clock
001: per_ck selected as reference clock
010: ic9_ck selected as reference clock
011: ic14_ck selected as reference clock
100: lse_ck selected as reference clock
101: msi_ck selected as reference clock
110: hsi_div_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 USART2SEL[2:0]: Source selection for the USART2 kernel clock
This bitfield is set and reset by software.
000: pclk1 selected as reference clock
001: per_ck selected as reference clock
010: ic9_ck selected as reference clock
011: ic14_ck selected as reference clock
100: lse_ck selected as reference clock
101: msi_ck selected as reference clock
110: hsi_div_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 3 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

Bits 2:0 USART1SEL[2:0]: Source selection for the USART1 kernel clock
This bitfield is set and reset by software.
000: pclk2 selected as reference clock
001: per_ck selected as reference clock
010: ic9_ck selected as reference clock
011: ic14_ck selected as reference clock
100: lse_ck selected as reference clock
101: msi_ck selected as reference clock
110: hsi_div_ck selected as reference clock
Others: Reserved, no clock provided as reference clock

14.10.61 RCC clock configuration for independent peripheral register 14

(RCC_CCIPR14)
Address offset: 0x178
Reset value: 0x0000 0000
This register is used to configure various clocks. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. LPUART1SEL[2:0] Res. USART10SEL[2:0] Res. UART9SEL[2:0]
rw rw rw rw rw rw rw rw rw

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:8 LPUART1SEL[2:0]: Source selection for the LPUART1 kernel clock
This bitfield is set and reset by software.
000: pclk4 selected as reference clock
001: per_ck selected as reference clock
010: ic9_ck selected as reference clock
011: ic14_ck selected as reference clock
100: lse_ck selected as reference clock
101: msi_ck selected as reference clock
110: hsi_div_ck selected as reference clock
Others: Reserved, no clock provided as reference clock
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 USART10SEL[2:0]: Source selection for the USART10 kernel clock
This bitfield is set and reset by software.
000: pclk2 selected as reference clock
001: per_ck selected as reference clock
010: ic9_ck selected as reference clock
011: ic14_ck selected as reference clock
100: lse_ck selected as reference clock
101: msi_ck selected as reference clock
110: hsi_div_ck selected as reference clock
Others: Reserved, no clock provided as reference clock

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Bit 3 Reserved, must be kept at reset value.

Bits 2:0 UART9SEL[2:0]: Source selection for the UART9 kernel clock
This bitfield is set and reset by software.
000: pclk2 selected as reference clock
001: per_ck selected as reference clock
010: ic9_ck selected as reference clock
011: ic14_ck selected as reference clock
100: lse_ck selected as reference clock
101: msi_ck selected as reference clock
110: hsi_div_ck selected as reference clock
Others: Reserved, no clock provided as reference clock

14.10.62 RCC miscellaneous configurations reset register

(RCC_MISCRSTR)
Address offset: 0x208
Reset value: 0x0000 0000
This register is used to reset the miscellaneous configurations. It is reset by sys_rstn, and is
in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMM SDMM XSPIP XSPIP
DBG
Res. Res. Res. Res. Res. Res. Res. C2DLL C1DLL Res. HY2 HY1 Res. Res. Res.
RST
RST RST RST RST
rw rw rw rw rw

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SDMMC2DLLRST: SDMMC2DLL reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SDMMC2DLLRSTS, and cleared with
SDMMC2DLLRSTC. This bit is set and reset by software.
0: SDMMC2DLL not under reset (default after reset)
1: SDMMC2DLL under reset
Bit 7 SDMMC1DLLRST: SDMMC1DLL reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SDMMC1DLLRSTS, and cleared with
SDMMC1DLLRSTC. This bit is set and reset by software.
0: SDMMC1DLL not under reset (default after reset)
1: SDMMC1DLL under reset
Bit 6 Reserved, must be kept at reset value.
Bit 5 XSPIPHY2RST: XSPIPHY2 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with XSPIPHY2RST,S and cleared with
XSPIPHY2RSTC. This bit is set and reset by software.
0: XSPIPHY2 not under reset (default after reset)
1: XSPIPHY2 under reset

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RM0486 Reset and clock control (RCC)

Bit 4 XSPIPHY1RST: XSPIPHY1 reset

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with XSPIPHY1RSTS, and cleared with
XSPIPHY1RSTC. This bit is set and reset by software.
0: XSPIPHY1 not under reset (default after reset)
1: XSPIPHY1 under reset
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 DBGRST: DBG reset
This bit is always security-protected. It can be set with DBGRSTS, and cleared
with DBGRSTC. This bit is set and reset by software.
0: DBG not under reset (default after reset)
1: DBG under reset

14.10.63 RCC embedded memories reset register (RCC_MEMRSTR)

Address offset: 0x20C
Reset value: 0x0000 0000
This register is used to reset the embedded memories. It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOT CACHE AXISR AXISR AHBSR AHBSR AXISR AXISR AXISR AXISR
VENCR FLEXR
Res. Res. Res. ROMR AXIRA AM2RS AM1RS Res. AM2RS AM1RS AM6RS AM5RS AM4RS AM3RS
AMRST AMRST
ST MRST T T T T T T T T
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 BOOTROMRST: BootROM reset
This bit is always security-protected. It can be set with BOOTROMRSTS, and cleared with
BOOTROMRSTC. This bit is set and reset by software.
0: BootROM not under reset (default after reset)
1: BootROM under reset
Bit 11 VENCRAMRST: VENCRAM reset
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if VENCRAMPUB = 1. It can be set with VENCRAMRSTS, and cleared with
VENCRAMRSTC. This bit is set and reset by software.
0: VENCRAM not under reset (default after reset)
1: VENCRAM under reset
Bit 10 CACHEAXIRAMRST: CACHEAXIRAM reset
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if CACHEAXIRAMPUB = 1. It can be set with CACHEAXIRAMRSTS, and cleared with
CACHEAXIRAMRSTC. This bit is set and reset by software.
0: CACHEAXIRAM not under reset (default after reset)
1: CACHEAXIRAM under reset

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Bit 9 FLEXRAMRST: FLEXRAM reset

This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if FLEXRAMPUB = 1. It can be set with FLEXRAMRSTS, and cleared with FLEXRAMRSTC.
This bit is set and reset by software.
0: FLEXRAM not under reset (default after reset)
1: FLEXRAM under reset
Bit 8 AXISRAM2RST: AXISRAM2 reset
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AXISRAM2PUB = 1. it can be set with AXISRAM2RSTS, and cleared with
AXISRAM2RSTC. This bit is set and reset by software.
0: AXISRAM2 s not under reset (default after reset)
1: AXISRAM2 under reset
Bit 7 AXISRAM1RST: AXISRAM1 reset
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AXISRAM1PUB = 1. It can be set with AXISRAM1RSTS, and cleared with
AXISRAM1RSTC. This bit is set and reset by software.
0: AXISRAM1 not under reset (default after reset)
1: AXISRAM1 under reset
Bit 6 Reserved, must be kept at reset value.
Bit 5 AHBSRAM2RST: AHBSRAM2 reset
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AHBSRAM2PUB = 1. It can be set with AHBSRAM2RSTS, and cleared with
AHBSRAM2RSTC. This bit is set and reset by software.
0: AHBSRAM2 not under reset (default after reset)
1: AHBSRAM2 under reset
Bit 4 AHBSRAM1RST: AHBSRAM1 reset
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AHBSRAM1PUB = 1. It can be set with AHBSRAM1RSTS, and cleared with
AHBSRAM1RSTC. This bit is set and reset by software.
0: AHBSRAM1 not under reset (default after reset)
1: AHBSRAM1 under reset
Bit 3 AXISRAM6RST: AXISRAM6 reset
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AXISRAM6PUB = 1. It can be set with AXISRAM6RSTS, and cleared with
AXISRAM6RSTC. This bit is set and reset by software.
0: AXISRAM6 not under reset (default after reset)
1: AXISRAM6 under reset
Bit 2 AXISRAM5RST: AXISRAM5 reset
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AXISRAM5PUB = 1. It can be set with AXISRAM5RSTS, and cleared with
AXISRAM5RSTC. This bit is set and reset by software.
0: AXISRAM5 not under reset (default after reset)
1: AXISRAM5 under reset
Bit 1 AXISRAM4RST: AXISRAM4 reset
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AXISRAM4PUB = 1. It can be set with AXISRAM4RSTS, and cleared with
AXISRAM4RSTC. This bit is set and reset by software.
0: AXISRAM4 not under reset (default after reset)
1: AXISRAM4 under reset

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RM0486 Reset and clock control (RCC)

Bit 0 AXISRAM3RST: AXISRAM3 reset

This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AXISRAM3PUB = 1. It can be set with AXISRAM3RSTS, and cleared with
AXISRAM3RSTC. This bit is set and reset by software.
0: AXISRAM3 not under reset (default after reset)
1: AXISRAM3 under reset

14.10.64 RCC AHB1 reset register (RCC_AHB1RSTR)

Address offset: 0x210
Reset value: 0x0000 0000
This register is used to reset the AHB1. It is reset by sys_rstn, and is in the VCORE voltage
domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC12 GPDM
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RST A1RST
rw rw

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 ADC12RST: ADC12 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with ADC12RSTS and cleared with
ADC12RSTC. This bit is set and reset by software.
0: ADC12 not under reset (default after reset)
1: ADC12 under reset
Bit 4 GPDMA1RST: GPDMA1 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPDMA1RSTS and cleared with
GPDMA1RSTC. This bit is set and reset by software.
0: GPDMA1 not under reset (default after reset)
1: GPDMA1 under reset
Bits 3:0 Reserved, must be kept at reset value.

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14.10.65 RCC AHB2 reset register (RCC_AHB2RSTR)

Address offset: 0x214
Reset value: 0x0000 0000
This register is used to reset the AHB2. It is reset by sys_rstn, and is in the VCORE voltage
domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADF1R MDF1R
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ST ST
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAMC
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
FGRST
rw

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 ADF1RST: ADF1 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with ADF1RSTS and cleared with
ADF1RSTC. This bit is set and reset by software.
0: ADF1 not under reset (default after reset)
1: ADF1 under reset
Bit 16 MDF1RST: MDF1 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with MDF1RSTS and cleared with
MDF1RSTC. This bit is set and reset by software.
0: MDF1 not under reset (default after reset)
1: MDF1 under reset
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 RAMCFGRST: RAMCFG reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with RAMCFGRSTS and cleared
with RAMCFGRSTC. This bit is set and reset by software.
0: RAMCFG not under reset (default after reset)
1: RAMCFG under reset
Bits 11:0 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

14.10.66 RCC AHB3 reset register (RCC_AHB3RSTR)

Address offset: 0x218
Reset value: 0x0000 0000
This register is used to reset the AHB3. It is reset by sys_rstn, and is in the VCORE voltage
domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IAC PKA SAES CRYP HASH RNG
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RST RST RST RST RST RST
rw rw rw rw rw rw

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 IACRST: IAC reset
This bit is always security-protected. It can be set with IACRSTS, and cleared with IACRSTC.
This bit is set and reset by software.
0: IAC not under reset (default after reset)
1: IAC under reset
Bit 9 Reserved, must be kept at reset value.
Bit 8 PKARST: PKA reset
This bit is security-protected by the SYSSEC bit, the SYSPRIV bit. It can be set with
PKARSTS, and cleared with PKARSTC. This bit is set and reset by software.
0: PKA not under reset (default after reset)
1: PKA under reset
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 SAESRST: SAES reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SAESRSTS, and cleared with
SAESRSTC. This bit is set and reset by software.
0: SAES not under reset (default after reset)
1: SAES under reset
Bit 3 Reserved, must be kept at reset value.
Bit 2 CRYPRST: CRYP reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with CRYPRSTS, and cleared with
CRYPRSTC. This bit is set and reset by software.
0: CRYP not under reset (default after reset)
1: CRYP under reset
Bit 1 HASHRST: HASH reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with HASHRSTS, and cleared with
HASHRSTC. This bit is set and reset by software.
0: HASH not under reset (default after reset)
1: HASH under reset

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Bit 0 RNGRST: RNG reset

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with RNGRSTS, and cleared with RNGRSTC.
This bit is set and reset by software.
0: RNG not under reset (default after reset)
1: RNG under reset

14.10.67 RCC AHB4 reset register (RCC_AHB4RSTR)

Address offset: 0x21C
Reset value: 0x0000 0000
This register is used to reset the AHB4. It is reset by sys_rstn, and is in the VCORE voltage
domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCR PWRR GPIOQ
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ST ST RST
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOP GPIOO GPION GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Res. Res. Res. Res. Res.
RST RST RST RST RST RST RST RST RST RST RST
rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 CRCRST: CRC reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with CRCRST,S and cleared with
[Link] bit is set and reset by software.
0: CRC not under reset (default after reset)
1: CRC under reset
Bit 18 PWRRST: PWR reset
This bit is always security-protected. It can be set with PWRRSTS, and cleared with
PWRRSTC. This bit is set and reset by software.
0: PWR not under reset (default after reset)
1: PWR under reset
Bit 17 Reserved, must be kept at reset value.
Bit 16 GPIOQRST: GPIO Q reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOQRSTS, and cleared with
GPIOQRSTC. This bit is set and reset by software.
0: GPIO Q not under reset (default after reset)
1: GPIO Q under reset
Bit 15 GPIOPRST: GPIO P reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOPRSTS, and cleared with
GPIOPRSTC. This bit is set and reset by software.
0: GPIO P not under reset (default after reset)
1: GPIO P under reset

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Bit 14 GPIOORST: GPIO O reset

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOORSTS, and cleared with
GPIOORSTC. This bit is set and reset by software.
0: GPIO O not under reset (default after reset)
1: GPIO O under reset
Bit 13 GPIONRST: GPIO N reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIONRSTS, and cleared with
GPIONRSTC. This bit is set and reset by software.
0: GPIO N not under reset (default after reset)
1: GPIO N under reset
Bits 12:8 Reserved, must be kept at reset value.
Bit 7 GPIOHRST: GPIO H reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOHRSTS, and cleared with
GPIOHRSTC. This bit is set and reset by software.
0: GPIO H not under reset (default after reset)
1: GPIO H under reset
Bit 6 GPIOGRST: GPIO G reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOGRSTS, and cleared with
GPIOGRSTC. This bit is set and reset by software.
0: GPIO G not under reset (default after reset)
1: GPIO G under reset
Bit 5 GPIOFRST: GPIO F reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOFRSTS, and cleared with
GPIOFRSTC. This bit is set and reset by software.
0: GPIO F not under reset (default after reset)
1: GPIO F under reset
Bit 4 GPIOERST: GPIO E reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOERSTS, and cleared with
GPIOERSTC. This bit is set and reset by software.
0: GPIO E not under reset (default after reset)
1: GPIO E under reset
Bit 3 GPIODRST: GPIO D reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIODRSTS, and cleared with
GPIODRSTC. This bit is set and reset by software.
0: GPIO D not under reset (default after reset)
1: GPIO D under reset
Bit 2 GPIOCRST: GPIO C reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOCRSTS, and cleared with
GPIOCRSTC. This bit is set and reset by software.
0: GPIO C not under reset (default after reset)
1: GPIO C under reset

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Bit 1 GPIOBRST: GPIO B reset

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOBRSTS, and cleared with
GPIOBRSTC. This bit is set and reset by software.
0: GPIO B not under reset (default after reset)
1: GPIO B under reset
Bit 0 GPIOARST: GPIO A reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOARSTS, and cleared with
GPIOARSTC. This bit is set and reset by software.
0: GPIO A not under reset (default after reset)
1: GPIO A under reset

14.10.68 RCC AHB5 reset register (RCC_AHB5RSTR)

Address offset: 0x220
Reset value: 0x0000 0000
This register is used to reset the AHB5. It is reset by sys_rstn, and is in the VCORE voltage
domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CACHE OTGP OTGP OTG2P OTG1P GFXM
NPU OTG2R OTG1 ETH1 GPU2D XSPI3
AXI HY2 HY1 HYCTL HYCTL Res. Res. MU Res. Res.
RST ST RST RST RST RST
RST RST RST RST RST RST
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMM SDMM HP
XSPIM XSPI2 PSSI XSPI1 FMC JPEG DMA2D
Res. Res. Res. Res. Res. C1 C2 Res. DMA1
RST RST RST RST RST RST RST
RST RST RST
rw rw rw rw rw rw rw rw rw rw

Bit 31 NPURST: NPU reset

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with NPURSTS, and cleared with NPURSTC.
This bit is set and reset by software.
0: NPU not under reset (default after reset)
1: NPU under reset
Bit 30 CACHEAXIRST: CACHEAXI reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with CACHEAXIRSTS, and cleared
with CACHEAXIRSTC. This bit is set and reset by software.
0: CACHEAXI not under reset (default after reset)
1: CACHEAXI under reset
Bit 29 OTG2RST: OTG2 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with OTG2RSTS, and cleared with
OTG2RSTC. This bit is set and reset by software.
0: OTG2 not under reset (default after reset)
1: OTG2 under reset

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Bit 28 OTGPHY2RST: OTGPHY2 reset

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with OTGPHY2RSTS, and cleared with
OTGPHY2RSTC. This bit is set and reset by software.
0: OTGPHY2 not under reset (default after reset)
1: OTGPHY2 under reset
Bit 27 OTGPHY1RST: OTGPHY1 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with OTGPHY1RSTS, and cleared with
OTGPHY1RSTC. This bit is set and reset by software.
0: OTGPHY1 not under reset (default after reset)
1: OTGPHY1 under reset
Bit 26 OTG1RST: OTG1 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with OTG1RSTS, and cleared with
OTG1RSTC. This bit is set and reset by software.
0: OTG1 not under reset (default after reset)
1: OTG1 under reset
Bit 25 ETH1RST: ETH1 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with ETH1RSTS, and cleared with
ETH1RSTC. This bit is set and reset by software.
0: ETH1 not under reset (default after reset)
1: ETH1 under reset
Bit 24 OTG2PHYCTLRST: OTG2PHYCTL reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with OTG2PHYCTLRSTS, and cleared with
OTG2PHYCTLRSTC. This bit is set and reset by software.
0: OTG2PHYCTL not under reset (default after reset)
1: OTG2PHYCTL under reset
Bit 23 OTG1PHYCTLRST: OTG1PHYCTL reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with OTG1PHYCTLRSTS, and cleared with
OTG1PHYCTLRSTC. This bit is set and reset by software.
0: OTG1PHYCTL not under reset (default after reset)
1: OTG1PHYCTL under reset
Bits 22:21 Reserved, must be kept at reset value.
Bit 20 GPU2DRST: GPU2D reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPURSTS, and cleared with GPURSTC.
This bit is set and reset by software.
0: GPU2D not under reset (default after reset)
1: GPU2D under reset
Bit 19 GFXMMURST: GFXMMU reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GFXMMURSTS, and cleared with
GFXMMURSTC. This bit is set and reset by software.
0: GFXMMU not under reset (default after reset)
1: GFXMMU under reset

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Bit 18 Reserved, must be kept at reset value.

Bit 17 XSPI3RST: XSPI3 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with XSPI3RSTS, and cleared with
XSPI3RSTC. This bit is set and reset by software.
0: XSPI3 not under reset (default after reset)
1: XSPI3 under reset
Bits 16:14 Reserved, must be kept at reset value.
Bit 13 XSPIMRST: XSPIM reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with XSPIMRSTS, and cleared with
XSPIMRSTC. This bit is set and reset by software.
0: XSPIM not under reset (default after reset)
1: XSPIM under reset
Bit 12 XSPI2RST: XSPI2 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with XSPI2RSTS, and cleared with
XSPI2RSTC. This bit is set and reset by software.
0: XSPI2 not under reset (default after reset)
1: XSPI2 under reset
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 SDMMC1RST: SDMMC1 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SDMMC1RSTS, and cleared with
SDMMC1RSTC. This bit is set and reset by software.
0: SDMMC1 not under reset (default after reset)
1: SDMMC1 under reset
Bit 7 SDMMC2RST: SDMMC2 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SDMMC2RSTS, and cleared with
SDMMC2RSTC. This bit is set and reset by software.
0: SDMMC2 not under reset (default after reset)
1: SDMMC2 under reset
Bit 6 PSSIRST: PSSI reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with PSSIRSTS, and cleared with PSSIRSTC.
This bit is set and reset by software.
0: PSSI not under reset (default after reset)
1: PSSI under reset
Bit 5 XSPI1RST: XSPI1 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with XSPI1RSTS, and cleared with
XSPI1RSTC. This bit is set and reset by software.
0: XSPI1 not under reset (default after reset)
1: XSPI1 under reset

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Bit 4 FMCRST: FMC reset

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with FMCRSTS and cleared with FMCRSTC.
This bit is set and reset by software.
0: FMC not under reset (default after reset)
1: FMC under reset
Bit 3 JPEGRST: JPEG reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with JPEGRSTS, and cleared with
JPEGRSTC. This bit is set and reset by software.
0: JPEG not under reset (default after reset)
1: JPEG under reset
Bit 2 Reserved, must be kept at reset value.
Bit 1 DMA2DRST: DMA2D reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with DMA2DRSTS, and cleared with
DMA2DRSTC. This bit is set and reset by software.
0: DMA2D not under reset (default after reset)
1: DMA2D under reset
Bit 0 HPDMA1RST: HPDMA1 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with HPDMA1RSTS, and cleared with
HPDMA1RSTC. This bit is set and reset by software.
0: HPDMA1 not under reset (default after reset)
1: HPDMA1 under reset

14.10.69 RCC APB1L reset register (RCC_APB1LRSTR)

Address offset: 0x224
Reset value: 0x0000 0000
This register is used to reset the APB1L. It is reset by sys_rstn, and is in the VCORE voltage
domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPDIF
UART8 UART7 I3C2 I3C1 I2C3 I2C2 I2C1 UART5 UART4 USART3 USART2
Res. Res. Res. Res. RX1
RST RST RST RST RST RST RST RST RST RST RST
RST
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3 SPI2 TIM11 TIM10 WWDG LPTIM1 TIM14 TIM13 TIM12 TIM7 TIM6 TIM5 TIM4 TIM3 TIM2
Res.
RST RST RST RST RST RST RST RST RST RST RST RST RST RST RST
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 UART8RST: UART8 reset

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with UART8RSTS, and cleared with
UART8RSTC. This bit is set and reset by software.
0: UART8 not under reset (default after reset)
1: UART8 under reset

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Bit 30 UART7RST: UART7 reset

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with UART7RSTS, and cleared with
UART7RSTC. This bit is set and reset by software.
0: UART7 not under reset (default after reset)
1: UART7 under reset
Bits 29:26 Reserved, must be kept at reset value.
Bit 25 I3C2RST: I3C2 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with I3C2RSTS, and cleared with I3C2RSTC.
This bit is set and reset by software.
0: I3C2 not under reset (default after reset)
1: I3C2 i under reset
Bit 24 I3C1RST: I3C1 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with I3C1RSTS, and cleared with I3C1RSTC.
This bit is set and reset by software.
0: I3C1 not under reset (default after reset)
1: I3C1 under reset
Bit 23 I2C3RST: I2C3 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with I2C3RSTS, and cleared with I2C3RSTC.
This bit is set and reset by software.
0: I2C3 not under reset (default after reset)
1: I2C3 under reset
Bit 22 I2C2RST: I2C2 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with I2C2RSTS, and cleared with I2C2RSTC.
This bit is set and reset by software.
0: I2C2 not under reset (default after reset)
1: I2C2 under reset
Bit 21 I2C1RST: I2C1 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with I2C1RST, S and cleared with I2C1RSTC.
This bit is set and reset by software.
0: I2C1 not under reset (default after reset)
1: I2C1 under reset
Bit 20 UART5RST: UART5 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with UART5RSTS, and cleared with
UART5RSTC. This bit is set and reset by software.
0: UART5 not under reset (default after reset)
1: UART5 under reset
Bit 19 UART4RST: UART4 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with UART4RSTS, and cleared with
UART4RSTC. This bit is set and reset by software.
0: UART4 not under reset (default after reset)
1: UART4 under reset

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Bit 18 USART3RST: USART3 reset

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with USART3RSTS, and cleared with
USART3RSTC.
This bit is set and reset by software.
0: USART3 not under reset (default after reset)
1: USART3 under reset
Bit 17 USART2RST: USART2 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with USART2RSTS, and cleared with
USART2RSTC.
This bit is set and reset by software.
0: USART2 not under reset (default after reset)
1: USART2 under reset
Bit 16 SPDIFRX1RST: SPDIFRX1 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with SPDIFRX1RSTS, and cleared with
SPDIFRX1RSTC. This bit is set and reset by software.
0: SPDIFRX1 not under reset (default after reset)
1: SPDIFRX1 under reset
Bit 15 SPI3RST: SPI3 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with SPI3RSTS, and cleared with SPI3RSTC.
This bit is set and reset by software.
0: SPI3 not under reset (default after reset)
1: SPI3 under reset
Bit 14 SPI2RST: SPI2 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SPI2RSTS, and cleared with SPI2RSTC.
This bit is set and reset by software.
0: SPI2 not under reset (default after reset)
1: SPI2 under reset
Bit 13 TIM11RST: TIM11 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM11RSTS, and cleared with
TIM11RSTC. This bit is set and reset by software.
0: TIM11 not under reset (default after reset)
1: TIM11 under reset
Bit 12 TIM10RST: TIM10 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. IT can be set with TIM10RSTS, and cleared with
TIM10RSTC. This bit is set and reset by software.
0: TIM10 not under reset (default after reset)
1: TIM10 under reset
Bit 11 WWDGRST: WWDG reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with WWDGRSTS, and cleared with
WWDGRSTC. This bit is set and reset by software.
0: WWDG not under reset (default after reset)
1: WWDG under reset

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Bit 10 Reserved, must be kept at reset value.

Bit 9 LPTIM1RST: LPTIM1 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with LPTIM1RSTS, and cleared with
LPTIM1RSTC. This bit is set and reset by software.
0: LPTIM1 not under reset (default after reset)
1: LPTIM1 under reset
Bit 8 TIM14RST: TIM14 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM14RSTS, and cleared with
TIM14RSTC. This bit is set and reset by software.
0: TIM14 not under reset (default after reset)
1: TIM14 under reset
Bit 7 TIM13RST: TIM13 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM13RSTS, and cleared with
TIM13RSTC. This bit is set and reset by software.
0: TIM13 not under reset (default after reset)
1: TIM13 under reset
Bit 6 TIM12RST: TIM12 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM12RSTS, and cleared with
TIM12RSTC. This bit is set and reset by software.
0: TIM12 not under reset (default after reset)
1: TIM12 under reset
Bit 5 TIM7RST: TIM7 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM7RSTS, and cleared with TIM7RSTC.
This bit is set and reset by software.
0: TIM7 not under reset (default after reset)
1: TIM7 under reset
Bit 4 TIM6RST: TIM6 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM6RSTS, and cleared with TIM6RSTC.
This bit is set and reset by software.
0: TIM6 not under reset (default after reset)
1: TIM6 under reset
Bit 3 TIM5RST: TIM5 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM5RSTS, and cleared with TIM5RSTC.
This bit is set and reset by software.
0: TIM5 not under reset (default after reset)
1: TIM5 under reset
Bit 2 TIM4RST: TIM4 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM4RSTS, and cleared with TIM4RSTC.
This bit is set and reset by software.
0: TIM4 not under reset (default after reset)
1: TIM4 under reset

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Bit 1 TIM3RST: TIM3 reset

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM3RSTS, and cleared with TIM3RSTC.
This bit is set and reset by software.
0: TIM3 not under reset (default after reset)
1: TIM3 under reset
Bit 0 TIM2RST: TIM2 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM2RSTS, and cleared with TIM2RSTC.
This bit is set and reset by software.
0: TIM2 not under reset (default after reset)
1: TIM2 under reset

14.10.70 RCC APB1H reset register (RCC_APB1HRSTR)

Address offset: 0x228
Reset value: 0x0000 0000
This register is used to reset the APB1H. It is reset by sys_rstn, and is in the VCORE voltage
domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN MDIOS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RST RST
rw rw

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 UCPD1RST: UCPD1 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with UCPD1RSTS, and cleared with
UCPD1RSTC. This bit is set and reset by software.
0: UCPD1 not under reset (default after reset)
1: UCPD1 under reset
Bits 17:9 Reserved, must be kept at reset value.
Bit 8 FDCANRST: FDCAN reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with FDCANRSTS, and cleared with
FDCANRSTC. This bit is set and reset by software.
0: FDCAN not under reset (default after reset)
1: FDCAN under reset
Bits 7:6 Reserved, must be kept at reset value.

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Bit 5 MDIOSRST: MDIOS reset

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with MDIOSRSTS, and cleared with
MDIOSRSTC. This bit is set and reset by software.
0: MDIOS not under reset (default after reset)
1: MDIOS under reset
Bits 4:0 Reserved, must be kept at reset value.

14.10.71 RCC APB2 reset register (RCC_APB2RSTR)

Address offset: 0x22C
Reset value: 0x0000 0000
This register is used to reset the APB2. It is reset by sys_rstn, and is in the VCORE voltage
domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAI2R SAI1R SPI5R TIM9R TIM17 TIM16 TIM15
Res. Res. Res. Res. Res. Res. Res. Res. Res.
ST ST ST ST RST RST RST
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIM18 SPI4R SPI1R USART UART9 USART USART TIM8R TIM1R
Res. Res. Res. Res. Res. Res. Res.
RST ST ST 10RST RST 6RST 1RST ST ST
rw rw rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 SAI2RST: SAI2 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SAI2RSTS, and cleared with SAI2RSTC.
This bit is set and reset by software.
0: SAI2 not under reset (default after reset)
1: SAI2 under reset
Bit 21 SAI1RST: SAI1 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SAI1RSTS, and cleared with SAI1RSTC.
This bit is set and reset by software.
0: SAI1 not under reset (default after reset)
1: SAI1 under reset
Bit 20 SPI5RST: SPI5 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with SPI5RSTS, and cleared with SPI5RSTC.
This bit is set and reset by software.
0: SPI5 not under reset (default after reset)
1: SPI5 under reset
Bit 19 TIM9RST: TIM9 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM9RSTS, and cleared with TIM9RSTC.
This bit is set and reset by software.
0: TIM9 not under reset (default after reset)
1: TIM9 under reset

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Bit 18 TIM17RST: TIM17 reset

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM17RSTS, and cleared with
TIM17RSTC. This bit is set and reset by software.
0: TIM17 not under reset (default after reset)
1: TIM17 under reset
Bit 17 TIM16RST: TIM16 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM16RSTS, and cleared with
TIM16RSTC. This bit is set and reset by software.
0: TIM16 not under reset (default after reset)
1: TIM16 under reset
Bit 16 TIM15RST: TIM15 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM15RSTS, and cleared with
TIM15RSTC. This bit is set and reset by software.
0: TIM15 not under reset (default after reset)
1: TIM15 under reset
Bit 15 TIM18RST: TIM18 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM18RSTS, and cleared with
TIM18RSTC. This bit is set and reset by software.
0: TIM18 not under reset (default after reset)
1: TIM18 under reset
Bit 14 Reserved, must be kept at reset value.
Bit 13 SPI4RST: SPI4 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SPI4RSTS, and cleared with SPI4RSTC.
This bit is set and reset by software.
0: SPI4 not under reset (default after reset)
1: SPI4 under reset
Bit 12 SPI1RST: SPI1 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SPI1RSTS, and cleared with SPI1RSTC.
This bit is set and reset by software.
0: SPI1 not under reset (default after reset)
1: SPI1 under reset
Bits 11:8 Reserved, must be kept at reset value.
Bit 7 USART10RST: USART10 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with USART10RSTS, and cleared with
USART10RSTC. This bit is set and reset by software.
0: USART10 not under reset (default after reset)
1: USART10 under reset

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Bit 6 UART9RST: UART9 reset

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with UART9RSTS, and cleared with
UART9RSTC. This bit is set and reset by software.
0: UART9 not under reset (default after reset)
1: UART9 under reset
Bit 5 USART6RST: USART6 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with USART6RSTS, and cleared with
USART6RSTC. This bit is set and reset by software.
0: USART6 not under reset (default after reset)
1: USART6 under reset
Bit 4 USART1RST: USART1 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with USART1RSTS, and cleared with
USART1RSTC. This bit is set and reset by software.
0: USART1 not under reset (default after reset)
1: USART1 under reset
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8RST: TIM8 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM8RSTS, and cleared with TIM8RSTC.
This bit is set and reset by software.
0: TIM8 not under reset (default after reset)
1: TIM8 under reset
Bit 0 TIM1RST: TIM1 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with TIM1RSTS, and cleared with TIM1RSTC.
This bit is set and reset by software.
0: TIM1 not under reset (default after reset)
1: TIM1 under reset

14.10.72 RCC APB4L reset register (RCC_APB4LRSTR)

Address offset: 0x234
Reset value: 0x0000 0000
This register is used to reset the APB4L. It is reset by sys_rstn, and is in the VCORE voltage
domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCRS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
T
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFB LPTIM5 LPTIM4 LPTIM3 LPTIM2 I2C4RS SPI6R LPUAR HDPRS
Res. Res. Res. Res. Res. Res. Res.
UFRST RST RST RST RST T ST T1RST T
rw rw rw rw rw rw rw rw rw

Bits 31:17 Reserved, must be kept at reset value.

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Bit 16 RTCRST: RTC reset

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with RTCRSTS, and cleared with RTCRSTC.
This bit is set and reset by software.
0: RTC not under reset (default after reset)
1: RTC under reset
Bit 15 VREFBUFRST: VREFBUF reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with VREFBUFRSTS, and cleared with
VREFBUFRSTC. This bit is set and reset by software.
0: VREFBUF not under reset (default after reset)
1: VREFBUF under reset
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 LPTIM5RST: LPTIM5 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with LPTIM5RSTS, and cleared with
LPTIM5RSTC. This bit is set and reset by software.
0: LPTIM5 not under reset (default after reset)
1: LPTIM5 under reset
Bit 11 LPTIM4RST: LPTIM4 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with LPTIM4RSTS, and cleared with
LPTIM4RSTC. This bit is set and reset by software.
0: LPTIM4 not under reset (default after reset)
1: LPTIM4 under reset
Bit 10 LPTIM3RST: LPTIM3 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with LPTIM3RSTS, and cleared with
LPTIM3RSTC. This bit is set and reset by software.
0: LPTIM3 not under reset (default after reset)
1: LPTIM3 under reset
Bit 9 LPTIM2RST: LPTIM2 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with LPTIM2RSTS, and cleared with
LPTIM2RSTC. This bit is set and reset by software.
0: LPTIM2 not under reset (default after reset)
1: LPTIM2 under reset
Bit 8 Reserved, must be kept at reset value.
Bit 7 I2C4RST: I2C4 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with I2C4RSTS, and cleared with I2C4RSTC.
This bit is set and reset by software.
0: I2C4 not under reset (default after reset)
1: I2C4 under reset
Bit 6 Reserved, must be kept at reset value.

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Bit 5 SPI6RST: SPI6 reset

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with SPI6RSTS, and cleared with SPI6RSTC.
This bit is set and reset by software.
0: SPI6 not under reset (default after reset)
1: SPI6 under reset
Bit 4 Reserved, must be kept at reset value.
Bit 3 LPUART1RST: LPUART1 reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with LPUART1RST, S and cleared with
LPUART1RSTC. This bit is set and reset by software.
0: LPUART1 not under reset (default after reset)
1: LPUART1 under reset
Bit 2 HDPRST: HDP reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with HDPRSTS, and cleared with HDPRSTC.
This bit is set and reset by software.
0: HDP not under reset (default after reset)
1: HDP under reset
Bits 1:0 Reserved, must be kept at reset value.

14.10.73 RCC APB4H reset register (RCC_APB4HRSTR)

Address offset: 0x238
Reset value: 0x0000 0000
This register is used to reset the APB4H. It is reset by sys_rstn, and is in the VCORE voltage
domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTSRS SYSCF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
T GRST
rw rw

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 DTSRST: DTS reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with DTSRSTS, and cleared with DTSRSTC.
This bit is set and reset by software.
0: DTS not under reset (default after reset)
1: DTS under reset
Bit 1 Reserved, must be kept at reset value.

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Bit 0 SYSCFGRST: SYSCFG reset

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with SYSCFGRSTS, and cleared
with SYSCFGRSTC. This bit is set and reset by software.
0: SYSCFG not under reset (default after reset)
1: SYSCFG under reset

14.10.74 RCC APB5 reset register (RCC_APB5RSTR)

Address offset: 0x23C
Reset value: 0x0000 0000
This register is used to reset the APB5. It is reset by sys_rstn, and is in the VCORE voltage
domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSIRS VENCR GFXTI DCMIP LTDCR
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
T ST MRST PRST ST
rw rw rw rw rw

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 CSIRST: CSI reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with CSIRSTS, and cleared with CSIRSTC.
This bit is set and reset by software.
0: CSI not under reset (default after reset)
1: CSI under reset
Bit 5 VENCRST: VENC reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with VENCRSTS, and cleared with
VENCRSTC. This bit is set and reset by software.
0: VENC not under reset (default after reset)
1: VENC under reset
Bit 4 GFXTIMRST: GFXTIM reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with GFXTIMRSTS, and cleared with
GFXTIMRSTC.
This bit is set and reset by software.
0: GFXTIM not under reset (default after reset)
1: GFXTIM under reset
Bit 3 Reserved, must be kept at reset value.

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Bit 2 DCMIPPRST: DCMIPP reset

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with DCMIPPRSTS, and cleared with
DCMIPPRSTC.
This bit is set and reset by software.
0: DCMIPP not under reset (default after reset)
1: DCMIPP under reset
Bit 1 LTDCRST: LTDC reset
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with LTDCRST, S and cleared with
LTDCRSTC. This bit is set and reset by software.
0: LTDC not under reset (default after reset)
1: LTDC under reset
Bit 0 Reserved, must be kept at reset value.

14.10.75 RCC IC dividers enable register (RCC_DIVENR)

Address offset: 0x240
Reset value: 0x0000 0000
This register is used to enable the IC dividers in Run, Sleep, and Stop modes. It is reset by
int_sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. IC20EN IC19EN IC18EN IC17EN
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC16EN IC15EN IC14EN IC13EN IC12EN IC11EN IC10EN IC9EN IC8EN IC7EN IC6EN IC5EN IC4EN IC3EN IC2EN IC1EN
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 IC20EN: IC20 enable
This bit is security-protected by IC20SEC or IC20PRIV, and is publicly readable if
IC20PUB = 1. It can be set with IC20ENS, and cleared with IC20ENC. This bit is set and
reset by software.
0: IC20 disabled (default after reset)
1: IC20 enabled
Bit 18 IC19EN: IC19 enable
This bit is security-protected by IC19SEC or IC19PRIV, and is publicly readable if
IC19PUB = 1. It can be set with IC19ENS, and cleared with IC19ENC. This bit is set and
reset by software.
0: IC19 disabled (default after reset)
1: IC19 enabled
Bit 17 IC18EN: IC18 enable
This bit is security-protected by IC18SEC or IC18PRIV, and is publicly readable if
IC18PUB = 1. It can be set with IC18ENS, and cleared with IC18ENC. This bit is set and
reset by software.
0: IC18 disabled (default after reset)
1: IC18 enabled

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Bit 16 IC17EN: IC17 enable

This bit is security-protected by IC17SEC or IC17PRIV, and is publicly readable if IC17PUB =
1. It can be set with IC17ENS, and cleared with IC17ENC. This bit is set and reset by
software.
0: IC17 disabled (default after reset)
1: IC17 enabled
Bit 15 IC16EN: IC16 enable
This bit is security-protected by IC16SEC or IC16PRIV, and is publicly readable if IC16PUB =
1. It can be set with IC16ENS, and cleared with IC16ENC. This bit is set and reset by
software.
0: IC16 disabled (default after reset)
1: IC16 enabled
Bit 14 IC15EN: IC15 enable
This bit is security-protected by IC15SEC or IC15PRIV, and is publicly readable if IC15PUB =
1. It can be set with IC15ENS, and cleared with IC15ENC. This bit is set and reset by
software.
0: IC15 disabled (default after reset)
1: IC15 enabled
Bit 13 IC14EN: IC14 enable
This bit is security-protected by IC14SEC or IC14PRIV, and is publicly readable if IC14PUB =
1. It can be set with IC14ENS, and cleared with IC14ENC. This bit is set and reset by
software.
0: IC14 disabled (default after reset)
1: IC14 enabled
Bit 12 IC13EN: IC13 enable
This bit is security-protected by IC13SEC or IC13PRIV, and is publicly readable if IC13PUB =
1. It can be set with IC13ENS, and cleared with IC13ENC. This bit is set and reset by
software.
0: IC13 disabled (default after reset)
1: IC13 enabled
Bit 11 IC12EN: IC12 enable
This bit is security-protected by IC12SEC or IC12PRIV, and is publicly readable if
IC12PUB = 1. It can be set with IC12ENS, and cleared with IC12ENC. This bit is set and
reset by software.
0: IC12 disabled (default after reset)
1: IC12 enabled
Bit 10 IC11EN: IC11 enable
This bit is security-protected by IC11SEC or IC11PRIV, and is publicly readable if
IC11PUB = 1. It can be set with IC11ENS, and cleared with IC11ENC. This bit is set and reset
by software.
0: IC11 disabled (default after reset)
1: IC11 enabled
Bit 9 IC10EN: IC10 enable
This bit is security-protected by IC10SEC or IC10PRIV, and is publicly readable if
IC10PUB = 1. It can be set with IC10ENS, and cleared with IC10ENC. This bit is set and
reset by software.
0: IC10 disabled (default after reset)
1: IC10 enabled

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Bit 8 IC9EN: IC9 enable

This bit is security-protected by IC9SEC or IC9PRIV, and is publicly readable if IC9PUB = 1.
It can be set with IC9ENS, and cleared with IC9ENC. This bit is set and reset by software.
0: IC9 disabled (default after reset)
1: IC9 enabled
Bit 7 IC8EN: IC8 enable
This bit is security-protected by IC8SEC or IC8PRIV, and is publicly readable if IC8PUB = 1.
It can be set with IC8ENS, and cleared with IC8ENC. This bit is set and reset by software.
0: IC8 disabled (default after reset)
1: IC8 enabled
Bit 6 IC7EN: IC7 enable
This bit is security-protected by IC7SEC or IC7PRIV, and is publicly readable if IC7PUB = 1.
It can be set with IC7ENS, and cleared with IC7ENC. This bit is set and reset by software.
0: IC7 disabled (default after reset)
1: IC7 enabled
Bit 5 IC6EN: IC6 enable
This bit is security-protected by IC6SEC or IC6PRIV, and is publicly readable if IC6PUB = 1.
It can be set with IC6ENS, and cleared with IC6ENC. This bit is set and reset by software.
0: IC6 disabled (default after reset)
1: IC6 enabled
Bit 4 IC5EN: IC5 enable
This bit is security-protected by IC5SEC or IC5PRIV, and is publicly readable if IC5PUB = 1.
It can be set with IC5ENS, and cleared with IC5ENC. This bit is Set and reset by software.
0: IC5 disabled (default after reset)
1: IC5 enabled
Bit 3 IC4EN: IC4 enable
This bit is security-protected by IC4SEC or IC4PRIV, and is publicly readable if IC4PUB = 1.
It can be set with IC4ENS, and cleared with IC4ENC. This bit is set and reset by software.
0: IC4 disabled (default after reset)
1: IC4 enabled
Bit 2 IC3EN: IC3 enable
This bit is security-protected by IC3SEC or IC3PRIV, and is publicly readable if IC3PUB = 1.
It can be set with IC3ENS, and cleared with IC3ENC. This bit is set and reset by software.
0: IC3 disabled (default after reset)
1: IC3 enabled
Bit 1 IC2EN: IC2 enable
This bit is security-protected by IC2SEC or IC2PRIV, and is publicly readable if IC2PUB = 1.
It can be set with IC2ENS, and cleared with IC2ENC. This bit is set and reset by software.
0: IC2 disabled (default after reset)
1: IC2 enabled
Bit 0 IC1EN: IC1 enable
This bit is security-protected by IC1SEC or IC1PRIV, and is publicly readable if IC1PUB = 1.
It can be set with IC1ENS, and cleared with IC1ENC. This bit is set and reset by software.
0: IC1 disabled (default after reset)
1: IC1 enabled

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RM0486 Reset and clock control (RCC)

14.10.76 RCC embedded buses enable register (RCC_BUSENR)

Address offset: 0x244
Reset value: 0x0000 0003
This register is used to enable the embedded buses in Run and Sleep modes (in Sleep
mode, each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rst, and is in
the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
APB5 APB4 APB3 APB2 APB1 AHB5 AHB4 AHB3 AHB2 AHB1 AHBM ACLKNC ACLKN
Res. Res. Res.
EN EN EN EN EN EN EN EN EN EN EN EN EN
rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 APB5EN: APB5 enable
This bit is security-protected by the APB5SEC bit, the APB5PV bit, and is publicly readable if
APB5PUB = 1. It can be set with APB5ENS, and cleared with APB5ENC. The bit field is non-
user. Set and reset by software. Debug field, must be kept at reset value.
0: APB5 disabled (default after reset)
1: APB5 enabled
Bit 11 APB4EN: APB4 enable
The bit field is security-protected by the APB4SEC bit, the APB4PV bit, and is publicly
readable if APB4PUB=1. The bit can be set with APB4ENS and cleared with APB4ENC. The
bit field is non-user. Set and reset by software. Debug field, must be kept at reset value.
0: APB4 disabled (default after reset)
1: APB4 enabled
Bit 10 APB3EN: APB3 enable
The bit field is security-protected by the APB3SEC bit, the APB3PV bit, and is publicly
readable if APB3PUB=1. The bit can be set with APB3ENS and cleared with APB3ENC. The
bit field is non-user. Set and reset by software. Debug field, must be kept at reset value.
0: APB3 disabled (default after reset)
1: APB3 enabled
Bit 9 APB2EN: APB2 enable
The bit field is security-protected by the APB2SEC bit, the APB2PV bit, and is publicly
readable if APB2PUB=1. The bit can be set with APB2ENS and cleared with APB2ENC. The
bit field is non-user. Set and reset by software. Debug field, must be kept at reset value.
0: APB2 is disabled (default after reset)
1: APB2 is enabled
Bit 8 APB1EN: APB1 enable
The bit field is security-protected by the APB1SEC bit, the APB1PV bit, and is publicly
readable if APB1PUB=1. The bit can be set with APB1ENS and cleared with APB1ENC. The
bit field is non-user. Set and reset by software. Debug field, must be kept at reset value.
0: APB1 is disabled (default after reset)
1: APB1 is enabled

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Bit 7 AHB5EN: AHB5 enable

The bit field is security-protected by the AHB5SEC bit, the AHB5PV bit, and is publicly
readable if AHB5PUB=1. The bit can be set with AHB5ENS and cleared with AHB5ENC. The
bit field is non-user. Set and reset by software. Debug field, must be kept at reset value.
0: AHB5 is disabled (default after reset)
1: AHB5 is enabled
Bit 6 AHB4EN: AHB4 enable
The bit field is security-protected by the AHB4SEC bit, the AHB4PV bit, and is publicly
readable if AHB4PUB=1. The bit can be set with AHB4ENS and cleared with AHB4ENC. The
bit field is non-user. Set and reset by software. Debug field, must be kept at reset value.
0: AHB4 is disabled (default after reset)
1: AHB4 is enabled
Bit 5 AHB3EN: AHB3 enable
The bit field is security-protected by the AHB3SEC bit, the AHB3PV bit, and is publicly
readable if AHB3PUB=1. The bit can be set with AHB3ENS and cleared with AHB3ENC. The
bit field is non-user. Set and reset by software. Debug field, must be kept at reset value.
0: AHB3 is disabled (default after reset)
1: AHB3 is enabled
Bit 4 AHB2EN: AHB2 enable
The bit field is security-protected by the AHB2SEC bit, the AHB2PV bit, and is publicly
readable if AHB2PUB=1. The bit can be set with AHB2ENS and cleared with AHB2ENC. The
bit field is non-user. Set and reset by software. Debug field, must be kept at reset value.
0: AHB2 is disabled (default after reset)
1: AHB2 is enabled
Bit 3 AHB1EN: AHB1 enable
The bit field is security-protected by the AHB1SEC bit, the AHB1PV bit, and is publicly
readable if AHB1PUB=1. The bit can be set with AHB1ENS and cleared with AHB1ENC. The
bit field is non-user. Set and reset by software. Debug field, must be kept at reset value.
0: AHB1 is disabled (default after reset)
1: AHB1 is enabled
Bit 2 AHBMEN: AHBM enable
The bit field is security-protected by the AHBMSEC bit, the AHBMPV bit, and is publicly
readable if AHBMPUB = 1. The bit can be set with AHBMENS and cleared with AHBMENC.
The bit field is non-user. Set and reset by software. Debug field, must be kept at reset value.
0: AHBM is disabled (default after reset)
1: AHBM is enabled
Bit 1 ACLKNCEN: ACLKNC enable
This bit is security-protected by ACLKNCSEC or ACLKNCPRIV, and is publicly readable if
ACLKNCPUB = 1. It can be set with ACLKNCENS, and cleared with ACLKNCENC. This bit is
set and reset by software.
0: ACLKNC disabled
1: ACLKNC enabled (default after reset)
Bit 0 ACLKNEN: ACLKN enable
This bit is security-protected by ACLKNSEC or ACLKNPRIV, and is publicly readable if
ACLKNPUB = 1. It can be set with ACLKNENS, and cleared with ACLKNENC. This bit is set
and reset by software.
0: ACLKN disabled
1: ACLKN enabled (default after reset)

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RM0486 Reset and clock control (RCC)

14.10.77 RCC miscellaneous configurations enable register

(RCC_MISCENR)
Address offset: 0x248
Reset value: 0x0000 0000
This register is used to enable the miscellaneous configurations in Run and Sleep modes (in
Sleep mode, each bit of this register is AND-ed with the LPEN bit). It is reset by
int_sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XSPIP
MCO2 MCO1 DBGE
Res. Res. Res. Res. Res. Res. Res. Res. Res. PEREN Res. Res. HYCO
EN EN N
MPEN
rw rw rw rw rw

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 PEREN: PER enable
This bit is security-protected by PERSEC or PERPRIV. it can be set with PERENS, and
cleared with PERENC. This bit is set and reset by software.
0: PER disabled (default after reset)
1: PER enabled
Bits 5:4 Reserved, must be kept at reset value.
Bit 3 XSPIPHYCOMPEN: XSPIPHYCOMP enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with XSPIPHYCOMPENS, and cleared
with XSPIPHYCOMPENC. This bit is set and reset by software.
0: XSPIPHYCOMP disabled (default after reset)
1: XSPIPHYCOMP enabled
Bit 2 MCO2EN: MCO2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with MCO2ENS, and cleared with MCO2ENC.
This bit is set and reset by software.
0: MCO2 disabled (default after reset)
1: MCO2 enabled
Bit 1 MCO1EN: MCO1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with MCO1ENS, and cleared with MCO1ENC.
This bit is set and reset by software.
0: MCO1 disabled (default after reset)
1: MCO1 enabled
Bit 0 DBGEN: DBG enable
This bit is always security-protected. It can be set with DBGENS, and cleared with
[Link] bit is set and reset by software.
0: DBG disabled (default after reset)
1: DBG enabled

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Reset and clock control (RCC) RM0486

14.10.78 RCC embedded memories enable register (RCC_MEMENR)

Address offset: 0x24C
Reset value: 0x0000 13F0
This register is used to enable the embedded memories in Run and Sleep modes (in Sleep
mode, each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in
the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOT CACHE
VENCR FLEXR AXISR AXISR BKPSR AHBSR AHBSR AXISR AXISR AXISR AXISR
Res. Res. Res. ROME AXIRA
AMEN AMEN AM2EN AM1EN AMEN AM2EN AM1EN AM6EN AM5EN AM4EN AM3EN
N MEN
rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 BOOTROMEN: BootROM enable
This bit is always security-protected. It can be set with BOOTROMENS, and cleared with
BOOTROMENC. This bit is set and reset by software.
0: BootROM disabled
1: BootROM enabled (default after reset)
Bit 11 VENCRAMEN: VENCRAM enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if VENCRAMPUB = 1. It can be set with VENCRAMENS, and cleared with VENCRAMENC.
This bit is set and reset by software.
0: VENCRAM disabled (default after reset)
1: VENCRAM enabled
Bit 10 CACHEAXIRAMEN: CACHEAXIRAM enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if CACHEAXIRAMPUB = 1. It can be set with CACHEAXIRAMENS, and cleared with
CACHEAXIRAMENC. This bit is set and reset by software.
0: CACHEAXIRAM disabled (default after reset)
1: CACHEAXIRAM enabled
Bit 9 FLEXRAMEN: FLEXRAM enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if FLEXRAMPUB = 1. It can be set with FLEXRAMENS, and cleared with FLEXRAMENC.
This bit is set and reset by software.
0: FLEXRAM disabled
1: FLEXRAM enabled (default after reset)
Bit 8 AXISRAM2EN: AXISRAM2 enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AXISRAM2PUB = 1. It can be set with AXISRAM2ENS, and cleared with AXISRAM2ENC.
This bit is set and reset by software.
0: AXISRAM2 disabled
1: AXISRAM2 enabled (default after reset)

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RM0486 Reset and clock control (RCC)

Bit 7 AXISRAM1EN: AXISRAM1 enable

This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AXISRAM1PUB = 1. It can be set with AXISRAM1ENS, and cleared with AXISRAM1ENC.
This bit is set and reset by software.
0: AXISRAM1 disabled
1: AXISRAM1 enabled (default after reset)
Bit 6 BKPSRAMEN: BKPSRAM enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if BKPSRAMPUB = 1. It can be set with BKPSRAMENS, and cleared with BKPSRAMENC.
This bit is set and reset by software.
0: BKPSRAM disabled
1: BKPSRAM enabled (default after reset)
Bit 5 AHBSRAM2EN: AHBSRAM2 enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AHBSRAM2PUB = 1. It can be set with AHBSRAM2ENS, and cleared with
AHBSRAM2ENC. This bit is set and reset by software.
0: AHBSRAM2 disabled
1: AHBSRAM2 enabled (default after reset)
Bit 4 AHBSRAM1EN: AHBSRAM1 enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AHBSRAM1PUB = 1. It can be set with AHBSRAM1ENS, and cleared with
AHBSRAM1ENC. This bit is set and reset by software.
0: AHBSRAM1 disabled
1: AHBSRAM1 enabled (default after reset)
Bit 3 AXISRAM6EN: AXISRAM6 enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AXISRAM6PUB = 1. It can be set with AXISRAM6ENS, and cleared with AXISRAM6ENC.
This bit is set and reset by software.
0: AXISRAM6 disabled (default after reset)
1: AXISRAM6 enabled
Bit 2 AXISRAM5EN: AXISRAM5 enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AXISRAM5PUB = 1. It can be set with AXISRAM5ENS, and cleared with AXISRAM5ENC.
This bit is set and reset by software.
0: AXISRAM5 disabled (default after reset)
1: AXISRAM5 enabled
Bit 1 AXISRAM4EN: AXISRAM4 enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AXISRAM4PUB = 1. It can be set with AXISRAM4ENS, and cleared with AXISRAM4ENC.
This bit is set and reset by software.
0: AXISRAM4 disabled (default after reset)
1: AXISRAM4 enabled
Bit 0 AXISRAM3EN: AXISRAM3 enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AXISRAM3PUB = 1. It can be set with AXISRAM3ENS, and cleared with AXISRAM3ENC.
This bit is set and reset by software.
0: AXISRAM3 disabled (default after reset)
1: AXISRAM3 enabled

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14.10.79 RCC AHB1 enable register (RCC_AHB1ENR)

Address offset: 0x250
Reset value: 0x0000 0000
This register is used to enable the AHB1 in Run and Sleep modes (in Sleep mode, each bit
of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC12 GPDMA1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN EN
rw rw

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 ADC12EN: ADC12 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with ADC12ENS, and cleared with
ADC12ENC. This bit is set and reset by software.
0: ADC12 disabled (default after reset)
1: ADC12 enabled
Bit 4 GPDMA1EN: GPDMA1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPDMA1ENS, and cleared with
GPDMA1ENC. This bit is set and reset by software.
0: GPDMA1 disabled (default after reset)
1: GPDMA1 enabled
Bits 3:0 Reserved, must be kept at reset value.

14.10.80 RCC AHB2 enable register (RCC_AHB2ENR)

Address offset: 0x254
Reset value: 0x0000 1000
This register is used to enable the AHB2 in Run and Sleep modes (in Sleep mode, each bit
of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADF1E MDF1E
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
N N
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAMC
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
FGEN
rw

Bits 31:18 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

Bit 17 ADF1EN: ADF1 enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with ADF1ENS, and cleared with ADF1ENC.
This bit is set and reset by software.
0: ADF1 disabled (default after reset)
1: ADF1 enabled
Bit 16 MDF1EN: MDF1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with MDF1ENS, and cleared with MDF1ENC.
This bit is set and reset by software.
0: MDF1 disabled (default after reset)
1: MDF1 enabled
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 RAMCFGEN: RAMCFG enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with RAMCFGENS, and cleared with
RAMCFGENC. This bit is set and reset by software.
0: RAMCFG disabled
1: RAMCFG enabled (default after reset)
Bits 11:0 Reserved, must be kept at reset value.

14.10.81 RCC AHB3 enable register (RCC_AHB3ENR)

Address offset: 0x258
Reset value: 0x0000 4600
This register is used to enable the AHB3 in Run and Sleep modes (in Sleep mode, each bit
of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RISAF RIFSC SAESE CRYPE HASHE RNGE
Res. Res. Res. Res. IACEN PKAEN Res. Res. Res. Res.
EN EN N N N N
rw rw rw rw rw rw rw rw

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 RISAFEN: RISAF enable
This bit is always security-protected. It can be set with RISAFENS, and cleared with
RISAFENC. This bit is set and reset by software.
0: RISAF disabled
1: RISAF enabled (default after reset)
Bits 13:11 Reserved, must be kept at reset value.

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Bit 10 IACEN: IAC enable

This bit is always security-protected. It can be set with IACENS, and cleared with IACENC.
This bit is set and reset by software.
0: IAC disabled
1: IAC enabled (default after reset)
Bit 9 RIFSCEN: RIFSC enable
This bit is always security-protected. It can be set with RIFSCENS, and cleared with
RIFSCENC. This bit is set and reset by software.
0: RIFSC disabled
1: RIFSC enabled (default after reset)
Bit 8 PKAEN: PKA enable
This bit is security-protected by SYSSEC or SYSPRIV. It can be set with PKAENS, and
cleared with PKAENC. This bit is set and reset by software.
0: PKA disabled (default after reset)
1: PKA enabled
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 SAESEN: SAES enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with SAESENS, and cleared with SAESENC.
This bit is set and reset by software.
0: SAES disabled (default after reset)
1: SAES enabled
Bit 3 Reserved, must be kept at reset value.
Bit 2 CRYPEN: CRYP enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with CRYPENS, and cleared with CRYPENC.
This bit is set and reset by software.
0: CRYP disabled (default after reset)
1: CRYP enabled
Bit 1 HASHEN: HASH enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with HASHENS, and cleared with HASHENC.
This bit is set and reset by software.
0: HASH disabled (default after reset)
1: HASH enabled
Bit 0 RNGEN: RNG enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with RNGENS, and cleared with RNGENC.
This bit is set and reset by software.
0: RNG disabled (default after reset)
1: RNG enabled

14.10.82 RCC AHB4 enable register (RCC_AHB4ENR)

Address offset: 0x25C
Reset value: 0x0004 0000

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RM0486 Reset and clock control (RCC)

This register is used to enable the AHB4 in Run and Sleep modes (in Sleep mode, each bit
of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRC PWR GPIOQ
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN EN EN
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOP GPIOO GPION GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Res. Res. Res. Res. Res.
EN EN EN EN EN EN EN EN EN EN EN
rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 CRCEN: CRC enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with CRCENS, and cleared with CRCENC.
This bit is set and reset by software.
0: CRC disabled (default after reset)
1: CRC enabled
Bit 18 PWREN: PWR enable
This bit is always security-protected. It can be set with PWRENS, and cleared
with PWRENC. This bit is set and reset by software.
0: PWR disabled
1: PWR enabled (default after reset)
Bit 17 Reserved, must be kept at reset value.
Bit 16 GPIOQEN: GPIO Q enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOQENS, and cleared with
GPIOQENC. This bit is set and reset by software.
0: GPIO Q disabled (default after reset)
1: GPIO Q enabled
Bit 15 GPIOPEN: GPIO P enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOPENS, and cleared with
GPIOPENC. This bit is set and reset by software.
0: GPIO P disabled (default after reset)
1: GPIO P enabled
Bit 14 GPIOOEN: GPIO O enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOOENS, and cleared with
GPIOOENC. This bit is set and reset by software.
0: GPIO O disabled (default after reset)
1: GPIO O enabled

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Bit 13 GPIONEN: GPIO N enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIONENS, and cleared with
GPIONENC. This bit is set and reset by software.
0: GPIO N disabled (default after reset)
1: GPIO N enabled
Bits 12:8 Reserved, must be kept at reset value.
Bit 7 GPIOHEN: GPIO H enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOHENS, and cleared with
GPIOHENC. This bit is set and reset by software.
0: GPIO H disabled (default after reset)
1: GPIO H enabled
Bit 6 GPIOGEN: GPIO G enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOGENS, and cleared with
GPIOGENC. This bit is set and reset by software.
0: GPIO G disabled (default after reset)
1: GPIO G enabled
Bit 5 GPIOFEN: GPIO F enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. t can be set with GPIOFENS, and cleared with GPIOFENC.
This bit is set and reset by software.
0: GPIO F disabled (default after reset)
1: GPIO F enabled
Bit 4 GPIOEEN: GPIO E enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOEENS, and cleared with
GPIOEENC. This bit is set and reset by software.
0: GPIO E disabled (default after reset)
1: GPIO E enabled
Bit 3 GPIODEN: GPIO D enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIODENS, and cleared with
GPIODENC. This bit is set and reset by software.
0: GPIO D disabled (default after reset)
1: GPIO D enabled
Bit 2 GPIOCEN: GPIO C enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOCENS, and cleared with
GPIOCENC. This bit is set and reset by software.
0: GPIO C disabled (default after reset)
1: GPIO C enabled
Bit 1 GPIOBEN: GPIO B enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOBENS, and cleared with
GPIOBENC. This bit is set and reset by software.
0: GPIO B disabled (default after reset)
1: GPIO B enabled

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RM0486 Reset and clock control (RCC)

Bit 0 GPIOAEN: GPIO A enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOAENS, and cleared with
GPIOAENC. This bit is set and reset by software.
0: GPIO A disabled (default after reset)
1: GPIO A enabled

14.10.83 RCC AHB5 enable register (RCC_AHB5ENR)

Address offset: 0x260
Reset value: 0x0000 0000
This register is used to enable the AHB5 in Run and Sleep modes (in Sleep mode, each bit
of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CACHE OTG OTG ETH1 ETH1 ETH1 GFX
NPU OTG2 OTG1 ETH1 GPU2D MCE4 XSPI3 MCE3
AXI PHY2 PHY1 RX TX MAC Res. MMU
EN EN EN EN EN EN EN EN
EN EN EN EN EN EN EN
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMM SDMM HP
MCE2 MCE1 XSPIM XSPI2 PSSI XSPI1 FMC JPEG DMA2D
Res. Res. Res. C1 C2 Res. DMA1
EN EN EN EN EN EN EN EN EN
EN EN EN
rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 NPUEN: NPU enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with NPUENS, and cleared with NPUENC.
This bit is set and reset by software.
0: NPU disabled (default after reset)
1: NPU enabled
Bit 30 CACHEAXIEN: CACHEAXI enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with CACHEAXIENS and cleared with
CACHEAXIENC. This bit is set and reset by software.
0: CACHEAXI disabled (default after reset)
1: CACHEAXI enabled
Bit 29 OTG2EN: OTG2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with OTG2ENS, and cleared with OTG2ENC.
This bit is set and reset by software.
0: OTG2 i disabled (default after reset)
1: OTG2 enabled
Bit 28 OTGPHY2EN: OTGPHY2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with OTGPHY2ENS, and cleared with
OTGPHY2ENC. This bit is set and reset by software.
0: OTGPHY2 disabled (default after reset)
1: OTGPHY2 enabled

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Bit 27 OTGPHY1EN: OTGPHY1 enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, tor he PERPRIV bit. It can be set with OTGPHY1ENS, and cleared with
OTGPHY1ENC. This bit is set and reset by software.
0: OTGPHY1 disabled (default after reset)
1: OTGPHY1 enabled
Bit 26 OTG1EN: OTG1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with OTG1ENS, and cleared with OTG1ENC.
This bit is set and reset by software.
0: OTG1 disabled (default after reset)
1: OTG1 enabled
Bit 25 ETH1EN: ETH1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with ETH1ENS, and cleared with ETH1ENC.
This bit is set and reset by software.
0: ETH1 disabled (default after reset)
1: ETH1 enabled
Bit 24 ETH1RXEN: ETH1RX enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with ETH1RXENS, and cleared with
ETH1RXENC. This bit is set and reset by software.
0: ETH1RX disabled (default after reset)
1: ETH1RX enabled
Bit 23 ETH1TXEN: ETH1TX enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with ETH1TXENS, and cleared with
ETH1TXENC. This bit is set and reset by software.
0: ETH1TX disabled (default after reset)
1: ETH1TX enabled
Bit 22 ETH1MACEN: ETH1MAC enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with ETH1MACENS, and cleared with
ETH1MACENC. This bit is set and reset by software.
0: ETH1MAC disabled (default after reset)
1: ETH1MAC enabled
Bit 21 Reserved, must be kept at reset value.
Bit 20 GPU2DEN: GPU2D enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPU2DENS, and cleared with
GPU2DENC. This bit is set and reset by software.
0: GP2DU2D disabled (default after reset)
1: GPU enabled
Bit 19 GFXMMUEN: GFXMMU enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GFXMMUENS, and cleared with
GFXMMUENC. This bit is set and reset by software.
0: GFXMMU disabled (default after reset)
1: GFXMMU enabled

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RM0486 Reset and clock control (RCC)

Bit 18 MCE4EN: MCE4 enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with MCE4ENS, and cleared with MCE4ENC.
This bit is set and reset by software.
0: MCE4 disabled (default after reset)
1: MCE4 enabled
Bit 17 XSPI3EN: XSPI3 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with XSPI3ENS, and cleared with XSPI3ENC.
This bit is set and reset by software.
0: XSPI3 disabled (default after reset)
1: XSPI3 enabled
Bit 16 MCE3EN: MCE3 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with MCE3ENS, and cleared with MCE3ENC.
This bit is set and reset by software.
0: MCE3 disabled (default after reset)
1: MCE3 enabled
Bit 15 MCE2EN: MCE2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with MCE2ENS, and cleared with MCE2ENC.
This bit is set and reset by software.
0: MCE2 disabled (default after reset)
1: MCE2 enabled
Bit 14 MCE1EN: MCE1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with MCE1ENS, and cleared with MCE1ENC.
This bit is set and reset by software.
0: MCE1 disabled (default after reset)
1: MCE1 enabled
Bit 13 XSPIMEN: XSPIM enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with XSPIMENS, and cleared with
XSPIMENC. This bit is set and reset by software.
0: XSPIM disabled (default after reset)
1: XSPIM enabled
Bit 12 XSPI2EN: XSPI2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with XSPI2ENS, and cleared with XSPI2ENC.
This bit is set and reset by software.
0: XSPI2 disabled (default after reset)
1: XSPI2 enabled
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 SDMMC1EN: SDMMC1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SDMMC1ENS, and cleared with
SDMMC1ENC. This bit is set and reset by software.
0: SDMMC1 disabled (default after reset)
1: SDMMC1 enabled

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Bit 7 SDMMC2EN: SDMMC2 enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SDMMC2ENS, and cleared with
SDMMC2ENC. This bit is set and reset by software.
0: SDMMC2 disabled (default after reset)
1: SDMMC2 enabled
Bit 6 PSSIEN: PSSI enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with PSSIENS, and cleared with PSSIENC.
This bit is set and reset by software.
0: PSSI disabled (default after reset)
1: PSSI enabled
Bit 5 XSPI1EN: XSPI1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with XSPI1ENS, and cleared with XSPI1ENC.
This bit is set and reset by software.
0: XSPI1 disabled (default after reset)
1: XSPI1 enabled
Bit 4 FMCEN: FMC enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with FMCENS, and cleared with FMCENC.
This bit is set and reset by software.
0: FMC disabled (default after reset)
1: FMC enabled
Bit 3 JPEGEN: JPEG enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with JPEGENS, and cleared with JPEGENC.
This bit is set and reset by software.
0: JPEG disabled (default after reset)
1: JPEG enabled
Bit 2 Reserved, must be kept at reset value.
Bit 1 DMA2DEN: DMA2D enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with DMA2DENS, and cleared with
DMA2DENC. This bit is set and reset by software.
0: DMA2D disabled (default after reset)
1: DMA2D enabled
Bit 0 HPDMA1EN: HPDMA1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with HPDMA1ENS, and cleared with
HPDMA1ENC. This bit is set and reset by software.
0: HPDMA1 disabled (default after reset)
1: HPDMA1 enabled

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RM0486 Reset and clock control (RCC)

14.10.84 RCC APB1L enable register (RCC_APB1LENR)

Address offset: 0x264
Reset value: 0x0000 0000
This register is used to enable the APB1L in Run and Sleep modes (in Sleep mode, each bit
of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UART8 UART7 UART5 UART4 USART USART SPDIF
Res. Res. Res. Res. I3C2EN I3C1EN I2C3EN I2C2EN I2C1EN
EN EN EN EN 3EN 2EN RX1EN
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3E SPI2E TIM11E TIM10E WWDG LPTIM1 TIM14E TIM13E TIM12E TIM7E TIM6E TIM5E TIM4E TIM3E TIM2E
Res.
N N N N EN EN N N N N N N N N N
rw rw rw rw rs rw rw rw rw rw rw rw rw rw rw

Bit 31 UART8EN: UART8 enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with UART8ENS, and cleared with
UART8ENC. This bit is set and reset by software.
0: UART8 disabled (default after reset)
1: UART8 enabled
Bit 30 UART7EN: UART7 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with UART7ENS, and cleared with
UART7ENC. This bit is set and reset by software.
0: UART7 disabled (default after reset)
1: UART7 enabled
Bits 29:26 Reserved, must be kept at reset value.
Bit 25 I3C2EN: I3C2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with I3C2ENS, and cleared with I3C2ENC.
This bit is set and reset by software.
0: I3C2 disabled (default after reset)
1: I3C2 enabled
Bit 24 I3C1EN: I3C1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with I3C1ENS, and cleared with I3C1ENC.
This bit is set and reset by software.
0: I3C1 disabled (default after reset)
1: I3C1 enabled
Bit 23 I2C3EN: I2C3 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with I2C3ENS, and cleared with I2C3ENC.
This bit is set and reset by software.
0: I2C3 disabled (default after reset)
1: I2C3 enabled

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Bit 22 I2C2EN: I2C2 enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with I2C2ENS, and cleared with I2C2ENC.
This bit is set and reset by software.
0: I2C2 disabled (default after reset)
1: I2C2 enabled
Bit 21 I2C1EN: I2C1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with I2C1ENS, and cleared with I2C1ENC.
This bit is set and reset by software.
0: I2C1 disabled (default after reset)
1: I2C1 enabled
Bit 20 UART5EN: UART5 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit,. It can be set with UART5ENS, and cleared with
UART5ENC. This bit is set and reset by software.
0: UART5 disabled (default after reset)
1: UART5 enabled
Bit 19 UART4EN: UART4 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with UART4ENS, and cleared with
UART4ENC. This bit is set and reset by software.
0: UART4 disabled (default after reset)
1: UART4 enabled
Bit 18 USART3EN: USART3 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with USART3ENS, and cleared with
USART3ENC. This bit is set and reset by software.
0: USART3 disabled (default after reset)
1: USART3 enabled
Bit 17 USART2EN: USART2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with USART2ENS, and cleared with
USART2ENC. This bit is set and reset by software.
0: USART2 disabled (default after reset)
1: USART2 enabled
Bit 16 SPDIFRX1EN: SPDIFRX1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SPDIFRX1ENS, and cleared with
SPDIFRX1ENC. This bit is set and reset by software.
0: SPDIFRX1 disabled (default after reset)
1: SPDIFRX1 enabled
Bit 15 SPI3EN: SPI3 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SPI3ENS, and cleared with SPI3ENC.
This bit is set and reset by software.
0: SPI3 disabled (default after reset)
1: SPI3 enabled

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RM0486 Reset and clock control (RCC)

Bit 14 SPI2EN: SPI2 enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SPI2ENS, and cleared with SPI2ENC.
This bit is set and reset by software.
0: SPI2 disabled (default after reset)
1: SPI2 enabled
Bit 13 TIM11EN: TIM11 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM11ENS, and cleared with TIM11ENC.
This bit is set and reset by software.
0: TIM11 disabled (default after reset)
1: TIM11 enabled
Bit 12 TIM10EN: TIM10 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM10ENS, and cleared with TIM10ENC.
This bit is set and reset by software.
0: TIM10 disabled (default after reset)
1: TIM10 enabled
Bit 11 WWDGEN: WWDG enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with WWDGENS. This bit is set and reset by
software.
0: WWDG is disabled (default after reset)
1: WWDG is enabled
Bit 10 Reserved, must be kept at reset value.
Bit 9 LPTIM1EN: LPTIM1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with LPTIM1ENS, and cleared with
LPTIM1ENC. This bit is set and reset by software.
0: LPTIM1 is disabled (default after reset)
1: LPTIM1 is enabled
Bit 8 TIM14EN: TIM14 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM14ENS, and cleared with TIM14ENC.
This bit is set and reset by software.
0: TIM14 is disabled (default after reset)
1: TIM14 is enabled
Bit 7 TIM13EN: TIM13 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with TIM13ENS, and cleared with TIM13ENC.
This bit is set and reset by software.
0: TIM13 disabled (default after reset)
1: TIM13 enabled
Bit 6 TIM12EN: TIM12 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM12ENS, and cleared with TIM12ENC.
This bit is set and reset by software.
0: TIM12 disabled (default after reset)
1: TIM12 enabled

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Bit 5 TIM7EN: TIM7 enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM7ENS, and cleared with TIM7ENC.
This bit is set and reset by software.
0: TIM7 disabled (default after reset)
1: TIM7 enabled
Bit 4 TIM6EN: TIM6 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM6ENS, and cleared with TIM6ENC.
This bit is set and reset by software.
0: TIM6 disabled (default after reset)
1: TIM6 enabled
Bit 3 TIM5EN: TIM5 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM5ENS, and cleared with TIM5ENC.
This bit is set and reset by software.
0: TIM5 disabled (default after reset)
1: TIM5 enabled
Bit 2 TIM4EN: TIM4 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM4ENS, and cleared with TIM4ENC.
This bit is set and reset by software.
0: TIM4 disabled (default after reset)
1: TIM4 enabled
Bit 1 TIM3EN: TIM3 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM3ENS, and cleared with TIM3ENC.
This bit is set and reset by software.
0: TIM3 disabled (default after reset)
1: TIM3 enabled
Bit 0 TIM2EN: TIM2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM2ENS, and cleared with TIM2ENC.
This bit is set and reset by software.
0: TIM2 disabled (default after reset)
1: TIM2 enabled

14.10.85 RCC APB1H enable register (RCC_APB1HENR)

Address offset: 0x268
Reset value: 0x0000 0000
This register is used to enable the APB1H in Run and Sleep modes (in Sleep mode, each bit
of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the VCORE
voltage domain.

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RM0486 Reset and clock control (RCC)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN MDIOS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN EN
rw rw

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 UCPD1EN: UCPD1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with UCPD1ENS, and cleared with
UCPD1ENC. This bit is set and reset by software.
0: UCPD1 disabled (default after reset)
1: UCPD1 enabled
Bits 17:9 Reserved, must be kept at reset value.
Bit 8 FDCANEN: FDCAN enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with FDCANENS, and cleared with
FDCANENC. This bit is set and reset by software.
0: FDCAN disabled (default after reset)
1: FDCAN enabled
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 MDIOSEN: MDIOS enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with MDIOSENS, and cleared with
MDIOSENC. This bit is set and reset by software.
0: MDIOS disabled (default after reset)
1: MDIOS enabled
Bits 4:0 Reserved, must be kept at reset value.

14.10.86 RCC APB2 enable register (RCC_APB2ENR)

Address offset: 0x26C
Reset value: 0x0000 0000
This register is used to enable the APB2 in Run and Sleep modes (in Sleep mode, each bit
of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAI2E SAI1E SPI5E TIM9E TIM17E TIM16E TIM15E
Res. Res. Res. Res. Res. Res. Res. Res. Res.
N N N N N N N
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIM18E SPI4E SPI1E USART UART9 USART USART TIM8E TIM1E
Res. Res. Res. Res. Res. Res. Res.
N N N 10EN EN 6EN 1EN N N
rw rw rw rw rw rw rw rw rw

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Bits 31:23 Reserved, must be kept at reset value.

Bit 22 SAI2EN: SAI2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SAI2ENS, and cleared with SAI2ENC.
This bit is set and reset by software.
0: SAI2 disabled (default after reset)
1: SAI2 enabled
Bit 21 SAI1EN: SAI1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SAI1EN, and cleared with SAI1ENC. This
bit is set and reset by software.
0: SAI1 disabled (default after reset)
1: SAI1 enabled
Bit 20 SPI5EN: SPI5 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SPI5ENS, and cleared with
[Link] bit is set and reset by software.
0: SPI5 disabled (default after reset)
1: SPI5 enabled
Bit 19 TIM9EN: TIM9 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM9ENS, and cleared with TIM9ENC.
This bit is set and reset by software.
0: TIM9 disabled (default after reset)
1: TIM9 enabled
Bit 18 TIM17EN: TIM17 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM17ENS, and cleared with TIM17ENC.
This bit is set and reset by software.
0: TIM17 disabled (default after reset)
1: TIM17 enabled
Bit 17 TIM16EN: TIM16 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM16ENS, and cleared with TIM16ENC.
This bit is set and reset by software.
0: TIM16 disabled (default after reset)
1: TIM16 enabled
Bit 16 TIM15EN: TIM15 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit,. It can be set with TIM15ENS, and cleared with TIM15ENC.
This bit is set and reset by software.
0: TIM15 disabled (default after reset)
1: TIM15 enabled
Bit 15 TIM18EN: TIM18 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM18ENS, and cleared with TIM18ENC.
This bit is set and reset by software.
0: TIM18 disabled (default after reset)
1: TIM18 enabled

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RM0486 Reset and clock control (RCC)

Bit 14 Reserved, must be kept at reset value.

Bit 13 SPI4EN: SPI4 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SPI4ENS, and cleared with SPI4ENC.
This bit is set and reset by software.
0: SPI4 disabled (default after reset)
1: SPI4 enabled
Bit 12 SPI1EN: SPI1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SPI1ENS, and cleared with SPI1ENC.
This bit is set and reset by software.
0: SPI1 disabled (default after reset)
1: SPI1 enabled
Bits 11:8 Reserved, must be kept at reset value.
Bit 7 USART10EN: USART10 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with USART10ENS, and cleared with
USART10ENC. This bit is set and reset by software.
0: USART10 disabled (default after reset)
1: USART10 enabled
Bit 6 UART9EN: UART9 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with UART9ENS, and cleared with
UART9ENC. This bit is set and reset by software.
0: UART9 disabled (default after reset)
1: UART9 enabled
Bit 5 USART6EN: USART6 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with USART6ENS, and cleared with
USART6ENC. This bit is set and reset by software.
0: USART6 disabled (default after reset)
1: USART6 enabled
Bit 4 USART1EN: USART1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with USART1EN,S and cleared with
USART1ENC. This bit is set and reset by software.
0: USART1 disabled (default after reset)
1: USART1 enabled
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8EN: TIM8 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM8ENS, and cleared with TIM8ENC.
This bit is set and reset by software.
0: TIM8 disabled (default after reset)
1: TIM8 enabled

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Bit 0 TIM1EN: TIM1 enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM1ENS, and cleared with TIM1ENC.
This bit is set and reset by software.
0: TIM1 disabled (default after reset)
1: TIM1 enabled

14.10.87 RCC APB3 enable register (RCC_APB3ENR)

Address offset: 0x270
Reset value: 0x0000 0000
This register is used to enable the APB3 in Run and Sleep modes (in Sleep mode, each bit
of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DFTEN Res. Res.
rw

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 DFTEN: DFT enable
This bit is security-protected by DFTSEC or DFTPRIV. It can be set with DFTENS, and
cleared with DFTENC. This bit is set and reset by software.
0: DFT disabled (default after reset)
1: DFT enabled
Bits 1:0 Reserved, must be kept at reset value.

14.10.88 RCC APB4L enable register (RCC_APB4LENR)

Address offset: 0x274
Reset value: 0x0000 0000
This register is used to enable the APB4L in Run and Sleep modes (in Sleep mode, each bit
of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCAP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RTCEN
BEN
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFB LPTIM5 LPTIM4 LPTIM3 LPTIM2 SPI6E LPUAR
Res. Res. Res. I2C4EN Res. Res. HDPEN Res. Res.
UFEN EN EN EN EN N T1EN
rw rw rw rw rw rw rw rw rw

Bits 31:18 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

Bit 17 RTCAPBEN: RTCAPB enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with RTCAPBENS, and cleared with
RTCAPBENC. This bit is set and reset by software.
0: RTCAPB disabled (default after reset)
1: RTCAPB enabled
Bit 16 RTCEN: RTC enable
This bit is write-protected by the pwr_lock_backup_n signal. It is security-protected by a SEC
signal from RIFSC, the PERSEC bit, a PRIV signal from RIFSC, or the PERPRIV bit. This bit
can be set with RTCENS, and cleared with RTCENC.
0: RTC disabled (default after reset)
1: RTC enabled
Bit 15 VREFBUFEN: VREFBUF enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with VREFBUFENS, and cleared with
VREFBUFENC. This bit is set and reset by software.
0: VREFBUF disabled (default after reset)
1: VREFBUF enabled
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 LPTIM5EN: LPTIM5 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with LPTIM5ENS, and cleared with
LPTIM5ENC. This bit is set and reset by software.
0: LPTIM5 disabled (default after reset)
1: LPTIM5 enabled
Bit 11 LPTIM4EN: LPTIM4 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with LPTIM4ENS, and cleared with
LPTIM4ENC. This bit is set and reset by software.
0: LPTIM4 disabled (default after reset)
1: LPTIM4 enabled
Bit 10 LPTIM3EN: LPTIM3 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with LPTIM3ENS, and cleared with
LPTIM3ENC. This bit is set and reset by software.
0: LPTIM3 disabled (default after reset)
1: LPTIM3 enabled
Bit 9 LPTIM2EN: LPTIM2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with LPTIM2ENS, and cleared with
LPTIM2ENC. This bit is set and reset by software.
0: LPTIM2 disabled (default after reset)
1: LPTIM2 enabled
Bit 8 Reserved, must be kept at reset value.

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Bit 7 I2C4EN: I2C4 enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with I2C4ENS, and cleared with I2C4ENC.
This bit is set and reset by software.
0: I2C4 disabled (default after reset)
1: I2C4 enabled
Bit 6 Reserved, must be kept at reset value.
Bit 5 SPI6EN: SPI6 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SPI6ENS, and cleared with SPI6ENC.
This bit is set and reset by software.
0: SPI6 disabled (default after reset)
1: SPI6 enabled
Bit 4 Reserved, must be kept at reset value.
Bit 3 LPUART1EN: LPUART1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with LPUART1ENS, and cleared with
LPUART1ENC. This bit is set and reset by software.
0: LPUART1 disabled (default after reset)
1: LPUART1 enabled
Bit 2 HDPEN: HDP enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with HDPENS, and cleared with HDPENC.
This bit is set and reset by software.
0: HDP disabled (default after reset)
1: HDP enabled
Bits 1:0 Reserved, must be kept at reset value.

14.10.89 RCC APB4H enable register (RCC_APB4HENR)

Address offset: 0x278
Reset value: 0x0000 0002
This register is used to enable the APB4H in Run and Sleep modes (in Sleep mode, each bit
of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSECE SYSCF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DTSEN
N GEN
rw rw rw

Bits 31:3 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

Bit 2 DTSEN: DTS enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with DTSENS, and cleared with DTSENC.
This bit is set and reset by software.
0: DTS disabled (default after reset)
1: DTS enabled
Bit 1 BSECEN: BSEC enable
This bit is always security-protected. It can be set with BSECENS, and cleared with
BSECENC. This bit is set and reset by software.
0: BSEC disabled
1: BSEC enabled (default after reset)
Bit 0 SYSCFGEN: SYSCFG enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. IT can be set with SYSCFGENS, and cleared with
SYSCFGENC. This bit is set and reset by software.
0: SYSCFG disabled (default after reset)
1: SYSCFG enabled

14.10.90 RCC APB5 enable register (RCC_APB5ENR)

Address offset: 0x27C
Reset value: 0x0000 0000
This register is used to enable the APB5 in boh Run and Sleep modes (in Sleep mode, each
bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VENCE GFXTI DCMIP LTDCE
Res. Res. Res. Res. Res. Res. Res. Res. Res. CSIEN Res. Res.
N MEN PEN N
rw rw rw rw rw

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 CSIEN: CSI enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with CSIENS, and cleared with CSIENC. This
bit is set and reset by software.
0: CSI disabled (default after reset)
1: CSI enabled
Bit 5 VENCEN: VENC enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with VENCENS, and cleared with VENCENC.
This bit is set and reset by software.
0: VENC disabled (default after reset)
1: VENC enabled

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Bit 4 GFXTIMEN: GFXTIM enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GFXTIMENS, and cleared with
GFXTIMENC. This bit is set and reset by software.
0: GFXTIM disabled (default after reset)
1: GFXTIM enabled
Bit 3 Reserved, must be kept at reset value.
Bit 2 DCMIPPEN: DCMIPP enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with DCMIPPENS, and cleared with
DCMIPPENC. This bit is set and reset by software.
0: DCMIPP disabled (default after reset)
1: DCMIPP enabled
Bit 1 LTDCEN: LTDC enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with LTDCENS, and cleared with LTDCENC.
This bit is set and reset by software.
0: LTDC disabled (default after reset)
1: LTDC enabled
Bit 0 Reserved, must be kept at reset value.

14.10.91 RCC embedded buses sleep enable register (RCC_BUSLPENR)

Address offset: 0x284
Reset value: 0x0000 0003
This register is used to enable the embedded buses in Sleep mode (each bit in this register
is AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACLKN ACLKN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
CLPEN LPEN
rw rw

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 ACLKNCLPEN: ACLKNC enable
This bit is security-protected by ACLKNCSEC or ACLKNCPRIV, and is publicly readable if
ACLKNCPUB = 1. It can be set with ACLKNCLPENS, and cleared with ACLKNCLPENC.
This bit is set and reset by software.
0: ACLKNC disabled in Sleep mode
1: ACLKNC enabled in Sleep mode (default after reset)

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RM0486 Reset and clock control (RCC)

Bit 0 ACLKNLPEN: ACLKN enable

This bit is security-protected by ACLKNSEC or ACLKNPRIV, and is publicly readable if
ACLKNPUB = 1. It can be set with ACLKNLPENS, and cleared with ACLKNLPENC. This bit
is set and reset by software.
0: ACLKN disabled in Sleep mode
1: ACLKN enabled in Sleep mode (default after reset)

14.10.92 RCC miscellaneous configurations sleep enable register

(RCC_MISCLPENR)
Address offset: 0x288
Reset value: 0x0000 0000
This register is used to enable the miscellaneous configurations in Sleep mode (each bit of
this register is AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage
domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XSPIP
PERLP HYCO DBGLP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN MPLPE EN
N
rw rw rw

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 PERLPEN: PER enable
This bit is security-protected by PERSEC or PERPRIV. It can be set with PERLPENS, and
cleared with PERLPENC. This bit is set and reset by software.
0: PER disabled in Sleep mode (default after reset)
1: PER enabled in Sleep mode
Bits 5:4 Reserved, must be kept at reset value.
Bit 3 XSPIPHYCOMPLPEN: XSPIPHYCOMP enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with XSPIPHYCOMPLPENS, and cleared with
XSPIPHYCOMPLPENC. This bit is set and reset by software.
0: XSPIPHYCOMP disabled in Sleep mode (default after reset)
1: XSPIPHYCOMP enabled in Sleep mode
Bits 2:1 Reserved, must be kept at reset value.
Bit 0 DBGLPEN: DBG enable
This bit is always security-protected. It can be set with DBGLPENS, and cleared with
DBGLPENC. This bit is set and reset by software.
0: DBG disabled in Sleep mode (default after reset)
1: DBG enabled in Sleep mode

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14.10.93 RCC embedded memories sleep enable register

(RCC_MEMLPENR)
Address offset: 0x28C
Reset value: 0x0000 0000
This register is used to enable the embedded memories in Sleep mode (each bit of this
register is AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage
domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOT VENCR CACHE FLEXR AXISR AXISR BKPSR AHBSR AHBSR AXISR AXISR AXISR AXISR
Res. Res. Res. ROML AMLPE AXIRA AMLPE AM2LP AM1LP AMLPE AM2LP AM1LP AM6LP AM5LP AM4LP AM3LP
PEN N MLPEN N EN EN N EN EN EN EN EN EN
rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 BOOTROMLPEN: BootROM enable
This bit is always security-protected. It can be set with BOOTROMLPENS, and cleared with
BOOTROMLPENC. This bit is set and reset by software.
0: BootROM disabled in Sleep mode (default after reset)
1: BootROM enabled in Sleep mode
Bit 11 VENCRAMLPEN: VENCRAM enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if VENCRAMPUB = 1. It can be set with VENCRAMLPENS, and cleared with
VENCRAMLPENC. This bit is set and reset by software.
0: VENCRAM disabled in Sleep mode (default after reset)
1: VENCRAM enabled in Sleep mode
Bit 10 CACHEAXIRAMLPEN: CACHEAXIRAM enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if CACHEAXIRAMPUB = 1. It can be set with CACHEAXIRAMLPENS and cleared with
CACHEAXIRAMLPENC. This bit is set and reset by software.
0: CACHEAXIRAM disabled in Sleep mode (default after reset)
1: CACHEAXIRAM enabled in Sleep mode
Bit 9 FLEXRAMLPEN: FLEXRAM enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if FLEXRAMPUB = 1. It can be set with FLEXRAMLPENS, and cleared with
FLEXRAMLPENC. This bit is set and reset by software.
0: FLEXRAM disabled in Sleep mode (default after reset)
1: FLEXRAM enabled in Sleep mode
Bit 8 AXISRAM2LPEN: AXISRAM2 enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AXISRAM2PUB = 1. It can be set with AXISRAM2LPENS, and cleared with
[Link] bit is set and reset by software.
0: AXISRAM2 disabled in Sleep mode (default after reset)
1: AXISRAM2 enabled in Sleep mode

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RM0486 Reset and clock control (RCC)

Bit 7 AXISRAM1LPEN: AXISRAM1 enable

This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AXISRAM1PUB = 1. It can be set with AXISRAM1LPENS, and cleared with
[Link] bit is set and reset by software.
0: AXISRAM1 disabled in Sleep mode (default after reset)
1: AXISRAM1 enabled in Sleep mode
Bit 6 BKPSRAMLPEN: BKPSRAM enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if BKPSRAMPUB = 1. It can be set with BKPSRAMLPENS, and cleared with
BKPSRAMLPENC. This bit is set and reset by software.
0: BKPSRAM disabled in Sleep mode (default after reset)
1: BKPSRAM enabled in Sleep mode
Bit 5 AHBSRAM2LPEN: AHBSRAM2 enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AHBSRAM2PUB = 1. It can be set with AHBSRAM2LPENS, and cleared with
AHBSRAM2LPENC. This bit is set and reset by software.
0: AHBSRAM2 disabled in Sleep mode (default after reset)
1: AHBSRAM2 enabled in Sleep mode
Bit 4 AHBSRAM1LPEN: AHBSRAM1 enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AHBSRAM1PUB = 1. It can be set with AHBSRAM1LPENS, and cleared with
AHBSRAM1LPENC. This bit is set and reset by software.
0: AHBSRAM1 disabled in Sleep mode (default after reset)
1: AHBSRAM1 enabled in Sleep mode
Bit 3 AXISRAM6LPEN: AXISRAM6 enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AXISRAM6PUB = 1. It can be set with AXISRAM6LPENS, and cleared with
AXISRAM6LPENC. This bit is set and reset by software.
0: AXISRAM6 disabled in Sleep mode (default after reset)
1: AXISRAM6 enabled in Sleep mode
Bit 2 AXISRAM5LPEN: AXISRAM5 enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AXISRAM5PUB = 1. It can be set with AXISRAM5LPENS, and cleared with
AXISRAM5LPENC. This bit is set and reset by software.
0: AXISRAM5 disabled in Sleep mode (default after reset)
1: AXISRAM5 enabled in Sleep mode
Bit 1 AXISRAM4LPEN: AXISRAM4 enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AXISRAM4PUB = 1. It can be set with AXISRAM4LPENS, and cleared with
AXISRAM4LPENC. This bit is set and reset by software.
0: AXISRAM4 disabled in Sleep mode (default after reset)
1: AXISRAM4 enabled in Sleep mode
Bit 0 AXISRAM3LPEN: AXISRAM3 enable
This bit is security-protected by a SEC or a PRIV signal from RIFSC, and is publicly readable
if AXISRAM3PUB = 1. It can be set with AXISRAM3LPENS, and cleared with
AXISRAM3LPENC. This bit is set and reset by software.
0: AXISRAM3 disabled in Sleep mode (default after reset)
1: AXISRAM3 enabled in Sleep mode

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14.10.94 RCC AHB1 sleep enable register (RCC_AHB1LPENR)

Address offset: 0x290
Reset value: 0x0000 0000
This register is used to enable the AHB1 in Sleep mode (each bit in this register is AND-ed
with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPDM
ADC12
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. A1LPE Res. Res. Res. Res.
LPEN
N
rw rw

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 ADC12LPEN: ADC12 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with ADC12LPENS, and cleared with
ADC12LPENC. This bit is set and reset by software.
0: ADC12 disabled in Sleep mode (default after reset)
1: ADC12 enabled in Sleep mode
Bit 4 GPDMA1LPEN: GPDMA1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPDMA1LPENS, and cleared with
GPDMA1LPENC. This bit is set and reset by software.
0: GPDMA1 disabled in Sleep mode (default after reset)
1: GPDMA1 enabled in Sleep mode
Bits 3:0 Reserved, must be kept at reset value.

14.10.95 RCC AHB2 sleep enable register (RCC_AHB2LPENR)

Address offset: 0x294
Reset value: 0x0000 0000
This register is used to enable the AHB2 in Sleep mode (each bit in this register is AND-ed
with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADF1 MDF1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LPEN LPEN
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAMCFG
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LPEN
rw

Bits 31:18 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

Bit 17 ADF1LPEN: ADF1 enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with ADF1LPENS, and cleared with
ADF1LPENC. This bit is set and reset by software.
0: ADF1 disabled in Sleep mode (default after reset)
1: ADF1 enabled in Sleep mode
Bit 16 MDF1LPEN: MDF1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with MDF1LPENS, and cleared with
MDF1LPENC. This bit is set and reset by software.
0: MDF1 disabled in Sleep mode (default after reset)
1: MDF1 enabled in Sleep mode
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 RAMCFGLPEN: RAMCFG enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with RAMCFGLPENS, and cleared with
RAMCFGLPENC. This bit is set and reset by software.
0: RAMCFG disabled in Sleep mode (default after reset)
1: RAMCFG enabled in Sleep mode
Bits 11:0 Reserved, must be kept at reset value.

14.10.96 RCC AHB3 sleep enable register (RCC_AHB3LPENR)

Address offset: 0x298
Reset value: 0x0000 0400
This register is used to enable the AHB3 in Sleep mode (each bit of this register is AND-ed
with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RISAFL IACLP RIFSC PKALP SAESL CRYPL HASHL RNGLP
Res. Res. Res. Res. Res. Res. Res. Res.
PEN EN LPEN EN PEN PEN PEN EN
rw rw rw rw rw rw rw rw

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 RISAFLPEN: RISAF enable
This bit is always security-protected. It can be set with RISAFLPENS, and cleared with
RISAFLPENC. This bit is set and reset by software.
0: RISAF disabled in Sleep mode (default after reset)
1: RISAF enabled in Sleep mode
Bits 13:11 Reserved, must be kept at reset value.
Bit 10 IACLPEN: IAC enable
This bit is always security-protected. It can be set with IACLPENS, and cleared with
IACLPENC. This bit is set and reset by software.
0: IAC disabled in Sleep mode
1: IAC enabled in Sleep mode (default after reset)

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Bit 9 RIFSCLPEN: RIFSC enable

This bit is always security-protected. It can be set with RIFSCLPENS, and cleared with
RIFSCLPENC. This bit is set and reset by software.
0: RIFSC disabled in Sleep mode (default after reset)
1: RIFSC enabled in Sleep mode
Bit 8 PKALPEN: PKA enable
This bit is security-protected by SYSSEC or SYSPRIV. It can be set with PKALPENS, and
cleared with PKALPENC. This bit is set and reset by software.
0: PKA disabled in Sleep mode (default after reset)
1: PKA enabled in Sleep mode
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 SAESLPEN: SAES enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SAESLPENS, and cleared with
SAESLPENC. This bit is set and reset by software.
0: SAES disabled in Sleep mode (default after reset)
1: SAES enabled in Sleep mode
Bit 3 Reserved, must be kept at reset value.
Bit 2 CRYPLPEN: CRYP enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with CRYPLPENS, and cleared with
CRYPLPENC. This bit is set and reset by software.
0: CRYP disabled in Sleep mode (default after reset)
1: CRYP enabled in Sleep mode
Bit 1 HASHLPEN: HASH enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with HASHLPENS, and cleared with
HASHLPENC. This bit is set and reset by software.
0: HASH disabled in Sleep mode (default after reset)
1: HASH enabled in Sleep mode
Bit 0 RNGLPEN: RNG enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with RNGLPENS, and cleared with
RNGLPENC. This bit is set and reset by software.
0: RNG disabled in Sleep mode (default after reset)
1: RNG enabled in Sleep mode

14.10.97 RCC AHB4 sleep enable register (RCC_AHB4LPENR)

Address offset: 0x29C
Reset value: 0x0004 0000
This register is used to enable the AHB4 in Sleep mode (each bit of this register is AND-ed
with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

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RM0486 Reset and clock control (RCC)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCLP PWRL GPIOQ
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN PEN LPEN
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOP GPIOO GPION GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Res. Res. Res. Res. Res.
LPEN LPEN LPEN LPEN LPEN LPEN LPEN LPEN LPEN LPEN LPEN
rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 CRCLPEN: CRC enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with CRCLPENS, and cleared with
CRCLPENC. This bit is set and reset by software.
0: CRC disabled in Sleep mode (default after reset)
1: CRC enabled in Sleep mode
Bit 18 PWRLPEN: PWR enable
This bit is always security-protected. It can be set with PWRLPENS, and cleared with
[Link] bit is set and reset by software.
0: PWR disabled in Sleep mode
1: PWR enabled in Sleep mode (default after reset)
Bit 17 Reserved, must be kept at reset value.
Bit 16 GPIOQLPEN: GPIO Q enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOQLPENS, and cleared with
GPIOQLPENC. This bit is set and reset by software.
0: GPIO Q disabled in Sleep mode (default after reset)
1: GPIO Q enabled in Sleep mode
Bit 15 GPIOPLPEN: GPIO P enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOPLPENS, and cleared with
GPIOPLPENC. This bit is set and reset by software.
0: GPIO P disabled in Sleep mode (default after reset)
1: GPIO P enabled in Sleep mode
Bit 14 GPIOOLPEN: GPIO O enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOOLPENS, and cleared with
GPIOOLPENC. This bit is set and reset by software.
0: GPIO O disabled in Sleep mode (default after reset)/
1: GPIO O enabled in Sleep mode
Bit 13 GPIONLPEN: GPIO N enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIONLPENS, and cleared with
GPIONLPENC. This bit is set and reset by software.
0: GPIO N disabled in Sleep mode (default after reset)
1: GPIO N enabled in Sleep mode
Bits 12:8 Reserved, must be kept at reset value.

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Bit 7 GPIOHLPEN: GPIO H enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOHLPENS, and cleared with
GPIOHLPENC. This bit is set and reset by software.
0: GPIO H disabled in Sleep mode (default after reset)
1: GPIO H enabled in Sleep mode
Bit 6 GPIOGLPEN: GPIO G enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOGLPENS, and cleared with
GPIOGLPENC. This bit is set and reset by software.
0: GPIO G disabled in Sleep mode (default after reset)
1: GPIO G enabled in Sleep mode
Bit 5 GPIOFLPEN: GPIO F enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOFLPENS, and cleared with
GPIOFLPENC. This bit is set and reset by software.
0: GPIO F disabled in Sleep mode (default after reset)
1: GPIO F enabled in Sleep mode
Bit 4 GPIOELPEN: GPIO E enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOELPENS, and cleared with
GPIOELPENC. This bit is set and reset by software.
0: GPIO E disabled in Sleep mode (default after reset)
1: GPIO E enabled in Sleep mode
Bit 3 GPIODLPEN: GPIO D enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with GPIODLPENS, and cleared with
GPIODLPENC. This bit is set and reset by software.
0: GPIO D disabled in Sleep mode (default after reset)
1: GPIO D enabled in Sleep mode
Bit 2 GPIOCLPEN: GPIO C enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOCLPENS, and cleared with
GPIOCLPENC. This bit is set and reset by software.
0: GPIO C disabled in Sleep mode (default after reset)
1: GPIO C enabled in Sleep mode
Bit 1 GPIOBLPEN: GPIO B enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOBLPENS, and cleared with
GPIOBLPENC. This bit is set and reset by software.
0: GPIO B disabled in Sleep mode (default after reset)
1: GPIO B enabled in Sleep mode
Bit 0 GPIOALPEN: GPIO A enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GPIOALPENS, and cleared with
GPIOALPENC. This bit is set and reset by software.
0: GPIO A disabled in Sleep mode (default after reset)
1: GPIO A enabled in Sleep mode

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RM0486 Reset and clock control (RCC)

14.10.98 RCC AHB5 sleep enable register (RCC_AHB5LPENR)

Address offset: 0x2A0
Reset value: 0x0000 0000
This register is used to enable the AHB5 in Sleep mode (each bit of this register is AND-ed
with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CACHE OTGP OTGP ETH1M GFXM
NPULP OTG2L OTG1L ETH1L ETH1R ETH1T GPU2D MCE4L XSPI3L MCE3L
AXILPE HY2LP HY1LP ACLPE Res. MULPE
EN PEN PEN PEN XLPEN XLPEN LPEN PEN PEN PEN
N EN EN N N
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMM SDMM HPDM
MCE2L MCE1L XSPIM XSPI2L PSSILP XSPI1L FMCLP JPEGL DMA2D
Res. Res. Res. C1LPE C2LPE Res. A1LPE
PEN PEN LPEN PEN EN PEN EN PEN LPEN
N N N
rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 NPULPEN: NPU enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with NPULPENS, and cleared with
NPULPENC. This bit is set and reset by software.
0: NPU disabled in Sleep mode (default after reset)
1: NPU enabled in Sleep mode
Bit 30 CACHEAXILPEN: CACHEAXI enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with CACHEAXILPENS, and cleared with
CACHEAXILPENC. This bit is set and reset by software.
0: CACHEAXI disabled in Sleep mode (default after reset)
1: CACHEAXI enabled in Sleep mode
Bit 29 OTG2LPEN: OTG2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with OTG2LPENS, and cleared with
OTG2LPENC. This bit is set and reset by software.
0: OTG2 disabled in Sleep mode (default after reset)
1: OTG2 enabled in Sleep mode
Bit 28 OTGPHY2LPEN: OTGPHY2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with OTGPHY2LPENS, and cleared with
OTGPHY2LPENC. This bit is set and reset by software.
0: OTGPHY2 disabled in Sleep mode (default after reset)
1: OTGPHY2 enabled in Sleep mode
Bit 27 OTGPHY1LPEN: OTGPHY1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with OTGPHY1LPENS, and cleared with
OTGPHY1LPENC. This bit is set and reset by software.
0: OTGPHY1 disabled in Sleep mode (default after reset)
1: OTGPHY1 enabled in Sleep mode

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Bit 26 OTG1LPEN: OTG1 enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with OTG1LPENS, and cleared with
OTG1LPENC. This bit is set and reset by software.
0: OTG1 disabled in Sleep mode (default after reset)
1: OTG1 enabled in Sleep mode
Bit 25 ETH1LPEN: ETH1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with ETH1LPENS, and cleared with
ETH1LPENC. This bit is set and reset by software.
0: ETH1 disabled in Sleep mode (default after reset)
1: ETH1 enabled in Sleep mode
Bit 24 ETH1RXLPEN: ETH1RX enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with ETH1RXLPENS, and cleared with
ETH1RXLPENC. This bit is set and reset by software.
0: ETH1RX disabled in Sleep mode (default after reset)
1: ETH1RX enabled in Sleep mode
Bit 23 ETH1TXLPEN: ETH1TX enable
This bit is security-protected by a SEC signal from RIFSC, th,e PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with ETH1TXLPENS and cleared with
ETH1TXLPENC. This bit is set and reset by software.
0: ETH1TX disabled in Sleep mode (default after reset)
1: ETH1TX enabled in Sleep mode
Bit 22 ETH1MACLPEN: ETH1MAC enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with ETH1MACLPENS, and cleared with
ETH1MACLPENC. This bit is set and reset by software.
0: ETH1MAC disabled in Sleep mode (default after reset)
1: ETH1MAC enabled in Sleep mode
Bit 21 Reserved, must be kept at reset value.
Bit 20 GPU2DLPEN: GPU2D enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with GPU2DLPENS, and cleared with
GPU2DLPENC. This bit is set and reset by software.
0: GPU2D disabled in Sleep mode (default after reset)
1: GPU2D enabled in Sleep mode
Bit 19 GFXMMULPEN: GFXMMU enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with GFXMMULPENS, and cleared with
GFXMMULPENC. This bit is set and reset by software.
0: GFXMMU disabled in Sleep mode (default after reset)
1: GFXMMU enabled in Sleep mode
Bit 18 MCE4LPEN: MCE4 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with MCE4LPENS, and cleared with
MCE4LPENC. This bit is set and reset by software.
0: MCE4 disabled in Sleep mode (default after reset)
1: MCE4 enabled in Sleep mode

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RM0486 Reset and clock control (RCC)

Bit 17 XSPI3LPEN: XSPI3 enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with XSPI3LPENS, and cleared with
XSPI3LPENC. This bit is set and reset by software.
0: XSPI3 disabled in Sleep mode (default after reset)
1: XSPI3 enabled in Sleep mode
Bit 16 MCE3LPEN: MCE3 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with MCE3LPENS, and cleared with
MCE3LPENC. This bit is set and reset by software.
0: MCE3 disabled in Sleep mode (default after reset)
1: MCE3 enabled in Sleep mode
Bit 15 MCE2LPEN: MCE2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with MCE2LPENS, and cleared with
MCE2LPENC. This bit is set and reset by software.
0: MCE2 disabled in Sleep mode (default after reset)
1: MCE2 enabled in Sleep mode
Bit 14 MCE1LPEN: MCE1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with MCE1LPENS, and cleared with
MCE1LPENC. This bit is set and reset by software.
0: MCE1 disabled in Sleep mode (default after reset)
1: MCE1 enabled in Sleep mode
Bit 13 XSPIMLPEN: XSPIM enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with XSPIMLPENS, and cleared with
[Link] bit is set and reset by software.
0: XSPIM disabled in Sleep mode (default after reset)
1: XSPIM enabled in sleep mode
Bit 12 XSPI2LPEN: XSPI2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with XSPI2LPENS, and cleared with
XSPI2LPENC. This bit is set and reset by software.
0: XSPI2 disabled in Sleep mode (default after reset)
1: XSPI2 enabled in Sleep mode
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 SDMMC1LPEN: SDMMC1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with SDMMC1LPENS, and cleared with
SDMMC1LPENC. This bit is set and reset by software.
0: SDMMC1 disabled in Sleep mode (default after reset)
1: SDMMC1 enabled in Sleep mode
Bit 7 SDMMC2LPEN: SDMMC2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SDMMC2LPENS, and cleared with
SDMMC2LPENC. This bit is set and reset by software.
0: SDMMC2 disabled in Sleep mode (default after reset)
1: SDMMC2 enabled in Sleep mode

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Bit 6 PSSILPEN: PSSI enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with PSSILPENS, and cleared with
PSSILPENC. This bit is set and reset by software.
0: PSSI disabled in Sleep mode (default after reset)
1: PSSI enabled in Sleep mode
Bit 5 XSPI1LPEN: XSPI1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with XSPI1LPENS, and cleared with
XSPI1LPENC. This bit is set and reset by software.
0: XSPI1 disabled in Sleep mode (default after reset)
1: XSPI1 enabled in Sleep mode
Bit 4 FMCLPEN: FMC enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with FMCLPENS, and cleared with
FMCLPENC. This bit is set and reset by software.
0: FMC disabled in Sleep mode (default after reset)
1: FMC enabled in Sleep mode
Bit 3 JPEGLPEN: JPEG enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with JPEGLPENS, and cleared with
JPEGLPENC. This bit is set and reset by software.
0: JPEG disabled in Sleep mode (default after reset)
1: JPEG enabled in Sleep mode
Bit 2 Reserved, must be kept at reset value.
Bit 1 DMA2DLPEN: DMA2D enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with DMA2DLPENS, and cleared with
DMA2DLPENC. This bit is set and reset by software.
0: DMA2D disabled in Sleep mode (default after reset)
1: DMA2D enabled in Sleep mode
Bit 0 HPDMA1LPEN: HPDMA1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with HPDMA1LPENS, and cleared with
HPDMA1LPENC. This bit is set and reset by software.
0: HPDMA1 disabled in Sleep mode (default after reset)
1: HPDMA1 enabled in Sleep mode

14.10.99 RCC APB1L sleep enable register (RCC_APB1LLPENR)

Address offset: 0x2A4
Reset value: 0x0000 0000
This register is used to enable the APB1L in Sleep mode (each bit of this register is AND-ed
with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

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RM0486 Reset and clock control (RCC)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPDIF
UART8 UART7 I3C2LP I3C1LP I2C3LP I2C2LP I2C1LP UART5 UART4 USART USART
Res. Res. Res. Res. RX1LP
LPEN LPEN EN EN EN EN EN LPEN LPEN 3LPEN 2LPEN
EN
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3LP SPI2LP TIM11L TIM10L WWDG LPTIM1 TIM14L TIM13L TIM12L TIM7LP TIM6LP TIM5LP TIM4LP TIM3LP TIM2LP
Res.
EN EN PEN PEN LPEN LPEN PEN PEN PEN EN EN EN EN EN EN
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 UART8LPEN: UART8 enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with UART8LPENS, and cleared with
UART8LPENC. This bit is set and reset by software.
0: UART8 disabled in Sleep mode (default after reset)
1: UART8 enabled in Sleep mode
Bit 30 UART7LPEN: UART7 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with UART7LPENS, and cleared with
UART7LPENC. This bit is set and reset by software.
0: UART7 disabled in Sleep mode (default after reset)
1: UART7 enabled in Sleep mode
Bits 29:26 Reserved, must be kept at reset value.
Bit 25 I3C2LPEN: I3C2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with I3C2LPENS, and cleared with
I3C2LPENC. This bit is set and reset by software.
0: I3C2 disabled in Sleep mode (default after reset)
1: I3C2 enabled in Sleep mode
Bit 24 I3C1LPEN: I3C1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with I3C1LPENS, and cleared with
I3C1LPENC. This bit is set and reset by software.
0: I3C1 disabled in Sleep mode (default after reset)
1: I3C1 enabled in Sleep mode
Bit 23 I2C3LPEN: I2C3 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with I2C3LPENS, and cleared with
I2C3LPENC. This bit is set and reset by software.
0: I2C3 disabled in Sleep mode (default after reset)
1: I2C3 enabled in Sleep mode
Bit 22 I2C2LPEN: I2C2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with I2C2LPENS, and cleared with
I2C2LPENC. This bit is set and reset by software.
0: I2C2 disabled in Sleep mode (default after reset)
1: I2C2 enabled in Sleep mode

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Bit 21 I2C1LPEN: I2C1 enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with I2C1LPENS, and cleared with
I2C1LPENC. This bit is set and reset by software.
0: I2C1 disabled in Sleep mode (default after reset)
1: I2C1 enabled in Sleep mode
Bit 20 UART5LPEN: UART5 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with UART5LPENS, and cleared with
UART5LPENC. This bit is set and reset by software.
0: UART5 disabled in Sleep mode (default after reset)
1: UART5 enabled in Sleep mode
Bit 19 UART4LPEN: UART4 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with UART4LPENS, and cleared with
UART4LPENC. This bit is set and reset by software.
0: UART4 disabled in Sleep mode (default after reset)
1: UART4 enabled in Sleep mode
Bit 18 USART3LPEN: USART3 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with USART3LPENS, and cleared with
USART3LPENC. This bit is set and reset by software.
0: USART3 disabled in Sleep mode (default after reset)
1: USART3 enabled in Sleep mode
Bit 17 USART2LPEN: USART2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with USART2LPENS, and cleared with
USART2LPENC. This bit is set and reset by software.
0: USART2 disabled in Sleep mode (default after reset)
1: USART2 enabled in Sleep mode
Bit 16 SPDIFRX1LPEN: SPDIFRX1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SPDIFRX1LPENS, and cleared with
SPDIFRX1LPENC. This bit is set and reset by software.
0: SPDIFRX1 disabled in Sleep mode (default after reset)
1: SPDIFRX1 enabled in Sleep mode
Bit 15 SPI3LPEN: SPI3 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SPI3LPENS, and cleared with
SPI3LPENC. This bit is set and reset by software.
0: SPI3 disabled in Sleep mode (default after reset)
1: SPI3 enabled in Sleep mode
Bit 14 SPI2LPEN: SPI2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SPI2LPENS, and cleared with
SPI2LPENC. This bit is set and reset by software.
0: SPI2 disabled in Sleep mode (default after reset)
1: SPI2 enabled in Sleep mode

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RM0486 Reset and clock control (RCC)

Bit 13 TIM11LPEN: TIM11 enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM11LPENS, and cleared with
TIM11LPENC. This bit is set and reset by software.
0: TIM11 disabled in Sleep mode (default after reset)
1: TIM11 enabled in Sleep mode
Bit 12 TIM10LPEN: TIM10 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM10LPENS, and cleared with
TIM10LPENC. This bit is set and reset by software.
0: TIM10 disabled in Sleep mode (default after reset)
1: TIM10 enabled in Sleep mode
Bit 11 WWDGLPEN: WWDG enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with WWDGLPENS, and cleared with
WWDGLPENC. This bit is set and reset by software.
0: WWDG disabled in Sleep mode (default after reset)
1: WWDG enabled in Sleep mode
Bit 10 Reserved, must be kept at reset value.
Bit 9 LPTIM1LPEN: LPTIM1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with LPTIM1LPENS, and cleared with
LPTIM1LPENC. This bit is set and reset by software.
0: LPTIM1 disabled in Sleep mode (default after reset)
1: LPTIM1 enabled in Sleep mode
Bit 8 TIM14LPEN: TIM14 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM14LPENS, and cleared with
TIM14LPENC. This bit is set and reset by software.
0: TIM14 disabled in Sleep mode (default after reset)
1: TIM14 enabled in Sleep mode
Bit 7 TIM13LPEN: TIM13 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM13LPEN,S and cleared with
TIM13LPENC. This bit is set and reset by software.
0: TIM13 disabled in Sleep mode (default after reset)
1: TIM13 enabled in Sleep mode
Bit 6 TIM12LPEN: TIM12 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM12LPENS, and cleared with
TIM12LPENC. This bit is set and reset by software.
0: TIM12 disabled in Sleep mode (default after reset)
1: TIM12 enabled in Sleep mode
Bit 5 TIM7LPEN: TIM7 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM7LPENS, and cleared with
TIM7LPENC. This bit is set and reset by software.
0: TIM7 disabled in Sleep mode (default after reset)
1: TIM7 enabled in Sleep mode

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Bit 4 TIM6LPEN: TIM6 enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM6LPENS, and cleared with
TIM6LPENC. This bit is set and reset by software.
0: TIM6 disabled in Sleep mode (default after reset)
1: TIM6 enabled in Sleep mode
Bit 3 TIM5LPEN: TIM5 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM5LPENS, and cleared with
TIM5LPENC. This bit is set and reset by software.
0: TIM5 disabled in Sleep mode (default after reset)
1: TIM5 enabled in Sleep mode
Bit 2 TIM4LPEN: TIM4 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM4LPENS, and cleared with
TIM4LPENC. This bit is set and reset by software.
0: TIM4 disabled in Sleep mode (default after reset)
1: TIM4 enabled in Sleep mode
Bit 1 TIM3LPEN: TIM3 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM3LPENS, and cleared with
TIM3LPENC. This bit is set and reset by software.
0: TIM3 disabled in Sleep mode (default after reset)
1: TIM3 enabled in Sleep mode
Bit 0 TIM2LPEN: TIM2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM2LPENS, and cleared with
TIM2LPENC. This bit is set and reset by software.
0: TIM2 disabled in Sleep mode (default after reset)
1: TIM2 enabled in Sleep mode

14.10.100 RCC APB1H sleep enable register (RCC_APB1HLPENR)

Address offset: 0x2A8
Reset value: 0x0000 0000
This register is used to enable the APB1H in Sleep mode (each bit of this register is AND-ed
with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN MDIOS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LPEN LPEN
rw rw

Bits 31:19 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

Bit 18 UCPD1LPEN: UCPD1 enable in Sleep mode

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with UCPD1LPENS, and cleared with
UCPD1LPENC. This bit is set and reset by software.
0: UCPD1 disabled in Sleep mode (default after reset)
1: UCPD1 enabled in Sleep mode
Bits 17:9 Reserved, must be kept at reset value.
Bit 8 FDCANLPEN: FDCAN enablein Sleep mode
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with FDCANLPENS, and cleared with
FDCANLPENC. This bit is set and reset by software.
0: FDCAN disabled in Sleep mode (default after reset)
1: FDCAN enabled in Sleep mode
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 MDIOSLPEN: MDIOS enable in Sleep mode
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with MDIOSLPENS, and cleared with
[Link] bit is set and reset by software.
0: MDIOS disabled in Sleep mode (default after reset)
1: MDIOS enabled in Sleep mode
Bits 4:0 Reserved, must be kept at reset value.

14.10.101 RCC APB2 sleep enable register (RCC_APB2LPENR)

Address offset: 0x2AC
Reset value: 0x0000 0000
This register is used to enable the APB2 in Sleep mode (each bit of this register is AND-ed
with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAI2LP SAI1LP SPI5LP TIM9LP TIM17L TIM16L TIM15L
Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN EN EN EN PEN PEN PEN
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART
TIM18L SPI4LP SPI1LP UART9 USART USART TIM8LP TIM1LP
Res. Res. Res. Res. Res. 10LPE Res. Res.
PEN EN EN LPEN 6LPEN 1LPEN EN EN
N
rw rw rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 SAI2LPEN: SAI2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with SAI2LPENS, and cleared with
SAI2LPENC. This bit is set and reset by software.
0: SAI2 disabled in Sleep mode (default after reset)
1: SAI2 enabled in Sleep mode

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Bit 21 SAI1LPEN: SAI1 enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SAI1LPENS, and cleared with
SAI1LPENC. This bit is set and reset by software.
0: SAI1 disabled in Sleep mode (default after reset)
1: SAI1 enabled in Sleep mode
Bit 20 SPI5LPEN: SPI5 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SPI5LPENS, and cleared with
SPI5LPENC. This bit is set and reset by software.
0: SPI5 disabled in Sleep mode (default after reset)
1: SPI5 enabled in Sleep mode
Bit 19 TIM9LPEN: TIM9 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM9LPENS, and cleared with
TIM9LPENC. This bit is set and reset by software.
0: TIM9 disabled in Sleep mode (default after reset)
1: TIM9 enabled in Sleep mode
Bit 18 TIM17LPEN: TIM17 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM17LPENS, and cleared with
TIM17LPENC. This bit is set and reset by software.
0: TIM17 disabled in Sleep mode (default after reset)
1: TIM17 enabled in Sleep mode
Bit 17 TIM16LPEN: TIM16 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM16LPENS, and cleared with
TIM16LPENC. This bit is set and reset by software.
0: TIM16 disabled in Sleep mode (default after reset)
1: TIM16 enabled in Sleep mode
Bit 16 TIM15LPEN: TIM15 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM15LPENS, and cleared with
TIM15LPENC. This bit is set and reset by software.
0: TIM15 disabled in Sleep mode (default after reset)
1: TIM15 enabled in Sleep mode
Bit 15 TIM18LPEN: TIM18 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM18LPENS, and cleared with
TIM18LPENC. This bit is set and reset by software.
0: TIM18 disabled in Sleep mode (default after reset)
1: TIM18 enabled in Sleep mode
Bit 14 Reserved, must be kept at reset value.
Bit 13 SPI4LPEN: SPI4 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SPI4LPENS, and cleared with
SPI4LPENC. This bit is set and reset by software.
0: SPI4 disabled in Sleep mode (default after reset)
1: SPI4 enabled in Sleep mode

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RM0486 Reset and clock control (RCC)

Bit 12 SPI1LPEN: SPI1 enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SPI1LPENS, and cleared with
SPI1LPENC. This bit is set and reset by software.
0: SPI1 disabled in Sleep mode (default after reset)
1: SPI1 enabled in Sleep mode
Bits 11:8 Reserved, must be kept at reset value.
Bit 7 USART10LPEN: USART10 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with USART10LPENS, and cleared with
USART10LPENC. This bit is set and reset by software.
0: USART10 disabled in Sleep mode (default after reset)
1: USART10 enabled in Sleep mode
Bit 6 UART9LPEN: UART9 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with UART9LPENS, and cleared with
UART9LPENC. This bit is set and reset by software.
0: UART9 disabled in Sleep mode (default after reset)
1: UART9 enabled in Sleep mode
Bit 5 USART6LPEN: USART6 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with USART6LPENS, and cleared with
USART6LPENC. This bit is set and reset by software.
0: USART6 disabled in Sleep mode (default after reset)
1: USART6 enabled in Sleep mode
Bit 4 USART1LPEN: USART1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with USART1LPENS, and cleared with
USART1LPENC. This bit is set and reset by software.
0: USART1 disabled in Sleep mode (default after reset)
1: USART1 enabled in Sleep mode
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8LPEN: TIM8 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM8LPENS, and cleared with
TIM8LPENC. This bit is set and reset by software.
0: TIM8 disabled in Sleep mode (default after reset)
1: TIM8 enabled in Sleep mode
Bit 0 TIM1LPEN: TIM1 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with TIM1LPENS, and cleared with
TIM1LPENC. This bit is set and reset by software.
0: TIM1 disabled in Sleep mode (default after reset)
1: TIM1 enabled in Sleep mode

14.10.102 RCC APB3 sleep enable register (RCC_APB3LPENR)

Address offset: 0x2B0
Reset value: 0x0000 0000

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This register is used to enable the APB3 in Sleep mode (each bit of this register is AND-ed
with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DFTLP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN
rw

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 DFTLPEN: DFT enable
This bit is security-protected by DFTSEC or DFTPRIV. It can be set with DFTLPENS, and
cleared with DFTLPENC. This bit is set and reset by software.
0: DFT disabled in Sleep mode (default after reset)
1: DFT enabled in Sleep mode
Bits 1:0 Reserved, must be kept at reset value.

14.10.103 RCC APB4L sleep enable register (RCC_APB4LLPENR)

Address offset: 0x2B4
Reset value: 0x0000 0000
This register is used to enable the APB4L in Sleep mode (each bit of this register is AND-ed
with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCAP RTCLP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
BLPEN EN
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFB LPUAR
LPTIM5 LPTIM4 LPTIM3 LPTIM2 I2C4LP SPI6LP HDPLP
UFLPE Res. Res. Res. Res. Res. T1LPE Res. Res.
LPEN LPEN LPEN LPEN EN EN EN
N N
rw rw rw rw rw rw rw rw rw

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 RTCAPBLPEN: RTCAPB enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with RTCAPBLPENS, and cleared with
RTCAPBLPENC. This bit is set and reset by software.
0: RTCAPB disabled in Sleep mode (default after reset)
1: RTCAPB enabled in Sleep mode
Bit 16 RTCLPEN: RTC enable
This bit is write-protected by the pwr_lock_backup_n signal. It is security-protected by a SEC
signal from RIFSC, the PERSEC bit, a PRIV signal from RIFSC, or the PERPRIV bit. This bit
can be set with RTCLPENS, and cleared with RTCLPENC.
0: RTC disabled in Sleep mode (default after reset)
1: RTC enabled in Sleep mode

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RM0486 Reset and clock control (RCC)

Bit 15 VREFBUFLPEN: VREFBUF enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with VREFBUFLPENS, and cleared with
[Link] bit is set and reset by software.
0: VREFBUF disabled in Sleep mode (default after reset)
1: VREFBUF enabled in Sleep mode
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 LPTIM5LPEN: LPTIM5 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with LPTIM5LPENS, and cleared with
LPTIM5LPENC. This bit is set and reset by software.
0: LPTIM5 disabled in Sleep mode (default after reset)
1: LPTIM5 enabled in Sleep mode
Bit 11 LPTIM4LPEN: LPTIM4 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with LPTIM4LPENS, and cleared with
LPTIM4LPENC. This bit is set and reset by software.
0: LPTIM4 disabled in Sleep mode (default after reset)
1: LPTIM4 enabled in Sleep mode
Bit 10 LPTIM3LPEN: LPTIM3 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with LPTIM3LPENS, and cleared with
LPTIM3LPENC. This bit is set and reset by software.
0: LPTIM3 disabled in Sleep mode (default after reset)
1: LPTIM3 enabled in Sleep mode
Bit 9 LPTIM2LPEN: LPTIM2 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with LPTIM2LPENS, and cleared with
LPTIM2LPENC. This bit is set and reset by software.
0: LPTIM2 disabled in Sleep mode (default after reset)
1: LPTIM2 enabled in Sleep mode
Bit 8 Reserved, must be kept at reset value.
Bit 7 I2C4LPEN: I2C4 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with I2C4LPENS, and cleared with
I2C4LPENC. This bit is set and reset by software.
0: I2C4 disabled in Sleep mode (default after reset)
1: I2C4 enabled in Sleep mode
Bit 6 Reserved, must be kept at reset value.
Bit 5 SPI6LPEN: SPI6 enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SPI6LPENS, and cleared with
SPI6LPENC. This bit is set and reset by software.
0: SPI6 disabled in Sleep mode (default after reset)
1: SPI6 enabled in Sleep mode
Bit 4 Reserved, must be kept at reset value.

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Bit 3 LPUART1LPEN: LPUART1 enable

This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with LPUART1LPENS, and cleared with
LPUART1LPENC. This bit is set and reset by software.
0: LPUART1 disabled in Sleep mode (default after reset)
1: LPUART1 enabled in Sleep mode
Bit 2 HDPLPEN: HDP enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with HDPLPENS, and cleared with
HDPLPENC. This bit is set and reset by software.
0: HDP disabled in Sleep mode (default after reset)
1: HDP enabled in Sleep mode
Bits 1:0 Reserved, must be kept at reset value.

14.10.104 RCC APB4H sleep enable register (RCC_APB4HLPENR)

Address offset: 0x2B8
Reset value: 0x0000 0002
This register is used to enable the APB4H in Sleep mode (each bit of this register is AND-ed
with the EN bit). It is reset by sys_rst, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTSLP BSECL SYSCF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN PEN GLPEN
rw rw rw

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 DTSLPEN: DTS enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. it can be set with DTSLPENS, and cleared with
DTSLPENC. This bit is set and reset by software.
0: DTS disabled in Sleep mode (default after reset)
1: DTS enabled in Sleep mode
Bit 1 BSECLPEN: BSEC enable
This bit is always security-protected. it can be set with BSECLPENS, and cleared with
BSECLPENC. This bit is set and reset by software.
0: BSEC disabled in Sleep mode
1: BSEC enabled in Sleep mode (default after reset)
Bit 0 SYSCFGLPEN: SYSCFG enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with SYSCFGLPENS, and cleared with
SYSCFGLPENC. This bit IS Set and reset by software.
0: SYSCFG disabled in Sleep mode (default after reset)
1: SYSCFG enabled in Sleep mode

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RM0486 Reset and clock control (RCC)

14.10.105 RCC APB5 sleep enable register (RCC_APB5LPENR)

Address offset: 0x2BC
Reset value: 0x0000 0000
This register is used to enable the APB5 in Sleep mode (each bit of this register is AND-ed
with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSILP VENCL GFXTI DCMIP LTDCL
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN PEN MLPEN PLPEN PEN
rw rw rw rw rw

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 CSILPEN: CSI enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with CSILPENS, and cleared with CSILPENC.
This bit is set and reset by software.
0: CSI disabled in Sleep mode (default after reset)
1: CSI enabled in Sleep mode
Bit 5 VENCLPEN: VENC enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with VENCLPENS, and cleared with
VENCLPENC. This bit is set and reset by software.
0: VENC disabled in Sleep mode (default after reset)
1: VENC enabled in Sleep mode
Bit 4 GFXTIMLPEN: GFXTIM enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with GFXTIMLPENS, and cleared with
GFXTIMLPENC. This bit is set and reset by software.
0: GFXTIM disabled in Sleep mode (default after reset)
1: GFXTIM enabled in Sleep mode
Bit 3 Reserved, must be kept at reset value.
Bit 2 DCMIPPLPEN: DCMIPP enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with DCMIPPLPENS, and cleared with
DCMIPPLPENC. This bit is set and reset by software.
0: DCMIPP disabled in Sleep mode (default after reset)
1: DCMIPP enabled in Sleep mode
Bit 1 LTDCLPEN: LTDC enable
This bit is security-protected by a SEC signal from RIFSC, the PERSEC bit, a PRIV signal
from RIFSC, or the PERPRIV bit. It can be set with LTDCLPENS, and cleared with
LTDCLPENC. This bit is set and reset by software.
0: LTDC disabled in Sleep mode (default after reset)
1: LTDC enabled in Sleep mode
Bit 0 Reserved, must be kept at reset value.

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14.10.106 RCC reset duration control register (RCC_RDCR)

Address offset: 0x44C
Reset value: 0x0600 0000
This register is used to control the minimum sys_rstn active duration. It is reset by
pwr_por_rstn, and is in the VRET voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. EADLY[3:0] Res. Res. Res. MRD[4:0]
rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:24 EADLY[3:0]: External access delay
The bit field is security-protected by the 1 bit. Set and reset by software.
Time to wait before the BOOTROM performs any external device access
0000: No extra delay added by the BOOTROM
0001: 100 μs
0010: 200 μs
0011: 500 μs
0100: 1 ms
0101: 2 ms
0110: 5 ms (default after reset)
0111: 10 ms
1000: 20 ms
1001: 50 ms
1010: 100 ms
1011: 200 ms
1100: 500 ms
1101: 1 s
1110: 2 s
1111: 5 s
Bits 23:21 Reserved, must be kept at reset value.
Bits 20:16 MRD[4:0]: Minimum reset duration
This bit is alway security-protected. It is set and reset by software. It defines the minimum
guaranteed duration of the NRST assertion. The LSI oscillator is automatically enabled when
needed by the RPCTL.
0x00: NRST duration is guaranteed by the pulse stretcher of the PAD. The RPCTL is
bypassed (default after reset).
0x01: The guaranteed NRST duration is about 1 ms (1 x 32 lsi_ck cycles).
0x02: The guaranteed NRST duration is about 2 ms (2 x 32 lsi_ck cycles).
{v}: guaranteed NRST duration is about {v} ms ({v} x 32 lsi_ck cycles).
Bits 15:0 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

14.10.107 RCC oscillator secure configuration register 0 (RCC_SECCFGR0)

Address offset: 0x780
Reset value: 0x0000 0000
This register is used to control the secure access rights to the configuration register of the
oscillators. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxSEC bit
defines the secure protection for the configuration registers of the oscillator: a write access
is denied if the access is nonsecure while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSE HSI MSI LSE LSI
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SEC SEC SEC SEC SEC
rw rw rw rw rw

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 HSESEC: Secure protection of HSE oscillator configuration bits
This bit is set and reset by secure privileged software only. it can be read by any software.
0: HSE configuration bits are accessible by nonsecure software only (default after reset).
1: HSE configuration bits are accessible by secure software only.
Bit 3 HSISEC: Secure protection of HSI oscillator configuration bits
This bit it set and reset by secure privileged software only. It can be read by any software.
0: HSI configuration bits are accessible by nonsecure software only (default after reset).
1: HSI configuration bits are accessible by secure software only.
Bit 2 MSISEC: Secure protection of MSI oscillator configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: MSI configuration bits are accessible by nonsecure software only (default after reset).
1: MSI configuration bits are accessible by secure software only.
Bit 1 LSESEC: Secure protection of LSE oscillator configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: LSE configuration bits are accessible by nonsecure software only (default after reset).
1: LSE configuration bits are accessible by secure software only.
Bit 0 LSISEC: Secure protection of LSI oscillator configuration bits.
This bit is set and reset by secure privileged software only. it can be read by any software.
0: LSI configuration bits are accessible by nonsecure software only (default after reset).
1: LSI configuration bits are accessible by secure software only.

14.10.108 RCC oscillator privilege configuration register 0

(RCC_PRIVCFGR0)
Address offset: 0x784
Reset value: 0x0000 0000
This register is used to control the privilege access rights to the configuration register of the
oscillators. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPRIV bit

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Reset and clock control (RCC) RM0486

defines the privileged protection for the configuration registers of the oscillator: a write
access is denied if the access is unprivileged while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSEPR HSIPRI MSIPRI LSEPR LSIPRI
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
IV V V IV V
rw rw rw rw rw

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 HSEPRIV: Privileged protection of HSE oscillator configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: HSE configuration bits are accessible by unprivileged software only (default after reset).
1: HSE configuration bits are accessible by privileged software only.
Bit 3 HSIPRIV: Privileged protection of HSI oscillator configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: HSI configuration bits are accessible by unprivileged software only (default after reset).
1: HSI configuration bits are accessible by privileged software only.
Bit 2 MSIPRIV: Privileged protection of MSI oscillator configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: MSI configuration bits are accessible by unprivileged software only (default after reset).
1: MSI configuration bits are accessible by privileged software only.
Bit 1 LSEPRIV: Privileged protection of LSE oscillator configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: LSE configuration bits are accessible by unprivileged software only (default after reset).
1: LSE configuration bits are accessible by privileged software only.
Bit 0 LSIPRIV: Privileged protection of LSI oscillator configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: LSI configuration bits are accessible by unprivileged software only (default after reset.)
1: LSI configuration bits are accessible by privileged software only.

14.10.109 RCC oscillator lock configuration register 0 (RCC_LOCKCFGR0)

Address offset: 0x788
Reset value: 0x0000 0000
This register is used to control the locked access rights to the configuration register of the
oscillators. It is reset by sys_rst, n and is in the VCORE voltage [Link] xxLOCK bit
defines the lock protection for the configuration registers of the oscillator: a write access is
denied if the access is unlocked while the respective bit is set.

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RM0486 Reset and clock control (RCC)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSE HSI MSI LSE LSI
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LOCK LOCK LOCK LOCK LOCK
w w w w w

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 HSELOCK: Locked protection of HSE oscillator configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: HSE configuration bits are accessible by unlocked software only (default after reset).
1: HSE configuration bits are accessible by locked software only.
Bit 3 HSILOCK: Locked protection of HSI oscillator configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: HSI configuration bits are accessible by unlocked software only (default after reset).
1: HSI configuration bits are accessible by locked software only.
Bit 2 MSILOCK: Locked protection of MSI oscillator configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: MSI configuration bits are accessible by unlocked software only (default after reset).
1: MSI configuration bits are accessible by locked software only.
Bit 1 LSELOCK: Locked protection of LSE oscillator configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: LSE configuration bits are accessible by unlocked software only (default after reset).
1: LSE configuration bits are accessible by locked software only.
Bit 0 LSILOCK: Locked protection of LSI oscillator configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: LSI configuration bits are accessible by unlocked software only (default after reset).
1: LSI configuration bits are accessible by locked software only.

14.10.110 RCC oscillator public configuration register 0 (RCC_PUBCFGR0)

Address offset: 0x78C
Reset value: 0x0000 0000
This register is used to control the public access rights to the configuration register of the
oscillators. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPUB bit
defines the public protection for the configuration registers of the oscillator: a write access is
denied if the access is non-public while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSE HSI MSI LSE LSI
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
PUB PUB PUB PUB PUB
rw rw rw rw rw

Bits 31:5 Reserved, must be kept at reset value.

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Bit 4 HSEPUB: Public protection of HSE oscillator configuration bits

This bit is set and reset by secure privileged software only. It can be read by any software.
0: HSE configuration bits are accessible by non-public software only (default after reset).
1: HSE configuration bits are accessible by public software only.
Bit 3 HSIPUB: Public protection of HSI oscillator configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: HSI configuration bits are accessible by non-public software only (default after reset).
1: HSI configuration bits are accessible by public software only.
Bit 2 MSIPUB: Public protection of MSI oscillator configuration bits
This bit is set and reset by secure privileged software only. it can be read by any software.
0: MSI configuration bits are accessible by non-public software only (default after reset).
1: MSI configuration bits are accessible by public software only.
Bit 1 LSEPUB: Public protection of LSE oscillator configuration bits.
This bit is set and reset by secure privileged software only. It can be read by any software.
0: LSE configuration bits are accessible by non-public software only (default after reset).
1: LSE configuration bits are accessible by public software only.
Bit 0 LSIPUB: Public protection of LSI oscillator configuration bits.
This bit is set and reset by secure privileged software only. It can be read by any software.
0: LSI configuration bits are accessible by non-public software only (default after reset).
1: LSI configuration bits are accessible by public software only.

14.10.111 RCC PLL secure configuration register 1 (RCC_SECCFGR1)

Address offset: 0x790
Reset value: 0x0000 0000
This register is used to control the secure access rights to the configuration register of the
PLLs. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxSEC bit defines
the secure protection for the configuration registers of the PLL: a write access is denied if
the access is nonsecure while the respective bit here is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4 PLL3 PLL2 PLL1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SEC SEC SEC SEC
rw rw rw rw

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 PLL4SEC: Secure protection of PLL4 configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: PLL4 configuration bits are accessible by nonsecure software only (default after reset).
1: PLL4 configuration bits are accessible by secure software only.
Bit 2 PLL3SEC: Secure protection of PLL3 configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: PLL3 configuration bits are accessible by nonsecure software only (default after reset).
1: PLL3 configuration bits are accessible by secure software only.

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RM0486 Reset and clock control (RCC)

Bit 1 PLL2SEC: Secure protection of PLL2 configuration bits

This bit is set and reset by secure privileged software only. It be read by any software.
0: PLL2 configuration bits are accessible by nonsecure software only (default after reset).
1: PLL2 configuration bits are accessible by secure software only.
Bit 0 PLL1SEC: Secure protection of PLL1 configuration bits.
This bit is set and reset by secure privileged software only. It can be read by any software.
0: PLL1 configuration bits are accessible by nonsecure software only (default after reset).
1: PLL1 configuration bits are accessible by secure software only.

14.10.112 RCC PLL privilege configuration register 1 (RCC_PRIVCFGR1)

Address offset: 0x794
Reset value: 0x0000 0000
This register is used to control the privileged access rights to the configuration register of
the PLLs. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPRIV defines
the privileged protection for the configuration registers of the PLL: a write access is denied if
the access is unprivileged while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4P PLL3P PLL2P PLL1P
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RIV RIV RIV RIV
rw rw rw rw

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 PLL4PRIV: Privileged protection of PLL4 configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: PLL4 configuration bits are accessible by unprivileged software only (default after reset).
1: PLL4 configuration bits are accessible by privileged software only.
Bit 2 PLL3PRIV: Privileged protection of PLL3 configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: PLL3 configuration bits are accessible by unprivileged software only (default after reset).
1: PLL3 configuration bits are accessible by privileged software only.
Bit 1 PLL2PRIV: Privileged protection of PLL2 configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: PLL2 configuration bits are accessible by unprivileged software only (default after reset).
1: PLL2 configuration bits are accessible by privileged software only.
Bit 0 PLL1PRIV: Privileged protection of PLL1 configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: PLL1 configuration bits are accessible by unprivileged software only (default after reset).
1: PLL1 configuration bits are accessible by privileged software only.

14.10.113 RCC PLL lock configuration register 1 (RCC_LOCKCFGR1)

Address offset: 0x798

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Reset value: 0x0000 0000

This register is used to control the locked access rights to the configuration register of the
PLLs. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxLOCK bit defines
the locked protection for the configuration registers of the PLL: a write access is denied if
the access is unlocked while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4 PLL3 PLL2 PLL1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LOCK LOCK LOCK LOCK
w w w w

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 PLL4LOCK: Locked protection of PLL4 configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: PLL4 configuration bits are accessible by unlocked software only (default after reset).
1: PLL4 configuration bits are accessible by locked software only.
Bit 2 PLL3LOCK: Locked protection of PLL3 configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: PLL3 configuration bits are accessible by unlocked software only (default after reset).
1: PLL3 configuration bits are accessible by locked software only.
Bit 1 PLL2LOCK: Locked protection of PLL2 configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: PLL2 configuration bits are accessible by unlocked software only (default after reset).
1: PLL2 configuration bits are accessible by locked software only.
Bit 0 PLL1LOCK: Locked protection of PLL1 configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: PLL1 configuration bits are accessible by unlocked software only (default after reset).
1: PLL1 configuration bits are accessible by locked software only.

14.10.114 RCC PLL public configuration register1 (RCC_PUBCFGR1)

Address offset: 0x79C
Reset value: 0x0000 0000
This register is used to control the public access rights to the configuration register of the
PLLs. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPUB defines the
public protection for the configuration registers of the PLL: a write access is denied if the
access is unlocked while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4 PLL3 PLL2 PLL1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
PUB PUB PUB PUB
rw rw rw rw

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RM0486 Reset and clock control (RCC)

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 PLL4PUB: Public protection of PLL4 configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: PLL4 configuration bits are accessible by non-public software. only (default after reset).
1: PLL4 configuration bits are accessible by public software only.
Bit 2 PLL3PUB: Public protection of PLL3 configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: PLL3 configuration bits are accessible by non-public software only (default after reset).
1: PLL3 configuration bits are accessible by public software only.
Bit 1 PLL2PUB: Public protection of PLL2 configuration bits
This bit is set and reset by secure privileged software only. It can my be read by any software.
0: PLL2 configuration bits are accessible by non-public software only (default after reset).
1: PLL2 configuration bits are accessible by public software only.
Bit 0 PLL1PUB: Public protection of PLL1 configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: PLL1 configuration bits are accessible by non-public software only (default after reset).
1: PLL1 configuration bits are accessible by public software only.

14.10.115 RCC divider secure configuration register 2 (RCC_SECCFGR2)

Address offset: 0x7A0
Reset value: 0x0000 0000
This register is used to control the secure access rights to the configuration register of the
dividers. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxSEC bit defines
the secure protection for the configuration registers of the divider: a write access is denied if
the access is nonsecure while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IC20 IC19 IC18 IC17
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SEC SEC SEC SEC
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC16 IC15 IC14 IC13 IC12 IC11 IC10 IC9 IC8 IC7 IC6 IC5 IC4 IC3 IC2 IC1
SEC SEC SEC SEC SEC SEC SEC SEC SEC SEC SEC SEC SEC SEC SEC SEC
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 IC20SEC: Secure protection of IC20 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC20 configuration bits are accessible by nonsecure software only (default after reset).
1: IC20 configuration bits are accessible by secure software only.
Bit 18 IC19SEC: Secure protection of IC19 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC19 configuration bits are accessible by nonsecure software only (default after reset).
1: IC19 configuration bits are accessible by secure software only.

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Bit 17 IC18SEC: Secure protection of IC18 divider configuration bits

This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC18 configuration bits are accessible by nonsecure software only (default after reset).
1: IC18 configuration bits are accessible by secure software only.
Bit 16 IC17SEC: Secure protection of IC17 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC17 configuration bits are accessible by nonsecure software only (default after reset).
1: IC17 configuration bits are accessible by secure software only.
Bit 15 IC16SEC: Secure protection of IC16 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC16 configuration bits are accessible by nonsecure software only (default after reset).
1: IC16 configuration bits are accessible by secure software only.
Bit 14 IC15SEC: Secure protection of IC15 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC15 configuration bits are accessible by nonsecure software only (default after reset).
1: IC15 configuration bits are accessible by secure software only.
Bit 13 IC14SEC: Secure protection of IC14 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC14 configuration bits are accessible by nonsecure software only (default after reset).
1: IC14 configuration bits are accessible by secure software only.
Bit 12 IC13SEC: Secure protection of IC13 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC13 configuration bits are accessible by nonsecure software only (default after reset).
1: IC13 configuration bits are accessible by secure software only.
Bit 11 IC12SEC: Secure protection of IC12 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC12 configuration bits are accessible by nonsecure software only (default after reset).
1: IC12 configuration bits are accessible by secure software only.
Bit 10 IC11SEC: Secure protection of IC11 divider configuration bits
Set and reset by secure privileged software only. It can read by any software.
0: IC11 configuration bits are accessible by nonsecure software only (default after reset).
1: IC11 configuration bits are accessible by secure software only.
Bit 9 IC10SEC: Secure protection of IC10 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC10 configuration bits are accessible by nonsecure software only (default after reset)
1: IC10 configuration bits are accessible by secure software only
Bit 8 IC9SEC: Secure protection of IC9 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC9 configuration bits are accessible by nonsecure software only (default after reset).
1: IC9 configuration bits are accessible by secure software only.
Bit 7 IC8SEC: Secure protection of IC8 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC8 configuration bits are accessible by nonsecure software only (default after reset).
1: IC8 configuration bits are accessible by secure software only.

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RM0486 Reset and clock control (RCC)

Bit 6 IC7SEC: Secure protection of IC7 divider configuration bits

This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC7 configuration bits are accessible by nonsecure software only (default after reset).
1: IC7 configuration bits are accessible by secure software only.
Bit 5 IC6SEC: Secure protection of IC6 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC6 configuration bits are accessible by nonsecure software only (default after reset).
1: IC6 configuration bits are accessible by secure software only.
Bit 4 IC5SEC: Secure protection of IC5 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC5 configuration bits are accessible by nonsecure software only (default after reset)
1: IC5 configuration bits are accessible by secure software only
Bit 3 IC4SEC: Secure protection of IC4 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC4 configuration bits are accessible by nonsecure software only (default after reset).
1: IC4 configuration bits are accessible by secure software only.
Bit 2 IC3SEC: Secure protection of IC3 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC3 configuration bits are accessible by nonsecure software only (default after reset).
1: IC3 configuration bits are accessible by secure software only.
Bit 1 IC2SEC: Secure protection of IC2 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC2 configuration bits are accessible by nonsecure software only (default after reset).
1: IC2 configuration bits are accessible by secure software only.
Bit 0 IC1SEC: Secure protection of IC1 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC1 configuration bits are accessible by nonsecure software only (default after reset).
1: IC1 configuration bits are accessible by secure software only.

14.10.116 RCC divider privilege configuration register 2 (RCC_PRIVCFGR2)

Address offset: 0x7A4
Reset value: 0x0000 0000
This register is used to control the privileged access rights to the configuration register of
the dividers. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPRIV bit
defines the privileged protection for the configuration registers of the divider: a write access
is denied if the access is unprivileged while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IC20 IC19 IC18 IC17
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
PRIV PRIV PRIV PRIV
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC16 IC15 IC14 IC13 IC12 IC11 IC10 IC9 IC8 IC7 IC6 IC5 IC4 IC3 IC2 IC1
PRIV PRIV PRIV PRIV PRIV PRIV PRIV PRIV PRIV PRIV PRIV PRIV PRIV PRIV PRIV PRIV
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

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Bit 19 IC20PRIV: Privileged protection of IC20 divider configuration bits

This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC20 configuration bits are accessible by unprivileged software only (default after reset).
1: IC20 configuration bits are accessible by privileged software only.
Bit 18 IC19PRIV: Privileged protection of IC19 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC19 configuration bits are accessible by unprivileged software only (default after reset).
1: IC19 configuration bits are accessible by privileged software only.
Bit 17 IC18PRIV: Privilege protection of IC18 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC18 configuration bits are accessible by unprivileged software only (default after reset).
1: IC18 configuration bits are accessible by privileged software only.
Bit 16 IC17PRIV: Privileges protection of IC17 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC17 configuration bits are accessible by unprivileged software only (default after reset).
1: IC17 configuration bits are accessible by privileged software only.
Bit 15 IC16PRIV: Privileged protection of IC16 divider configuration bits.
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC16 configuration bits are accessible by unprivileged software only (default after reset).
1: IC16 configuration bits are accessible by privileged software only.
Bit 14 IC15PRIV: Privileged protection of IC15 divider configuration bits.
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC15 configuration bits are accessible by unprivileged software only (default after reset).
1: IC15 configuration bits are accessible by privileged software only.
Bit 13 IC14PRIV: Privileged protection of IC14 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC14 configuration bits are accessible by unprivileged software only (default after reset).
1: IC14 configuration bits are accessible by privileged software only.
Bit 12 IC13PRIV: Privileged protection of IC13 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC13 configuration bits are accessible by unprivileged software only (default after reset).
1: IC13 configuration bits are accessible by privileged software only.
Bit 11 IC12PRIV: Privileged protection of IC12 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC12 configuration bits are accessible by unprivileged software only (default after reset).
1: IC12 configuration bits are accessible by privileged software only.
Bit 10 IC11PRIV: Privileged protection of IC11 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC11 configuration bits are accessible by unprivileged software only (default after reset).
1: IC11 configuration bits are accessible by privileged software only.
Bit 9 IC10PRIV: Privileged protection of IC10 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC10 configuration bits are accessible by unprivileged software only (default after reset).
1: IC10 configuration bits are accessible by privileged software only.

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RM0486 Reset and clock control (RCC)

Bit 8 IC9PRIV: Privileged protection of IC9 divider configuration bits

This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC9 configuration bits are accessible by unprivileged software only (default after reset).
1: IC9 configuration bits are accessible by privileged software only.
Bit 7 IC8PRIV: Privileged protection of IC8 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC8 configuration bits are accessible by unprivileged software only (default after reset).
1: IC8 configuration bits are accessible by privileged software only.
Bit 6 IC7PRIV: Privileged protection of IC7 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC7 configuration bits are accessible by unprivileged software only (default after reset).
1: IC7 configuration bits are accessible by privileged software only.
Bit 5 IC6PRIV: Privileged protection of IC6 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC6 configuration bits are accessible by unprivileged software only (default after reset).
1: IC6 configuration bits are accessible by privileged software only.
Bit 4 IC5PRIV: Privileged protection of IC5 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC5 configuration bits are accessible by unprivileged software only (default after reset).
1: IC5 configuration bits are accessible by privileged software only.
Bit 3 IC4PRIV: Privileged protection of IC4 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC4 configuration bits are accessible by unprivileged software only (default after reset).
1: IC4 configuration bits are accessible by privileged software only.
Bit 2 IC3PRIV: Privileged protection of IC3 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC3 configuration bits are accessible by unprivileged software only (default after reset).
1: IC3 configuration bits are accessible by privileged software only.
Bit 1 IC2PRIV: Privileged protection of IC2 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC2 configuration bits are accessible by unprivileged software only (default after reset).
1: IC2 configuration bits are accessible by privileged software only.
Bit 0 IC1PRIV: Privileged protection of IC1 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC1 configuration bits are accessible by unprivileged software only (default after reset).
1: IC1 configuration bits are accessible by privileged software only.

14.10.117 RCC divider lock configuration register 2 (RCC_LOCKCFGR2)

Address offset: 0x7A8
Reset value: 0x0000 0000
This register is used to control the locked access rights to the configuration register of the
dividers. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxLOCK bit
defines the locked protection for the configuration registers of the divider: a write access is
denied if the access is unlocked while the respective bit is set.

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IC20LO IC19LO IC18LO IC17LO
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
CK CK CK CK
w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC16LO IC15LO IC14LO IC13LO IC12LO IC11LO IC10LO IC9LO IC8LO IC7LO IC6LO IC5LO IC4LO IC3LO IC2LO IC1LO
CK CK CK CK CK CK CK CK CK CK CK CK CK CK CK CK
w w w w w w w w w w w w w w w w

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 IC20LOCK: Locked protection of IC20 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC20 configuration bits are accessible by unlocked software only (default after reset).
1: IC20 configuration bits are accessible by locked software only.
Bit 18 IC19LOCK: Locked protection of IC19 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC19 configuration bits are accessible by unlocked software only (default after reset).
1: IC19 configuration bits are accessible by locked software only.
Bit 17 IC18LOCK: Locked protection of IC18 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC18 configuration bits are accessible by unlocked software only (default after reset).
1: IC18 configuration bits are accessible by locked software only.
Bit 16 IC17LOCK: Locked protection of IC17 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC17 configuration bits are accessible by unlocked software only (default after reset).
1: IC17 configuration bits are accessible by locked software only.
Bit 15 IC16LOCK: Locked protection of IC16 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC16 configuration bits are accessible by unlocked software only (default after reset).
1: IC16 configuration bits are accessible by locked software only.
Bit 14 IC15LOCK: Locked protection of IC15 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC15 configuration bits are accessible by unlocked software only (default after reset).
1: IC15 configuration bits are accessible by locked software only.
Bit 13 IC14LOCK: Locked protection of IC14 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC14 configuration bits are accessible by unlocked software only (default after reset).
1: IC14 configuration bits are accessible by locked software only.
Bit 12 IC13LOCK: Locked protection of IC13 divider configuration bits.
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC13 configuration bits are accessible by unlocked software only (default after reset).
1: IC13 configuration bits are accessible by locked software only.
Bit 11 IC12LOCK: Locked protection of IC12 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC12 configuration bits are accessible by unlocked software only (default after reset).
1: IC12 configuration bits are accessible by locked software only.

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RM0486 Reset and clock control (RCC)

Bit 10 IC11LOCK: Locked protection of IC11 divider configuration bits

This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC11 configuration bits are accessible by unlocked software only (default after reset).
1: IC11 configuration bits are accessible by locked software only.
Bit 9 IC10LOCK: Locked protection of IC10 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC10 configuration bits are accessible by unlocked software only (default after reset).
1: IC10 configuration bits are accessible by locked software only.
Bit 8 IC9LOCK: Locked protection of IC9 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC9 configuration bits are accessible by unlocked software only (default after reset).
1: IC9 configuration bits are accessible by locked software only.
Bit 7 IC8LOCK: Locked protection of IC8 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC8 configuration bits are accessible by unlocked software only (default after reset).
1: IC8 configuration bits are accessible by locked software only.
Bit 6 IC7LOCK: Locked protection of IC7 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC7 configuration bits are accessible by unlocked software only (default after reset).
1: IC7 configuration bits are accessible by locked software only.
Bit 5 IC6LOCK: Locked protection of IC6 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC6 configuration bits are accessible by unlocked software only (default after reset).
1: IC6 configuration bits are accessible by locked software only.
Bit 4 IC5LOCK: Locked protection of IC5 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC5 configuration bits are accessible by unlocked software only (default after reset).
1: IC5 configuration bits are accessible by locked software only.
Bit 3 IC4LOCK: Locked protection of IC4 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC4 configuration bits are accessible by unlocked software only (default after reset).
1: IC4 configuration bits are accessible by locked software only.
Bit 2 IC3LOCK: Locked protection of IC3 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC3 configuration bits are accessible by unlocked software only (default after reset).
1: IC3 configuration bits are accessible by locked software only.
Bit 1 IC2LOCK: Locked protection of IC2 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC2 configuration bits are accessible by unlocked software only (default after reset).
1: IC2 configuration bits are accessible by locked software only.
Bit 0 IC1LOCK: Locked protection of IC1 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC1 configuration bits are accessible by unlocked software only (default after reset).
1: IC1 configuration bits are accessible by locked software only.

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14.10.118 RCC divider public configuration register 2 (RCC_PUBCFGR2)

Address offset: 0x7AC
Reset value: 0x0000 0000
This register is used to control the public access rights to the configuration register of the
dividers. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPUB bit defines
the public protection for the configuration registers of the divider: a write access is denied if
the access is non-public while the respective bit here is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IC20PU IC19PU IC18PU IC17PU
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
B B B B
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC16PU IC15PU IC14PU IC13PU IC12PU IC11PU IC10PU IC9PU IC8PU IC7PU IC6PU IC5PU IC4PU IC3PU IC2PU IC1PU
B B B B B B B B B B B B B B B B
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 IC20PUB: Public protection of IC20 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC20 configuration bits are accessible by non-public software only (default after reset).
1: IC20 configuration bits are accessible by public software only.
Bit 18 IC19PUB: Public protection of IC19 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC19 configuration bits are accessible by non-public software only (default after reset).
1: IC19 configuration bits are accessible by public software only.
Bit 17 IC18PUB: Public protection of IC18 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC18 configuration bits are accessible by non-public software only (default after reset).
1: IC18 configuration bits are accessible by public software only.
Bit 16 IC17PUB: Public protection of IC17 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC17 configuration bits are accessible by non-public software only (default after reset).
1: IC17 configuration bits are accessible by public software only.
Bit 15 IC16PUB: Public protection of IC16 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC16 configuration bits are accessible by non-public software only (default after reset).
1: IC16 configuration bits are accessible by public software only.
Bit 14 IC15PUB: Public protection of IC15 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC15 configuration bits are accessible by non-public software only (default after reset).
1: IC15 configuration bits are accessible by public software only.
Bit 13 IC14PUB: Public protection of IC14 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC14 configuration bits are accessible by non-public software only (default after reset).
1: IC14 configuration bits are accessible by public software only.

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RM0486 Reset and clock control (RCC)

Bit 12 IC13PUB: Public protection of IC13 divider configuration bits

This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC13 configuration bits are accessible by non-public software only (default after reset).
1: IC13 configuration bits are accessible by public software only.
Bit 11 IC12PUB: Public protection of IC12 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC12 configuration bits are accessible by non-public software only (default after reset).
1: IC12 configuration bits are accessible by public software only.
Bit 10 IC11PUB: Public protection of IC11 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC11 configuration bits are accessible by non-public software only (default after reset).
1: IC11 configuration bits are accessible by public software only.
Bit 9 IC10PUB: Public protection of IC10 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC10 configuration bits are accessible by non-public software only (default after reset).
1: IC10 configuration bits are accessible by public software only.
Bit 8 IC9PUB: Public protection of IC9 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC9 configuration bits are accessible by non-public software only (default after reset).
1: IC9 configuration bits are accessible by public software only.
Bit 7 IC8PUB: Public protection of IC8 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC8 configuration bits are accessible by non-public software only (default after reset).
1: IC8 configuration bits are accessible by public software only.
Bit 6 IC7PUB: Public protection of IC7 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC7 configuration bits are accessible by non-public software only (default after reset).
1: IC7 configuration bits are accessible by public software only.
Bit 5 IC6PUB: Public protection of IC6 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC6 configuration bits are accessible by non-public software only (default after reset).
1: IC6 configuration bits are accessible by public software only.
Bit 4 IC5PUB: Public protection of IC5 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC5 configuration bits are accessible by non-public software only (default after reset).
1: IC5 configuration bits are accessible by public software only.
Bit 3 IC4PUB: Public protection of IC4 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC4 configuration bits are accessible by non-public software only (default after reset).
1: IC4 configuration bits are accessible by public software only.
Bit 2 IC3PUB: Public protection of IC3 divider configuration bits.
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC3 configuration bits are accessible by non-public software only (default after reset).
1: IC3 configuration bits are accessible by public software only.

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Bit 1 IC2PUB: Public protection of IC2 divider configuration bits

This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC2 configuration bits are accessible by non-public software only (default after reset).
1: IC2 configuration bits are accessible by public software only.
Bit 0 IC1PUB: Public protection of IC1 divider configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: IC1 configuration bits are accessible by non-public software only (default after reset).
1: IC1 configuration bits are accessible by public software only.

14.10.119 RCC system secure configuration register 3 (RCC_SECCFGR3)

Address offset: 0x7B0
Reset value: 0x0000 0000
This register is used to control the secure access rights to the system configuration
registers. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxSEC bit
defines the secure protection for the configuration registers: a write access is denied if the
access is nonsecure while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RST INT PER BUS SYS MOD
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SEC SEC SEC SEC SEC SEC
rw rw rw rw rw rw

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 RSTSEC: Secure protection of RST system configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: RST configuration bits are accessible by nonsecure software only (default after reset).
1: RST configuration bits are accessible by secure software only.
Bit 4 INTSEC: Secure protection of INT system configuration bits.
This bit is set and reset by secure privileged software only. It can be read by any software.
0: INT configuration bits are accessible by nonsecure software only (default after reset).
1: INT configuration bits are accessible by secure software only.
Bit 3 PERSEC: Secure protection of PER system configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: PER configuration bits are accessible by nonsecure software only (default after reset).
1: PER configuration bits are accessible by secure software only.
Bit 2 BUSSEC: Secure protection of BUS system configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: BUS configuration bits are accessible by nonsecure software only (default after reset).
1: BUS configuration bits are accessible by secure software only.
Bit 1 SYSSEC: Secure protection of SYS system configuration bit.
This bit is set and reset by secure privileged software only. It can be read by any software.
0: SYS configuration bits are accessible by nonsecure software only (default after reset).
1: SYS configuration bits are accessible by secure software only.

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Bit 0 MODSEC: Secure protection of MOD system configuration bits

This bit is set and reset by secure privileged software only. It can be read by any software.
0: MOD configuration bits are accessible by nonsecure software only (default after reset).
1: MOD configuration bits are accessible by secure software only.

14.10.120 RCC system privilege configuration register3 (RCC_PRIVCFGR3)

Address offset: 0x7B4
Reset value: 0x0000 0000
This register is used to control the privileged access rights to the system configuration
registers. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPRIV bit
defines the privileged protection for the system configuration registers: a write access is
denied if the access is unprivileged while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RST INT PER BUS SYS MOD
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
PRIV PRIV PRIV PRIV PRIV PRIV
rw rw rw rw rw rw

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 RSTPRIV: Privileged protection of RST system configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: RST configuration bits are accessible by unprivileged software only (default after reset).
1: RST configuration bits are accessible by privileged software only.
Bit 4 INTPRIV: Privileged protection of INT system configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: INT configuration bits are accessible by unprivileged software only (default after reset).
1: INT configuration bits are accessible by privileged software only.
Bit 3 PERPRIV: Privileged protection of PER system configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: PER configuration bits are accessible by unprivileged software only (default after reset).
1: PER configuration bits are accessible by privileged software only.
Bit 2 BUSPRIV: Privileged protection of BUS system configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: BUS configuration bits are accessible by unprivileged software only (default after reset.)
1: BUS configuration bits are accessible by privileged software only.
Bit 1 SYSPRIV: Privileged protection of SYS system configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: SYS configuration bits are accessible by unprivileged software only (default after reset).
1: SYS configuration bits are accessible by privileged software only.
Bit 0 MODPRIV: Privileged protection of MOD system configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: MOD configuration bits are accessible by unprivileged software only (default after reset).
1: MOD configuration bits are accessible by privileged software only.

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14.10.121 RCC system lock configuration register 3 (RCC_LOCKCFGR3)

Address offset: 0x7B8
Reset value: 0x0000 0000
This register is used to control the locked access rights to the system configuration
registers. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxLOCK bit
defines the locked protection for the system configuration registers: a write access is denied
if the access is unlocked while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RST INT PER BUS SYS MOD
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LOCK LOCK LOCK LOCK LOCK LOCK
w w w w w w

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 RSTLOCK: Locked protection of RST system configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: RST configuration bits are accessible by unlocked software only (default after reset).
1: RST configuration bits are accessible by locked software only.
Bit 4 INTLOCK: Locked protection of INT system configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: INT configuration bits are accessible by unlocked software only (default after reset).
1: INT configuration bits are accessible by locked software only.
Bit 3 PERLOCK: Locked protection of PER system configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: PER configuration bits are accessible by unlocked software only (default after reset).
1: PER configuration bits are accessible by locked software only.
Bit 2 BUSLOCK: Locked protection of BUS system configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: BUS configuration bits are accessible by unlocked software only (default after reset).
1: BUS configuration bits are accessible by locked software only.
Bit 1 SYSLOCK: Locked protection of SYS system configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: SYS configuration bits are accessible by unlocked software only (default after reset).
1: SYS configuration bits are accessible by locked software only.
Bit 0 MODLOCK: Locked protection of MOD system configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: MOD configuration bits are accessible by unlocked software only (default after reset).
1: MOD configuration bits are accessible by locked software only.

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RM0486 Reset and clock control (RCC)

14.10.122 RCC system public configuration register 3 (RCC_PUBCFGR3)

Address offset: 0x7BC
Reset value: 0x0000 0000
This register is used to control the public access rights to the system configuration registers.
It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPUB defines the public
protection for the system configuration registers: a write access is denied if the access is
non-public while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RST INT PER BUS SYS MOD
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
PUB PUB PUB PUB PUB PUB
rw rw rw rw rw rw

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 RSTPUB: Public protection of RST system configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: RST configuration bits are accessible by non-public software only (default after reset).
1: RST configuration bits are accessible by public software only.
Bit 4 INTPUB: Public protection of INT system configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: INT configuration bits are accessible by non-public software only (default after reset).
1: INT configuration bits are accessible by public software only.
Bit 3 PERPUB: Public protection of PER system configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: PER configuration bits are accessible by non-public software only (default after reset).
1: PER configuration bits are accessible by public software only.
Bit 2 BUSPUB: Public protection of BUS system configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: BUS configuration bits are accessible by non-public software only (default after reset).
1: BUS configuration bits are accessible by public software only.
Bit 1 SYSPUB: Public protection of SYS system configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: SYS configuration bits are accessible by non-public software only (default after reset).
1: SYS configuration bits are accessible by public software only.
Bit 0 MODPUB: Public protection of MOD system configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: MOD configuration bits are accessible by non-public software only (default after reset).
1: MOD configuration bits are accessible by public software only.

14.10.123 RCC bus secure configuration register 4 (RCC_SECCFGR4)

Reset value: 0x0000 0000
Address offset: 0x7C0

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This register is used to control the secure access rights to the configuration register of the
buses. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxSEC pub defines
the secure protection for the configuration registers of the bus: a write access is denied if the
access is nonsecure while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOC APB5 APB4 APB3 APB2 APB1 AHB5 AHB4 AHB3 AHB2 AHB1 AHBM ACLKNC ACLKN
Res. Res.
SEC SEC SEC SEC SEC SEC SEC SEC SEC SEC SEC SEC SEC SEC
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 NOCSEC: Secure protection of NOC bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: NOC configuration bits are accessible by nonsecure software only (default after reset).
1: NOC configuration bits are accessible by secure software only.
Bit 12 APB5SEC: Secure protection of APB5 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: APB5 configuration bits are accessible by nonsecure software only (default after reset).
1: APB5 configuration bits are accessible by secure software only.
Bit 11 APB4SEC: Secure protection of APB4 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: APB4 configuration bits are accessible by nonsecure software only (default after reset).
1: APB4 configuration bits are accessible by secure software only.
Bit 10 APB3SEC: Secure protection of APB3 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: APB3 configuration bits are accessible by nonsecure software only (default after reset).
1: APB3 configuration bits are accessible by secure software only.
Bit 9 APB2SEC: Secure protection of APB2 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: APB2 configuration bits are accessible by nonsecure software only (default after reset).
1: APB2 configuration bits are accessible by secure software only.
Bit 8 APB1SEC: Secure protection of APB1 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: APB1 configuration bits are accessible by nonsecure software only (default after reset).
1: APB1 configuration bits are accessible by secure software only.
Bit 7 AHB5SEC: Secure protection of AHB5 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHB5 configuration bits are accessible by nonsecure software only (default after reset).
1: AHB5 configuration bits are accessible by secure software only.
Bit 6 AHB4SEC: Secure protection of AHB4 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHB4 configuration bits are accessible by nonsecure software only (default after reset).
1: AHB4 configuration bits are accessible by secure software only.

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Bit 5 AHB3SEC: Secure protection of AHB3 bus configuration bits

This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHB3 configuration bits are accessible by nonsecure software only (default after reset).
1: AHB3 configuration bits are accessible by secure software only.
Bit 4 AHB2SEC: Secure protection of AHB2 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHB2 configuration bits are accessible by nonsecure software only (default after reset).
1: AHB2 configuration bits are accessible by secure software only.
Bit 3 AHB1SEC: Secure protection of AHB1 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHB1 configuration bits are accessible by nonsecure software only (default after reset).
1: AHB1 configuration bits are accessible by secure software only.
Bit 2 AHBMSEC: Secure protection of AHBM bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHBM configuration bits are accessible by nonsecure software only (default after reset).
1: AHBM configuration bits are accessible by secure software only.
Bit 1 ACLKNCSEC: Secure protection of ACLKNC bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: ACLKNC configuration bits are accessible by nonsecure software only (default after reset).
1: ACLKNC configuration bits are accessible by secure software only.
Bit 0 ACLKNSEC: Secure protection of ACLKN bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: ACLKN configuration bits are accessible by nonsecure software only (default after reset).
1: ACLKN configuration bits are accessible by secure software only.

14.10.124 RCC bus privilege configuration register 4 (RCC_PRIVCFGR4)

Address offset: 0x7C4
Reset value: 0x0000 0000
This register is used to control the privileged access rights to the configuration register of
the bus. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPRIV bit defines
the privileged protection for the configuration registers of the bus: a write access is denied if
the access is unprivileges while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOC APB5 APB4 APB3 APB2 APB1 AHB5 AHB4 AHB3 AHB2 AHB1 AHBM ACLKNC ACLKN
Res. Res.
PRIV PRIV PRIV PRIV PRIV PRIV PRIV PRIV PRIV PRIV PRIV PRIV PRIV PRIV
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 NOCPRIV: Privileged protection of NOC bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: NOC configuration bits are accessible by unprivileged software only (default after reset).
1: NOC configuration bits are accessible by privileged software only.

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Bit 12 APB5PRIV: Privileged protection of APB5 bus configuration bits

This bit is set and reset by secure privileged software only. It can be read by any software.
0: APB5 configuration bits are accessible by unprivileged software only (default after reset).
1: APB5 configuration bits are accessible by privileged software only.
Bit 11 APB4PRIV: Privileged protection of APB4 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: APB4 configuration bits are accessible by unprivileged software only (default after reset).
1: APB4 configuration bits are accessible by privileged software only.
Bit 10 APB3PRIV: Privileged protection of APB3 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: APB3 configuration bits are accessible by unprivileged software only (default after reset).
1: APB3 configuration bits are accessible by privileged software only.
Bit 9 APB2PRIV: Privileged protection of APB2 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: APB2 configuration bits are accessible by unprivileged software only (default after reset).
1: APB2 configuration bits are accessible by privileged software only.
Bit 8 APB1PRIV: Privileged protection of APB1 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: APB1 configuration bits are accessible by unprivileged software only (default after reset).
1: APB1 configuration bits are accessible by privileged software only.
Bit 7 AHB5PRIV: Privileged protection of AHB5 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHB5 configuration bits are accessible by unprivileged software only (default after reset).
1: AHB5 configuration bits are accessible by privileged software only.
Bit 6 AHB4PRIV: Privileged protection of AHB4 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHB4 configuration bits are accessible by unprivileged software only (default after reset).
1: AHB4 configuration bits are accessible by privileged software only.
Bit 5 AHB3PRIV: Privileged protection of AHB3 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHB3 configuration bits are accessible by unprivileged software only (default after reset).
1: AHB3 configuration bits are accessible by privileged software only.
Bit 4 AHB2PRIV: Privileged protection of AHB2 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHB2 configuration bits are accessible by unprivileged software only (default after reset).
1: AHB2 configuration bits are accessible by privileged software only.
Bit 3 AHB1PRIV: Privileged protection of AHB1 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHB1 configuration bits are accessible by unprivileged software only (default after reset).
1: AHB1 configuration bits are accessible by privileged software only.
Bit 2 AHBMPRIV: Privileged protection of AHBM bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHBM configuration bits are accessible by unprivileged software only (default after reset).
1: AHBM configuration bits are accessible by privileged software only.

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Bit 1 ACLKNCPRIV: Privileged protection of ACLKNC bus configuration bits

This bit is set and reset by secure privileged software only. It can be read by any software.
0: ACLKNC configuration bits are accessible by unprivileged software only (default after
reset).
1: ACLKNC configuration bits are accessible by privileged software only.
Bit 0 ACLKNPRIV: Privileged protection of ACLKN bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: ACLKN configuration bits are accessible by unprivileged software only (default after reset).
1: ACLKN configuration bits are accessible by privileged software only.

14.10.125 RCC bus lock configuration register 4 (RCC_LOCKCFGR4)

Address offset: 0x7C8
Reset value: 0x0000 0000
This register is used to control the locked access rights to the configuration register of the
bus. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxLOCK defines the
locked protection for the configuration registers of the bus: a write access is denied if the
access is unlocked while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOCL APB5L APB4L APB3L APB2L APB1L AHB5L AHB4L AHB3L AHB2L AHB1L AHBML ACLKN ACLKN
Res. Res.
OCK OCK OCK OCK OCK OCK OCK OCK OCK OCK OCK OCK CLOCK LOCK
w w w w w w w w w w w w w w

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 NOCLOCK: Locked protection of NOC bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: NOC configuration bits are accessible by unlocked software only (default after reset).
1: NOC configuration bits are accessible by locked software only.
Bit 12 APB5LOCK: Locked protection of APB5 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: APB5 configuration bits are accessible by unlocked software only (default after reset).
1: APB5 configuration bits are accessible by locked software only.
Bit 11 APB4LOCK: Locked protection of APB4 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: APB4 configuration bits are accessible by unlocked software only (default after reset).
1: APB4 configuration bits are accessible by lock software only.
Bit 10 APB3LOCK: Locked protection of APB3 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: APB3 configuration bits are accessible by unlocked software only (default after reset).
1: APB3 configuration bits are accessible by locked software only.

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Bit 9 APB2LOCK: Locked protection of APB2 bus configuration bits

This bit is set and reset by secure privileged software only. It can be read by any software.
0: APB2 configuration bits are accessible by unlocked software only (default after reset).
1: APB2 configuration bits are accessible by locked software only.
Bit 8 APB1LOCK: Locked protection of APB1 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: APB1 configuration bits are accessible by unlocked software only (default after reset).
1: APB1 configuration bits are accessible by locked software only.
Bit 7 AHB5LOCK: Locked protection of AHB5 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHB5 configuration bits are accessible by unlocked software only (default after reset).
1: AHB5 configuration bits are accessible by locked software only.
Bit 6 AHB4LOCK: Locked protection of AHB4 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHB4 configuration bits are accessible by unlocked software only (default after reset).
1: AHB4 configuration bits are accessible by locked software only.
Bit 5 AHB3LOCK: Locked protection of AHB3 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHB3 configuration bits are accessible by unlocked software only (default after reset).
1: AHB3 configuration bits are accessible by locked software only.
Bit 4 AHB2LOCK: Locked protection of AHB2 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHB2 configuration bits are accessible by unlocked software only (default after reset).
1: AHB2 configuration bits are accessible by locked software only.
Bit 3 AHB1LOCK: Locked protection of AHB1 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHB1 configuration bits are accessible by unlocked software only (default after reset).
1: AHB1 configuration bits are accessible by locked software only.
Bit 2 AHBMLOCK: Locked protection of AHBM bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHBM configuration bits are accessible by unlocked software only (default after reset).
1: AHBM configuration bits are accessible by locked software only.
Bit 1 ACLKNCLOCK: Locked protection of ACLKNC bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: ACLKNC configuration bits are accessible by unlocked software only (default after reset).
1: ACLKNC configuration bits are accessible by locked software only.
Bit 0 ACLKNLOCK: Locked protection of ACLKN bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: ACLKN configuration bits are accessible by unlocked software only (default after reset).
1: ACLKN configuration bits are accessible by locked software only.

14.10.126 RCC bus public configuration register 4 (RCC_PUBCFGR4)

Address offset: 0x7CC
Reset value: 0x0000 0000

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This register is used to control the public access rights to the configuration register of the
bus. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPUB defines the
public protection for the configuration registers of the bus: a write access is denied if the
access is non-public while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOCP APB5P APB4P APB3P APB2P APB1P AHB5P AHB4P AHB3P AHB2P AHB1P AHBM ACLKN ACLKN
Res. Res.
UB UB UB UB UB UB UB UB UB UB UB PUB CPUB PUB
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 NOCPUB: Public protection of NOC bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: NOC configuration bits are accessible by non-public software only (default after reset).
1: NOC configuration bits are accessible by public software only.
Bit 12 APB5PUB: Public protection of APB5 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: APB5 configuration bits are accessible by non-public software only (default after reset)
1: APB5 configuration bits are accessible by public software only
Bit 11 APB4PUB: Public protection of APB4 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: APB4 configuration bits are accessible by non-public software only (default after reset).
1: APB4 configuration bits are accessible by public software only.
Bit 10 APB3PUB: Public protection of APB3 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: APB3 configuration bits are accessible by non-public software only (default after reset).
1: APB3 configuration bits are accessible by public software only.
Bit 9 APB2PUB: Public protection of APB2 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: APB2 configuration bits are accessible by non-public software only (default after reset).
1: APB2 configuration bits are accessible by public software only.
Bit 8 APB1PUB: Public protection of APB1 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: APB1 configuration bits are accessible by non-public software only (default after reset).
1: APB1 configuration bits are accessible by public software only.
Bit 7 AHB5PUB: Public protection of AHB5 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHB5 configuration bits are accessible by non-public software only (default after reset).
1: AHB5 configuration bits are accessible by public software only.
Bit 6 AHB4PUB: Public protection of AHB4 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHB4 configuration bits are accessible by non-public software only (default after reset).
1: AHB4 configuration bits are accessible by public software only.

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Bit 5 AHB3PUB: Public protection of AHB3 bus configuration bits

This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHB3 configuration bits are accessible by non-public software only (default after reset).
1: AHB3 configuration bits are accessible by public software only.
Bit 4 AHB2PUB: Public protection of AHB2 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHB2 configuration bits are accessible by non-public software only (default after reset).
1: AHB2 configuration bits are accessible by public software only.
Bit 3 AHB1PUB: Public protection of AHB1 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHB1 configuration bits are accessible by non-public software only (default after reset).
1: AHB1 configuration bits are accessible by public software only.
Bit 2 AHBMPUB: Public protection of AHBM bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHBM configuration bits are accessible by non-public software only (default after reset).
1: AHBM configuration bits are accessible by public software only.
Bit 1 ACLKNCPUB: Public protection of ACLKNC bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: ACLKNC configuration bits are accessible by non-public software only (default after reset).
1: ACLKNC configuration bits are accessible by public software only.
Bit 0 ACLKNPUB: Public protection of the ACLKN bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: ACLKN configuration bits are accessible by non-public software only (default after reset).
1: ACLKN configuration bits are accessible by public software only.

14.10.127 RCC bus public configuration register 4 (RCC_PUBCFGR5)

Address offset: 0x7D0
Reset value: 0x0000 0000
This register is used to control the public access rights to the configuration register of the
bus. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPUB bit defines the
public protection for the configuration registers of the bus: a write access is denied if the
access is non-public while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VENCR CACHE FLEXR AXISR AXISR BKPSR AHBSR AHBSR AXISR AXISR AXISR AXISR
Res. Res. Res. Res. AMPU AXIRA AMPU AM2PU AM1PU AMPU AM2PU AM1PU AM6PU AM5PU AM4PU AM3PU
B MPUB B B B B B B B B B B
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept at reset value.

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Bit 11 VENCRAMPUB: Public protection of VENCRAM bus configuration bits

This bit is set and reset by secure privileged software only. It can be read by any software.
0: VENCRAM configuration bits are accessible by non-public software only (default after
reset).
1: VENCRAM configuration bits are accessible by public software only.
Bit 10 CACHEAXIRAMPUB: Public protection of CACHEAXIRAM bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: CACHEAXIRAM configuration bits are accessible by non-public software only (default after
reset).
1: CACHEAXIRAM configuration bits are accessible by public software only.
Bit 9 FLEXRAMPUB: Public protection of FLEXRAM bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: FLEXRAM configuration bits are accessible by non-public software only (default after
reset).
1: FLEXRAM configuration bits are accessible by public software only.
Bit 8 AXISRAM2PUB: Public protection of AXISRAM2 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AXISRAM2 configuration bits are accessible by non-public software only (default after
reset).
1: AXISRAM2 configuration bits are accessible by public software only.
Bit 7 AXISRAM1PUB: Public protection of AXISRAM1 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AXISRAM1 configuration bits are accessible by non-public software only (default after
reset).
1: AXISRAM1 configuration bits are accessible by public software only.
Bit 6 BKPSRAMPUB: Public protection of BKPSRAM bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: BKPSRAM configuration bits are accessible by non-public software only (default after
reset).
1: BKPSRAM configuration bits are accessible by public software only.
Bit 5 AHBSRAM2PUB: Public protection of AHBSRAM2 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHBSRAM2 configuration bits are accessible by non-public software only (default after
reset).
1: AHBSRAM2 configuration bits are accessible by public software only.
Bit 4 AHBSRAM1PUB: Public protection of AHBSRAM1 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AHBSRAM1 configuration bits are accessible by non-public software only (default after
reset).
1: AHBSRAM1 configuration bits are accessible by public software only.
Bit 3 AXISRAM6PUB: Public protection of AXISRAM6 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AXISRAM6 configuration bits are accessible by non-public software only (default after
reset).
1: AXISRAM6 configuration bits are accessible by public software only.

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Bit 2 AXISRAM5PUB: Public protection of AXISRAM5 bus configuration bits

This bit is set and reset by secure privileged software only. It can be read by any software.
0: AXISRAM5 configuration bits are accessible by non-public software only (default after
reset).
1: AXISRAM5 configuration bits are accessible by public software only.
Bit 1 AXISRAM4PUB: Public protection of AXISRAM4 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AXISRAM4 configuration bits are accessible by non-public software only (default after
reset).
1: AXISRAM4 configuration bits are accessible by public software only.
Bit 0 AXISRAM3PUB: Public protection of AXISRAM3 bus configuration bits
This bit is set and reset by secure privileged software only. It can be read by any software.
0: AXISRAM3 configuration bits are accessible by non-public software only (default after
reset).
1: AXISRAM3 configuration bits are accessible by public software only.

14.10.128 RCC control set register (RCC_CSR)

Address offset: 0x800
Reset value: 0x0000 0000
This register is used to enable the RCC oscillators and PLLs in Run or Sleep mode. It is
reset by nreset_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4O PLL3O PLL2O PLL1O HSEO HSION MSION LSEON LSION
Res. Res. Res. Res. Res. Res. Res.
NS NS NS NS NS S S S S
w w w w w w w w w

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 PLL4ONS: PLL4 oscillator enable
Written at 1 to set PLL4ON.
Bit 10 PLL3ONS: PLL3 oscillator enable
Written at 1 to set PLL3ON.
Bit 9 PLL2ONS: PLL2 oscillator enable
Written at 1 to set PLL2ON.
Bit 8 PLL1ONS: PLL1 oscillator enable
Written at 1 to set PLL1ON.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 HSEONS: HSE oscillator enable
Written at 1 to set HSEON.
Bit 3 HSIONS: HSI oscillator enable
Written at 1 to set HSION.

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RM0486 Reset and clock control (RCC)

Bit 2 MSIONS: MSI oscillator enable

Written at 1 to set MSION.
Bit 1 LSEONS: LSE oscillator enable
Written at 1 to set LSEON.
Bit 0 LSIONS: LSI oscillator enable
Written at 1 to set LSION.

14.10.129 RCC Stop mode configuration set register (RCC_STOPCSR)

Address offset: 0x808
Reset value: 0x0000 0000
This register is used to enable the RCC oscillators and PLLs in Stop mode. It is reset by
sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSIST MSIST
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
OPENS OPENS
w w

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 HSISTOPENS: HSI oscillator enable
Written at 1 to set HSISTOPEN.
Bit 0 MSISTOPENS: MSI oscillator enable
Written at 1 to set MSISTOPEN.

14.10.130 RCC miscellaneous reset register (RCC_MISCRSTSR)

Address offset: 0xA08
Reset value: 0x0000 0000
This register is used to reset the RCC miscellaneous. It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMM SDMM XSPIP XSPIP
DBGR
Res. Res. Res. Res. Res. Res. Res. C2DLL C1DLL Res. HY2RS HY1RS Res. Res. Res.
STS
RSTS RSTS TS TS
w w w w w

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SDMMC2DLLRSTS: SDMMC2DLL reset
Written at 1 to set SDMMC2DLLRST.

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Bit 7 SDMMC1DLLRSTS: SDMMC1DLL reset

Written at 1 to set SDMMC1DLLRST.
Bit 6 Reserved, must be kept at reset value.
Bit 5 XSPIPHY2RSTS: XSPIPHY2 reset
Written at 1 to set XSPIPHY2RST.
Bit 4 XSPIPHY1RSTS: XSPIPHY1 reset
Written at 1 to set XSPIPHY1RST.
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 DBGRSTS: DBG reset
Written at 1 to set DBGRST.

14.10.131 RCC memory reset register (RCC_MEMRSTSR)

Address offset: 0xA0C
Reset value: 0x0000 0000
This register is used to reset the RCC memories. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOT VENCR CACHE FLEXR AXISR AXISR AHBSR AHBSR AXISR AXISR AXISR AXISR
Res. Res. Res. ROMR AMRST AXIRA AMRST AM2RS AM1RS Res. AM2RS AM1RS AM6RS AM5RS AM4RS AM3RS
STS S MRSTS S TS TS TS TS TS TS TS TS
w w w w w w w w w w w w

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 BOOTROMRSTS: BootROM reset
Written at 1 to set BOOTROMRST.
Bit 11 VENCRAMRSTS: VENCRAM reset
Written at 1 to set VENCRAMRST.
Bit 10 CACHEAXIRAMRSTS: CACHEAXIRAM reset
Written at 1 to set CACHEAXIRAM.
Bit 9 FLEXRAMRSTS: FLEXRAM reset
Written at 1 to set FLEXRAMRST.
Bit 8 AXISRAM2RSTS: AXISRAM2 reset
Written at 1 to set AXISRAM2RST.
Bit 7 AXISRAM1RSTS: AXISRAM1 reset
Written at 1 to set AXISRAM1RST.
Bit 6 Reserved, must be kept at reset value.
Bit 5 AHBSRAM2RSTS: AHBSRAM2 reset
Written at 1 to set AHBSRAM2RST.

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RM0486 Reset and clock control (RCC)

Bit 4 AHBSRAM1RSTS: AHBSRAM1 reset

Written at 1 to set AHBSRAM1RST.
Bit 3 AXISRAM6RSTS: AXISRAM6 reset
Written at 1 to set AXISRAM6RST.
Bit 2 AXISRAM5RSTS: AXISRAM5 reset
Written at 1 to set AXISRAM5RST.
Bit 1 AXISRAM4RSTS: AXISRAM4 reset
Written at 1 to set AXISRAM4RST.
Bit 0 AXISRAM3RSTS: AXISRAM3 reset
Written at 1 to set AXISRAM3RST.

14.10.132 RCC AHB1 reset register (RCC_AHB1RSTSR)

Address offset: 0xA10
Reset value: 0x0000 0000
This register is used to reset the RCC AHB1. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPDM
ADC12
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. A1RST Res. Res. Res. Res.
RSTS
S
w w

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 ADC12RSTS: ADC12 reset
Written at 1 to set ADC12RST.
Bit 4 GPDMA1RSTS: GPDMA1 reset
Written at 1 to set GPDMA1RST.
Bits 3:0 Reserved, must be kept at reset value.

14.10.133 RCC AHB2 reset register (RCC_AHB2RSTSR)

Address offset: 0xA14
Reset value: 0x0000 0000
This register is used to reset the RCC AHB2. It is reset by sys_rstn, and is in the VCORE
voltage domain.

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADF1 MDF1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RSTS RSTS
w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAMCFG
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RSTS
w

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 ADF1RSTS: ADF1 reset
Written at 1 to set ADF1RST.
Bit 16 MDF1RSTS: MDF1 reset
Written at 1 to set MDF1RST.
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 RAMCFGRSTS: RAMCFG reset
Written at 1 to set RAMCFGRST.
Bits 11:0 Reserved, must be kept at reset value.

14.10.134 RCC AHB3 reset register (RCC_AHB3RSTSR)

Address offset: 0xA18
Reset value: 0x0000 0000
This register is used to reset the RCC AHB3. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IACRS PKARS SAESR CRYPR HASHR RNGR
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
TS TS STS STS STS STS
w w w w w w

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 IACRSTS: IAC reset
Written at 1 to set IACRST.
Bit 9 Reserved, must be kept at reset value.
Bit 8 PKARSTS: PKA reset
Written at 1 to set PKARST.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 SAESRSTS: SAES reset
Written at 1 to set SAESRST.
Bit 3 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

Bit 2 CRYPRSTS: CRYP reset

Written at 1 to set CRYPRST.
Bit 1 HASHRSTS: HASH reset
Written at 1 to set HASHRST.
Bit 0 RNGRSTS: RNG reset
Written at 1 to set RNGRST.

14.10.135 RCC AHB4 reset register (RCC_AHB4RSTSR)

Address offset: 0xA1C
Reset value: 0x0000 0000
This register is used to reset the RCC AHB4. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCR PWRR GPIOQ
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
STS STS RSTS
w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOP GPIOO GPION GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Res. Res. Res. Res. Res.
RSTS RSTS RSTS RSTS RSTS RSTS RSTS RSTS RSTS RSTS RSTS
w w w w w w w w w w w

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 CRCRSTS: CRC reset
Written at 1 to set CRCRST.
Bit 18 PWRRSTS: PWR reset
Written at 1 to set PWRRST.
Bit 17 Reserved, must be kept at reset value.
Bit 16 GPIOQRSTS: GPIO Q reset
Written at 1 to set GPIOQRST.
Bit 15 GPIOPRSTS: GPIO P reset
Written at 1 to set GPIOPRST.
Bit 14 GPIOORSTS: GPIO O reset
Written at 1 to set GPIOORST.
Bit 13 GPIONRSTS: GPIO N reset
Written at 1 to set GPIONRST.
Bits 12:8 Reserved, must be kept at reset value.
Bit 7 GPIOHRSTS: GPIO H reset
Written at 1 to set GPIOHRST.
Bit 6 GPIOGRSTS: GPIO G reset
Written at 1 to set GPIOGRST.
Bit 5 GPIOFRSTS: GPIO F reset
Written at 1 to set GPIOFRST.

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Bit 4 GPIOERSTS: GPIO E reset

Written at 1 to set GPIOERST.
Bit 3 GPIODRSTS: GPIO D reset
Written at 1 to set GPIODRST.
Bit 2 GPIOCRSTS: GPIO C reset
Written at 1 to set GPIOCRST.
Bit 1 GPIOBRSTS: GPIO B reset
Written at 1 to set GPIOBRST.
Bit 0 GPIOARSTS: GPIO A reset
Written at 1 to set GPIOARST.

14.10.136 RCC AHB5 reset register (RCC_AHB5RSTSR)

Address offset: 0xA20
Reset value: 0x0000 0000
This register is used to reset the RCC AHB5. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CACHE OTGP OTGP OTG2P OTG1P GFXM
NPURS OTG2R OTG1R ETH1R GPU2D XSPI3
AXIRS HY2RS HY1RS HYCTL HYCTL Res. Res. MURS Res. Res.
TS STS STS STS RSTS RSTS
TS TS TS RSTS RSTS TS
w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMM SDMM HPDM
XSPIM XSPI2 PSSIR XSPI1 FMCR JPEGR DMA2D
Res. Res. Res. Res. Res. C1RST C2RST Res. A1RST
RSTS RSTS STS RSTS STS STS RSTS
S S S
w w w w w w w w w w

Bit 31 NPURSTS: NPU reset

Written at 1 to set NPURST.
Bit 30 CACHEAXIRSTS: CACHEAXI reset
Written at 1 to set CACHEAXIRST.
Bit 29 OTG2RSTS: OTG2 reset
Written at 1 to set OTG2RST.
Bit 28 OTGPHY2RSTS: OTGPHY2 reset
Written at 1 to set OTGPHY2RST.
Bit 27 OTGPHY1RSTS: OTGPHY1 reset
Written at 1 to set OTGPHY1RST.
Bit 26 OTG1RSTS: OTG1 reset
Written at 1 to set OTG1RST.
Bit 25 ETH1RSTS: ETH1 reset
Written at 1 to set ETH1RST.
Bit 24 OTG2PHYCTLRSTS: OTG2PHYCTL reset
Written at 1 to set OTG2PHYCTLRST.

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RM0486 Reset and clock control (RCC)

Bit 23 OTG1PHYCTLRSTS: OTG1PHYCTL reset

Written at 1 to set OTG1PHYCTLRST.
Bits 22:21 Reserved, must be kept at reset value.
Bit 20 GPU2DRSTS: GPU2D reset
Written at 1 to set GPU2DRST.
Bit 19 GFXMMURSTS: GFXMMU reset
Written at 1 to set GFXMMURST.
Bit 18 Reserved, must be kept at reset value.
Bit 17 XSPI3RSTS: XSPI3 reset
Written at 1 to set XSPI3RST.
Bits 16:14 Reserved, must be kept at reset value.
Bit 13 XSPIMRSTS: XSPIM reset
Written at 1 to set XSPIMRST.
Bit 12 XSPI2RSTS: XSPI2 reset
Written at 1 to set XSPI2RST.
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 SDMMC1RSTS: SDMMC1 reset
Written at 1 to set SDMMC1RST.
Bit 7 SDMMC2RSTS: SDMMC2 reset
Written at 1 to set SDMMC2RST.
Bit 6 PSSIRSTS: PSSI reset
Written at 1 to set PSSIRST.
Bit 5 XSPI1RSTS: XSPI1 reset
Written at 1 to set XSPI1RST.
Bit 4 FMCRSTS: FMC reset
Written at 1 to set FMCRST.
Bit 3 JPEGRSTS: JPEG reset
Written at 1 to set JPEGRST.
Bit 2 Reserved, must be kept at reset value.
Bit 1 DMA2DRSTS: DMA2D reset
Written at 1 to set DMA2DRST.
Bit 0 HPDMA1RSTS: HPDMA1 reset
Written at 1 to set HPDMA1RST.

14.10.137 RCC APB1L reset register (RCC_APB1LRSTSR)

Address offset: 0xA24
Reset value: 0x0000 0000
This register is used to reset the RCC APB1L. It is reset by sys_rstn, and is in the VCORE
voltage domain.

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPDIF
UART8 UART7 I3C2RS I3C1RS I2C3RS I2C2RS I2C1RS UART5 UART4 USART USART
Res. Res. Res. Res. RX1RS
RSTS RSTS TS TS TS TS TS RSTS RSTS 3RSTS 2RSTS
TS
w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3R SPI2R TIM11R TIM10 WWDG LPTIM1 TIM14 TIM13 TIM12 TIM7R TIM6R TIM5R TIM4R TIM3R TIM2R
Res.
STS STS STS RSTS RSTS RSTS RSTS RSTS RSTS STS STS STS STS STS STS
w w w w w w w w w w w w w w w

Bit 31 UART8RSTS: UART8 reset

Written at 1 to set UART8RST.
Bit 30 UART7RSTS: UART7 reset
Written at 1 to set UART7RST.
Bits 29:26 Reserved, must be kept at reset value.
Bit 25 I3C2RSTS: I3C2 reset
Written at 1 to set I3C2RST.
Bit 24 I3C1RSTS: I3C1 reset
Written at 1 to set I3C1RST.
Bit 23 I2C3RSTS: I2C3 reset
Written at 1 to set I2C3RST.
Bit 22 I2C2RSTS: I2C2 reset
Written at 1 to set I2C2RST.
Bit 21 I2C1RSTS: I2C1 reset
Written at 1 to set I2C1RST.
Bit 20 UART5RSTS: UART5 reset
Written at 1 to set UART5RST.
Bit 19 UART4RSTS: UART4 reset
Written at 1 to set UART4RST.
Bit 18 USART3RSTS: USART3 reset
Written at 1 to set USART3RST.
Bit 17 USART2RSTS: USART2 reset
Written at 1 to set USART2RST.
Bit 16 SPDIFRX1RSTS: SPDIFRX1 reset
Written at 1 to set SPDIFRX1RST.
Bit 15 SPI3RSTS: SPI3 reset
Written at 1 to set SPI3RST.
Bit 14 SPI2RSTS: SPI2 reset
Written at 1 to set SPI2RST.
Bit 13 TIM11RSTS: TIM11 reset
Written at 1 to set TIM11RST.
Bit 12 TIM10RSTS: TIM10 reset
Written at 1 to set TIM10RST.

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Bit 11 WWDGRSTS: WWDG reset

Written at 1 to set WWDGRST.
Bit 10 Reserved, must be kept at reset value.
Bit 9 LPTIM1RSTS: LPTIM1 reset
Written at 1 to set LPTIM1RST.
Bit 8 TIM14RSTS: TIM14 reset
Written at 1 to set TIM14RST.
Bit 7 TIM13RSTS: TIM13 reset
Written at 1 to set TIM13RST.
Bit 6 TIM12RSTS: TIM12 reset
Written at 1 to set TIM12RST.
Bit 5 TIM7RSTS: TIM7 reset
Written at 1 to set TIM7RST.
Bit 4 TIM6RSTS: TIM6 reset
Written at 1 to set TIM6RST.
Bit 3 TIM5RSTS: TIM5 reset
Written at 1 to set TIM5RST.
Bit 2 TIM4RSTS: TIM4 reset
Written at 1 to set TIM4RST.
Bit 1 TIM3RSTS: TIM3 reset
Written at 1 to set TIM3RST.
Bit 0 TIM2RSTS: TIM2 reset
Written at 1 to set TIM2RST.

14.10.138 RCC APB1H reset register (RCC_APB1HRSTSR)

Address offset: 0xA28
Reset value: 0x0000 0000
This register is used to reset the RCC APB1H. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RSTS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN MDIOS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RSTS RSTS
w w

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 UCPD1RSTS: UCPD1 reset
Written at 1 to set UCPD1RST.
Bits 17:9 Reserved, must be kept at reset value.

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Bit 8 FDCANRSTS: FDCAN reset

Written at 1 to set FDCANRST.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 MDIOSRSTS: MDIOS reset
Written at 1 to set MDIOSRST.
Bits 4:0 Reserved, must be kept at reset value.

14.10.139 RCC APB2 reset register (RCC_APB2RSTSR)

Address offset: 0xA2C
Reset value: 0x0000 0000
This register is used to reset the RCC APB2. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAI2R SAI1R SPI5R TIM9R TIM17 TIM16 TIM15
Res. Res. Res. Res. Res. Res. Res. Res. Res.
STS STS STS STS RSTS RSTS RSTS
w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART
TIM18 SPI4R SPI1R UART9 USART USART TIM8R TIM1R
Res. Res. Res. Res. Res. 10RST Res. Res.
RSTS STS STS RSTS 6RSTS 1RSTS STS STS
S
w w w w w w w w w

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 SAI2RSTS: SAI2 reset
Written at 1 to set SAI2RST.
Bit 21 SAI1RSTS: SAI1 reset
Written at 1 to set SAI1RST.
Bit 20 SPI5RSTS: SPI5 reset
Written at 1 to set SPI5RST.
Bit 19 TIM9RSTS: TIM9 reset
Written at 1 to set TIM9RST.
Bit 18 TIM17RSTS: TIM17 reset
Written at 1 to set TIM17RST.
Bit 17 TIM16RSTS: TIM16 reset
Written at 1 to set TIM16RST.
Bit 16 TIM15RSTS: TIM15 reset
Written at 1 to set TIM15RST.
Bit 15 TIM18RSTS: TIM18 reset
Written at 1 to set TIM18RST.
Bit 14 Reserved, must be kept at reset value.
Bit 13 SPI4RSTS: SPI4 reset
Written at 1 to set SPI4RST.

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RM0486 Reset and clock control (RCC)

Bit 12 SPI1RSTS: SPI1 reset

Written at 1 to set SPI1RST.
Bits 11:8 Reserved, must be kept at reset value.
Bit 7 USART10RSTS: USART10 reset
Written at 1 to set USART10RST.
Bit 6 UART9RSTS: UART9 reset
Written at 1 to set UART9RST.
Bit 5 USART6RSTS: USART6 reset
Written at 1 to set USART6RST.
Bit 4 USART1RSTS: USART1 reset
Written at 1 to set USART1RST.
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8RSTS: TIM8 reset
Written at 1 to set TIM8RST.
Bit 0 TIM1RSTS: TIM1 reset
Written at 1 to set TIM1RST.

14.10.140 RCC APB4L reset register (RCC_APB4LRSTSR)

Address offset: 0xA34
Reset value: 0x0000 0000
This register is used to reset the RCC APB4L. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCRS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
TS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFB LPUAR
LPTIM5 LPTIM4 LPTIM3 LPTIM2 I2C4RS SPI6R HDPRS
UFRST Res. Res. Res. Res. Res. T1RST Res. Res.
RSTS RSTS RSTS RSTS TS STS TS
S S
w w w w w w w w w

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 RTCRSTS: RTC reset
Written at 1 to set RTCRST.
Bit 15 VREFBUFRSTS: VREFBUF reset
Written at 1 to set VREFBUFRST.
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 LPTIM5RSTS: LPTIM5 reset
Written at 1 to set LPTIM5RST.
Bit 11 LPTIM4RSTS: LPTIM4 reset
Written at 1 to set LPTIM4RST.

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Bit 10 LPTIM3RSTS: LPTIM3 reset

Written at 1 to set LPTIM3RST.
Bit 9 LPTIM2RSTS: LPTIM2 reset
Written at 1 to set LPTIM2RST.
Bit 8 Reserved, must be kept at reset value.
Bit 7 I2C4RSTS: I2C4 reset
Written at 1 to set I2C4RST.
Bit 6 Reserved, must be kept at reset value.
Bit 5 SPI6RSTS: SPI6 reset
Written at 1 to set SPI6RST.
Bit 4 Reserved, must be kept at reset value.
Bit 3 LPUART1RSTS: LPUART1 reset
Written at 1 to set LPUART1RST.
Bit 2 HDPRSTS: HDP reset
Written at 1 to set HDPRST.
Bits 1:0 Reserved, must be kept at reset value.

14.10.141 RCC APB4H reset register (RCC_APB4HRSTSR)

Address offset: 0xA38
Reset value: 0x0000 0000
This register is used to reset the RCC APB4H. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTSRS SYSCF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
TS GRSTS
w w

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 DTSRSTS: DTS reset
Written at 1 to set DTSRST.
Bit 1 Reserved, must be kept at reset value.
Bit 0 SYSCFGRSTS: SYSCFG reset
Written at 1 to set SYSCFGRST.

14.10.142 RCC APB5 reset register (RCC_APB5RSTSR)

Address offset: 0xA3C
Reset value: 0x0000 0000

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This register is used to reset the RCC APB5. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSIRS VENCR GFXTI DCMIP LTDCR
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
TS STS MRSTS PRSTS STS
w w w w w

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 CSIRSTS: CSI reset
Written at 1 to set CSIRST.
Bit 5 VENCRSTS: VENC reset
Written at 1 to set VENCRST.
Bit 4 GFXTIMRSTS: GFXTIM reset
Written at 1 to set GFXTIMRST.
Bit 3 Reserved, must be kept at reset value.
Bit 2 DCMIPPRSTS: DCMIPP reset
Written at 1 to set DCMIPPRST.
Bit 1 LTDCRSTS: LTDC reset
Written at 1 to set LTDCRST.
Bit 0 Reserved, must be kept at reset value.

14.10.143 RCC divider enable register (RCC_DIVENSR)

Address offset: 0xA40
Reset value: 0x0000 0000
This register is used to enable the RCC IC dividers in Run, Sleep, or Stop mode. It is reset
by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IC20 IC19 IC18 IC17
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ENS ENS ENS ENS
w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC16 IC15 IC14 IC13 IC12 IC11 IC10 IC9 IC8 IC7 IC6 IC5 IC4 IC3 IC2 IC1
ENS ENS ENS ENS ENS ENS ENS ENS ENS ENS ENS ENS ENS ENS ENS ENS
w w w w w w w w w w w w w w w w

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 IC20ENS: IC20 enable
Written at 1 to set IC20EN.
Bit 18 IC19ENS: IC19 enable
Written at 1 to set IC19EN.

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Bit 17 IC18ENS: IC18 enable

Written at 1 to set IC18EN.
Bit 16 IC17ENS: IC17 enable
Written at 1 to set IC17EN.
Bit 15 IC16ENS: IC16 enable
Written at 1 to set IC16EN.
Bit 14 IC15ENS: IC15 enable
Written at 1 to set IC15EN.
Bit 13 IC14ENS: IC14 enable
Written at 1 to set IC14EN.
Bit 12 IC13ENS: IC13 enable
Written at 1 to set IC13EN.
Bit 11 IC12ENS: IC12 enable
Written at 1 to set IC12EN.
Bit 10 IC11ENS: IC11 enable
Written at 1 to set IC11EN.
Bit 9 IC10ENS: IC10 enable
Written at 1 to set IC10EN.
Bit 8 IC9ENS: IC9 enable
Written at 1 to set IC9EN.
Bit 7 IC8ENS: IC8 enable
Written at 1 to set IC8EN.
Bit 6 IC7ENS: IC7 enable
Written at 1 to set IC7EN.
Bit 5 IC6ENS: IC6 enable
Written at 1 to set IC6EN.
Bit 4 IC5ENS: IC5 enable
Written at 1 to set IC5EN.
Bit 3 IC4ENS: IC4 enable
Written at 1 to set IC4EN.
Bit 2 IC3ENS: IC3 enable
Written at 1 to set IC3EN.
Bit 1 IC2ENS: IC2 enable
Written at 1 to set IC2EN.
Bit 0 IC1ENS: IC1 enable
Written at 1 to set IC1EN.

14.10.144 RCC bus enable register (RCC_BUSENSR)

Address offset: 0xA44
Reset value: 0x0000 0000

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This register is used to enable the RCC bus in Run and Sleep modes (in Sleep mode, each
bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACLKN ACLKN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
CENS ENS
w w

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 ACLKNCENS: ACLKNC enable
Written at 1 to set ACLKNCEN.
Bit 0 ACLKNENS: ACLKN enable
Written at 1 to set ACLKNEN.

14.10.145 RCC miscellaneous enable register (RCC_MISCENSR)

Address offset: 0xA48
Reset value: 0x0000 0000
This register is used to enable the RCC miscellaneous in Run and Sleep modes (in Sleep
mode, each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in
the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XSPIP
PEREN HYCO MCO2 MCO1 DBGE
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
S MPEN ENS ENS NS
S
w w w w w

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 PERENS: PER enable
Written at 1 to set PEREN.
Bits 5:4 Reserved, must be kept at reset value.
Bit 3 XSPIPHYCOMPENS: XSPIPHYCOMP enable
Written at 1 to set XSPIPHYCOMPEN.
Bit 2 MCO2ENS: MCO2 enable
Written at 1 to set MCO2EN.
Bit 1 MCO1ENS: MCO1 enable
Written at 1 to set MCO1EN.

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Bit 0 DBGENS: DBG enable

Written at 1 to set DBGEN.

14.10.146 RCC memory enable register (RCC_MEMENSR)

Address offset: 0xA4C
Reset value: 0x0000 0000
This register is used to enable the RCC memory in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOT VENCR CACHE FLEXR AXISR AXISR BKPSR AHBSR AHBSR AXISR AXISR AXISR AXISR
Res. Res. Res. ROME AMEN AXIRA AMEN AM2EN AM1EN AMEN AM2EN AM1EN AM6EN AM5EN AM4EN AM3EN
NS S MENS S S S S S S S S S S
w w w w w w w w w w w w w

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 BOOTROMENS: BootROM enable
Written at 1 to set BOOTROMEN.
Bit 11 VENCRAMENS: VENCRAM enable
Written at 1 to set VENCRAMEN.
Bit 10 CACHEAXIRAMENS: CACHEAXIRAM enable
Written at 1 to set CACHEAXIRAMEN.
Bit 9 FLEXRAMENS: FLEXRAM enable
Written at 1 to set FLEXRAMEN.
Bit 8 AXISRAM2ENS: AXISRAM2 enable
Written at 1 to set AXISRAM2EN.
Bit 7 AXISRAM1ENS: AXISRAM1 enable
Written at 1 to set AXISRAM1EN.
Bit 6 BKPSRAMENS: BKPSRAM enable
Written at 1 to set BKPSRAMEN.
Bit 5 AHBSRAM2ENS: AHBSRAM2 enable
Written at 1 to set AHBSRAM2EN.
Bit 4 AHBSRAM1ENS: AHBSRAM1 enable
Written at 1 to set AHBSRAM1EN.
Bit 3 AXISRAM6ENS: AXISRAM6 enable
Written at 1 to set AXISRAM6EN.
Bit 2 AXISRAM5ENS: AXISRAM5 enable
Written at 1 to set AXISRAM5EN.
Bit 1 AXISRAM4ENS: AXISRAM4 enable
Written at 1 to set AXISRAM4EN.

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RM0486 Reset and clock control (RCC)

Bit 0 AXISRAM3ENS: AXISRAM3 enable

Written at 1 to set AXISRAM3EN.

14.10.147 RCC AHB1 enable register (RCC_AHB1ENSR)

Address offset: 0xA50
Reset value: 0x0000 0000
This register is used to enable the RCC AHB1 in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is
in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC12 GPDM
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ENS A1ENS
w w

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 ADC12ENS: ADC12 enable
Written at 1 to set ADC12EN.
Bit 4 GPDMA1ENS: GPDMA1 enable
Written at 1 to set GPDMA1EN.
Bits 3:0 Reserved, must be kept at reset value.

14.10.148 RCC AHB2 enable register (RCC_AHB2ENSR)

Address offset: 0xA54
Reset value: 0x0000 0000
This register is used to enable the RCC AHB2 in Run and Sleep modes (in Sleep mode,
each bit of this registers is AND-ed with the LPEN bit). It is reset by sys_rstn, and is
in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADF1E MDF1E
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
NS NS
w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAMC
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
FGENS
w

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 ADF1ENS: ADF1 enable
Written at 1 to set ADF1EN.

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Bit 16 MDF1ENS: MDF1 enable

Written at 1 to set MDF1EN.
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 RAMCFGENS: RAMCFG enable
Written at 1 to set RAMCFGEN.
Bits 11:0 Reserved, must be kept at reset value.

14.10.149 RCC AHB3 enable register (RCC_AHB3ENSR)

Address offset: 0xA58
Reset value: 0x0000 0000
This register is used to enable the RCC AHB3 in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RISAF IACEN RIFSC PKAEN SAESE CRYPE HASHE RNGE
Res. Res. Res. Res. Res. Res. Res. Res.
ENS S ENS S NS NS NS NS
w w w w w w w w

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 RISAFENS: RISAF enable
Written at 1 to set RISAFEN.
Bits 13:11 Reserved, must be kept at reset value.
Bit 10 IACENS: IAC enable
Written at 1 to set IACEN.
Bit 9 RIFSCENS: RIFSC enable
Written at 1 to set RIFSCEN.
Bit 8 PKAENS: PKA enable
Written at 1 to set PKAEN.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 SAESENS: SAES enable
Written at 1 to set SAESEN.
Bit 3 Reserved, must be kept at reset value.
Bit 2 CRYPENS: CRYP enable
Written at 1 to set CRYPEN.
Bit 1 HASHENS: HASH enable
Written at 1 to set HASHEN.
Bit 0 RNGENS: RNG enable
Written at 1 to set RNGEN.

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RM0486 Reset and clock control (RCC)

14.10.150 RCC AHB4 enable register (RCC_AHB4ENSR)

Address offset: 0xA5C
Reset value: 0x0000 0000
This register is used to enable the RCC AHB4 in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCE PWRE GPIOQ
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
NS NS ENS
w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOP GPIOO GPION GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Res. Res. Res. Res. Res.
ENS ENS ENS ENS ENS ENS ENS ENS ENS ENS ENS
w w w w w w w w w w w

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 CRCENS: CRC enable
Written at 1 to set CRCEN.
Bit 18 PWRENS: PWR enable
Written at 1 to set PWREN.
Bit 17 Reserved, must be kept at reset value.
Bit 16 GPIOQENS: GPIO Q enable
Written at 1 to set GPIOQEN.
Bit 15 GPIOPENS: GPIO P enable
Written at 1 to set GPIOPEN.
Bit 14 GPIOOENS: GPIO O enable
Written at 1 to set GPIOOEN.
Bit 13 GPIONENS: GPIO N enable
Written at 1 to set GPIONEN.
Bits 12:8 Reserved, must be kept at reset value.
Bit 7 GPIOHENS: GPIO H enable
Written at 1 to set GPIOHEN.
Bit 6 GPIOGENS: GPIO G enable
Written at 1 to set GPIOGEN.
Bit 5 GPIOFENS: GPIO F enable
Written at 1 to set GPIOFEN.
Bit 4 GPIOEENS: GPIO E enable
Written at 1 to set GPIOEEN.
Bit 3 GPIODENS: GPIO D enable
Written at 1 to set GPIODEN.
Bit 2 GPIOCENS: GPIO C enable
Written at 1 to set GPIOCEN.

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Bit 1 GPIOBENS: GPIO B enable

Written at 1 to set GPIOBEN.
Bit 0 GPIOAENS: GPIO A enable
Written at 1 to set GPIOAEN.

14.10.151 RCC AHB5 enable register (RCC_AHB5ENSR)

Address offset: 0xA60
Reset value: 0x0000 0000
This register is used to enable the RCC AHB5 in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CACHE OTGP OTGP GFXM
NPUEN OTG2E OTG1E ETH1E ETH1R ETH1T ETH1M GPU2D MCE4E XSPI3E MCE3E
AXIEN HY2EN HY1EN Res. MUEN
S NS NS NS XENS XENS ACENS ENS NS NS NS
S S S S
w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCE2E MCE1E XSPIM XSPI2E SDMM SDMM PSSIE XSPI1E FMCE JPEGE DMA2D HPDM
Res. Res. Res. Res.
NS NS ENS NS C1ENS C2ENS NS NS NS NS ENS A1ENS
w w w w w w w w w w w w

Bit 31 NPUENS: NPU enable

Written at 1 to set NPUEN.
Bit 30 CACHEAXIENS: CACHEAXI enable
Written at 1 to set CACHEAXIEN.
Bit 29 OTG2ENS: OTG2 enable
Written at 1 to set OTG2EN.
Bit 28 OTGPHY2ENS: OTGPHY2 enable
Written at 1 to set OTGPHY2EN.
Bit 27 OTGPHY1ENS: OTGPHY1 enable
Written at 1 to set OTGPHY1EN.
Bit 26 OTG1ENS: OTG1 enable
Written at 1 to set OTG1EN.
Bit 25 ETH1ENS: ETH1 enable
Written at 1 to set ETH1EN.
Bit 24 ETH1RXENS: ETH1RX enable
Written at 1 to set ETH1RXEN.
Bit 23 ETH1TXENS: ETH1TX enable
Written at 1 to set ETH1TXEN.
Bit 22 ETH1MACENS: ETH1MAC enable
Written at 1 to set ETH1MACEN.
Bit 21 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

Bit 20 GPU2DENS: GPU2D enable

Written at 1 to set GPU2DEN.
Bit 19 GFXMMUENS: GFXMMU enable
Written at 1 to set GFXMMUEN.
Bit 18 MCE4ENS: MCE4 enable
Written at 1 to set MCE4EN.
Bit 17 XSPI3ENS: XSPI3 enable
Written at 1 to set XSPI3EN.
Bit 16 MCE3ENS: MCE3 enable
Written at 1 to set MCE3EN.
Bit 15 MCE2ENS: MCE2 enable
Written at 1 to set MCE2EN.
Bit 14 MCE1ENS: MCE1 enable
Written at 1 to set MCE1EN.
Bit 13 XSPIMENS: XSPIM enable
Written at 1 to set XSPIMEN.
Bit 12 XSPI2ENS: XSPI2 enable
Written at 1 to set XSPI2EN.
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 SDMMC1ENS: SDMMC1 enable
Written at 1 to set SDMMC1EN.
Bit 7 SDMMC2ENS: SDMMC2 enable
Written at 1 to set SDMMC2EN.
Bit 6 PSSIENS: PSSI enable
Written at 1 to set PSSIEN.
Bit 5 XSPI1ENS: XSPI1 enable
Written at 1 to set XSPI1EN.
Bit 4 FMCENS: FMC enable
Written at 1 to set FMCEN.
Bit 3 JPEGENS: JPEG enable
Written at 1 to set JPEGEN.
Bit 2 Reserved, must be kept at reset value.
Bit 1 DMA2DENS: DMA2D enable
Written at 1 to set DMA2DEN.
Bit 0 HPDMA1ENS: HPDMA1 enable
Written at 1 to set HPDMA1EN.

14.10.152 RCC APB1L enable register (RCC_APB1LENSR)

Address offset: 0xA64
Reset value: 0x0000 0000

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This register is used to enable the RCC APB1L in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPDIF
UART8 UART7 I3C2EN I3C1EN I2C3EN I2C2EN I2C1EN UART5 UART4 USART USART
Res. Res. Res. Res. RX1EN
ENS ENS S S S S S ENS ENS 3ENS 2ENS
S
w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3E SPI2E TIM11E TIM10E WWDG LPTIM1 TIM14E TIM13E TIM12E TIM7E TIM6E TIM5E TIM4E TIM3E TIM2E
Res.
NS NS NS NS ENS ENS NS NS NS NS NS NS NS NS NS
w w w w w w w w w w w w w w w

Bit 31 UART8ENS: UART8 enable

Written at 1 to set UART8EN.
Bit 30 UART7ENS: UART7 enable
Written at 1 to set UART7EN.
Bits 29:26 Reserved, must be kept at reset value.
Bit 25 I3C2ENS: I3C2 enable
Written at 1 to set I3C2EN.
Bit 24 I3C1ENS: I3C1 enable
Written at 1 to set I3C1EN.
Bit 23 I2C3ENS: I2C3 enable
Written at 1 to set I2C3EN.
Bit 22 I2C2ENS: I2C2 enable
Written at 1 to set I2C2EN.
Bit 21 I2C1ENS: I2C1 enable
Written at 1 to set I2C1EN.
Bit 20 UART5ENS: UART5 enable
Written at 1 to set UART5EN.
Bit 19 UART4ENS: UART4 enable
Written at 1 to set UART4EN.
Bit 18 USART3ENS: USART3 enable
Written at 1 to set USART3EN.
Bit 17 USART2ENS: USART2 enable
Written at 1 to set USART2EN.
Bit 16 SPDIFRX1ENS: SPDIFRX1 enable
Written at 1 to set SPDIFRX1EN.
Bit 15 SPI3ENS: SPI3 enable
Written at 1 to set SPI3EN.
Bit 14 SPI2ENS: SPI2 enable
Written at 1 to set SPI2EN.
Bit 13 TIM11ENS: TIM11 enable
Written at 1 to set TIM11EN.

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RM0486 Reset and clock control (RCC)

Bit 12 TIM10ENS: TIM10 enable

Written at 1 to set TIM10EN.
Bit 11 WWDGENS: WWDG enable
Written at 1 to set WWDGEN.
Bit 10 Reserved, must be kept at reset value.
Bit 9 LPTIM1ENS: LPTIM1 enable
Written at 1 to set LPTIM1EN.
Bit 8 TIM14ENS: TIM14 enable
Written at 1 to set TIM14EN.
Bit 7 TIM13ENS: TIM13 enable
Written at 1 to set TIM13EN.
Bit 6 TIM12ENS: TIM12 enable
Written at 1 to set TIM12EN.
Bit 5 TIM7ENS: TIM7 enable
Written at 1 to set TIM7EN.
Bit 4 TIM6ENS: TIM6 enable
Written at 1 to set TIM6EN.
Bit 3 TIM5ENS: TIM5 enable
Written at 1 to set TIM5EN.
Bit 2 TIM4ENS: TIM4 enable
Written at 1 to set TIM4EN.
Bit 1 TIM3ENS: TIM3 enable
Written at 1 to set TIM3EN.
Bit 0 TIM2ENS: TIM2 enable
Written at 1 to set TIM2EN.

14.10.153 RCC APB1H enable register (RCC_APB1HENSR)

Address offset: 0xA68
Reset value: 0x0000 0000
This register is used to enable the RCC APB1H in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ENS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN MDIOS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ENS ENS
w w

Bits 31:19 Reserved, must be kept at reset value.

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Bit 18 UCPD1ENS: UCPD1 enable

Written at 1 to set UCPD1EN.
Bits 17:9 Reserved, must be kept at reset value.
Bit 8 FDCANENS: FDCAN enable
Written at 1 to set FDCANEN.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 MDIOSENS: MDIOS enable
Written at 1 to set MDIOSEN.
Bits 4:0 Reserved, must be kept at reset value.

14.10.154 RCC APB2 enable register (RCC_APB2ENSR)

Address offset: 0xA6C
Reset value: 0x0000 0000
This register is used to enable the RCC APB2 in Run and Sleep modes (in Sleep mode,
each bit in this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAI2E SAI1E SPI5E TIM9E TIM17E TIM16E TIM15E
Res. Res. Res. Res. Res. Res. Res. Res. Res.
NS NS NS NS NS NS NS
w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIM18E SPI4E SPI1E USART UART9 USART USART TIM8E TIM1E
Res. Res. Res. Res. Res. Res. Res.
NS NS NS 10ENS ENS 6ENS 1ENS NS NS
w w w w w w w w w

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 SAI2ENS: SAI2 enable
Written at 1 to set SAI2EN.
Bit 21 SAI1ENS: SAI1 enable
Written at 1 to set SAI1EN.
Bit 20 SPI5ENS: SPI5 enable
Written at 1 to set SPI5EN.
Bit 19 TIM9ENS: TIM9 enable
Written at 1 to set TIM9EN.
Bit 18 TIM17ENS: TIM17 enable
Written at 1 to set TIM17EN.
Bit 17 TIM16ENS: TIM16 enable
Written at 1 to set TIM16EN.
Bit 16 TIM15ENS: TIM15 enable
Written at 1 to set TIM15EN.
Bit 15 TIM18ENS: TIM18 enable
Written at 1 to set TIM18EN.

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RM0486 Reset and clock control (RCC)

Bit 14 Reserved, must be kept at reset value.

Bit 13 SPI4ENS: SPI4 enable
Written at 1 to set SPI4EN.
Bit 12 SPI1ENS: SPI1 enable
Written at 1 to set SPI1EN.
Bits 11:8 Reserved, must be kept at reset value.
Bit 7 USART10ENS: USART10 enable
Written at 1 to set USART10EN.
Bit 6 UART9ENS: UART9 enable
Written at 1 to set UART9EN.
Bit 5 USART6ENS: USART6 enable
Written at 1 to set USART6EN.
Bit 4 USART1ENS: USART1 enable
Written at 1 to set USART1EN.
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8ENS: TIM8 enable
Written at 1 to set TIM8EN.
Bit 0 TIM1ENS: TIM1 enable
Written at 1 to set TIM1EN.

14.10.155 RCC APB3 enable register (RCC_APB3ENSR)

Address offset: 0xA70
Reset value: 0x0000 0000
This register is used to enable the RCC APB3 in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DFTEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
S
w

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 DFTENS: DFT enable
Written at 1 to set DFTEN.
Bits 1:0 Reserved, must be kept at reset value.

14.10.156 RCC APB4L enable register (RCC_APB4LENSR)

Address offset: 0xA74

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Reset value: 0x0000 0000

This register is used to enable the RCC APB4L in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCAP RTCEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
BENS S
w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFB LPTIM5 LPTIM4 LPTIM3 LPTIM2 I2C4EN SPI6E LPUAR HDPEN
Res. Res. Res. Res. Res. Res. Res.
UFENS ENS ENS ENS ENS S NS T1ENS S
w w w w w w w w w

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 RTCAPBENS: RTCAPB enable
Written at 1 to set RTCAPBEN.
Bit 16 RTCENS: RTC enable
Written at 1 to set RTCEN.
Bit 15 VREFBUFENS: VREFBUF enable
Written at 1 to set VREFBUFEN.
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 LPTIM5ENS: LPTIM5 enable
Written at 1 to set LPTIM5EN.
Bit 11 LPTIM4ENS: LPTIM4 enable
Written at 1 to set LPTIM4EN.
Bit 10 LPTIM3ENS: LPTIM3 enable
Written at 1 to set LPTIM3EN.
Bit 9 LPTIM2ENS: LPTIM2 enable
Written at 1 to set LPTIM2EN.
Bit 8 Reserved, must be kept at reset value.
Bit 7 I2C4ENS: I2C4 enable
Written at 1 to set I2C4EN.
Bit 6 Reserved, must be kept at reset value.
Bit 5 SPI6ENS: SPI6 enable
Written at 1 to set SPI6EN.
Bit 4 Reserved, must be kept at reset value.
Bit 3 LPUART1ENS: LPUART1 enable
Written at 1 to set LPUART1EN.
Bit 2 HDPENS: HDP enable
Written at 1 to set HDPEN.
Bits 1:0 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

14.10.157 RCC APB4H enable register (RCC_APB4HENSR)

Address offset: 0xA78
Reset value: 0x0000 0000
This register is used to enable the RCC APB4H in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTSEN BSECE SYSCF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
S NS GENS
w w w

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 DTSENS: DTS enable
Written at 1 to set DTSEN.
Bit 1 BSECENS: BSEC enable
Written at 1 to set BSECEN.
Bit 0 SYSCFGENS: SYSCFG enable
Written at 1 to set SYSCFGEN.

14.10.158 RCC APB5 enable register (RCC_APB5ENSR)

Address offset: 0xA7C
Reset value: 0x0000 0000
This register is used to enable the RCC APB5 in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSIEN VENCE GFXTI DCMIP LTDCE
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
S NS MENS PENS NS
w w w w w

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 CSIENS: CSI enable
Written at 1 to set CSIEN.
Bit 5 VENCENS: VENC enable
Written at 1 to set VENCEN.
Bit 4 GFXTIMENS: GFXTIM enable
Written at 1 to set GFXTIMEN.

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Bit 3 Reserved, must be kept at reset value.

Bit 2 DCMIPPENS: DCMIPP enable
Written at 1 to set DCMIPPEN.
Bit 1 LTDCENS: LTDC enable
Written at 1 to set LTDCEN.
Bit 0 Reserved, must be kept at reset value.

14.10.159 RCC bus sleep enable register (RCC_BUSLPENSR)

Address offset: 0xA84
Reset value: 0x0000 0000
This register is used to enable the RCC bus in Sleep mode (each bit of this register is AND-
ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACLKNC ACLKN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LPENS LPENS
w w

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 ACLKNCLPENS: ACLKNC enable
Written at 1 to set ACLKNCLPEN.
Bit 0 ACLKNLPENS: ACLKN enable
Written at 1 to set ACLKNLPEN.

14.10.160 RCC miscellaneous sleep enable register (RCC_MISCLPENSR)

Address offset: 0xA88
Reset value: 0x0000 0000
This register is used to enable the RCC miscellaneous in Sleep mode (each bit of this
register is AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage
domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XSPIPH
PERLP DBGLP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. YCOMP Res. Res.
ENS ENS
LPENS
w w w

Bits 31:7 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

Bit 6 PERLPENS: PER enable

Written at 1 to set PERLPEN.
Bits 5:4 Reserved, must be kept at reset value.
Bit 3 XSPIPHYCOMPLPENS: XSPIPHYCOMP enable
Written at 1 to set XSPIPHYCOMPLPEN.
Bits 2:1 Reserved, must be kept at reset value.
Bit 0 DBGLPENS: DBG enable
Written at 1 to set DBGLPEN.

14.10.161 RCC memory sleep enable register (RCC_MEMLPENSR)

Address offset: 0xA8C
Reset value: 0x0000 0000
This register is used to enable the RCC memory in Sleep mode (each bit of this register is
AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CACHE
BOOT VENCR FLEXR AXISR AXISR BKPSR AHBSR AHBSR AXISR AXISR AXISR AXISR
AXIRA
Res. Res. Res. ROML AMLPE AMLPE AM2LP AM1LP AMLPE AM2LP AM1LP AM6LP AM5LP AM4LP AM3LP
MLPEN
PENS NS NS ENS ENS NS ENS ENS ENS ENS ENS ENS
S
w w w w w w w w w w w w w

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 BOOTROMLPENS: BootROM enable
Written at 1 to set BOOTROMLPEN.
Bit 11 VENCRAMLPENS: VENCRAM enable
Written at 1 to set VENCRAMLPEN.
Bit 10 CACHEAXIRAMLPENS: CACHEAXIRAM enable
Written at 1 to set CACHEAXIRAMLPEN.
Bit 9 FLEXRAMLPENS: FLEXRAM enable
Written at 1 to set FLEXRAMLPEN.
Bit 8 AXISRAM2LPENS: AXISRAM2 enable
Written at 1 to set AXISRAM2LPEN.
Bit 7 AXISRAM1LPENS: AXISRAM1 enable
Written at 1 to set AXISRAM1LPEN.
Bit 6 BKPSRAMLPENS: BKPSRAM enable
Written at 1 to set BKPSRAMLPEN.
Bit 5 AHBSRAM2LPENS: AHBSRAM2 enable
Written at 1 to set AHBSRAM2LPEN.
Bit 4 AHBSRAM1LPENS: AHBSRAM1 enable
Written at 1 to set AHBSRAM1LPEN.

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Reset and clock control (RCC) RM0486

Bit 3 AXISRAM6LPENS: AXISRAM6 enable

Written at 1 to set AXISRAM6LPEN.
Bit 2 AXISRAM5LPENS: AXISRAM5 enable
Written at 1 to set AXISRAM5LPEN.
Bit 1 AXISRAM4LPENS: AXISRAM4 enable
Written at 1 to set AXISRAM4LPEN.
Bit 0 AXISRAM3LPENS: AXISRAM3 enable
Written at 1 to set AXISRAM3LPEN.

14.10.162 RCC AHB1 sleep enable register (RCC_AHB1LPENSR)

Address offset: 0xA90
Reset value: 0x0000 0000
This register is used to enable the RCC AHB1 in Sleep mode (each bit of this register is
AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC12 GPDMA1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LPENS LPENS
w w

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 ADC12LPENS: ADC12 enable
Written at 1 to set ADC12LPEN.
Bit 4 GPDMA1LPENS: GPDMA1 enable
Written at 1 to set GPDMA1LPEN.
Bits 3:0 Reserved, must be kept at reset value.

14.10.163 RCC AHB2 sleep enable register (RCC_AHB2LPENSR)

Address offset: 0xA94
Reset value: 0x0000 0000
This register is used to enable the RCC AHB2 in Sleep mode (each bit of this register is
AND-ed with the EN bit).It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADF1L MDF1L
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
PENS PENS
w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAMCF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
GLPENS
w

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RM0486 Reset and clock control (RCC)

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 ADF1LPENS: ADF1 enable
Written at 1 to set ADF1LPEN.
Bit 16 MDF1LPENS: MDF1 enable
Written at 1 to set MDF1LPEN.
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 RAMCFGLPENS: RAMCFG enable
Written at 1 to set RAMCFGLPEN.
Bits 11:0 Reserved, must be kept at reset value.

14.10.164 RCC AHB3 sleep enable register (RCC_AHB3LPENSR)

Address offset: 0xA98
Reset value: 0x0000 0000
This register is used to enable the RCC AHB3 in Sleep mode (each bit of this register is
AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RISAFL IACLP RIFSC PKALP SAESL CRYPL HASHL RNGLP
Res. Res. Res. Res. Res. Res. Res. Res.
PENS ENS LPENS ENS PENS PENS PENS ENS
w w w w w w w w

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 RISAFLPENS: RISAF enable
Written at 1 to set RISAFLPEN.
Bits 13:11 Reserved, must be kept at reset value.
Bit 10 IACLPENS: IAC enable in Sleep mode
Written at 1 to set IACLPEN.
Bit 9 RIFSCLPENS: RIFSC enable
Written at 1 to set RIFSCLPEN.
Bit 8 PKALPENS: PKA enable
Written at 1 to set PKALPEN.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 SAESLPENS: SAES enable
Written at 1 to set SAESLPEN.
Bit 3 Reserved, must be kept at reset value.
Bit 2 CRYPLPENS: CRYP enable
Written at 1 to set CRYPLPEN.
Bit 1 HASHLPENS: HASH enable
Written at 1 to set HASHLPEN.

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Bit 0 RNGLPENS: RNG enable

Written at 1 to set RNGLPEN.

14.10.165 RCC AHB4 sleep enable register (RCC_AHB4LPENSR)

Address offset: 0xA9C
Reset value: 0x0000 0000
This register is used to enable the RCC AHB4 in Sleep mode (each bit of this register is
AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCLP PWRL GPIOQ
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ENS PENS LPENS
w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOP GPIOO GPION GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Res. Res. Res. Res. Res.
LPENS LPENS LPENS LPENS LPENS LPENS LPENS LPENS LPENS LPENS LPENS
w w w w w w w w w w w

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 CRCLPENS: CRC enable
Written at 1 to set CRCLPEN.
Bit 18 PWRLPENS: PWR enable
Written at 1 to set PWRLPEN.
Bit 17 Reserved, must be kept at reset value.
Bit 16 GPIOQLPENS: GPIO Q enable
Written at 1 to set GPIOQLPEN.
Bit 15 GPIOPLPENS: GPIO P enable
Written at 1 to set GPIOPLPEN.
Bit 14 GPIOOLPENS: GPIO O enable
Written at 1 to set GPIOOLPEN.
Bit 13 GPIONLPENS: GPIO N enable
Written at 1 to set GPIONLPEN.
Bits 12:8 Reserved, must be kept at reset value.
Bit 7 GPIOHLPENS: GPIO H enable
Written at 1 to set GPIOHLPEN.
Bit 6 GPIOGLPENS: GPIO G enable
Written at 1 to set GPIOGLPEN.
Bit 5 GPIOFLPENS: GPIO F enable
Written at 1 to set GPIOFLPEN.
Bit 4 GPIOELPENS: GPIO E enable
Written at 1 to set GPIOELPEN.
Bit 3 GPIODLPENS: GPIO D enable
Written at 1 to set GPIODLPEN.

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RM0486 Reset and clock control (RCC)

Bit 2 GPIOCLPENS: GPIO C enable

Written at 1 to set GPIOCLPEN.
Bit 1 GPIOBLPENS: GPIO B enable
Written at 1 to set GPIOBLPEN.
Bit 0 GPIOALPENS: GPIO A enable
Written at 1 to set GPIOALPEN.

14.10.166 RCC AHB5 sleep enable register (RCC_AHB5LPENSR)

Address offset: 0xAA0
Reset value: 0x0000 0000
This register is used to enable the RCC AHB5 in Sleep mode (each bit of this register is
AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CACHE OTGP OTGP ETH1R ETH1T ETH1M GFXM
NPULP OTG2L OTG1L ETH1L GPU2D MCE4L XSPI3L MCE3L
AXILPE HY2LP HY1LP XLPEN XLPEN ACLPE Res. MULPE
ENS PENS PENS PENS LPENS PENS PENS PENS
NS ENS ENS S S NS NS
w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMM SDMM HPDM
MCE2L MCE1L XSPIM XSPI2L PSSILP XSPI1L FMCLP JPEGL DMA2D
Res. Res. Res. C1LPE C2LPE Res. A1LPE
PENS PENS LPENS PENS ENS PENS ENS PENS LPENS
NS NS NS
w w w w w w w w w w w w

Bit 31 NPULPENS: NPU enable

Written at 1 to set NPULPEN.
Bit 30 CACHEAXILPENS: CACHEAXI enable
Written at 1 to set CACHEAXILPEN.
Bit 29 OTG2LPENS: OTG2 enable
Written at 1 to set OTG2LPEN.
Bit 28 OTGPHY2LPENS: OTGPHY2 enable
Written at 1 to set OTGPHY2LPEN.
Bit 27 OTGPHY1LPENS: OTGPHY1 enable
Written at 1 to set OTGPHY1LPEN.
Bit 26 OTG1LPENS: OTG1 enable
Written at 1 to set OTG1LPEN.
Bit 25 ETH1LPENS: ETH1 enable
Written at 1 to set ETH1LPEN.
Bit 24 ETH1RXLPENS: ETH1RX enable
Written at 1 to set ETH1RXLPEN.
Bit 23 ETH1TXLPENS: ETH1TX enable
Written at 1 to set ETH1TXLPEN.
Bit 22 ETH1MACLPENS: ETH1MAC enable
Written at 1 to set ETH1MACLPEN.

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Bit 21 Reserved, must be kept at reset value.

Bit 20 GPU2DLPENS: GPU2D enable
Written at 1 to set GPU2DLPEN.
Bit 19 GFXMMULPENS: GFXMMU enable
Written at 1 to set GFXMMULPEN.
Bit 18 MCE4LPENS: MCE4 enable
Written at 1 to set MCE4LPEN.
Bit 17 XSPI3LPENS: XSPI3 enable
Written at 1 to set XSPI3LPEN.
Bit 16 MCE3LPENS: MCE3 enable
Written at 1 to set MCE3LPEN.
Bit 15 MCE2LPENS: MCE2 enable
Written at 1 to set MCE2LPEN.
Bit 14 MCE1LPENS: MCE1 enable
Written at 1 to set MCE1LPEN.
Bit 13 XSPIMLPENS: XSPIM enable
Written at 1 to set XSPIMLPEN.
Bit 12 XSPI2LPENS: XSPI2 enable
Written at 1 to set XSPI2LPEN.
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 SDMMC1LPENS: SDMMC1 enable
Written at 1 to set SDMMC1LPEN.
Bit 7 SDMMC2LPENS: SDMMC2 enable
Written at 1 to set SDMMC2LPEN.
Bit 6 PSSILPENS: PSSI enable
Written at 1 to set PSSILPEN.
Bit 5 XSPI1LPENS: XSPI1 enable
Written at 1 to set XSPI1LPEN.
Bit 4 FMCLPENS: FMC enable
Written at 1 to set FMCLPEN.
Bit 3 JPEGLPENS: JPEG enable
Written at 1 to set JPEGLPEN.
Bit 2 Reserved, must be kept at reset value.
Bit 1 DMA2DLPENS: DMA2D enable
Written at 1 to set DMA2DLPEN.
Bit 0 HPDMA1LPENS: HPDMA1 enable
Written at 1 to set HPDMA1LPEN.

14.10.167 RCC APB1L sleep enable register (RCC_APB1LLPENSR)

Address offset: 0xAA4
Reset value: 0x0000 0000

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RM0486 Reset and clock control (RCC)

This register is used to enable the RCC APB1L in Sleep mode (each bit of this register is
AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USART USART SPDIF
UART8 UART7 I3C2LP I3C1LP I2C3LP I2C2LP I2C1LP UART5 UART4
Res. Res. Res. Res. 3LPEN 2LPEN RX1LP
LPENS LPENS ENS ENS ENS ENS ENS LPENS LPENS
S S ENS
w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3LP SPI2LP TIM11L TIM10L WWDG LPTIM1 TIM14L TIM13L TIM12L TIM7LP TIM6LP TIM5LP TIM4LP TIM3LP TIM2LP
Res.
ENS ENS PENS PENS LPENS LPENS PENS PENS PENS ENS ENS ENS ENS ENS ENS
w w w w w w w w w w w w w w w

Bit 31 UART8LPENS: UART8 enable

Written at 1 to set UART8LPEN.
Bit 30 UART7LPENS: UART7 enable
Written at 1 to set UART7LPEN.
Bits 29:26 Reserved, must be kept at reset value.
Bit 25 I3C2LPENS: I3C2 enable
Written at 1 to set I3C2LPEN.
Bit 24 I3C1LPENS: I3C1 enable
Written at 1 to set I3C1LPEN.
Bit 23 I2C3LPENS: I2C3 enable
Written at 1 to set I2C3LPEN.
Bit 22 I2C2LPENS: I2C2 enable
Written at 1 to set I2C2LPEN.
Bit 21 I2C1LPENS: I2C1 enable
Written at 1 to set I2C1LPEN.
Bit 20 UART5LPENS: UART5 enable
Written at 1 to set UART5LPEN.
Bit 19 UART4LPENS: UART4 enable
Written at 1 to set UART4LPEN.
Bit 18 USART3LPENS: USART3 enable
Written at 1 to set USART3LPEN.
Bit 17 USART2LPENS: USART2 enable
Written at 1 to set USART2LPEN.
Bit 16 SPDIFRX1LPENS: SPDIFRX1 enable
Written at 1 to set SPDIFRX1LPEN.
Bit 15 SPI3LPENS: SPI3 enable
Written at 1 to set SPI3LPEN.
Bit 14 SPI2LPENS: SPI2 enable
Written at 1 to set SPI2LPEN.
Bit 13 TIM11LPENS: TIM11 enable
Written at 1 to set TIM11LPEN.

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Bit 12 TIM10LPENS: TIM10 enable

Written at 1 to set TIM10LPEN.
Bit 11 WWDGLPENS: WWDG enable
Written at 1 to set WWDGLPEN.
Bit 10 Reserved, must be kept at reset value.
Bit 9 LPTIM1LPENS: LPTIM1 enable
Written at 1 to set LPTIM1LPEN.
Bit 8 TIM14LPENS: TIM14 enable
Written at 1 to set TIM14LPEN.
Bit 7 TIM13LPENS: TIM13 enable
Written at 1 to set TIM13LPEN.
Bit 6 TIM12LPENS: TIM12 enable
Written at 1 to set TIM12LPEN.
Bit 5 TIM7LPENS: TIM7 enable
Written at 1 to set TIM7LPEN.
Bit 4 TIM6LPENS: TIM6 enable
Written at 1 to set TIM6LPEN.
Bit 3 TIM5LPENS: TIM5 enable
Written at 1 to set TIM5LPEN.
Bit 2 TIM4LPENS: TIM4 enable
Written at 1 to set TIM4LPEN.
Bit 1 TIM3LPENS: TIM3 enable
Written at 1 to set TIM3LPEN.
Bit 0 TIM2LPENS: TIM2 enable
Written at 1 to set TIM2LPEN.

14.10.168 RCC APB1H sleep enable register (RCC_APB1HLPENSR)

Address offset: 0xAA8
Reset value: 0x0000 0000
This register is used to enable the RCC APB1H in Sleep mode (each bit of this register is
AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LPENS
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN MDIOS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LPENS LPENS
w w

Bits 31:19 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

Bit 18 UCPD1LPENS: UCPD1 enable

Written at 1 to set UCPD1LPEN.
Bits 17:9 Reserved, must be kept at reset value.
Bit 8 FDCANLPENS: FDCAN enable
Written at 1 to set FDCANLPEN.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 MDIOSLPENS: MDIOS enable
Written at 1 to set MDIOSLPEN.
Bits 4:0 Reserved, must be kept at reset value.

14.10.169 RCC APB2 sleep enable register (RCC_APB2LPENSR)

Address offset: 0xAAC
Reset value: 0x0000 0000
This register is used to enable the RCC APB2 in Sleep mode (each bit of this register is
AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAI2LP SAI1LP SPI5LP TIM9LP TIM17L TIM16L TIM15L
Res. Res. Res. Res. Res. Res. Res. Res. Res.
ENS ENS ENS ENS PENS PENS PENS
w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART USART USART
TIM18L SPI4LP SPI1LP UART9 TIM8LP TIM1LP
Res. Res. Res. Res. Res. 10LPE 6LPEN 1LPEN Res. Res.
PENS ENS ENS LPENS ENS ENS
NS S S
w w w w w w w w w

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 SAI2LPENS: SAI2 enable
Written at 1 to set SAI2LPEN.
Bit 21 SAI1LPENS: SAI1 enable
Written at 1 to set SAI1LPEN.
Bit 20 SPI5LPENS: SPI5 enable
Written at 1 to set SPI5LPEN.
Bit 19 TIM9LPENS: TIM9 enable
Written at 1 to set TIM9LPEN.
Bit 18 TIM17LPENS: TIM17 enable
Written at 1 to set TIM17LPEN.
Bit 17 TIM16LPENS: TIM16 enable
Written at 1 to set TIM16LPEN.
Bit 16 TIM15LPENS: TIM15 enable
Written at 1 to set TIM15LPEN.
Bit 15 TIM18LPENS: TIM18 enable
Written at 1 to set TIM18LPEN.

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Bit 14 Reserved, must be kept at reset value.

Bit 13 SPI4LPENS: SPI4 enable
Written at 1 to set SPI4LPEN.
Bit 12 SPI1LPENS: SPI1 enable
Written at 1 to set SPI1LPEN.
Bits 11:8 Reserved, must be kept at reset value.
Bit 7 USART10LPENS: USART10 enable
Written at 1 to set USART10LPEN.
Bit 6 UART9LPENS: UART9 enable
Written at 1 to set UART9LPEN.
Bit 5 USART6LPENS: USART6 enable
Written at 1 to set USART6LPEN.
Bit 4 USART1LPENS: USART1 enable
Written at 1 to set USART1LPEN.
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8LPENS: TIM8 enable
Written at 1 to set TIM8LPEN.
Bit 0 TIM1LPENS: TIM1 enable
Written at 1 to set TIM1LPEN.

14.10.170 RCC APB3 sleep enable register (RCC_APB3LPENSR)

Address offset: 0xAB0
Reset value: 0x0000 0000
This register is used to enable the RCC APB3 in Sleep mode (each bit of this register is
AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DFTLP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ENS
w

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 DFTLPENS: DFT enable
Written at 1 to set DFTLPEN.
Bits 1:0 Reserved, must be kept at reset value.

14.10.171 RCC APB4L sleep enable register (RCC_APB4LLPENSR)

Address offset: 0xAB4
Reset value: 0x0000 0000

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RM0486 Reset and clock control (RCC)

This register is used to enable the RCC APB4L in Sleep mode (each bit of this register is
AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCAP RTCLP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
BLPENS ENS
w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFB LPUAR
LPTIM5 LPTIM4 LPTIM3 LPTIM2 I2C4LP SPI6LP HDPLP
UFLPE Res. Res. Res. Res. Res. T1LPE Res. Res.
LPENS LPENS LPENS LPENS ENS ENS ENS
NS NS
w w w w w w w w w

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 RTCAPBLPENS: RTCAPB enable
Written at 1 to set RTCAPBLPEN.
Bit 16 RTCLPENS: RTC enable
Written at 1 to set RTCLPEN.
Bit 15 VREFBUFLPENS: VREFBUF enable
Written at 1 to set VREFBUFLPEN.
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 LPTIM5LPENS: LPTIM5 enable
Written at 1 to set LPTIM5LPEN.
Bit 11 LPTIM4LPENS: LPTIM4 enable
Written at 1 to set LPTIM4LPEN.
Bit 10 LPTIM3LPENS: LPTIM3 enable
Written at 1 to set LPTIM3LPEN.
Bit 9 LPTIM2LPENS: LPTIM2 enable
Written at 1 to set LPTIM2LPEN.
Bit 8 Reserved, must be kept at reset value.
Bit 7 I2C4LPENS: I2C4 enable
Written at 1 to set I2C4LPEN.
Bit 6 Reserved, must be kept at reset value.
Bit 5 SPI6LPENS: SPI6 enable
Written at 1 to set SPI6LPEN.
Bit 4 Reserved, must be kept at reset value.
Bit 3 LPUART1LPENS: LPUART1 enable
Written at 1 to set LPUART1LPEN.
Bit 2 HDPLPENS: HDP enable
Written at 1 to set HDPLPEN.
Bits 1:0 Reserved, must be kept at reset value.

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14.10.172 RCC APB4H sleep enable register (RCC_APB4HLPENSR)

Address offset: 0xAB8
Reset value: 0x0000 0000
This register is used to enable the RCC APB4H in Sleep mode (each bit of this register is
AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTSLP BSECL SYSCFG
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ENS PENS LPENS
w w w

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 DTSLPENS: DTS enable
Written at 1 to set DTSLPEN.
Bit 1 BSECLPENS: BSEC enable
Written at 1 to set BSECLPEN.
Bit 0 SYSCFGLPENS: SYSCFG enable
Written at 1 to set SYSCFGLPEN.

14.10.173 RCC APB5 sleep enable register (RCC_APB5LPENSR)

Address offset: 0xABC
Reset value: 0x0000 0000
This register is used to enable the RCC APB5 in Sleep mode (each bit of this register is
AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSI VENC GFXTIM DCMIPP LTDC
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LPENS LPENS LPENS LPENS LPENS
w w w w w

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 CSILPENS: CSI enable
Written at 1 to set CSILPEN.
Bit 5 VENCLPENS: VENC enable
Written at 1 to set VENCLPEN.
Bit 4 GFXTIMLPENS: GFXTIM enable
Written at 1 to set GFXTIMLPEN.
Bit 3 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

Bit 2 DCMIPPLPENS: DCMIPP enable

Written at 1 to set DCMIPPLPEN.
Bit 1 LTDCLPENS: LTDC enable
Written at 1 to set LTDCLPEN.
Bit 0 Reserved, must be kept at reset value.

14.10.174 RCC oscillator privilege configuration set register 0

(RCC_PRIVCFGSR0)
Address offset: 0xF84
Reset value: 0x0000 0000
This register is used to control the privileged access rights to the configuration register of
the oscillators. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPRIV bit
defines the privileged protection for the configuration registers of the oscillator: a write
access is denied if the access is unprivileged while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSE HSIP MSI LSE LSI
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
PRIVS RIVS PRIVS PRIVS PRIVS
w w w w w

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 HSEPRIVS: Privileged protection of HSE configuration bits (enable, ready, divider)
Written at 1 to set HSEPRIV by secure privileged software only. It can be read by any
software.
Bit 3 HSIPRIVS: Privileged protection of HSI configuration bits (enable, ready, divider)
Written at 1 to set HSIPRIV by secure privileged software only. It can be read by any
software.
Bit 2 MSIPRIVS: Privileged protection of MSI configuration bits (enable, ready, divider)
Written at 1 to set MSIPRIV by secure privileged software only. It can be read by any
software.
Bit 1 LSEPRIVS: Privileged protection of LSE configuration bits (enable, ready, divider)
Written at 1 to set LSEPRIV by secure privileged software only. It can be read by any
software.
Bit 0 LSIPRIVS: Privileged protection of the LSI configuration bits (enable, ready, divider)
Written at 1 to set LSIPRIV by secure privileged software only. It can be read by any
software.

14.10.175 RCC oscillator public configuration set register 0

(RCC_PUBCFGSR0)
Address offset: 0xF8C
Reset value: 0x0000 0000

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Reset and clock control (RCC) RM0486

This register is used to control the public access rights to the configuration register of the
oscillators. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPUB bit
defines the public protection for the configuration registers of the oscillator: a write access is
denied if the access is non-public while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSE HSI MSI LSE LSI
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
PUBS PUBS PUBS PUBS PUBS
w w w w w

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 HSEPUBS: Public protection of he HSE configuration bits (enable, ready, divider)
Written at 1 to set HSEPUB by secure privileged software only. It can be read by any
software.
Bit 3 HSIPUBS: Public protection of HSI configuration bits (enable, ready, divider)
Written at 1 to set HSIPUB by secure privileged software only. It can be read by any software.
Bit 2 MSIPUBS: Public protection of MSI configuration bits (enable, ready, divider)
Written at 1 to set MSIPUB by secure privileged software only. It can be read by any
software.
Bit 1 LSEPUBS: Public protection of LSE configuration bits (enable, ready, divider)
Written at 1 to set LSEPUB by secure privileged software only. It can be read by any
software.
Bit 0 LSIPUBS: Public protection of LSI configuration bits (enable, ready, divider)
Written at 1 to set LSIPUB by secure privileged software only. It can be read by any software.

14.10.176 RCC PLL privilege configuration set register 1 (RCC_PRIVCFGSR1)

Address offset: 0xF94
Reset value: 0x0000 0000
This register is used to control the privileged access rights to the configuration register of
the PLLs. It is reset by sys_rst, and is in the VCORE voltage domain. Each xxPRIV bit defines
the privileged protection for the configuration registers of the PLL: a write access is denied if
the access is unprivilege while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4P PLL3P PLL2P PLL1P
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RIVS RIVS RIVS RIVS
w w w w

Bits 31:4 Reserved, must be kept at reset value.

686/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bit 3 PLL4PRIVS: Privileged protection of PLL4 configuration bits (enable, ready, divider)
Written at 1 to set PLL4PRIV by secure privileged software only. It can be read by any
software.
Bit 2 PLL3PRIVS: Privileged protection of PLL3 configuration bits (enable, ready, divider)
Written at 1 to set PLL3PRIV by secure privileged software only. It can be read by any
software.
Bit 1 PLL2PRIVS: Privileged protection of PLL2 configuration bits (enable, ready, divider)
Written at 1 to set PLL2PRIV by secure privileged software only. It can be read by any
software.
Bit 0 PLL1PRIVS: Privileged protection of PLL1 configuration bits (enable, ready, divider)
Written at 1 to set PLL1PRIV by secure privileged software only. It can be read by any
software.

14.10.177 RCC PLL public configuration set register 1 (RCC_PUBCFGSR1)

Address offset: 0xF9C
Reset value: 0x0000 0000
This register is used to control the public access rights to the configuration register of the
PLLs. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPUB bit defines
the public protection for the configuration registers of the PLL: a write access is denied if the
access is non-public while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4P PLL3P PLL2P PLL1P
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
UBS UBS UBS UBS
w w w w

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 PLL4PUBS: Public protection of PLL4 configuration bits (enable, ready, divider)
Written at 1 to set PLL4PUB by secure privileged software only. It can be read by any
software.
Bit 2 PLL3PUBS: Public protection of PLL3 configuration bits (enable, ready, divider)
Written at 1 to set PLL3PUB by secure privileged software only. It can be read by any
software.
Bit 1 PLL2PUBS: Public protection of PLL2 configuration bits (enable, ready, divider)
Written at 1 to set PLL2PUB by secure privileged software only. It can be read by any
software.
Bit 0 PLL1PUBS: Public protection of PLL1 configuration bits (enable, ready, divider)
Written at 1 to set PLL1PUB by secure privileged software only. It can be read by any
software.

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Reset and clock control (RCC) RM0486

14.10.178 RCC divider privilege configuration set register 2

(RCC_PRIVCFGSR2)
Address offset: 0xFA4
Reset value: 0x0000 0000
This register is used to control the privileged access rights to the configuration register of
the dividers. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPRIV bit
defines the privileged protection for the configuration registers of the divider: a write access
is denied if the access is unprivileged while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IC20PR IC19PR IC18PR IC17PR
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
IVS IVS IVS IVS
w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC16PR IC15PR IC14PR IC13PR IC12PR IC11PR IC10PR IC9PRI IC8PRI IC7PRI IC6PRI IC5PRI IC4PRI IC3PRI IC2PRI IC1PRI
IVS IVS IVS IVS IVS IVS IVS VS VS VS VS VS VS VS VS VS
w w w w w w w w w w w w w w w w

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 IC20PRIVS: Privileged protection of IC20 configuration bits (enable, ready, divider)
Written at 1 to set IC20PRIV by secure privileged software only. It can be read by any
software.
Bit 18 IC19PRIVS: Privileged protection of IC19 configuration bits (enable, ready, divider)
Written at 1 to set IC19PRIV by secure privileged software only. It can be read by any
software.
Bit 17 IC18PRIVS: Privileged protection of IC18 configuration bits (enable, ready, divider)
Written at 1 to set IC18PRIV by secure privileged software only. It can be read by any
software.
Bit 16 IC17PRIVS: Privileged protection of IC17 configuration bits (enable, ready, divider)
Written at 1 to set IC17PRIV by secure privileged software only. It can be read by any
software.
Bit 15 IC16PRIVS: Privileged protection of IC16 configuration bits (enable, ready, divider)
Written at 1 to set IC16PRIV by secure privileged software only. It can rbe ead by any
software.
Bit 14 IC15PRIVS: Privileged protection of IC15 configuration bits (enable, ready, divider)
Written at 1 to set IC15PRIV by secure privileged software only. It can be read by any
software.
Bit 13 IC14PRIVS: Privileged protection of IC14 configuration bits (enable, ready, divider)
Written at 1 to set IC14PRIV by secure privileged software only. It can be read by any
software.
Bit 12 IC13PRIVS: Privileged protection of IC13 configuration bits (enable, ready, divider)
Written at 1 to set IC13PRIV by secure privileged software only. It can be read by any
software.
Bit 11 IC12PRIVS: Privileged protection of IC12 configuration bits (enable, ready, divider)
Written at 1 to set IC12PRIV by secure privileged software only. It can be read by any
software.

688/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bit 10 IC11PRIVS: Privileged protection of IC11 configuration bits (enable, ready, divider)
Written at 1 to set IC11PRIV by secure privileged software only. It can be read by any
software.
Bit 9 IC10PRIVS: Privileged protection of IC10 configuration bits (enable, ready, divider)
Written at 1 to set IC10PRIV by secure privileged software only. It can be read by any
software.
Bit 8 IC9PRIVS: Privileged protection of IC9 configuration bits (enable, ready, divider)
Written at 1 to set IC9PRIV by secure privileged software only. It can be read by any
software.
Bit 7 IC8PRIVS: Privileged protection of IC8 configuration bits (enable, ready, divider)
Written at 1 to set IC8PRIV by secure privileged software only. It can be read by any
software.
Bit 6 IC7PRIVS: Privileged protection of IC7 configuration bits (enable, ready, divider)
Written at 1 to set IC7PRIV by secure privileged software only. It can be read by any
software.
Bit 5 IC6PRIVS: Privileged protection of IC6 configuration bits (enable, ready, divider)
Written at 1 to set IC6PRIV by secure privileged software only. It can be read by any
software.
Bit 4 IC5PRIVS: Privileged protection of IC5 configuration bits (enable, ready, divider)
Written at 1 to set IC5PRIV by secure privileged software only. It can be read by any
software.
Bit 3 IC4PRIVS: Privileged protection of IC4 configuration bits (enable, ready, divider)
Written at 1 to set IC4PRIV by secure privileged software only. It can be read by any
software.
Bit 2 IC3PRIVS: Privileged protection of IC3 configuration bits (enable, ready, divider)
Written at 1 to set IC3PRIV by secure privileged software only. It can be read by any
software.
Bit 1 IC2PRIVS: Privileged protection of IC2 configuration bits (enable, ready, divider)
Written at 1 to set IC2PRIV by secure privileged software only. It can be read by any
software.
Bit 0 IC1PRIVS: Privileged protection of IC1 configuration bits (enable, ready, divider)
Written at 1 to set IC1PRIV by secure privileged software only. It can be read by any
software.

14.10.179 RCC divider public configuration set register 2

(RCC_PUBCFGSR2)
Address offset: 0xFAC
Reset value: 0x0000 0000
This register is used to control the public access rights to the configuration register of the
dividers. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPUB bit defines

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Reset and clock control (RCC) RM0486

the public protection for the configuration registers of the divider: a write access is denied if
the access is non-public while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IC20PU IC19PU IC18PU IC17PU
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
BS BS BS BS
w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC16PU IC15PU IC14PU IC13PU IC12PU IC11PU IC10PU IC9PU IC8PU IC7PU IC6PU IC5PU IC4PU IC3PU IC2PU IC1PU
BS BS BS BS BS BS BS BS BS BS BS BS BS BS BS BS
w w w w w w w w w w w w w w w w

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 IC20PUBS: Public protection of IC20 configuration bits (enable, ready, divider)
Written at 1 to set IC20PUB by secure privileged software only. It can be read by any
software.
Bit 18 IC19PUBS: Public protection of IC19 configuration bits (enable, ready, divider)
Written at 1 to set IC19PUB by secure privileged software only. It can be read by any
software.
Bit 17 IC18PUBS: Public protection of IC18 configuration bits (enable, ready, divider)
Written at 1 to set IC18PUB by secure privileged software only. It can be read by any
software.
Bit 16 IC17PUBS: Public protection of IC17 configuration bits (enable, ready, divider)
Written at 1 to set IC17PUB by secure privileged software only. It can be read by any
software.
Bit 15 IC16PUBS: Public protection of th IC16 configuration bits (enable, ready, divider
Written at 1 to set IC16PUB by secure privileged software only. It can be read by any
software.
Bit 14 IC15PUBS: Public protection of IC15 configuration bits (enable, ready, divider)
Written at 1 to set IC15PUB by secure privileged software only. It can be read by any
software.
Bit 13 IC14PUBS: Public protection of IC14 configuration bits (enable, ready, divider)
Written at 1 to set IC14PUB by secure privileged software only. It can be read by any
software.
Bit 12 IC13PUBS: Public protection of IC13 configuration bits (enable, ready, divider)
Written at 1 to set IC13PUB by secure privileged software only. It can be read by any
software.
Bit 11 IC12PUBS: Public protection of IC12 configuration bits (enable, ready, divider)
Written at 1 to set IC12PUB by secure privileged software only. It can be read by any
software.
Bit 10 IC11PUBS: Public protection of IC11 configuration bits (enable, ready, divider)
Written at 1 to set IC11PUB by secure privileged software only. It can be read by any
software.
Bit 9 IC10PUBS: Public protection of IC10 configuration bits (enable, ready, divider)
Written at 1 to set IC10PUB by secure privileged software only. It can be read by any
software.

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RM0486 Reset and clock control (RCC)

Bit 8 IC9PUBS: Public protection of IC9 configuration bits (enable, ready, divider)
Written at 1 to set IC9PUB by secure privileged software only. It can be read by any software.
Bit 7 IC8PUBS: Public protection of IC8 configuration bits (enable, ready, divider)
Written at 1 to set IC8PUB by secure privileged software only. It can be read by any software.
Bit 6 IC7PUBS: Public protection of IC7 configuration bits (enable, ready, divider)
Written at 1 to set IC7PUB by secure privileged software only. It can be read by any software.
Bit 5 IC6PUBS: Public protection of IC6 configuration bits (enable, ready, divider)
Written at 1 to set IC6PUB by secure privileged software only. It can be read by any software.
Bit 4 IC5PUBS: Public protection of IC5 configuration bits (enable, ready, divider)
Written at 1 to set IC5PUB by secure privileged software only. It can be read by any software.
Bit 3 IC4PUBS: Public protection of IC4 configuration bits (enable, ready, divider)
Written at 1 to set IC4PUB by secure privileged software only. It can be read by any software.
Bit 2 IC3PUBS: Public protection of IC3 configuration bits (enable, ready, divider)
Written at 1 to set IC3PUB by secure privileged software only. It can be read by any software.
Bit 1 IC2PUBS: Public protection of IC2 configuration bits (enable, ready, divider)
Written at 1 to set IC2PUB by secure privileged software only. It can be read by any software.
Bit 0 IC1PUBS: Public protection of IC1 configuration bits (enable, ready, divider)
Written at 1 to set IC1PUB by secure privileged software only. It can be read by any software.

14.10.180 RCC system privilege configuration set register 3

(RCC_PRIVCFGSR3)
Address offset: 0xFB4
Reset value: 0x0000 0000
This register is used to control the privileged access rights to the configuration register of
the system. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPRIV bit
defines the privilege protection for the configuration registers of the system: a write access
is denied if the access is unprivileged while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DFTPR RSTPR INTPRI PERPR BUSPR SYSPR MODP
Res. Res. Res. Res. Res. Res. Res. Res. Res.
IVS IVS VS IVS IVS IVS RIVS
w w w w w w w

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 DFTPRIVS: Privileged protection of DFT configuration bits (enable, ready, divider)
Written at 1 to set DFTPRIV by secure privileged software only. It can be read by any
software.
Bit 5 RSTPRIVS: Privileged protection of RST configuration bits (enable, ready, divider)
Written at 1 to set RSTPRIV by secure privileged software only. It can be read by any
software.

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Reset and clock control (RCC) RM0486

Bit 4 INTPRIVS: Privileged protection of INT configuration bits (enable, ready, divider)
Written at 1 to set INTPRIV by secure privileged software only. It can be read by any
software.
Bit 3 PERPRIVS: Privileged protection of PER configuration bits (enable, ready, divider)
Written at 1 to set PERPRIV by secure privileged software only. It can be read by any
software.
Bit 2 BUSPRIVS: Privileged protection of BUS configuration bits (enable, ready, divider)
Written at 1 to set BUSPRIV by secure privileged software only. It can be read by any
software.
Bit 1 SYSPRIVS: Privileged protection of SYS configuration bits (enable, ready, divider)
Written at 1 to set SYSPRIV by secure privileged software only. It can be read by any
software.
Bit 0 MODPRIVS: Privileged protection of MOD configuration bits (enable, ready, divider)
Written at 1 to set MODPRIV by secure privileged software only. It can be read by any
software.

14.10.181 RCC system public configuration set register 3 (RCC_PUBCFGSR3)

Address offset: 0xFBC
Reset value: 0x0000 0000
This register is used to control the public access rights to the configuration register of the
system. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPUB bit defines
the public protection for the configuration registers of the system: a write access is denied if
the access is non-public while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTPU INTPU PERPU BUSPU SYSPU MODP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
BS BS BS BS BS UBS
w w w w w w

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 RSTPUBS: Public protection of RST configuration bits (enable, ready, divider)
Written at 1 to set RSTPUB by secure privileged software only. It can be read by any
software.
Bit 4 INTPUBS: Public protection of INT configuration bits (enable, ready, divider)
Written at 1 to set INTPUB by secure privileged software only. It can be read by any software.
Bit 3 PERPUBS: Public protection of PER configuration bits (enable, ready, divider)
Written at 1 to set PERPUB by secure privileged software only. It can be read by any
software.
Bit 2 BUSPUBS: Public protection of BUS configuration bits (enable, ready, divider)
Written at 1 to set BUSPUB by secure privileged software only. It can be read by any
software.

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RM0486 Reset and clock control (RCC)

Bit 1 SYSPUBS: Public protection of SYS configuration bits (enable, ready, divider)
Written at 1 to set SYSPUB by secure privileged software only. It can be read by any
software.
Bit 0 MODPUBS: Public protection of MOD configuration bits (enable, ready, divider)
Written at 1 to set MODPUB by secure privileged software only. It can be read by any
software.

14.10.182 RCC privilege configuration set register 4 (RCC_PRIVCFGSR4)

Address offset: 0xFC4
Reset value: 0x0000 0000
This register is used to control the privileged access rights to the configuration register of
the buses. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPRIV bit
defines the privileged protection for the configuration registers of each bus: a write access is
denied if the access is unprivileged while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOCP APB5P APB4P APB3P APB2P APB1P AHB5P AHB4P AHB3P AHB2P AHB1P AHBM ACLKNC ACLKN
Res. Res.
RIVS RIVS RIVS RIVS RIVS RIVS RIVS RIVS RIVS RIVS RIVS PRIVS PRIVS PRIVS
w w w w w w w w w w w w w w

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 NOCPRIVS: Privileged protection of NOC configuration bits (enable, ready, divider)
Written at 1 to set NOCPRIV by secure privileged software only. It can be read by any
software.
Bit 12 APB5PRIVS: Privileged protection of APB5 configuration bits (enable, ready, divider)
Written at 1 to set APB5PRIV by secure privileged software only. It can be read by any
software.
Bit 11 APB4PRIVS: Privileged protection of APB4 configuration bits (enable, ready, divider)
Written at 1 to set APB4PRIV by secure privileged software only. It can be read by any
software.
Bit 10 APB3PRIVS: Privileged protection of APB3 configuration bits (enable, ready, divider)
Written at 1 to set APB3PRIV by secure privileged software only. It can be read by any
software.
Bit 9 APB2PRIVS: Privileged protection of APB2 configuration bits (enable, ready, divider)
Written at 1 to set APB2PRIV by secure privileged software only. It can be read by any
software.
Bit 8 APB1PRIVS: Privileged protection of APB1 configuration bits (enable, ready, divider)
Written at 1 to set APB1PRIV by secure privileged software only. It can be read by any
software.
Bit 7 AHB5PRIVS: Privileged protection of AHB5 configuration bits (enable, ready, divider)
Written at 1 to set AHB5PRIV by secure privileged software only. It can be read by any
software.

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Reset and clock control (RCC) RM0486

Bit 6 AHB4PRIVS: Privileged protection of AHB4 configuration bits (enable, ready, divider)
Written at 1 to set AHB4PRIV by secure privileged software only. It can be read by any
software.
Bit 5 AHB3PRIVS: Privileged protection of AHB3 configuration bits (enable, ready, divider)
Written at 1 to set AHB3PRIV by secure privileged software only. It can be read by any
software.
Bit 4 AHB2PRIVS: Privileged protection of AHB2 configuration bits (enable, ready, divider)
Written at 1 to set AHB2PRIV by secure privileged software only. It can be read by any
software.
Bit 3 AHB1PRIVS: Privileged protection of AHB1 configuration bits (enable, ready, divider)
Written at 1 to set AHB1PRIV by secure privileged software only. It can be read by any
software.
Bit 2 AHBMPRIVS: Privileged protection of AHBM configuration bits (enable, ready, divider)
Written at 1 to set AHBMPRIV by secure privileged software only. It can be read by any
software.
Bit 1 ACLKNCPRIVS: Privileged protection of th ACLKNC configuration bits (enable, ready, divider)
Written at 1 to set ACLKNCPRIV by secure privileged software only. It can be read by any
software.
Bit 0 ACLKNPRIVS: Privileged protection of ACLKN configuration bits (enable, ready, divider)
Written at 1 to set ACLKNPRIV by secure privileged software only. It can be read by any
software.

14.10.183 RCC public configuration set register 4 (RCC_PUBCFGSR4)

Address offset: 0xFCC
Reset value: 0x0000 0000
This register is used to control the public access rights to the configuration register of the
buses. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPUB bit defines
the public protection for the configuration registers of each bus: a write access is denied if
the access is non-public while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOCP APB5P APB4P APB3P APB2P APB1P AHB5P AHB4P AHB3P AHB2P AHB1P AHBM ACLKN ACLKN
Res. Res.
UBS UBS UBS UBS UBS UBS UBS UBS UBS UBS UBS PUBS CPUBS PUBS
w w w w w w w w w w w w w w

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 NOCPUBS: Public protection of NOC configuration bits (enable, ready, divider)
Written at 1 to set NOCPUB by secure privileged software only. It can be read by any
software.
Bit 12 APB5PUBS: Public protection of APB5 configuration bits (enable, ready, divider)
Written at 1 to set APB5PUB by secure privileged software only. It can be read by any
software.

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RM0486 Reset and clock control (RCC)

Bit 11 APB4PUBS: Public protection of APB4 configuration bits (enable, ready, divider)
Written at 1 to set APB4PUB by secure privileged software only. It can be read by any
software.
Bit 10 APB3PUBS: Public protection of APB3 configuration bits (enable, ready, divider)
Written at 1 to set APB3PUB by secure privileged software only. It can be read by any
software.
Bit 9 APB2PUBS: Public protection of APB2 configuration bits (enable, ready, divider)
Written at 1 to set APB2PUB by secure privileged software only. It can be read by any
software.
Bit 8 APB1PUBS: Public protection of APB1 configuration bits (enable, ready, divider)
Written at 1 to set APB1PUB by secure privileged software only. It can be read by any
software.
Bit 7 AHB5PUBS: Public protection of AHB5 configuration bits (enable, ready, divider)
Written at 1 to set AHB5PUB by secure privileged software only. It can be read by any
software.
Bit 6 AHB4PUBS: Public protection of AHB4 configuration bits (enable, ready, divider)
Written at 1 to set AHB4PUB by secure privileged software only. It can be read by any
software.
Bit 5 AHB3PUBS: Public protection of AHB3 configuration bits (enable, ready, divider)
Written at 1 to set AHB3PUB by secure privileged software only. It can be read by any
software.
Bit 4 AHB2PUBS: Public protection of AHB2 configuration bits (enable, ready, divider)
Written at 1 to set AHB2PUB by secure privileged software only. It can be read by any
software.
Bit 3 AHB1PUBS: Public protection of AHB1 configuration bits (enable, ready, divider)
Written at 1 to set AHB1PUB by secure privileged software only. It can be read by any
software.
Bit 2 AHBMPUBS: Public protection of AHBM configuration bits (enable, ready, divider)
Written at 1 to set AHBMPUB by secure privileged software only. It can be read by any
software.
Bit 1 ACLKNCPUBS: Public protection of ACLKNC configuration bits (enable, ready, divider)
Written at 1 to set ACLKNCPUB by secure privileged software only. It can be read by any
software.
Bit 0 ACLKNPUBS: Public protection of ACLKN configuration bits (enable, ready, divider)
Written at 1 to set ACLKNPUB by secure privileged software only. It can be read by any
software.

14.10.184 RCC public configuration set register 5 (RCC_PUBCFGSR5)

Address offset: 0xFD0
Reset value: 0x0000 0000
This register is used to control the public access rights to the configuration register of the
SRAMs. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPUB bit defines
the public protection for the configuration registers of each SRAM: a write access is denied
if the access is non-public while the respective bit is set.

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Reset and clock control (RCC) RM0486

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CACHE
VENCR FLEXR AXISR AXISR BKPSR AHBSR AHBSR AXISR AXISR AXISR AXISR
AXIRA
Res. Res. Res. Res. AMPU AMPU AM2PU AM1PU AMPU AM2PU AM1PU AM6PU AM5PU AM4PU AM3PU
MPUB
BS BS BS BS BS BS BS BS BS BS BS
S
w w w w w w w w w w w w

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 VENCRAMPUBS: Public protection of VENCRAM configuration bits (enable, ready, divider)
Written at 1 to set VENCRAMPUB by secure privileged software only. It can be read by any
software.
Bit 10 CACHEAXIRAMPUBS: Public protection of CACHEAXIRAM configuration bits (enable, ready,
divider)
Written at 1 to set CACHEAXIRAMPUB by secure privileged software only. It can be read by
any software.
Bit 9 FLEXRAMPUBS: Public protection of FLEXRAM configuration bits (enable, ready, divider)
Written at 1 to set FLEXRAMPUB by secure privileged software only. It can be read by any
software.
Bit 8 AXISRAM2PUBS: Public protection of AXISRAM2 configuration bits (enable, ready, divider)
Written at 1 to set AXISRAM2PUB by secure privileged software only. It can rbe ead by any
software.
Bit 7 AXISRAM1PUBS: Public protection of AXISRAM1 configuration bits (enable, ready, divider)
Written at 1 to set AXISRAM1PUB by secure privileged software only. It can be read by any
software.
Bit 6 BKPSRAMPUBS: Public protection of BKPSRAM configuration bits (enable, ready, divider)
Written at 1 to set BKPSRAMPUB by secure privileged software only. It can be read by any
software.
Bit 5 AHBSRAM2PUBS: Public protection of AHBSRAM2 configuration bits (enable, ready, divider)
Written at 1 to set AHBSRAM2PUB by secure privileged software only. It can be read by any
software.
Bit 4 AHBSRAM1PUBS: Public protection of AHBSRAM1 configuration bits (enable, ready, divider)
Written at 1 to set AHBSRAM1PUB by secure privileged software only. It can be read by any
software.
Bit 3 AXISRAM6PUBS: Public protection of AXISRAM6 configuration bits (enable, ready, divider)
Written at 1 to set AXISRAM6PUB by secure privileged software only. It can be read by any
software.
Bit 2 AXISRAM5PUBS: Public protection of AXISRAM5 configuration bits (enable, ready, divider)
Written at 1 to set AXISRAM5PUB by secure privileged software only. It can be read by any
software.
Bit 1 AXISRAM4PUBS: Public protection of AXISRAM4 configuration bits (enable, ready, divider)
Written at 1 to set AXISRAM4PUB by secure privileged software only. It can be read by any
software.

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RM0486 Reset and clock control (RCC)

Bit 0 AXISRAM3PUBS: Public protection of AXISRAM3 configuration bits (enable, ready, divider)
Written at 1 to set AXISRAM3PUB by secure privileged software only. It can be read by any
software.

14.10.185 RCC control clear register (RCC_CCR)

Address offset: 0x1000
Reset value: 0x0000 0000
This register is used to enable the RCC oscillators and PLLs in Run or Sleep mode. It is
reset by nreset_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4 PLL3 PLL2 PLL1 HSE HSI MSI LSE LSI
Res. Res. Res. Res. Res. Res. Res.
ONC ONC ONC ONC ONC ONC ONC ONC ONC
w w w w w w w w w

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 PLL4ONC: PLL4 oscillator enable
Written at 1 to clear PLL4ON.
Bit 10 PLL3ONC: PLL3 oscillator enable
Written at 1 to clear PLL3ON.
Bit 9 PLL2ONC: PLL2 oscillator enable
Written at 1 to clear PLL2ON.
Bit 8 PLL1ONC: PLL1 oscillator enable
Written at 1 to clear PLL1ON.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 HSEONC: HSE oscillator enable
Written at 1 to clear HSEON.
Bit 3 HSIONC: HSI oscillator enable
Written at 1 to clear HSION.
Bit 2 MSIONC: MSI oscillator enable
Written at 1 to clear MSION.
Bit 1 LSEONC: LSE oscillator enable
Written at 1 to clear LSEON.
Bit 0 LSIONC: LSI oscillator enable
Written at 1 to clear LSION.

14.10.186 RCC Stop mode configuration clear register (RCC_STOPCCR)

Address offset: 0x1008
Reset value: 0x0000 0000

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This register is used to enable the RCC oscillators and PLLs in Stop mode. It is reset by
sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSISTO MSISTO
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
PENC PENC
w w

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 HSISTOPENC: HSI oscillator enable
Written at 1 to clear HSISTOPEN.
Bit 0 MSISTOPENC: MSI oscillator enable
Written at 1 to clear MSISTOPEN.

14.10.187 RCC miscellaneous reset clear register (RCC_MISCRSTCR)

Address offset: 0x1208
Reset value: 0x0000 0000
This register is used to clear miscellaneous RCC resets. It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMM SDMM XSPIP XSPIP
DBGR
Res. Res. Res. Res. Res. Res. Res. C2DLL C1DLL Res. HY2RS HY1RS Res. Res. Res.
STC
RSTC RSTC TC TC
w w w w w

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SDMMC2DLLRSTC: SDMMC2DLL reset
Written at 1 to clear SDMMC2DLLRST.
Bit 7 SDMMC1DLLRSTC: SDMMC1DLL reset
Written at 1 to clear SDMMC1DLLRST.
Bit 6 Reserved, must be kept at reset value.
Bit 5 XSPIPHY2RSTC: XSPIPHY2 reset
Written at 1 hto clear XSPIPHY2RST.
Bit 4 XSPIPHY1RSTC: XSPIPHY1 reset
Written at 1 to clear XSPIPHY1RST.
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 DBGRSTC: DBG reset
Written at 1 to clear DBGRST.

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RM0486 Reset and clock control (RCC)

14.10.188 RCC memory reset clear register (RCC_MEMRSTCR)

Address offset: 0x120C
Reset value: 0x0000 0000
This register is used to reset the RCC memory. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOT VENCR CACHE FLEXR AXISR AXISR AHBSR AHBSR AXISR AXISR AXISR AXISR
Res. Res. Res. ROMR AMRST AXIRAM AMRST AM2RS AM1RS Res. AM2RS AM1RS AM6RS AM5RS AM4RS AM3RS
STC C RSTC C TC TC TC TC TC TC TC TC
w w w w w w w w w w w w

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 BOOTROMRSTC: BootROM reset
Written at 1 to clear BOOTROMRST.
Bit 11 VENCRAMRSTC: VENCRAM reset
Written at 1 to clear VENCRAMRST.
Bit 10 CACHEAXIRAMRSTC: CACHEAXIRAM reset
Written at 1 to clear CACHEAXIRAMRST.
Bit 9 FLEXRAMRSTC: FLEXRAM reset
Written at 1 to clear FLEXRAMRST.
Bit 8 AXISRAM2RSTC: AXISRAM2 reset
Written at 1 to clear AXISRAM2RST.
Bit 7 AXISRAM1RSTC: AXISRAM1 reset
Written at 1 to clear AXISRAM1RST.
Bit 6 Reserved, must be kept at reset value.
Bit 5 AHBSRAM2RSTC: AHBSRAM2 reset
Written at 1 to clear AHBSRAM2RST.
Bit 4 AHBSRAM1RSTC: AHBSRAM1 reset
Written at 1 to clear AHBSRAM1RST.
Bit 3 AXISRAM6RSTC: AXISRAM6 reset
Written at 1 to clear AXISRAM6RST.
Bit 2 AXISRAM5RSTC: AXISRAM5 reset
Written at 1 to clear AXISRAM5RST.
Bit 1 AXISRAM4RSTC: AXISRAM4 reset
Written at 1 to clear AXISRAM4RST.
Bit 0 AXISRAM3RSTC: AXISRAM3 reset
Written at 1 to clear AXISRAM3RST.

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14.10.189 RCC AHB1 reset clear register (RCC_AHB1RSTCR)

Address offset: 0x1210
Reset value: 0x0000 0000
This register is used to reset the RCC AHB1. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC12 GPDMA1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RSTC RSTC
w w

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 ADC12RSTC: ADC12 reset
Written at 1 to clear ADC12RST.
Bit 4 GPDMA1RSTC: GPDMA1 reset
Written at 1 to clear GPDMA1RST.
Bits 3:0 Reserved, must be kept at reset value.

14.10.190 RCC AHB2 reset clear register (RCC_AHB2RSTCR)

Address offset: 0x1214
Reset value: 0x0000 0000
This register is used to reset the RCC AHB2. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADF1R MDF1R
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
STC STC
w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAMC
Res. Res. Res. FGRST Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
C
w

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 ADF1RSTC: ADF1 reset
Written at 1 to clear ADF1RST.
Bit 16 MDF1RSTC: MDF1 reset
Written at 1 to clear MDF1RST.
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 RAMCFGRSTC: RAMCFG reset
Written at 1 to clear RAMCFGRST.

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RM0486 Reset and clock control (RCC)

Bits 11:0 Reserved, must be kept at reset value.

14.10.191 RCC AHB3 reset clear register (RCC_AHB3RSTCR)

Address offset: 0x1218
Reset value: 0x0000 0000
This register is used to reset the RCC AHB3. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IACRS PKARS SAESR CRYPR HASHR RNGR
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
TC TC STC STC STC STC
w w w w w w

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 IACRSTC: IAC reset
Written at 1 to clear IACRST.
Bit 9 Reserved, must be kept at reset value.
Bit 8 PKARSTC: PKA reset
Written at 1 to clear PKARST.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 SAESRSTC: SAES reset
Written at 1 to clear SAESRST.
Bit 3 Reserved, must be kept at reset value.
Bit 2 CRYPRSTC: CRYP reset
Written at 1 to clear CRYPRST.
Bit 1 HASHRSTC: HASH reset
Written at 1 to clear HASHRST.
Bit 0 RNGRSTC: RNG reset
Written at 1 to clear RNGRST.

14.10.192 RCC AHB4 reset clear register (RCC_AHB4RSTCR)

Address offset: 0x121C
Reset value: 0x0000 0000
This register is used to reset the RCC AHB4. It is reset by sys_rstn, and is in the VCORE
voltage domain.

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCR PWRR GPIOQ
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
STC STC RSTC
w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOP GPIOO GPION GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Res. Res. Res. Res. Res.
RSTC RSTC RSTC RSTC RSTC RSTC RSTC RSTC RSTC RSTC RSTC
w w w w w w w w w w w

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 CRCRSTC: CRC reset
Written at 1 to clear CRCRST.
Bit 18 PWRRSTC: PWR reset
Written at 1 to clear PWRRST.
Bit 17 Reserved, must be kept at reset value.
Bit 16 GPIOQRSTC: GPIO Q reset
Written at 1 to clear GPIOQRST.
Bit 15 GPIOPRSTC: GPIO P reset
Written at 1 to clear GPIOPRST.
Bit 14 GPIOORSTC: GPIO O reset
Written at 1 to clear GPIOORST.
Bit 13 GPIONRSTC: GPIO N reset
Written at 1 to clear GPIONRST.
Bits 12:8 Reserved, must be kept at reset value.
Bit 7 GPIOHRSTC: GPIO H reset
Written at 1 to clear GPIOHRST.
Bit 6 GPIOGRSTC: GPIO G reset
Written at 1 to clear GPIOGRST.
Bit 5 GPIOFRSTC: GPIO F reset
Written at 1 to clear GPIOFRST.
Bit 4 GPIOERSTC: GPIO E reset
Written at 1 to clear GPIOERST.
Bit 3 GPIODRSTC: GPIO D reset
Written at 1 to clear GPIODRST.
Bit 2 GPIOCRSTC: GPIO C reset
Written at 1 to clear GPIOCRST.
Bit 1 GPIOBRSTC: GPIO B reset
Written at 1 to clear GPIOBRST.
Bit 0 GPIOARSTC: GPIO A reset
Written at 1 to clear GPIOARST.

14.10.193 RCC AHB5 reset clear register (RCC_AHB5RSTCR)

Address offset: 0x1220

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RM0486 Reset and clock control (RCC)

Reset value: 0x0000 0000

This register is used to reset the RCC AHB5. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTG2 OTG1
CACHE OTG OTG GFX
NPU OTG2 OTG1 ETH1 PHY PHY GPU2D XSPI3
AXI PHY2 PHY1 Res. Res. MMU Res. Res.
RSTC RSTC RSTC RSTC CTL CTL RSTC RSTC
RSTC RSTC RSTC RSTC
RSTC RSTC
w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMM SDMM HPD
XSPIM XSPI2 PSSI XSPI1 FMC JPEG DMA2D
Res. Res. Res. Res. Res. C1 C2 Res. MA1
RSTC RSTC RSTC RSTC RSTC RSTC RSTC
RSTC RSTC RSTC
w w w w w w w w w w

Bit 31 NPURSTC: NPU reset

Written at 1 to clear NPURST.
Bit 30 CACHEAXIRSTC: CACHEAXI reset
Written at 1 to clear CACHEAXIRST.
Bit 29 OTG2RSTC: OTG2 reset
Written at 1 to clear OTG2RST.
Bit 28 OTGPHY2RSTC: OTGPHY2 reset
Written at 1 to clear OTGPHY2RST.
Bit 27 OTGPHY1RSTC: OTGPHY1 reset
Written at 1 to clear OTGPHY1RST.
Bit 26 OTG1RSTC: OTG1 reset
Written at 1 to clear OTG1RST.
Bit 25 ETH1RSTC: ETH1 reset
Written at 1 to clear ETH1RST.
Bit 24 OTG2PHYCTLRSTC: OTG2PHYCTL reset
Written at 1 to clear OTG2PHYCTLRST.
Bit 23 OTG1PHYCTLRSTC: OTG1PHYCTL reset
Written at 1 to clear OTG1PHYCTLRST.
Bits 22:21 Reserved, must be kept at reset value.
Bit 20 GPU2DRSTC: GPU2D reset
Written at 1 to clear GPU2DRST.
Bit 19 GFXMMURSTC: GFXMMU reset
Written at 1 to clear GFXMMURST.
Bit 18 Reserved, must be kept at reset value.
Bit 17 XSPI3RSTC: XSPI3 reset
Written at 1 to clear XSPI3RST.
Bits 16:14 Reserved, must be kept at reset value.
Bit 13 XSPIMRSTC: XSPIM reset
Written at 1 to clear XSPIMRST.

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Bit 12 XSPI2RSTC: XSPI2 reset

Written at 1 to clear XSPI2RST.
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 SDMMC1RSTC: SDMMC1 reset
Written at 1 to clear SDMMC1RST.
Bit 7 SDMMC2RSTC: SDMMC2 reset
Written at 1 to clear SDMMC2RST.
Bit 6 PSSIRSTC: PSSI reset
Written at 1 to clear PSSIRST.
Bit 5 XSPI1RSTC: XSPI1 reset
Written at 1 to clear XSPI1RST.
Bit 4 FMCRSTC: FMC reset
Written at 1 to clear FMCRST.
Bit 3 JPEGRSTC: JPEG reset
Written at 1 to clear JPEGRST.
Bit 2 Reserved, must be kept at reset value.
Bit 1 DMA2DRSTC: DMA2D reset
Written at 1 to clear DMA2DRST.
Bit 0 HPDMA1RSTC: HPDMA1 reset
Written at 1 to clear HPDMA1RST.

14.10.194 RCC APB1L reset clear register (RCC_APB1LRSTCR)

Address offset: 0x1224
Reset value: 0x0000 0000
This register is used to reset the RCC APB1L. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPDIF
UART8 UART7 I3C2RS I3C1RS I2C3RS I2C2RS I2C1RS UART5 UART4 USART USART
Res. Res. Res. Res. RX1RS
RSTC RSTC TC TC TC TC TC RSTC RSTC 3RSTC 2RSTC
TC
w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3R SPI2R TIM11R TIM10 WWDG LPTIM1 TIM14 TIM13 TIM12 TIM7R TIM6R TIM5R TIM4R TIM3R TIM2R
Res.
STC STC STC RSTC RSTC RSTC RSTC RSTC RSTC STC STC STC STC STC STC
w w w w w w w w w w w w w w w

Bit 31 UART8RSTC: UART8 reset

Written at 1 to clear UART8RST.
Bit 30 UART7RSTC: UART7 reset
Written at 1 to clear UART7RST.
Bits 29:26 Reserved, must be kept at reset value.
Bit 25 I3C2RSTC: I3C2 reset
Written at 1 to clear I3C2RST.

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RM0486 Reset and clock control (RCC)

Bit 24 I3C1RSTC: I3C1 reset

Written at 1 to clear I3C1RST.
Bit 23 I2C3RSTC: I2C3 reset
Written at 1 to clear I2C3RST.
Bit 22 I2C2RSTC: I2C2 reset
Written at 1 to clear I2C2RST.
Bit 21 I2C1RSTC: I2C1 reset
Written at 1 to clear I2C1RST.
Bit 20 UART5RSTC: UART5 reset
Written at 1 to clear UART5RST.
Bit 19 UART4RSTC: UART4 reset
Written at 1 to clear UART4RST.
Bit 18 USART3RSTC: USART3 reset
Written at 1 to clear USART3RST.
Bit 17 USART2RSTC: USART2 reset
Written at 1 to clear USART2RST.
Bit 16 SPDIFRX1RSTC: SPDIFRX1 reset
Written at 1 to clear SPDIFRX1RST.
Bit 15 SPI3RSTC: SPI3 reset
Written at 1 to clear SPI3RST.
Bit 14 SPI2RSTC: SPI2 reset
Written at 1 to clear SPI2RST.
Bit 13 TIM11RSTC: TIM11 reset
Written at 1 to clear TIM11RST.
Bit 12 TIM10RSTC: TIM10 reset
Written at 1 to clear TIM10RST.
Bit 11 WWDGRSTC: WWDG reset
Written at 1 to clear WWDGRST.
Bit 10 Reserved, must be kept at reset value.
Bit 9 LPTIM1RSTC: LPTIM1 reset
Written at 1 to clear LPTIM1RST.
Bit 8 TIM14RSTC: TIM14 reset
Written at 1 to clear TIM14RST.
Bit 7 TIM13RSTC: TIM13 reset
Written at 1 to clear TIM13RST.
Bit 6 TIM12RSTC: TIM12 reset
Written at 1 to clear TIM12RST.
Bit 5 TIM7RSTC: TIM7 reset
Written at 1 to clear TIM7RST.
Bit 4 TIM6RSTC: TIM6 reset
Written at 1 to clear TIM6RST.

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Bit 3 TIM5RSTC: TIM5 reset

Written at 1 to clear TIM5RST.
Bit 2 TIM4RSTC: TIM4 reset
Written at 1 to clear TIM4RST.
Bit 1 TIM3RSTC: TIM3 reset
Written at 1 to clear TIM3RST.
Bit 0 TIM2RSTC: TIM2 reset
Written at 1 to clear TIM2RST.

14.10.195 RCC APB1H reset clear register (RCC_APB1HRSTCR)

Address offset: 0x1228
Reset value: 0x0000 0000
This register is used to reset the RCC APB1H. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RSTC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN MDIOS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RSTC RSTC
w w

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 UCPD1RSTC: UCPD1 reset
Written at 1 to clear UCPD1RST.
Bits 17:9 Reserved, must be kept at reset value.
Bit 8 FDCANRSTC: FDCAN reset
Written at 1 to clear FDCANRST.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 MDIOSRSTC: MDIOS reset
Written at 1 to clear MDIOSRST.
Bits 4:0 Reserved, must be kept at reset value.

14.10.196 RCC APB2 reset clear register (RCC_APB2RSTCR)

Address offset: 0x122C
Reset value: 0x0000 0000
This register is used to reset the RCC APB2. It is reset by sys_rstn, and is in the VCORE
voltage domain.

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RM0486 Reset and clock control (RCC)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAI2R SAI1R SPI5R TIM9R TIM17 TIM16 TIM15
Res. Res. Res. Res. Res. Res. Res. Res. Res.
STC STC STC STC RSTC RSTC RSTC
w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART
TIM18 SPI4R SPI1R UART9 USART USART TIM8R TIM1R
Res. Res. Res. Res. Res. 10RST Res. Res.
RSTC STC STC RSTC 6RSTC 1RSTC STC STC
C
w w w w w w w w w

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 SAI2RSTC: SAI2 reset
Written at 1 to clear SAI2RST.
Bit 21 SAI1RSTC: SAI1 reset
Written at 1 to clear SAI1RST.
Bit 20 SPI5RSTC: SPI5 reset
Written at 1 to clear SPI5RST.
Bit 19 TIM9RSTC: TIM9 reset
Written at 1 to clear TIM9RST.
Bit 18 TIM17RSTC: TIM17 reset
Written at 1 to clear TIM17RST.
Bit 17 TIM16RSTC: TIM16 reset
Written at 1 to clear TIM16RST.
Bit 16 TIM15RSTC: TIM15 reset
Written at 1 to clear TIM15RST.
Bit 15 TIM18RSTC: TIM18 reset
Written at 1 to clear TIM18RST.
Bit 14 Reserved, must be kept at reset value.
Bit 13 SPI4RSTC: SPI4 reset
Written at 1 to clear SPI4RST.
Bit 12 SPI1RSTC: SPI1 reset
Written at 1 to clear SPI1RST.
Bits 11:8 Reserved, must be kept at reset value.
Bit 7 USART10RSTC: USART10 reset
Written at 1 to clear USART10RST.
Bit 6 UART9RSTC: UART9 reset
Written at 1 to clear UART9RST.
Bit 5 USART6RSTC: USART6 reset
Written at 1 to clear USART6RST.
Bit 4 USART1RSTC: USART1 reset
Written at 1 to clear USART1RST.
Bits 3:2 Reserved, must be kept at reset value.

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Bit 1 TIM8RSTC: TIM8 reset

Written at 1 to clear TIM8RST.
Bit 0 TIM1RSTC: TIM1 reset
Written at 1 to clear TIM1RST.

14.10.197 RCC APB4L reset clear register (RCC_APB4LRSTCR)

Address offset: 0x1234
Reset value: 0x0000 0000
This register is used to reset the RCC APB4L. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTC
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RSTC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFBUF LPTIM5 LPTIM4 LPTIM3 LPTIM2 I2C4 SPI6 LPUART1 HDP
Res. Res. Res. Res. Res. Res. Res.
RSTC RSTC RSTC RSTC RSTC RSTC RSTC RSTC RSTC
w w w w w w w w w

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 RTCRSTC: RTC reset
Written at 1 to clear RTCRST.
Bit 15 VREFBUFRSTC: VREFBUF reset
Written at 1 to clear VREFBUFRST.
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 LPTIM5RSTC: LPTIM5 reset
Written at 1 to clear LPTIM5RST.
Bit 11 LPTIM4RSTC: LPTIM4 reset
Written at 1 to clear LPTIM4RST.
Bit 10 LPTIM3RSTC: LPTIM3 reset
Written at 1 to clear LPTIM3RST.
Bit 9 LPTIM2RSTC: LPTIM2 reset
Written at 1 to clear LPTIM2RST.
Bit 8 Reserved, must be kept at reset value.
Bit 7 I2C4RSTC: I2C4 reset
Written at 1 to clear I2C4RST.
Bit 6 Reserved, must be kept at reset value.
Bit 5 SPI6RSTC: SPI6 reset
Written at 1 to clear SPI6RST.
Bit 4 Reserved, must be kept at reset value.
Bit 3 LPUART1RSTC: LPUART1 reset
Written at 1 to clear LPUART1RST.

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RM0486 Reset and clock control (RCC)

Bit 2 HDPRSTC: HDP reset

Written at 1 to clear HDPRST.
Bits 1:0 Reserved, must be kept at reset value.

14.10.198 RCC APB4H reset clear register (RCC_APB4HRSTCR)

Address offset: 0x1238
Reset value: 0x0000 0000
This register is used to reset the RCC APB4H. It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTSRS SYSCF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
TC GRSTC
w w

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 DTSRSTC: DTS reset
Written at 1 to clear DTSRST.
Bit 1 Reserved, must be kept at reset value.
Bit 0 SYSCFGRSTC: SYSCFG reset
Written at 1 to clear SYSCFGRST.

14.10.199 RCC APB5 reset clear register (RCC_APB5RSTCR)

Address offset: 0x123C
Reset value: 0x0000 0000
This register is used to clear the reset of APB5 peripherals. It is reset by sys_rstn, and is in
the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSIRS VENCR GFXTIM DCMIP LTDCR
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
TC STC RSTC PRSTC STC
w w w w w

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 CSIRSTC: CSI reset
Written at 1 to clear CSIRST.
Bit 5 VENCRSTC: VENC reset
Written at 1 to clear VENCRST.

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Reset and clock control (RCC) RM0486

Bit 4 GFXTIMRSTC: GFXTIM reset

Written at 1 to clear GFXTIMRST.
Bit 3 Reserved, must be kept at reset value.
Bit 2 DCMIPPRSTC: DCMIPP reset
Written at 1 to clear DCMIPPRST.
Bit 1 LTDCRSTC: LTDC reset
Written at 1 to clear LTDCRST.
Bit 0 Reserved, must be kept at reset value.

14.10.200 RCC divider enable clear register (RCC_DIVENCR)

Address offset: 0x1240
Reset value: 0x0000 0000
This register is used to enable the RCC IC dividers in Run, Sleep, or Stop mode. It is reset
by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IC20EN IC19EN IC18EN IC17EN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
C C C C
w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC16EN IC15EN IC14EN IC13EN IC12EN IC11EN IC10EN IC9EN IC8EN IC7EN IC6EN IC5EN IC4EN IC3EN IC2EN IC1EN
C C C C C C C C C C C C C C C C
w w w w w w w w w w w w w w w w

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 IC20ENC: IC20 enable
Written at 1 to clear IC20EN.
Bit 18 IC19ENC: IC19 enable
Written at 1 to clear IC19EN.
Bit 17 IC18ENC: IC18 enable
Written at 1 to clear IC18EN.
Bit 16 IC17ENC: IC17 enable
Written at 1 to clear IC17EN.
Bit 15 IC16ENC: IC16 enable
Written at 1 to clear IC16EN.
Bit 14 IC15ENC: IC15 enable
Written at 1 to clear IC15EN.
Bit 13 IC14ENC: IC14 enable
Written at 1 to clear IC14EN.
Bit 12 IC13ENC: IC13 enable
Written at 1 to clear IC13EN.
Bit 11 IC12ENC: IC12 enable
Written at 1 to clear IC12EN.

710/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bit 10 IC11ENC: IC11 enable

Written at 1 to clear IC11EN.
Bit 9 IC10ENC: IC10 enable
Written at 1 to clear IC10EN.
Bit 8 IC9ENC: IC9 enable
Written at 1 to clear IC9EN.
Bit 7 IC8ENC: IC8 enable
Written at 1 to clear IC8EN.
Bit 6 IC7ENC: IC7 enable
Written at 1 to clear IC7EN.
Bit 5 IC6ENC: IC6 enable
Written at 1 to clear IC6EN.
Bit 4 IC5ENC: IC5 enable
Written at 1 to clear IC5EN.
Bit 3 IC4ENC: IC4 enable
Written at 1 to clear IC4EN.
Bit 2 IC3ENC: IC3 enable
Written at 1 to clear IC3EN.
Bit 1 IC2ENC: IC2 enable
Written at 1 to clear IC2EN.
Bit 0 IC1ENC: IC1 enable
Written at 1 to clear IC1EN.

14.10.201 RCC bus enable clear register (RCC_BUSENCR)

Address offset: 0x1244
Reset value: 0x0000 0000
This register is used to enable the RCC bus in Run and Sleep modes (in Sleep mode, each
bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the VCORE
voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACLKN ACLKN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
CENC ENC
w w

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 ACLKNCENC: ACLKNC enable
Written at 1 to clear ACLKNCEN.
Bit 0 ACLKNENC: ACLKN enable
Written at 1 to clear ACLKNEN.

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Reset and clock control (RCC) RM0486

14.10.202 RCC miscellaneous enable clear register (RCC_MISCENCR)

Address offset: 0x1248
Reset value: 0x0000 0000
This register is used to enable the RCC miscellaneous in Run and Sleep modes (in Sleep
mode, each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in
the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XSPIPHY
PER MCO2 MCO1 DBG
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. COMP
ENC ENC ENC ENC
ENC
w w w w w

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 PERENC: PER enable
Written at 1 to clear PEREN.
Bits 5:4 Reserved, must be kept at reset value.
Bit 3 XSPIPHYCOMPENC: XSPIPHYCOMP enable
Written at 1 to clear XSPIPHYCOMPEN.
Bit 2 MCO2ENC: MCO2 enable
Written at 1 to clear MCO2EN.
Bit 1 MCO1ENC: MCO1 enable
Written at 1 to clear MCO1EN.
Bit 0 DBGENC: DBG enable
Written at 1 to clear DBGEN.

14.10.203 RCC memory enable clear register (RCC_MEMENCR)

Address offset: 0x124C
Reset value: 0x0000 0000
This register is used to enable the RCC memory in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOT VENCR CACHE FLEXR AXISR AXISR BKPSR AHBSR AHBSR AXISR AXISR AXISR AXISR
Res. Res. Res. ROME AMEN AXIRA AMEN AM2EN AM1EN AMEN AM2EN AM1EN AM6EN AM5EN AM4EN AM3EN
NC C MENC C C C C C C C C C C
w w w w w w w w w w w w w

712/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 BOOTROMENC: BootROM enable
Written at 1 to clear BOOTROMEN.
Bit 11 VENCRAMENC: VENCRAM enable
Written at 1 to clear VENCRAMEN.
Bit 10 CACHEAXIRAMENC: CACHEAXIRAM enable
Written at 1 to clear CACHEAXIRAMEN.
Bit 9 FLEXRAMENC: FLEXRAM enable
Written at 1 to clear FLEXRAMEN.
Bit 8 AXISRAM2ENC: AXISRAM2 enable
Written at 1 to clear AXISRAM2EN.
Bit 7 AXISRAM1ENC: AXISRAM1 enable
Written at 1 to clear AXISRAM1EN.
Bit 6 BKPSRAMENC: BKPSRAM enable
Written at 1 to clear BKPSRAMEN.
Bit 5 AHBSRAM2ENC: AHBSRAM2 enable
Written at 1 to clear AHBSRAM2EN.
Bit 4 AHBSRAM1ENC: AHBSRAM1 enable
Written at 1 to clear AHBSRAM1EN.
Bit 3 AXISRAM6ENC: AXISRAM6 enable
Written at 1 to clear AXISRAM6EN.
Bit 2 AXISRAM5ENC: AXISRAM5 enable
Written at 1 to clear AXISRAM5EN.
Bit 1 AXISRAM4ENC: AXISRAM4 enable
Written at 1 to clear AXISRAM4EN.
Bit 0 AXISRAM3ENC: AXISRAM3 enable
Written at 1 to clear AXISRAM3EN.

14.10.204 RCC AHB1 enable clear register (RCC_AHB1ENCR)

Address offset: 0x1250
Reset value: 0x0000 0000
This register is used to enable the RCC AHB1 in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC12 GPDM
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ENC A1ENC
w w

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Reset and clock control (RCC) RM0486

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 ADC12ENC: ADC12 enable
Written at 1 to clear ADC12EN.
Bit 4 GPDMA1ENC: GPDMA1 enable
Written at 1 to clear GPDMA1EN.
Bits 3:0 Reserved, must be kept at reset value.

14.10.205 RCC AHB2 enable clear register (RCC_AHB2ENCR)

Address offset: 0x1254
Reset value: 0x0000 0000
This register is used to enable the RCC AHB2 in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADF1E MDF1E
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
NC NC
w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAMC
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
FGENC
w

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 ADF1ENC: ADF1 enable
Written at 1 to clear ADF1EN.
Bit 16 MDF1ENC: MDF1 enable
Written at 1 to clear MDF1EN.
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 RAMCFGENC: RAMCFG enable
Written at 1 to clear RAMCFGEN.
Bits 11:0 Reserved, must be kept at reset value.

14.10.206 RCC AHB3 enable clear register (RCC_AHB3ENCR)

Address offset: 0x1258
Reset value: 0x0000 0000
This register is used to enable the RCC AHB3 in Run and Sleep modes (in Sleep mode,
each bit in this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

714/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RISAF IACEN RIFSC PKAEN SAESE CRYPE HASHE RNGE
Res. Res. Res. Res. Res. Res. Res. Res.
ENC C ENC C NC NC NC NC
w w w w w w w w

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 RISAFENC: RISAF enable
Written at 1 to clear RISAFEN.
Bits 13:11 Reserved, must be kept at reset value.
Bit 10 IACENC: IAC enable
Written at 1 to clear IACEN.
Bit 9 RIFSCENC: RIFSC enable
Written at 1 to clear RIFSCEN.
Bit 8 PKAENC: PKA enable
Written at 1 to clear PKAEN.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 SAESENC: SAES enable
Written at 1 to clear SAESEN.
Bit 3 Reserved, must be kept at reset value.
Bit 2 CRYPENC: CRYP enable
Written at 1 to clear CRYPEN.
Bit 1 HASHENC: HASH enable
Written at 1 to clear HASHEN.
Bit 0 RNGENC: RNG enable
Written at 1 to clear RNGEN.

14.10.207 RCC AHB4 enable clear register (RCC_AHB4ENCR)

Address offset: 0x125C
Reset value: 0x0000 0000
This register is used to enable the RCC AHB4 in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCE PWRE GPIOQ
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
NC NC ENC
w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOP GPIOO GPION GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Res. Res. Res. Res. Res.
ENC ENC ENC ENC ENC ENC ENC ENC ENC ENC ENC
w w w w w w w w w w w

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Reset and clock control (RCC) RM0486

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 CRCENC: CRC enable
Written at 1 to clear CRCEN.
Bit 18 PWRENC: PWR enable
Written at 1 to clear PWREN.
Bit 17 Reserved, must be kept at reset value.
Bit 16 GPIOQENC: GPIO Q enable
Written at 1 to clear GPIOQEN.
Bit 15 GPIOPENC: GPIO P enable
Written at 1 to clear GPIOPEN.
Bit 14 GPIOOENC: GPIO O enable
Written at 1 to clear GPIOOEN.
Bit 13 GPIONENC: GPIO N enable
Written at 1 to clear GPIONEN.
Bits 12:8 Reserved, must be kept at reset value.
Bit 7 GPIOHENC: GPIO H enable
Written at 1 to clear GPIOHEN.
Bit 6 GPIOGENC: GPIO G enable
Written at 1 to clear GPIOGEN.
Bit 5 GPIOFENC: GPIO F enable
Written at 1 to clear GPIOFEN.
Bit 4 GPIOEENC: GPIO E enable
Written at 1 to clear GPIOEEN.
Bit 3 GPIODENC: GPIO D enable
Written at 1 to clear GPIODEN.
Bit 2 GPIOCENC: GPIO C enable
Written at 1 to clear GPIOCEN.
Bit 1 GPIOBENC: GPIO B enable
Written at 1 to clear GPIOBEN.
Bit 0 GPIOAENC: GPIO A enable
Written at 1 to clear GPIOAEN.

14.10.208 RCC AHB5 enable clear register (RCC_AHB5ENCR)

Address offset: 0x1260
Reset value: 0x0000 0000
This register is used to enable the RCC AHB5 in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

716/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CACHE OTGP OTGP GFXM
NPUEN OTG2E OTG1E ETH1E ETH1R ETH1T ETH1M GPU2D MCE4E XSPI3E MCE3E
AXIEN HY2EN HY1EN Res. MUEN
C NC NC NC XENC XENC ACENC ENC NC NC NC
C C C C
w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCE2E MCE1E XSPIM XSPI2E SDMM SDMM PSSIE XSPI1E FMCE JPEGE DMA2D HPDM
Res. Res. Res. Res.
NC NC ENC NC C1ENC C2ENC NC NC NC NC ENC A1ENC
w w w w w w w w w w w w

Bit 31 NPUENC: NPU enable

Written at 1 to clear NPUEN.
Bit 30 CACHEAXIENC: CACHEAXI enable
Written at 1 to clear CACHEAXIEN.
Bit 29 OTG2ENC: OTG2 enable
Written at 1 to clear OTG2EN.
Bit 28 OTGPHY2ENC: OTGPHY2 enable
Written at 1 to clear OTGPHY2EN.
Bit 27 OTGPHY1ENC: OTGPHY1 enable
Written at 1 to clear OTGPHY1EN.
Bit 26 OTG1ENC: OTG1 enable
Written at 1 to clear OTG1EN.
Bit 25 ETH1ENC: ETH1 enable
Written at 1 to clear ETH1EN.
Bit 24 ETH1RXENC: ETH1RX enable
Written at 1 to clear ETH1RXEN.
Bit 23 ETH1TXENC: ETH1TX enable
Written at 1 to clear ETH1TXEN.
Bit 22 ETH1MACENC: ETH1MAC enable
Written at 1 to clear ETH1MACEN.
Bit 21 Reserved, must be kept at reset value.
Bit 20 GPU2DENC: GPU2D enable
Written at 1 to clear GPU2DEN.
Bit 19 GFXMMUENC: GFXMMU enable
Written at 1 to clear GFXMMUEN.
Bit 18 MCE4ENC: MCE4 enable
Written at 1 to clear MCE4EN.
Bit 17 XSPI3ENC: XSPI3 enable
Written at 1 to clear XSPI3EN.
Bit 16 MCE3ENC: MCE3 enable
Written at 1 to clear MCE3EN.
Bit 15 MCE2ENC: MCE2 enable
Written at 1 to clear MCE2EN.

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Reset and clock control (RCC) RM0486

Bit 14 MCE1ENC: MCE1 enable

Written at 1 to clear MCE1EN.
Bit 13 XSPIMENC: XSPIM enable
Written at 1 to clear XSPIMEN.
Bit 12 XSPI2ENC: XSPI2 enable
Written at 1 to clear XSPI2EN.
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 SDMMC1ENC: SDMMC1 enable
Written at 1 to clear SDMMC1EN.
Bit 7 SDMMC2ENC: SDMMC2 enable
Written at 1 to clear SDMMC2EN.
Bit 6 PSSIENC: PSSI enable
Written at 1 to clear PSSIEN.
Bit 5 XSPI1ENC: XSPI1 enable
Written at 1 to clear XSPI1EN.
Bit 4 FMCENC: FMC enable
Written at 1 to clear FMCEN.
Bit 3 JPEGENC: JPEG enable
Written at 1 to clear JPEGEN.
Bit 2 Reserved, must be kept at reset value.
Bit 1 DMA2DENC: DMA2D enable
Written at 1 to clear DMA2DEN.
Bit 0 HPDMA1ENC: HPDMA1 enable
Written at 1 to clear HPDMA1EN.

14.10.209 RCC APB1L enable clear register (RCC_APB1LENCR)

Address offset: 0x1264
Reset value: 0x0000 0000
This register is used to enable the RCC APB1L in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPDIF
UART8 UART7 I3C2EN I3C1EN I2C3EN I2C2EN I2C1EN UART5 UART4 USART USART
Res. Res. Res. Res. RX1EN
ENC ENC C C C C C ENC ENC 3ENC 2ENC
C
w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3E SPI2E TIM11E TIM10E LPTIM1 TIM14E TIM13E TIM12E TIM7E TIM6E TIM5E TIM4E TIM3E TIM2E
Res. Res.
NC NC NC NC ENC NC NC NC NC NC NC NC NC NC
w w w w w w w w w w w w w w

Bit 31 UART8ENC: UART8 enable

Written at 1 to clear UART8EN.

718/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bit 30 UART7ENC: UART7 enable

Written at 1 to clear UART7EN.
Bits 29:26 Reserved, must be kept at reset value.
Bit 25 I3C2ENC: I3C2 enable
Written at 1 to clear I3C2EN.
Bit 24 I3C1ENC: I3C1 enable
Written at 1 to clear I3C1EN.
Bit 23 I2C3ENC: I2C3 enable
Written at 1 to clear I2C3EN.
Bit 22 I2C2ENC: I2C2 enable
Written at 1 to clear I2C2EN.
Bit 21 I2C1ENC: I2C1 enable
Written at 1 to clear I2C1EN.
Bit 20 UART5ENC: UART5 enable
Written at 1 to clear UART5EN.
Bit 19 UART4ENC: UART4 enable
Written at 1 to clear UART4EN.
Bit 18 USART3ENC: USART3 enable
Written at 1 to clear USART3EN.
Bit 17 USART2ENC: USART2 enable
Written at 1 to clear USART2EN.
Bit 16 SPDIFRX1ENC: SPDIFRX1 enable
Written at 1 to clear SPDIFRX1EN.
Bit 15 SPI3ENC: SPI3 enable
Written at 1 to clear SPI3EN.
Bit 14 SPI2ENC: SPI2 enable
Written at 1 to clear SPI2EN.
Bit 13 TIM11ENC: TIM11 enable
Written at 1 to clear TIM11EN.
Bit 12 TIM10ENC: TIM10 enable
Written at 1 to clear TIM10EN.
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 LPTIM1ENC: LPTIM1 enable
Written at 1 to clear LPTIM1EN.
Bit 8 TIM14ENC: TIM14 enable
Written at 1 to clear TIM14EN.
Bit 7 TIM13ENC: TIM13 enable
Written at 1 to clear TIM13EN.
Bit 6 TIM12ENC: TIM12 enable
Written at 1 to clear TIM12EN.

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Reset and clock control (RCC) RM0486

Bit 5 TIM7ENC: TIM7 enable

Written at 1 to clear TIM7EN.
Bit 4 TIM6ENC: TIM6 enable
Written at 1 to clear TIM6EN.
Bit 3 TIM5ENC: TIM5 enable
Written at 1 to clear TIM5EN.
Bit 2 TIM4ENC: TIM4 enable
Written at 1 to clear TIM4EN.
Bit 1 TIM3ENC: TIM3 enable
Written at 1 to clear TIM3EN.
Bit 0 TIM2ENC: TIM2 enable
Written at 1 to clear TIM2EN.

14.10.210 RCC APB1H enable clear register (RCC_APB1HENCR)

Address offset: 0x1268
Reset value: 0x0000 0000
This register is used to enable the RCC APB1H in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ENC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN MDIOS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ENC ENC
w w

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 UCPD1ENC: UCPD1 enable
Written at 1 to clear UCPD1EN.
Bits 17:9 Reserved, must be kept at reset value.
Bit 8 FDCANENC: FDCAN enable
Written at 1 to clear FDCANEN.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 MDIOSENC: MDIOS enable
Written at 1 to clear MDIOSEN.
Bits 4:0 Reserved, must be kept at reset value.

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RM0486 Reset and clock control (RCC)

14.10.211 RCC APB2 enable clear register (RCC_APB2ENCR)

Address offset: 0x126C
Reset value: 0x0000 0000
This register is used to enable the RCC APB2 in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAI2E SAI1E SPI5E TIM9E TIM17E TIM16E TIM15E
Res. Res. Res. Res. Res. Res. Res. Res. Res.
NC NC NC NC NC NC NC
w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIM18E SPI4E SPI1E USART UART9 USART USART TIM8E TIM1E
Res. Res. Res. Res. Res. Res. Res.
NC NC NC 10ENC ENC 6ENC 1ENC NC NC
w w w w w w w w w

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 SAI2ENC: SAI2 enable
Written at 1 to clear SAI2EN.
Bit 21 SAI1ENC: SAI1 enable
Written at 1 to clear SAI1EN.
Bit 20 SPI5ENC: SPI5 enable
Written at 1 to clear SPI5EN.
Bit 19 TIM9ENC: TIM9 enable
Written at 1 to clear TIM9EN.
Bit 18 TIM17ENC: TIM17 enable
Written at 1 to clear TIM17EN.
Bit 17 TIM16ENC: TIM16 enable
Written at 1 to clear TIM16EN.
Bit 16 TIM15ENC: TIM15 enable
Written at 1 to clear TIM15EN.
Bit 15 TIM18ENC: TIM18 enable
Written at 1 to clear TIM18EN.
Bit 14 Reserved, must be kept at reset value.
Bit 13 SPI4ENC: SPI4 enable
Written at 1 to clear SPI4EN.
Bit 12 SPI1ENC: SPI1 enable
Written at 1 to clear SPI1EN.
Bits 11:8 Reserved, must be kept at reset value.
Bit 7 USART10ENC: USART10 enable
Written at 1 to clear USART10EN.
Bit 6 UART9ENC: UART9 enable
Written at 1 to clear UART9EN.

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Reset and clock control (RCC) RM0486

Bit 5 USART6ENC: USART6 enable

Written at 1 to clear USART6EN.
Bit 4 USART1ENC: USART1 enable
Written at 1 to clear USART1EN.
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8ENC: TIM8 enable
Written at 1 to clear TIM8EN.
Bit 0 TIM1ENC: TIM1 enable
Written at 1 to clear TIM1EN.

14.10.212 RCC APB3 enable clear register (RCC_APB3ENCR)

Address offset: 0x1270
Reset value: 0x0000 0000
This register is used to enable the RCC APB3 in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DFTENC Res. Res.
w

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 DFTENC: DFT enable
Written at 1 to clear DFTEN.
Bits 1:0 Reserved, must be kept at reset value.

14.10.213 RCC APB4L enable clear register (RCC_APB4LENCR)

Address offset: 0x1274
Reset value: 0x0000 0000
This register is used to enable the RCC APB4L in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCAP RTCEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
BENC C
w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFB LPTIM5 LPTIM4 LPTIM3 LPTIM2 I2C4EN SPI6E LPUAR HDPEN
Res. Res. Res. Res. Res. Res. Res.
UFENC ENC ENC ENC ENC C NC T1ENC C
w w w w w w w w w

722/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 RTCAPBENC: RTCAPB enable
Written at 1 to clear RTCAPBEN.
Bit 16 RTCENC: RTC enable
Written at 1 to clear RTCEN.
Bit 15 VREFBUFENC: VREFBUF enable
Written at 1 to clear VREFBUFEN.
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 LPTIM5ENC: LPTIM5 enable
Written at 1 to clear LPTIM5EN.
Bit 11 LPTIM4ENC: LPTIM4 enable
Written at 1 to clear LPTIM4EN.
Bit 10 LPTIM3ENC: LPTIM3 enable
Written at 1 to clear LPTIM3EN.
Bit 9 LPTIM2ENC: LPTIM2 enable
Written at 1 to clear LPTIM2EN.
Bit 8 Reserved, must be kept at reset value.
Bit 7 I2C4ENC: I2C4 enable
Written at 1 to clear I2C4EN.
Bit 6 Reserved, must be kept at reset value.
Bit 5 SPI6ENC: SPI6 enable
Written at 1 to clear SPI6EN.
Bit 4 Reserved, must be kept at reset value.
Bit 3 LPUART1ENC: LPUART1 enable
Written at 1 to clear LPUART1EN.
Bit 2 HDPENC: HDP enable
Written at 1 to clear HDPEN.
Bits 1:0 Reserved, must be kept at reset value.

14.10.214 RCC APB4H enable clear register (RCC_APB4HENCR)

Address offset: 0x1278
Reset value: 0x0000 0000
This register is used to enable the RCC APB4H in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

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Reset and clock control (RCC) RM0486

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTSEN BSECE SYSCF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
C NC GENC
w w w

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 DTSENC: DTS enable
Written at 1 to clear DTSEN.
Bit 1 BSECENC: BSEC enable
Written at 1 to clear BSECEN.
Bit 0 SYSCFGENC: SYSCFG enable
Written at 1 to clear SYSCFGEN.

14.10.215 RCC APB5 enable clear register (RCC_APB5ENCR)

Address offset: 0x127C
Reset value: 0x0000 0000
This register is used to enable the RCC APB5 in Run and Sleep modes (in Sleep mode,
each bit of this register is AND-ed with the LPEN bit). It is reset by sys_rstn, and is in the
VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSIEN VENCE GFXTI DCMIP LTDCE
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
C NC MENC PENC NC
w w w w w

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 CSIENC: CSI enable
Written at 1 to clear CSIEN.
Bit 5 VENCENC: VENC enable
Written at 1 to clear VENCEN.
Bit 4 GFXTIMENC: GFXTIM enable
Written at 1 to clear GFXTIMEN.
Bit 3 Reserved, must be kept at reset value.
Bit 2 DCMIPPENC: DCMIPP enable
Written at 1 to clear DCMIPPEN.
Bit 1 LTDCENC: LTDC enable
Written at 1 to clear LTDCEN.
Bit 0 Reserved, must be kept at reset value.

724/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

14.10.216 RCC bus sleep enable clear register (RCC_BUSLPENCR)

Address offset: 0x1284
Reset value: 0x0000 0000
This register is used to enable the RCC ACLKN bus in Sleep mode (each bit of this register
is AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACLKN
ACLKN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLPEN
LPENC
C
w w

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 ACLKNCLPENC: ACLKNC enable in Sleep mode
Written at 1 to clear ACLKNCLPEN.
Bit 0 ACLKNLPENC: ACLKN enable in Sleep mode
Written at 1 to clear ACLKNLPEN.

14.10.217 RCC miscellaneous sleep enable clear register

(RCC_MISCLPENCR)
Address offset: 0x1288
Reset value: 0x0000 0000
This register is used to enable the RCC DBG miscellaneous in Sleep mode (each bit of this
register is AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage
domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XSPIP
PERLP HYCO DBGLP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ENC MPLPE ENC
NC
w w w

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 PERLPENC: PER enable in Sleep mode
Written at 1 to clear PERLPEN.
Bits 5:4 Reserved, must be kept at reset value.
Bit 3 XSPIPHYCOMPLPENC: XSPIPHYCOMP enable in Sleep mode
Written at 1 to clear XSPIPHYCOMPLPEN.
Bits 2:1 Reserved, must be kept at reset value.

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Reset and clock control (RCC) RM0486

Bit 0 DBGLPENC: DBG enable in Sleep mode

Written at 1 to clear DBGLPEN.

14.10.218 RCC memory sleep enable clear register (RCC_MEMLPENCR)

Address offset: 0x128C
Reset value: 0x0000 0000
This register is used to enable the RCC AXISRAM3 memory in Sleep mode (each bit of this
register is AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage
domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CACHE
BOOT VENCR FLEXR AXISR AXISR BKPSR AHBSR AHBSR AXISR AXISR AXISR AXISR
AXIRA
Res. Res. Res. ROML AMLPE AMLPE AM2LP AM1LP AMLPE AM2LP AM1LP AM6LP AM5LP AM4LP AM3LP
MLPEN
PENC NC NC ENC ENC NC ENC ENC ENC ENC ENC ENC
C
w w w w w w w w w w w w w

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 BOOTROMLPENC: BootROM enable in Sleep mode
Written at 1 to clear BOOTROMLPEN.
Bit 11 VENCRAMLPENC: VENCRAM enable in Sleep mode
Written at 1 to clear VENCRAMLPEN.
Bit 10 CACHEAXIRAMLPENC: CACHEAXIRAM enable in Sleep mode
Written at 1 to clear CACHEAXIRAMLPEN.
Bit 9 FLEXRAMLPENC: FLEXRAM enable in Sleep mode
Written at 1 to clear FLEXRAMLPEN.
Bit 8 AXISRAM2LPENC: AXISRAM2 enable in Sleep mode
Written at 1 to clear AXISRAM2LPEN.
Bit 7 AXISRAM1LPENC: AXISRAM1 enable in Sleep mode
Written at 1 to clear AXISRAM1LPEN.
Bit 6 BKPSRAMLPENC: BKPSRAM enable in Sleep mode
Written at 1 to clear BKPSRAMLPEN.
Bit 5 AHBSRAM2LPENC: AHBSRAM2 enable in Sleep mode
Written at 1 to clear AHBSRAM2LPEN.
Bit 4 AHBSRAM1LPENC: AHBSRAM1 enable in Sleep mode
Written at 1 to clear AHBSRAM1LPEN.
Bit 3 AXISRAM6LPENC: AXISRAM6 enable in Sleep mode
Written at 1 to clear AXISRAM6LPEN.
Bit 2 AXISRAM5LPENC: AXISRAM5 enable in Sleep mode
Written at 1 to clear AXISRAM5LPEN.

726/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bit 1 AXISRAM4LPENC: AXISRAM4 enable in Sleep mode

Written at 1 to clear AXISRAM4LPEN.
Bit 0 AXISRAM3LPENC: AXISRAM3 enable in Sleep mode
Written at 1 to clear AXISRAM3LPEN.

14.10.219 RCC AHB1 sleep enable clear register (RCC_AHB1LPENCR)

Address offset: 0x1290
Reset value: 0x0000 0000
This register is used to enable the RCC AHB1 in Sleep mode (each bit of this register is
AND-ed with the EN bit).It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPDM
ADC12
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. A1LPE Res. Res. Res. Res.
LPENC
NC
w w

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 ADC12LPENC: ADC12 enable in Sleep mode
Written at 1 to clear ADC12LPEN.
Bit 4 GPDMA1LPENC: GPDMA1 enable in Sleep mode
Written at 1 to clear GPDMA1LPEN.
Bits 3:0 Reserved, must be kept at reset value.

14.10.220 RCC AHB2 sleep enable clear register (RCC_AHB2LPENCR)

Address offset: 0x1294
Reset value: 0x0000 0000
This register is used to enable the RCC AHB2 in Sleep mode (each bit of this register is
AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADF1L MDF1L
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
PENC PENC
w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAMC
Res. Res. Res. FGLPE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
NC
w

Bits 31:18 Reserved, must be kept at reset value.

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Reset and clock control (RCC) RM0486

Bit 17 ADF1LPENC: ADF1 enable in Sleep mode

Written at 1 to clear ADF1LPEN.
Bit 16 MDF1LPENC: MDF1 enable in Sleep mode
Written at 1 to clear MDF1LPEN.
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 RAMCFGLPENC: RAMCFG enable in Sleep mode
Written at 1 to clear RAMCFGLPEN.
Bits 11:0 Reserved, must be kept at reset value.

14.10.221 RCC AHB3 sleep enable clear register (RCC_AHB3LPENCR)

Address offset: 0x1298
Reset value: 0x0000 0000
This register is used to enable the RCC RNG AHB3 in Sleep mode (each bit of this register
is AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RISAFL IACLP RIFSC PKALP SAESL CRYPL HASHL RNGLP
Res. Res. Res. Res. Res. Res. Res. Res.
PENC ENC LPENC ENC PENC PENC PENC ENC
w w w w w w w w

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 RISAFLPENC: RISAF enable in Sleep mode
Written at 1 to clear RISAFLPEN.
Bits 13:11 Reserved, must be kept at reset value.
Bit 10 IACLPENC: IAC enable in Sleep mode
Written at 1 to clear IACLPEN.
Bit 9 RIFSCLPENC: RIFSC enable in Sleep mode
Written at 1 to clear RIFSCLPEN.
Bit 8 PKALPENC: PKA enable in Sleep mode
Written at 1 to clear PKALPEN.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 SAESLPENC: SAES enable in Sleep mode
Written at 1 to clear SAESLPEN.
Bit 3 Reserved, must be kept at reset value.
Bit 2 CRYPLPENC: CRYP enable in Sleep mode
Written at 1 to clear CRYPLPEN.
Bit 1 HASHLPENC: HASH enable in Sleep mode
Written at 1 to clear HASHLPEN.

728/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bit 0 RNGLPENC: RNG enable in Sleep mode

Written at 1 to clear RNGLPEN.

14.10.222 RCC AHB4 sleep enable clear register (RCC_AHB4LPENCR)

Address offset: 0x129C
Reset value: 0x0000 0000
This register is used to enable the RCC GPIOA AHB4 in Sleep mode (each bit of this
register is AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage
domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCLP PWRL GPIOQ
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ENC PENC LPENC
w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOP GPIOO GPION GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Res. Res. Res. Res. Res.
LPENC LPENC LPENC LPENC LPENC LPENC LPENC LPENC LPENC LPENC LPENC
w w w w w w w w w w w

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 CRCLPENC: CRC enable in Sleep mode
Written at 1 to clear CRCLPEN.
Bit 18 PWRLPENC: PWR enable in Sleep mode
Written at 1 to clear PWRLPEN.
Bit 17 Reserved, must be kept at reset value.
Bit 16 GPIOQLPENC: GPIO Q enable in Sleep mode
Written at 1 to clear GPIOQLPEN.
Bit 15 GPIOPLPENC: GPIO P enable in Sleep mode
Written at 1 to clear GPIOPLPEN.
Bit 14 GPIOOLPENC: GPIO O enable in Sleep mode
Written at 1 to clear GPIOOLPEN.
Bit 13 GPIONLPENC: GPIO N enable in Sleep mode
Written at 1 to clear GPIONLPEN.
Bits 12:8 Reserved, must be kept at reset value.
Bit 7 GPIOHLPENC: GPIO H enable in Sleep mode
Written at 1 to clear GPIOHLPEN.
Bit 6 GPIOGLPENC: GPIO G enable in Sleep mode
Written at 1 to clear GPIOGLPEN.
Bit 5 GPIOFLPENC: GPIO F enable in Sleep mode
Written at 1 to clear GPIOFLPEN.
Bit 4 GPIOELPENC: GPIO E enable in Sleep mode
Written at 1 to clear GPIOELPEN.

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Reset and clock control (RCC) RM0486

Bit 3 GPIODLPENC: GPIO D enable in Sleep mode

Written at 1 to clear GPIODLPEN.
Bit 2 GPIOCLPENC: GPIO C enable in Sleep mode
Written at 1 to clear GPIOCLPEN.
Bit 1 GPIOBLPENC: GPIO B enable in Sleep mode
Written at 1 to clear GPIOBLPEN.
Bit 0 GPIOALPENC: GPIO A enable in Sleep mode
Written at 1 to clear GPIOALPEN.

14.10.223 RCC AHB5 sleep enable clear register (RCC_AHB5LPENCR)

Address offset: 0x12A0
Reset value: 0x0000 0000
This register is used to enable the RCC HPDMA1 AHB5 in Sleep mode (each bit of this
register is AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage
domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CACHE OTGP OTGP ETH1R ETH1T ETH1M GFXM
NPULP OTG2L OTG1L ETH1L GPU2D MCE4L XSPI3L MCE3L
AXILPE HY2LP HY1LP XLPEN XLPEN ACLPE Res. MULPE
ENC PENC PENC PENC LPENC PENC PENC PENC
NC ENC ENC C C NC NC
w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMM SDMM HPDM
MCE2L MCE1L XSPIM XSPI2L PSSILP XSPI1L FMCLP JPEGL DMA2D
Res. Res. Res. C1LPE C2LPE Res. A1LPE
PENC PENC LPENC PENC ENC PENC ENC PENC LPENC
NC NC NC
w w w w w w w w w w w w

Bit 31 NPULPENC: NPU enable in Sleep mode

Written at 1 to clear NPULPEN.
Bit 30 CACHEAXILPENC: CACHEAXI enable in Sleep mode
Written at 1 to clear CACHEAXILPEN.
Bit 29 OTG2LPENC: OTG2 enable in Sleep mode
Written at 1 to clear OTG2LPEN.
Bit 28 OTGPHY2LPENC: OTGPHY2 enable in Sleep mode
Written at 1 to clear OTGPHY2LPEN.
Bit 27 OTGPHY1LPENC: OTGPHY1 enable in Sleep mode
Written at 1 to clear OTGPHY1LPEN.
Bit 26 OTG1LPENC: OTG1 enable in Sleep mode
Written at 1 to clear OTG1LPEN.
Bit 25 ETH1LPENC: ETH1 enable in Sleep mode
Written at 1 to clear ETH1LPEN.
Bit 24 ETH1RXLPENC: ETH1RX enable in Sleep mode
Written at 1 to clear ETH1RXLPEN.
Bit 23 ETH1TXLPENC: ETH1TX enable in Sleep mode
Written at 1 to clear ETH1TXLPEN.

730/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bit 22 ETH1MACLPENC: ETH1MAC enable in Sleep mode

Written at 1 to clear ETH1MACLPEN.
Bit 21 Reserved, must be kept at reset value.
Bit 20 GPU2DLPENC: GPU2D enable in Sleep mode
Written at 1 to clear GPULPEN.
Bit 19 GFXMMULPENC: GFXMMU enable in Sleep mode
Written at 1 to clear GFXMMULPEN.
Bit 18 MCE4LPENC: MCE4 enable in Sleep mode
Written at 1 to clear MCE4LPEN.
Bit 17 XSPI3LPENC: XSPI3 enable in Sleep mode
Written at 1 to clear XSPI3LPEN.
Bit 16 MCE3LPENC: MCE3 enable in Sleep mode
Written at 1 to clear MCE3LPEN.
Bit 15 MCE2LPENC: MCE2 enable in Sleep mode
Written at 1 to clear MCE2LPEN.
Bit 14 MCE1LPENC: MCE1 enable in Sleep mode
Written at 1 to clear MCE1LPEN.
Bit 13 XSPIMLPENC: XSPIM enable in Sleep mode
Written at 1 to clear XSPIMLPEN.
Bit 12 XSPI2LPENC: XSPI2 enable in Sleep mode
Written at 1 to clear XSPI2LPEN.
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 SDMMC1LPENC: SDMMC1 enable in Sleep mode
Written at 1 to clear SDMMC1LPEN.
Bit 7 SDMMC2LPENC: SDMMC2 enable in Sleep mode
Written at 1 to clear SDMMC2LPEN.
Bit 6 PSSILPENC: PSSI enable in Sleep mode
Written at 1 to clear PSSILPEN.
Bit 5 XSPI1LPENC: XSPI1 enable in Sleep mode
Written at 1 to clear XSPI1LPEN.
Bit 4 FMCLPENC: FMC enable in Sleep mode
Written at 1 to clear FMCLPEN.
Bit 3 JPEGLPENC: JPEG enable in Sleep mode
Written at 1 to clear JPEGLPEN.
Bit 2 Reserved, must be kept at reset value.
Bit 1 DMA2DLPENC: DMA2D enable in Sleep mode
Written at 1 to clear DMA2DLPEN.
Bit 0 HPDMA1LPENC: HPDMA1 enable in Sleep mode
Written at 1 to clear HPDMA1LPEN.

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Reset and clock control (RCC) RM0486

14.10.224 RCC APB1L sleep enable clear register (RCC_APB1LLPENCR)

Address offset: 0x12A4
Reset value: 0x0000 0000
This register is used to enable the RCC APB1L in Sleep mode (each bit in this register is
AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USART USART SPDIF
UART8 UART7 I3C2LP I3C1LP I2C3LP I2C2LP I2C1LP UART5 UART4
Res. Res. Res. Res. 3LPEN 2LPEN RX1LP
LPENC LPENC ENC ENC ENC ENC ENC LPENC LPENC
C C ENC
w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3LP SPI2LP TIM11L TIM10L WWDG LPTIM1 TIM14L TIM13L TIM12L TIM7LP TIM6LP TIM5LP TIM4LP TIM3LP TIM2LP
Res.
ENC ENC PENC PENC LPENC LPENC PENC PENC PENC ENC ENC ENC ENC ENC ENC
w w w w w w w w w w w w w w w

Bit 31 UART8LPENC: UART8 enable

Written at 1 to clear UART8LPEN.
Bit 30 UART7LPENC: UART7 enable
Written at 1 to clear UART7LPEN.
Bits 29:26 Reserved, must be kept at reset value.
Bit 25 I3C2LPENC: I3C2 enable
Written at 1 to clear I3C2LPEN.
Bit 24 I3C1LPENC: I3C1 enable
Written at 1 to clear I3C1LPEN.
Bit 23 I2C3LPENC: I2C3 enable
Written at 1 to clear I2C3LPEN.
Bit 22 I2C2LPENC: I2C2 enable
Written at 1 to clear I2C2LPEN.
Bit 21 I2C1LPENC: I2C1 enable
Written at 1 to clear I2C1LPEN.
Bit 20 UART5LPENC: UART5 enable
Written at 1 to clear UART5LPEN.
Bit 19 UART4LPENC: UART4 enable
Written at 1 to clear UART4LPEN.
Bit 18 USART3LPENC: USART3 enable
Written at 1 to clear USART3LPEN.
Bit 17 USART2LPENC: USART2 enable
Written at 1 to clear USART2LPEN.
Bit 16 SPDIFRX1LPENC: SPDIFRX1 enable
Written at 1 to clear SPDIFRX1LPEN.
Bit 15 SPI3LPENC: SPI3 enable
Written at 1 to clear SPI3LPEN.

732/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bit 14 SPI2LPENC: SPI2 enable

Written at 1 to clear SPI2LPEN.
Bit 13 TIM11LPENC: TIM11 enable
Written at 1 to clear TIM11LPEN.
Bit 12 TIM10LPENC: TIM10 enable
Written at 1 to clear TIM10LPEN.
Bit 11 WWDGLPENC: WWDG enable
Written at 1 to clear WWDGLPEN.
Bit 10 Reserved, must be kept at reset value.
Bit 9 LPTIM1LPENC: LPTIM1 enable
Written at 1 to clear LPTIM1LPEN.
Bit 8 TIM14LPENC: TIM14 enable
Written at 1 to clear TIM14LPEN.
Bit 7 TIM13LPENC: TIM13 enable
Written at 1 to clear TIM13LPEN.
Bit 6 TIM12LPENC: TIM12 enable
Written at 1 to clear TIM12LPEN.
Bit 5 TIM7LPENC: TIM7 enable
Written at 1 to clear TIM7LPEN.
Bit 4 TIM6LPENC: TIM6 enable
Written at 1 to clear TIM6LPEN.
Bit 3 TIM5LPENC: TIM5 enable
Written at 1 to clear TIM5LPEN.
Bit 2 TIM4LPENC: TIM4 enable
Written at 1 to clear TIM4LPEN.
Bit 1 TIM3LPENC: TIM3 enable
Written at 1 to clear TIM3LPEN.
Bit 0 TIM2LPENC: TIM2 enable
Written at 1 to clear TIM2LPEN.

14.10.225 RCC APB1H sleep enable clear register (RCC_APB1HLPENCR)

Address offset: 0x12A8
Reset value: 0x0000 0000
This register is used to enable the RCC APB1H in Sleep mode (each bit of this register is
AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

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Reset and clock control (RCC) RM0486

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LPENC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN MDIOS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LPENC LPENC
w w

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 UCPD1LPENC: UCPD1 enable
Written at 1 to clear UCPD1LPEN.
Bits 17:9 Reserved, must be kept at reset value.
Bit 8 FDCANLPENC: FDCAN enable
Written at 1 to clear FDCANLPEN.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 MDIOSLPENC: MDIOS enable
Written at 1 to clear MDIOSLPEN.
Bits 4:0 Reserved, must be kept at reset value.

14.10.226 RCC APB2 sleep enable clear register (RCC_APB2LPENCR)

Address offset: 0x12AC
Reset value: 0x0000 0000
This register is used to enable the RCC APB2 in Sleep mode (each bit of this register is
AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAI2LP SAI1LP SPI5LP TIM9LP TIM17L TIM16L TIM15L
Res. Res. Res. Res. Res. Res. Res. Res. Res.
ENC ENC ENC ENC PENC PENC PENC
w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART USART USART
TIM18L SPI4LP SPI1LP UART9 TIM8LP TIM1LP
Res. Res. Res. Res. Res. 10LPE 6LPEN 1LPEN Res. Res.
PENC ENC ENC LPENC ENC ENC
NC C C
w w w w w w w w w

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 SAI2LPENC: SAI2 enable
Written at 1 to clear SAI2LPEN.
Bit 21 SAI1LPENC: SAI1 enable
Written at 1 to clear SAI1LPEN.
Bit 20 SPI5LPENC: SPI5 enable
Written at 1 to clear SPI5LPEN.
Bit 19 TIM9LPENC: TIM9 enable
Written at 1 to clear TIM9LPEN.

734/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bit 18 TIM17LPENC: TIM17 enable

Written at 1 to clear TIM17LPEN.
Bit 17 TIM16LPENC: TIM16 enable
Written at 1 to clear TIM16LPEN.
Bit 16 TIM15LPENC: TIM15 enable
Written at 1 to clear TIM15LPEN.
Bit 15 TIM18LPENC: TIM18 enable
Written at 1 to clear TIM18LPEN.
Bit 14 Reserved, must be kept at reset value.
Bit 13 SPI4LPENC: SPI4 enable
Written at 1 to clear SPI4LPEN.
Bit 12 SPI1LPENC: SPI1 enable
Written at 1 to clear SPI1LPEN.
Bits 11:8 Reserved, must be kept at reset value.
Bit 7 USART10LPENC: USART10 enable
Written at 1 to clear USART10LPEN.
Bit 6 UART9LPENC: UART9 enable
Written at 1 to clear UART9LPEN.
Bit 5 USART6LPENC: USART6 enable
Written at 1 to clear USART6LPEN.
Bit 4 USART1LPENC: USART1 enable
Written at 1 to clear USART1LPEN.
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8LPENC: TIM8 enable
Written at 1 to clear TIM8LPEN.
Bit 0 TIM1LPENC: TIM1 enable
Written at 1 to clear TIM1LPEN.

14.10.227 RCC APB3 sleep enable clear register (RCC_APB3LPENCR)

Address offset: 0x12B0
Reset value: 0x0000 0000
This register is used to enable the RCC- APB3 in Sleep mode (each bit of this register is
AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DFTLP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
ENC
w

RM0486 Rev 2 735/4691

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Reset and clock control (RCC) RM0486

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 DFTLPENC: DFT enable
Written at 1 to clear DFTLPEN.
Bits 1:0 Reserved, must be kept at reset value.

14.10.228 RCC APB4L sleep enable clear register (RCC_APB4LLPENCR)

Address offset: 0x12B4
Reset value: 0x0000 0000
This register is used to enable the RCC APB4L in Sleep mode (each bit of this register is
AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCAP
RTCLP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BLPEN
ENC
C
w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFB LPUAR
LPTIM5 LPTIM4 LPTIM3 LPTIM2 I2C4LP SPI6LP HDPLP
UFLPE Res. Res. Res. Res. Res. T1LPE Res. Res.
LPENC LPENC LPENC LPENC ENC ENC ENC
NC NC
w w w w w w w w w

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 RTCAPBLPENC: RTCAPB enable
Written at 1 to clear RTCAPBLPEN.
Bit 16 RTCLPENC: RTC enable
Written at 1 to clear RTCLPEN.
Bit 15 VREFBUFLPENC: VREFBUF enable
Written at 1 to clear VREFBUFLPEN.
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 LPTIM5LPENC: LPTIM5 enable
Written at 1 to clear LPTIM5LPEN.
Bit 11 LPTIM4LPENC: LPTIM4 enable
Written at 1 to clear LPTIM4LPEN.
Bit 10 LPTIM3LPENC: LPTIM3 enable
Written at 1 to clear LPTIM3LPEN.
Bit 9 LPTIM2LPENC: LPTIM2 enable
Written at 1 to clear LPTIM2LPEN.
Bit 8 Reserved, must be kept at reset value.
Bit 7 I2C4LPENC: I2C4 enable
Written at 1 to clear I2C4LPEN.
Bit 6 Reserved, must be kept at reset value.
Bit 5 SPI6LPENC: SPI6 enable
Written at 1 to clear SPI6LPEN.

736/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bit 4 Reserved, must be kept at reset value.

Bit 3 LPUART1LPENC: LPUART1 enable
Written at 1 to clear LPUART1LPEN.
Bit 2 HDPLPENC: HDP enable
Written at 1 to clear HDPLPEN.
Bits 1:0 Reserved, must be kept at reset value.

14.10.229 RCC APB4H sleep enable clear register (RCC_APB4HLPENCR)

Address offset: 0x12B8
Reset value: 0x0000 0000
This register is used to enable the RCC APB4H in Sleep mode (each bit of this register is
AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSCF
DTSLP BSECL
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. GLPEN
ENC PENC
C
w w w

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 DTSLPENC: DTS enable
Written at 1 to clear DTSLPEN.
Bit 1 BSECLPENC: BSEC enable
Written at 1 to clear BSECLPEN.
Bit 0 SYSCFGLPENC: SYSCFG enable
Written at 1 to clear SYSCFGLPEN.

14.10.230 RCC APB5 sleep enable clear register (RCC_APB5LPENCR)

Address offset: 0x12BC
Reset value: 0x0000 0000
This register is used to enable the RCC- APB5 in Sleep mode (each bit in this register is
AND-ed with the EN bit). It is reset by sys_rstn, and is in the VCORE voltage domain.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GFXTI DCMIP
CSILP VENCL LTDCL
Res. Res. Res. Res. Res. Res. Res. Res. Res. MLPEN Res. PLPEN Res.
ENC PENC PENC
C C
w w w w w

RM0486 Rev 2 737/4691

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Reset and clock control (RCC) RM0486

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 CSILPENC: CSI sleep enable
Written at 1 to clear CSILPEN.
Bit 5 VENCLPENC: VENC sleep enable
Written at 1 to clear VENCLPEN.
Bit 4 GFXTIMLPENC: GFXTIM sleep enable
Written at 1 to clear GFXTIMLPEN.
Bit 3 Reserved, must be kept at reset value.
Bit 2 DCMIPPLPENC: DCMIPP sleep enable
Written at 1 to clear DCMIPPLPEN.
Bit 1 LTDCLPENC: LTDC sleep enable
Written at 1 to clear LTDCLPEN.
Bit 0 Reserved, must be kept at reset value.

14.10.231 RCC oscillator privilege configuration clear register 0

(RCC_PRIVCFGCR0)
Address offset: 0x1784
Reset value: 0x0000 0000
This register is used to control the privileged access rights to the configuration register of
the oscillators. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPRIV bit
defines the privileged protection for the configuration registers of the oscillator: a write
access is denied if the access is unprivileged while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSEPR HSIPRI MSIPRI LSEPR LSIPRI
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
IVC VC VC IVC VC
w w w w w

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 HSEPRIVC: Privileged protection of HSE configuration bits (enable, ready, divider)
Written at 1 to clear HSEPRIV by secure privileged software only. It can be read by any
software.
Bit 3 HSIPRIVC: Privileged protection of HSI configuration bits (enable, ready, divider)
Written at 1 to clear HSIPRIV by secure privileged software only. It can be read by any
software.
Bit 2 MSIPRIVC: Privileged protection of MSI configuration bits (enable, ready, divider)
Written at 1 to clear MSIPRIV by secure privileged software only. It can be read by any
software.
Bit 1 LSEPRIVC: Privileged protection of LSE configuration bits (enable, ready, divider)
Written at 1 to clear LSEPRIV by secure privileged software only. It can be read by any
software.

738/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bit 0 LSIPRIVC: Privileged protection of LSI configuration bits (enable, ready, divider)
Written at 1 to clear LSIPRIV by secure privileged software only. It can be read by any
software.

14.10.232 RCC oscillator public configuration clear register 0

(RCC_PUBCFGCR0)
Address offset: 0x178C
Reset value: 0x0000 0000
This register is used to control the public access rights to the configuration register of the
oscillators. It is reset by sys_rstn and is in VCORE voltage domain. Each xxPUB bit defines
the public protection for the configuration registers of the oscillator: a write access is denied
if the access is non-public while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSEPU HSIPU MSIPU LSEPU LSIPU
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
BC BC BC BC BC
w w w w w

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 HSEPUBC: Public protection of HSE configuration bits (enable, ready, divider)
Written at 1 to clear HSEPUB by secure privileged software only. It can be read by any
software.
Bit 3 HSIPUBC: Public protection of HSI configuration bits (enable, ready, divider)
Written at 1 to clear HSIPUB by secure privileged software only. It can be read by any
software.
Bit 2 MSIPUBC: Public protection of MSI configuration bits (enable, ready, divider)
Written at 1 to clear MSIPUB by secure privileged software only. It can be read by any
software.
Bit 1 LSEPUBC: Public protection of LSE configuration bits (enable, ready, divider)
Written at 1 to clear LSEPUB by secure privileged software only. It can be read by any
software.
Bit 0 LSIPUBC: Public protection of LSI configuration bits (enable, ready, divider)
Written at 1 to clear LSIPUB by secure privileged software only. It can be read by any
software.

14.10.233 RCC PLL privilege configuration clear register 1

(RCC_PRIVCFGCR1)
Address offset: 0x1794
Reset value: 0x0000 0000

RM0486 Rev 2 739/4691

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Reset and clock control (RCC) RM0486

This register is used to control the privileged access rights to the configuration register of
the PLLs. It is reset by sys_rstn and is in VCORE voltage domain. Each xxPRIV bit defines
the privileged protection for the configuration registers of the PLL: a write access is denied if
the access is unprivileged while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4P PLL3P PLL2P PLL1P
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RIVC RIVC RIVC RIVC
w w w w

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 PLL4PRIVC: Privileged protection of PLL4 configuration bits (enable, ready, divider)
Written at 1 to clear PLL4PRIV by secure privileged software only. It can be read by any
software.
Bit 2 PLL3PRIVC: Privileged protection of PLL3 configuration bits (enable, ready, divider)
Written at 1 to clear PLL3PRIV by secure privileged software only. It can be read by any
software.
Bit 1 PLL2PRIVC: Privileged protection of PLL2 configuration bits (enable, ready, divider)
Written at 1 to clear PLL2PRIV by secure privileged software only. It can be read by any
software.
Bit 0 PLL1PRIVC: Privileged protection of PLL1 configuration bits (enable, ready, divider)
Written at 1 to clear PLL1PRIV by secure privileged software only. It can be read by any
software.

14.10.234 RCC PLL public configuration clear register 1 (RCC_PUBCFGCR1)

Address offset: 0x179C
Reset value: 0x0000 0000
This register is used to control the public access rights to the configuration register of the
PLLs. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPUB bit defines
the public protection for the configuration registers of the PLL: a write access is denied if the
access is non-public while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4P PLL3P PLL2P PLL1P
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
UBC UBC UBC UBC
w w w w

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 PLL4PUBC: Public protection of PLL4 configuration bits (enable, ready, divider)
Written at 1 to clear PLL4PUB by secure privileged software only. It can be read by any
software.

740/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bit 2 PLL3PUBC: Public protection of PLL3 configuration bits (enable, ready, divider)
Written at 1 to clear PLL3PUB by secure privileged software only. It can be read by any
software.
Bit 1 PLL2PUBC: Public protection of te PLL2 configuration bits (enable, ready, divider)
Written at 1 to clear PLL2PUB by secure privileged software only. It can be read by any
software.
Bit 0 PLL1PUBC: Public protection of th PLL1 configuration bits (enable, ready, divider)
Written at 1 to clear PLL1PUB by secure privileged software only. It can be read by any
software.

14.10.235 RCC divider privilege configuration clear register 2

(RCC_PRIVCFGCR2)
Address offset: 0x17A4
Reset value: 0x0000 0000
This register is used to control the privilege access rights to the configuration register of the
dividers. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPRIV bit
defines the privileged protection for the configuration registers of the divider: a write access
is denied if the access is unprivileged while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IC20PR IC19PR IC18PR IC17PR
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
IVC IVC IVC IVC
w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC16PR IC15PR IC14PR IC13PR IC12PR IC11PR IC10PR IC9PRI IC8PRI IC7PRI IC6PRI IC5PRI IC4PRI IC3PRI IC2PRI IC1PRI
IVC IVC IVC IVC IVC IVC IVC VC VC VC VC VC VC VC VC VC
w w w w w w w w w w w w w w w w

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 IC20PRIVC: Privileged protection of IC20 configuration bits (enable, ready, divider)
Written at 1 to clear IC20PRIV by secure privileged software only. It can be read by any
software.
Bit 18 IC19PRIVC: Privileged protection of IC19 configuration bits (enable, ready, divider)
Written at 1 to clear IC19PRIV by secure privileged software only. It can be read by any
software.
Bit 17 IC18PRIVC: Privileged protection of IC18 configuration bits (enable, ready, divider)
Written at 1 to clear IC18PRIV by secure privileged software only. It can be read by any
software.
Bit 16 IC17PRIVC: Privileged protection of IC17 configuration bits (enable, ready, divider)
Written at 1 to clear IC17PRIV by secure privileged software only. It can be read by any
software.
Bit 15 IC16PRIVC: Privileged protection of IC16 configuration bits (enable, ready, divider)
Written at 1 to clear IC16PRIV by secure privileged software only. It can be read by any
software.

RM0486 Rev 2 741/4691

779
Reset and clock control (RCC) RM0486

Bit 14 IC15PRIVC: Privileged protection of IC15 configuration bits (enable, ready, divider)
Written at 1 to clear IC15PRIV by secure privileged software only. It can be read by any
software.
Bit 13 IC14PRIVC: Privileged protection of IC14 configuration bits (enable, ready, divider)
Written at 1 to clear IC14PRIV by secure privileged software only. It can be read by any
software.
Bit 12 IC13PRIVC: Privileged protection of IC13 configuration bits (enable, ready, divider)
Written at 1 to clear IC13PRIV by secure privileged software only. It can be read by any
software.
Bit 11 IC12PRIVC: Privileged protection of IC12 configuration bits (enable, ready, divider)
Written at 1 to clear IC12PRIV by secure privileged software only. It can be read by any
software.
Bit 10 IC11PRIVC: Privileged protection of IC11 configuration bits (enable, ready, divider)
Written at 1 to clear IC11PRIV by secure privileged software only. It can be read by any
software.
Bit 9 IC10PRIVC: Privileged protection of IC10 configuration bits (enable, ready, divider)
Written at 1 to clear IC10PRIV by secure privileged software only. It can be read by any
software.
Bit 8 IC9PRIVC: Privileged protection of IC9 configuration bits (enable, ready, divider)
Written at 1 to clear IC9PRIV by secure privileged software only. It can be read by any
software.
Bit 7 IC8PRIVC: Privileged protection of IC8 configuration bits (enable, ready, divider)
Written at 1 to clear IC8PRIV by secure privileged software only. It can be read by any
software.
Bit 6 IC7PRIVC: Privileged protection of IC7 configuration bits (enable, ready, divider)
Written at 1 to clear IC7PRIV by secure privileged software only. It can be read by any
software.
Bit 5 IC6PRIVC: Privileged protection of IC6 configuration bits (enable, ready, divider)
Written at 1 to clear IC6PRIV by secure privileged software only. It can be read by any
software.
Bit 4 IC5PRIVC: Privileged protection of the IC5 configuration bits (enable, ready, divider).
Written at 1 to clear IC5PRIV by secure privileged software only. It can read by any software.
Bit 3 IC4PRIVC: Privileged protection of the IC4 configuration bits (enable, ready, divider).
Written at 1 to clear IC4PRIV by secure privileged software only. It can read by any software.
Bit 2 IC3PRIVC: Privileged protection of the IC3 configuration bits (enable, ready, divider).
Written at 1 to clear IC3PRIV by secure privileged software only. It can read by any software.
Bit 1 IC2PRIVC: Privileged protection of the IC2 configuration bits (enable, ready, divider).
Written at 1 to clear IC2PRIV by secure privileged software only. It can read by any software.
Bit 0 IC1PRIVC: Privileged protection of the IC1 configuration bits (enable, ready, divider).
Written at 1 to clear IC1PRIV by secure privileged software only. It can read by any software.

14.10.236 RCC divider public configuration clear register 2

(RCC_PUBCFGCR2)
Address offset: 0x17AC

742/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Reset value: 0x0000 0000

This register is used to control the public access rights to the configuration register of the
dividers. It is reset by sys_rstn, and is in the VCORE voltage [Link] xxPUB bit defines
the public protection for the configuration registers of the divider: a write access is denied if
the access is non-public while the respective bit here is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IC20PU IC19PU IC18PU IC17PU
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
BC BC BC BC
w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC16PU IC15PU IC14PU IC13PU IC12PU IC11PU IC10PU IC9PU IC8PU IC7PU IC6PU IC5PU IC4PU IC3PU IC2PU IC1PU
BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC BC
w w w w w w w w w w w w w w w w

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 IC20PUBC: Public protection of IC20 configuration bits (enable, ready, divider)
Written at 1 to clear IC20PUB by secure privileged software only. It can be read by any
software.
Bit 18 IC19PUBC: Public protection of IC19 configuration bits (enable, ready, divider)
Written at 1 to clear IC19PUB by secure privileged software only. It can be read by any
software.
Bit 17 IC18PUBC: Public protection of IC18 configuration bits (enable, ready, divider)
Written at 1 to clear IC18PUB by secure privileged software only. It can be read by any
software.
Bit 16 IC17PUBC: Public protection of IC17 configuration bits (enable, ready, divider)
Written at 1 to clear IC17PUB by secure privileged software only. It can be read by any
software.
Bit 15 IC16PUBC: Public protection of IC16 configuration bits (enable, ready, divider)
Written at 1 to clear IC16PUB by secure privileged software only. It can be read by any
software.
Bit 14 IC15PUBC: Public protection of IC15 configuration bits (enable, ready, divider)
Written at 1 to clear IC15PUB by secure privileged software only. It can be read by any
software.
Bit 13 IC14PUBC: Public protection of IC14 configuration bits (enable, ready, divider)
Written at 1 to clear IC14PUB by secure privileged software only. It can be read by any
software.
Bit 12 IC13PUBC: Public protection of IC13 configuration bits (enable, ready, divider)
Written at 1 to clear IC13PUB by secure privileged software only. It can be read by any
software.
Bit 11 IC12PUBC: Public protection of IC12 configuration bits (enable, ready, divider)
Written at 1 to clear IC12PUB by secure privileged software only. It can be read by any
software.
Bit 10 IC11PUBC: Public protection of IC11 configuration bits (enable, ready, divider)
Written at 1 to clear IC11PUB by secure privileged software only. It can be read by any
software.

RM0486 Rev 2 743/4691

779
Reset and clock control (RCC) RM0486

Bit 9 IC10PUBC: Public protection of IC10 configuration bits (enable, ready, divider)
Written at 1 to clear IC10PUB by secure privileged software only. It can be read by any
software.
Bit 8 IC9PUBC: Public protection of IC9 configuration bits (enable, ready, divider)
Written at 1 to clear IC9PUB by secure privileged software only. It can be read by any
software.
Bit 7 IC8PUBC: Public protection of IC8 configuration bits (enable, ready, divider)
Written at 1 to clear IC8PUB by secure privileged software only. It can be read by any
software.
Bit 6 IC7PUBC: Public protection of IC7 configuration bits (enable, ready, divider)
Written at 1 to clear IC7PUB by secure privileged software only. It can be read by any
software.
Bit 5 IC6PUBC: Public protection of IC6 configuration bits (enable, ready, divider)
Written at 1 to clear IC6PUB by secure privileged software only. It can be read by any
software.
Bit 4 IC5PUBC: Public protection of IC5 configuration bits (enable, ready, divider)
Written at 1 to clear IC5PUB by secure privileged software only. It can be read by any
software.
Bit 3 IC4PUBC: Public protection of IC4 configuration bits (enable, ready, divider)
Written at 1 to clear IC4PUB by secure privileged software only. It can be read by any
software.
Bit 2 IC3PUBC: Public protection of IC3 configuration bits (enable, ready, divider)
Written at 1 to clear IC3PUB by secure privileged software only. It can be read by any
software.
Bit 1 IC2PUBC: Public protection of IC2 configuration bits (enable, ready, divider)
Written at 1 to clear IC2PUB by secure privileged software only. It can be read by any
software.
Bit 0 IC1PUBC: Public protection of IC1 configuration bits (enable, ready, divider)
Written at 1 to clear IC1PUB by secure privileged software only. It can be read by any
software.

14.10.237 RCC system privilege configuration clear register 3

(RCC_PRIVCFGCR3)
Address offset: 0x17B4
Reset value: 0x0000 0000
This register is used to control the privilege access rights to the configuration register of the
system. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPRIV bit defines
the privileged protection for the configuration registers of the system: a write access is
denied if the access is unprivileged while the respective bit is set.

744/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DFTPR RSTPR INTPRI PERPR BUSPR SYSPR MODP
Res. Res. Res. Res. Res. Res. Res. Res. Res.
IVC IVC VC IVC IVC IVC RIVC
w w w w w w w

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 DFTPRIVC: Privileged protection of DFT configuration bits (enable, ready, divider)
Written at 1 to clear DFTPRIV by secure privileged software only. It can be read by any
software.
Bit 5 RSTPRIVC: Privileged protection of RST configuration bits (enable, ready, divider)
Written at 1 to clear RSTPRIV by secure privileged software only. It can be read by any
software.
Bit 4 INTPRIVC: Privileged protection of INT configuration bits (enable, ready, divider)
Written at 1 to clear INTPRIV by secure privileged software only. It can be read by any
software.
Bit 3 PERPRIVC: Privileged protection of PER configuration bits (enable, ready, divider)
Written at 1 to clear PERPRIV by secure privileged software only. It can be read by any
software.
Bit 2 BUSPRIVC: Privileged protection of BUS configuration bits (enable, ready, divider)
Written at 1 to clear BUSPRIV by secure privileged software only. It can be read by any
software.
Bit 1 SYSPRIVC: Privileged protection of SYS configuration bits (enable, ready, divider)
Written at 1 to clear SYSPRIV by secure privileged software only. It can be read by any
software.
Bit 0 MODPRIVC: Privileged protection of MOD configuration bits (enable, ready, divider)
Written at 1 to clear MODPRIV by secure privileged software only. It can be read by any
software.

14.10.238 RCC system public configuration clear register 3

(RCC_PUBCFGCR3)
Address offset: 0x17BC
Reset value: 0x0000 0000
This register is used to control the public access rights to the configuration register of the
system. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPUB defines the
public protection for the configuration registers of the system: a write access is denied if the
access is non-public while the respective bit is set.

RM0486 Rev 2 745/4691

779
Reset and clock control (RCC) RM0486

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTPU INTPU PERPU BUSPU SYSPU MODP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
BC BC BC BC BC UBC
w w w w w w

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 RSTPUBC: Public protection of RST configuration bits (enable, ready, divider)
Written at 1 to clear RSTPUB by secure privileged software only. It can be read by any
software.
Bit 4 INTPUBC: Public protection of INT configuration bits (enable, ready, divider)
Written at 1 to clear INTPUB by secure privileged software only. It can be read by any
software.
Bit 3 PERPUBC: Public protection of PER configuration bits (enable, ready, divider)
Written at 1 to clear PERPUB by secure privileged software only. It can be read by any
software.
Bit 2 BUSPUBC: Public protection of BUS configuration bits (enable, ready, divider)
Written at 1 to clear BUSPUB by secure privileged software only. It can be read by any
software.
Bit 1 SYSPUBC: Public protection of SYS configuration bits (enable, ready, divider)
Written at 1 to clear SYSPUB by secure privileged software only. It can be read by any
software.
Bit 0 MODPUBC: Public protection of MOD configuration bits (enable, ready, divider)
Written at 1 to clear MODPUB by secure privileged software only. It can be read by any
software.

14.10.239 RCC privilege configuration clear register 4 (RCC_PRIVCFGCR4)

Address offset: 0x17C4
Reset value: 0x0000 0000
This register is used to control the privileged access rights to the configuration register of
the buses. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPRIV bit
defines the privileged protection for the configuration registers of each bus: a write access is
denied if the access is unprivileged while the respective bit here is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACLKN
NOCP APB5P APB4P APB3P APB2P APB1P AHB5P AHB4P AHB3P AHB2P AHB1P AHBM ACLKN
Res. Res. CPRIV
RIVC RIVC RIVC RIVC RIVC RIVC RIVC RIVC RIVC RIVC RIVC PRIVC PRIVC
C
w w w w w w w w w w w w w w

Bits 31:14 Reserved, must be kept at reset value.

746/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bit 13 NOCPRIVC: Privileged protection of NOC configuration bits (enable, ready, divider)
Written at 1 to clear NOCPRIV by secure privileged software only. It can be read by any
software.
Bit 12 APB5PRIVC: Privileged protection of APB5 configuration bits (enable, ready, divider)
Written at 1 to clear APB5PRIV by secure privileged software only. It can be read by any
software.
Bit 11 APB4PRIVC: Privileged protection of APB4 configuration bits (enable, ready, divider)
Written at 1 to clear APB4PRIV by secure privileged software only. It can be read by any
software.
Bit 10 APB3PRIVC: Privileged protection of APB3 configuration bits (enable, ready, divider)
Written at 1 to clear APB3PRIV by secure privileged software only. It can be read by any
software.
Bit 9 APB2PRIVC: Privileged protection of APB2 configuration bits (enable, ready, divider)
Written at 1 to clear APB2PRIV by secure privileged software only. It can be read by any
software.
Bit 8 APB1PRIVC: Privileged protection of APB1 configuration bits (enable, ready, divider)
Written at 1 to clear APB1PRIV by secure privileged software only. It can be read by any
software.
Bit 7 AHB5PRIVC: Privileged protection of AHB5 configuration bits (enable, ready, divider)
Written at 1 to clear AHB5PRIV by secure privileged software only. It can be read by any
software.
Bit 6 AHB4PRIVC: Privileged protection of AHB4 configuration bits (enable, ready, divider)
Written at 1 to clear AHB4PRIV by secure privileged software only. It can be read by any
software.
Bit 5 AHB3PRIVC: Privileged protection of AHB3 configuration bits (enable, ready, divider)
Written at 1 to clear AHB3PRIV by secure privileged software only. It can be read by any
software.
Bit 4 AHB2PRIVC: Privileged protection of AHB2 configuration bits (enable, ready, divider)
Written at 1 to clear AHB2PRIV by secure privileged software only. It can be read by any
software.
Bit 3 AHB1PRIVC: Privileged protection of AHB1 configuration bits (enable, ready, divider)
Written at 1 to clear AHB1PRIV by secure privileged software only. It can be read by any
software.
Bit 2 AHBMPRIVC: Privileged protection of AHBM configuration bits (enable, ready, divider)
Written at 1 to clear AHBMPRIV by secure privileged software only. It can be read by any
software.
Bit 1 ACLKNCPRIVC: Privileged protection of ACLKNC configuration bits (enable, ready, divider)
Written at 1 to clear ACLKNCPRIV by secure privileged software only. It can read by any
software.
Bit 0 ACLKNPRIVC: Privileged protection of ACLKN configuration bits (enable, ready, divider)
Written at 1 to clear ACLKNPRIV by secure privileged software only. It can read by any
software.

RM0486 Rev 2 747/4691

779
Reset and clock control (RCC) RM0486

14.10.240 RCC public configuration clear register 4 (RCC_PUBCFGCR4)

Address offset: 0x17CC
Reset value: 0x0000 0000
This register is used to control the public access rights to the configuration register of the
buses. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPUB bit defines
the public protection for the configuration registers of each bus: a write access is denied if
the access is non-public while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOCP APB5P APB4P APB3P APB2P APB1P AHB5P AHB4P AHB3P AHB2P AHB1P AHBM ACLKN ACLKN
Res. Res.
UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC PUBC CPUBC PUBC
w w w w w w w w w w w w w w

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 NOCPUBC: Public protection of NOC configuration bits (enable, ready, divider)
Written at 1 to clear NOCPUB by secure privileged software only. It can be read by any
software.
Bit 12 APB5PUBC: Public protection of APB5 configuration bits (enable, ready, divider)
Written at 1 to clear APB5PUB by secure privileged software only. It can be read by any
software.
Bit 11 APB4PUBC: Public protection of APB4 configuration bits (enable, ready, divider)
Written at 1 to clear APB4PUB by secure privileged software only. It can be read by any
software.
Bit 10 APB3PUBC: Public protection of APB3 configuration bits (enable, ready, divider)
Written at 1 to clear APB3PUB by secure privileged software only. It can be read by any
software.
Bit 9 APB2PUBC: Public protection of APB2 configuration bits (enable, ready, divider)
Written at 1 to clear APB2PUB by secure privileged software only. It can be read by any
software.
Bit 8 APB1PUBC: Public protection of APB1 configuration bits (enable, ready, divider)
Written at 1 to clear APB1PUB by secure privileged software only. It can be read by any
software.
Bit 7 AHB5PUBC: Public protection of AHB5 configuration bits (enable, ready, divider)
Written at 1 to clear AHB5PUB by secure privileged software only. It can be read by any
software.
Bit 6 AHB4PUBC: Public protection of AHB4 configuration bits (enable, ready, divider)
Written at 1 to clear AHB4PUB by secure privileged software only. It can be read by any
software.
Bit 5 AHB3PUBC: Public protection of AHB3 configuration bits (enable, ready, divider)
Written at 1 to clear AHB3PUB by secure privileged software only. It can be read by any
software.

748/4691 RM0486 Rev 2

RM0486 Reset and clock control (RCC)

Bit 4 AHB2PUBC: Public protection of AHB2 configuration bits (enable, ready, divider)
Written at 1 to clear AHB2PUB by secure privileged software only. It can be read by any
software.
Bit 3 AHB1PUBC: Public protection of AHB1 configuration bits (enable, ready, divider)
Written at 1 to clear AHB1PUB by secure privileged software only. It can be read by any
software.
Bit 2 AHBMPUBC: Public protection of AHBM configuration bits (enable, ready, divider)
Written at 1 to clear AHBMPUB by secure privileged software only. It can be read by any
software.
Bit 1 ACLKNCPUBC: Public protection of ACLKNC configuration bits (enable, ready, divider)
Written at 1 to clear ACLKNCPUB by secure privileged software only. It can be read by any
software.
Bit 0 ACLKNPUBC: Public protection of ACLKN configuration bits (enable, ready, divider)
Written at 1 to clear ACLKNPUB by secure privileged software only. It can be read by any
software.

14.10.241 RCC public configuration clear register 4 (RCC_PUBCFGCR5)

Address offset: 0x17D0
Reset value: 0x0000 0000
This register is used to control the public access rights to the configuration register of the
SRAMs. It is reset by sys_rstn, and is in the VCORE voltage domain. Each xxPUB bit defines
the public protection for the configuration registers of each SRAM: a write access is denied
if the access is non-public while the respective bit is set.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CACHE
VENCR FLEXR AXISR AXISR BKPSR AHBSR AHBSR AXISR AXISR AXISR AXISR
AXIRA
Res. Res. Res. Res. AMPU AMPU AM2PU AM1PU AMPU AM2PU AM1PU AM6PU AM5PU AM4PU AM3PU
MPUB
BC BC BC BC BC BC BC BC BC BC BC
C
w w w w w w w w w w w w

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 VENCRAMPUBC: Public protection of VENCRAM configuration bits (enable, ready, divider)
This bit is written to 1 to clear VENCRAMPUB by secure privileged software only. It can be
read by any software.
Bit 10 CACHEAXIRAMPUBC: Public protection of CACHEAXIRAM configuration bits
(enable, ready, divider)
This bit is written to 1 to clear CACHEEXIRAMPUB by secure privileged software only. It can
be read by any software.
Bit 9 FLEXRAMPUBC: Public protection of FLEXRAM configuration bits (enable, ready, divider)
This bit is written to 1 to clear FLEXRAMPUB by secure privileged software only. It can be
read by any software.

RM0486 Rev 2 749/4691

779
Reset and clock control (RCC) RM0486

Bit 8 AXISRAM2PUBC: Public protection of AXISRAM2 configuration bits (enable, ready, divider)
This bit is written to 1 to clear AXISRAM2PUB by secure privileged software only. It can be
read by any software.
Bit 7 AXISRAM1PUBC: Public protection of AXISRAM1 configuration bits (enable, ready, divider)
This bit is written to 1 to clear AXISRAM1PUB by secure privileged software only. It can be
read by any software.
Bit 6 BKPSRAMPUBC: Public protection of BKPSRAM configuration bits (enable, ready, divider)
This bit is written to 1 to clear BKPSRAMPUB by secure privileged software only. It can be
read by any software.
Bit 5 AHBSRAM2PUBC: Public protection of AHBSRAM2 configuration bits (enable, ready, divider)
This bit is written to 1 to clear AHBSRAM2PUB by secure privileged software only. It can be
read by any software.
Bit 4 AHBSRAM1PUBC: Public protection of AHBSRAM1 configuration bits (enable, ready, divider)
This bit is written to 1 to clear AHBSRAM1PUB by secure privileged software only. It can be
read by any software.
Bit 3 AXISRAM6PUBC: Public protection of AXISRAM6 configuration bits (enable, ready, divider)
This bit is written to 1 to clear AXISRAM6PUB by secure privileged software only. It can be
read by any software.
Bit 2 AXISRAM5PUBC: Public protection of AXISRAM5 configuration bits (enable, ready, divider)
Written at 1 to clear AXISRAM5PUB by secure privileged software only. It can be read by any
software.
Bit 1 AXISRAM4PUBC: Public protection of AXISRAM4 configuration bits (enable, ready, divider)
Written at 1 to clear AXISRAM4PUB by secure privileged software only. It can be read by any
software.
Bit 0 AXISRAM3PUBC: Public protection of AXISRAM3 configuration bits (enable, ready, divider)
Written at 1 to clear AXISRAM3PUB by secure privileged software only. It can be read by any
software.

750/4691 RM0486 Rev 2

 0x034
0x030
0x024
0x020
0x008
0x004
0x000

0x028

0x03C
0x02C
0x01C
Offset

0x038-
0x00C-
RM0486

RCC_SR
RCC_CR

Reserved

Reserved
Reserved

RCC_RSR

Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value

RCC_BDCR
RCC_CFGR2
RCC_CFGR1

RCC_HWRSR
RCC_STOPCR
Register name

0
Res. Res. VSWRST Res. Res. Res. Res. Res. 31

0
0
LPWRRSTF LPWRRSTF Res. Res. Res. Res. Res. Res. 30

0
Res. Res. Res. Res. SYSSWS Res. Res. Res. 29
[1:0]

0
0
0
WWDGRSTF WWDGRSTF Res. Res. Res. Res. Res. 28
14.10.242 RCC register map

Res. Res. Res. Res. Res. Res. Res. Res. 27

0
0
IWDGRSTF IWDGRSTF Res. Res. Res. Res. Res. Res. 26

0
0
Res. Res. Res. TIMPRE SYSSW Res. Res. Res. 25
[1:0] [1:0]

0
0
0
0
SFTRSTF SFTRSTF Res. Res. Res. Res. 24

1
1
PORRSTF PORRSTF Res. Res. Res. Res. Res. Res. 23

0
0
0
PINRSTF PINRSTF Res. Res. Res. Res. Res. 22

1
1
0
0
BORRSTF BORRSTF Res. CPUSWS Res. Res. Res. 21

[2:0]
HPRE
[1:0]

1
0
Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. 19

RM0486 Rev 2
Res. Res. Res. Res. Res. Res. Res. 18

0
0
0
0
LCKRSTF LCKRSTF Res. CPUSW Res. Res. Res. 17

[2:0]
PPRE5
[1:0]

0
0
0
0
RMVF RMVF Res. Res. Res. Res. 16
Res. Res. Res. Res. Res. Res. Res. Res. 15

Reserved
Reserved
Reserved

0
Res. Res. Res. Res. Res. Res. Res. 14

0
Res. Res. Res. Res. Res. Res. Res. 13

[2:0]
PPRE4

0
Res. Res. Res. Res. Res. Res. Res. 12
Table 78. RCC register map and reset values

0
0

Res. Res. Res. Res. Res. Res. PLL4RDY PLL4ON 11

0
0

Res. Res. Res. Res. Res. Res. PLL3RDY PLL3ON 10

0
0

Res. Res. Res. Res. Res. Res. PLL2RDY PLL2ON 9

0
0

Res. Res. Res. Res. Res. Res. PLL1RDY PLL1ON 8

Res. Res. Res. Res. Res. Res. Res. Res. 7
0

Res. Res. Res. Res. Res. Res. Res. 6

0

Res. Res. Res. Res. Res. Res. Res. 5

[2:0]
PPRE2

0
0
0

Res. Res. Res. Res. Res. HSERDY HSEON 4

0
1

Res. Res. Res. Res. Res. Res. HSIRDY HSION 3

0
0
0

Res. Res. Res. Res. Res. MSIRDY MSION 2

0
1
0
0

Res. Res. Res. Res. HSISTOPEN LSERDY LSEON 1

[2:0]
PPRE1

0
0
0
0

Res. Res. Res. STOPWUCK MSISTOPEN LSIRDY LSION 0

Reset and clock control (RCC)

751/4691
779
 0x090
0x088
0x084
0x080
0x054
0x050
0x048
0x044
0x040

0x08C
0x07C
0x04C
Offset

0x058-

752/4691
Reserved
Reserved

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

Reset value
RCC_HSIMSR
RCC_HSIMCR
Register name

RCC_HSICFGR
RCC_MSICFGR
RCC_LSECFGR

RCC_HSECFGR

RCC_PLL2CFGR1
RCC_PLL1CFGR3
RCC_PLL1CFGR2
RCC_PLL1CFGR1
0
0
Res. Res. Res. Res. Res. Res. HSIMONEN Res. Res. 31

0
1
0
0
0
PLL1PDIVEN Res. Res. Res. Res. Res. 30
PLL2SEL PLL1SEL

0
0
0
0
0
[2:0] Res. [2:0] Res. Res. Res. Res. 29
Reset and clock control (RCC)

PLL1PDIV1

0
0
0
0
0
[2:0] Res. Res. Res. Res. Res. 28

1
1
1
0
0
PLL2BYP Res. PLL1BYP Res. Res. Res. Res. 27

0
0
Res. Res. Res. Res. Res. Res. 0 Res. 26

HSICAL[8:0]
PLL1PDIV2

0
0
0
0
0
MSICAL[7:0]

[2:0] Res. Res. Res. Res. Res. 25

0
1
0
0
0

Res. Res. Res. Res. Res. 24

0
1
0
0
0

Res. Res. Res. Res. Res. 23

0
0

0
0
Res. Res. Res. Res. Res. Res. 22

0
0

0
1
0
Res. Res. Res. Res. Res. 21

PLL2DIVM[5:0]
PLL1DIVM[5:0]

0
0
0

0
0
1
0

Res. Res. Res. 20

0
0
0

0
0
1
0

0
0

HSEDRV Res. LSEDRV[1:0] 19

PLL1MODSPR [1:0]

0
0
0

0
0
0
1
0
0

RM0486 Rev 2
[4:0] Res. 18
HSITRIM[6:0]

0
0
0

0
0
0
1
0
0

HSIDEV[5:0]

HSEGFON Res. LSEGFON 17

MSITRIM[4:0]

0
0
0

0
0
0
1
0
0

HSEEXT Res. LSEEXT 16

0
0
0
0
0

Res. HSEBYP Res. Res. Res. Res. LSEBYP 15

Reserved
Reserved

0
0
0
0
Res. Res. Res. Res. Res. Res. 14

0
0
1
0
Res. HSECSSBPRE Res. Res. Res. Res. Res. 13
[3:0]

0
0
0
0
Res. Res. Res. Res. Res. Res. 12

PLL2DIVN[11:0]
PLL1DIVN[11:0]

0
0
0
0
1
Res. Res. Res. Res. Res. 11

0
0
0
1
0
1

PLL1MODDIV HSECSSBYP Res. Res. Res. 10

[3:0]

0
0
0
0
0
1
0

0
0

HSECSSD Res. MSIFREQSE LSECSSD 9

PLL1DIVNFRAC[23:0]
Table 78. RCC register map and reset values (continued)

0
0
0
1
0
1
0

0
0

HSECSSRA HSIDIV Res. LSECSSRA 8

[1:0]

0
0
1
0

0
0

Res. Res. Res. HSECSSON Res. LSECSSON 7

0
0
0

Res. Res. Res. HSEDIV2SEL Res. Res. Res. 6

0
1

Res. Res. Res. Res. Res. Res. Res. 5

0
0
0

Res. PLL1MODSPRDW Res. Res. Res. Res. Res. 4

HSIVAL[10:0]
HSIREF[10:0]

1
0
0

Res. PLL1MODDSEN Res. Res. Res. Res. Res. 3

1
0
0

Res. PLL1MODSSDIS Res. Res. Res. Res. Res. 2

0
0
0

Res. PLL1DACEN Res. Res. Res. Res. Res. 1

1
0
1

Res. PLL1MODSSRST Res. Res. Res. Res. Res. 0

RM0486
 0x098
0x094

0x0B8
0x0B4
0x0B0
0x0A8
0x0A4
0x0A0

0x0C4
0x0C0
0x09C
Offset

0x0AC

0x0BC-
RM0486

Reserved

Reserved
Reserved

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Register name

RCC_IC1CFGR
RCC_PLL4CFGR3
RCC_PLL4CFGR2
RCC_PLL4CFGR1
RCC_PLL3CFGR3
RCC_PLL3CFGR2
RCC_PLL3CFGR1
RCC_PLL2CFGR3
RCC_PLL2CFGR2

Res. Res. Res. Res. Res. Res. Res. Res. Res. 31

1
0
1
0
1
Res. PLL4PDIVEN Res. PLL3PDIVEN Res. PLL2PDIVEN Res. 30
PLL4SEL PLL3SEL

0
0
0
0
0
0
IC1SEL[1:0] Res. [2:0] Res. [2:0] Res. 29
PLL4PDIV1 PLL3PDIV1 PLL2PDIV1

0
0
0
0
0
0
[2:0] Res. [2:0] Res. [2:0] Res. 28

1
1
1
1
Res. Res. PLL4BYP Res. PLL3BYP 1 Res. 27

0
0
0
Res. Res. Res. Res. Res. Res. 26
PLL4PDIV2 PLL3PDIV2 PLL2PDIV2

0
0
0
0
0

Res. [2:0] Res. [2:0] Res. [2:0] Res. 25

1
0
1
0
1

Res. Res. Res. Res. 24

0
0
0
0
0
0

Res. Res. Res. 23

0
0
0
0
0
0

Res. Res. Res. 22

0
0
0
0
0
0

Res. Res. Res. 21

PLL4DIVM[5:0]
PLL3DIVM[5:0]

0
0
0
0
0
0
0
0
0

20

0
0
0
0
0
0
0
0
0

19
PLL4MODSPR PLL3MODSPR PLL2MODSPR

IC1INT[7:0]

0
0
0
0
0
0
0
0
0

RM0486 Rev 2
[4:0] [4:0] [4:0] 18

1
0
0
0
0
0
0
0
0

17

0
0
0
0
0
0
0
0
0

16

0
0
0
0
0

Res. Res. Res. Res. 15

Reserved
Reserved
Reserved

0
0
0
0
0

Res. Res. Res. Res. 14

0
0
0
0
0

Res. Res. Res. Res. 13

0
0
0
0
0

Res. Res. Res. Res. 12

PLL4DIVN[11:0]
PLL3DIVN[11:0]

0
0
0
0
0
0
0
0

Res. 11

0
0
0
0
0
0
0
0

Res. PLL4MODDIV PLL3MODDIV PLL2MODDIV 10

[3:0] [3:0] [3:0]

0
0
0
0
0
0
0
0

Res. 9

PLL4DIVNFRAC[23:0]
PLL3DIVNFRAC[23:0]
PLL2DIVNFRAC[23:0]
Table 78. RCC register map and reset values (continued)

0
0
0
0
0
0
0
0

Res. 8

0
0
0

Res. Res. Res. Res. Res. Res. 7

0
0
0

Res. Res. Res. Res. Res. Res. 6

0
0
0

Res. Res. Res. Res. Res. Res. 5

0
0
0
0
0
0

Res. PLL4MODSPRDW Res. PLL3MODSPRDW Res. PLL2MODSPRDW 4

0
0
0
0
0
0

Res. PLL4MODDSEN Res. PLL3MODDSEN Res. PLL2MODDSEN 3

1
0
1
0
1
0

Res. PLL4MODSSDIS Res. PLL3MODSSDIS Res. PLL2MODSSDIS 2

0
0
0
0
0
0

Res. PLL4DACEN Res. PLL3DACEN Res. PLL2DACEN 1

1
0
1
0
1
0

Res. PLL4MODSSRST Res. PLL3MODSSRST Res. PLL2MODSSRST 0

Reset and clock control (RCC)

753/4691
779
 0x0E8
0x0E4
0x0E0
0x0D8
0x0D4
0x0D0
0x0C8
Offset

0x0EC
0x0DC
0x0CC

754/4691
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Register name

RCC_IC9CFGR
RCC_IC8CFGR
RCC_IC7CFGR
RCC_IC6CFGR
RCC_IC5CFGR
RCC_IC4CFGR
RCC_IC3CFGR
RCC_IC2CFGR

RCC_IC11CFGR
RCC_IC10CFGR
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30

0
0
0
0
0
0
0
0
0
0

IC11SEL IC10SEL
Reset and clock control (RCC)

IC9SEL[1:0] IC8SEL[1:0] IC7SEL[1:0] IC6SEL[1:0] IC5SEL[1:0] IC4SEL[1:0] IC3SEL[1:0] IC2SEL[1:0] 29

[1:0] [1:0]

0
1
1
1
1
0
0
0
0
0

28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24

0
0
0
0
0
0
0
0
0
0

23

0
0
0
0
0
0
0
0
0
0

22

0
0
0
0
0
0
0
0
0
0

21

0
0
0
0
0
0
0
0
0
0

20

0
0
0
0
0
0
0
0
0
0

19

IC9INT[7:0]
IC8INT[7:0]
IC7INT[7:0]
IC6INT[7:0]
IC5INT[7:0]
IC4INT[7:0]
IC3INT[7:0]
IC2INT[7:0]

0
0
0
0
0
0
0
0
0
0

RM0486 Rev 2
IC11INT[7:0]
IC10INT[7:0]
18

1
0
0
0
0
1
0
0
0
1

17

1
0
0
0
0
1
0
0
0
1

16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 10
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 9
Table 78. RCC register map and reset values (continued)

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 8
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 7
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 6
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 5
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 4
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 3
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 2
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0
RM0486
 0x110

0x128
0x124
0x120
0x108
0x104
0x100
0x0F8
0x0F4
0x0F0

0x10C
Offset

0x0FC

0x114-
RM0486

Reserved

RCC_CIFR
RCC_CIER

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Register name

RCC_IC20CFGR
RCC_IC19CFGR
RCC_IC18CFGR
RCC_IC17CFGR
RCC_IC16CFGR
RCC_IC15CFGR
RCC_IC14CFGR
RCC_IC13CFGR
RCC_IC12CFGR

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30

1
1
1
1
1
1
1
1
1

Res. Res. IC20SEL IC19SEL IC18SEL IC17SEL IC16SEL IC15SEL IC14SEL IC13SEL IC12SEL 29
[1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0]

1
1
1
1
1
0
0
0
0

Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25

0
0
WKUPF WKUPIE Res. Res. Res. Res. Res. Res. Res. Res. Res. 24

0
0
0
0
0
0
0
0
0

Res. Res. 23

0
0
0
0
0
0
0
0
0

Res. Res. 22

0
0
0
0
0
0
0
0
0

Res. Res. 21

0
0
0
0
0
0
0
0
0

Res. Res. 20

0
0
0
0
0
0
0
0
0

Res. Res. 19

0
0
0
0
0
0
0
0
0

RM0486 Rev 2
IC20INT[7:0]
IC19INT[7:0]
IC18INT[7:0]
IC17INT[7:0]
IC16INT[7:0]
IC15INT[7:0]
IC14INT[7:0]
IC13INT[7:0]
IC12INT[7:0]

Res. Res. 18

0
1
0
0
0
0
0
0
0
0
0

HSECSSF HSECSSIE 17

0
0
0
0
0
0
0
0
0
0
0

LSECSSF LSECSSIE 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15

Reserved
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 12

0
0
PLL4RDYF PLL4RDYIE Res. Res. Res. Res. Res. Res. Res. Res. Res. 11

0
0
PLL3RDYF PLL3RDYIE Res. Res. Res. Res. Res. Res. Res. Res. Res. 10

0
0
PLL2RDYF PLL2RDYIE Res. Res. Res. Res. Res. Res. Res. Res. Res. 9
Table 78. RCC register map and reset values (continued)

0
0
PLL1RDYF PLL1RDYIE Res. Res. Res. Res. Res. Res. Res. Res. Res. 8
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 7
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 6
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 5

0
0
HSERDYF HSERDYIE Res. Res. Res. Res. Res. Res. Res. Res. Res. 4

0
0
HSIRDYF HSIRDYIE Res. Res. Res. Res. Res. Res. Res. Res. Res. 3

0
0
MSIRDYF MSIRDYIE Res. Res. Res. Res. Res. Res. Res. Res. Res. 2

0
0
LSERDYF LSERDYIE Res. Res. Res. Res. Res. Res. Res. Res. Res. 1

0
0
LSIRDYF LSIRDYIE Res. Res. Res. Res. Res. Res. Res. Res. Res. 0
Reset and clock control (RCC)

755/4691
779
 0x158
0x154
0x150
0x148
0x144
0x140

0x15C
0x14C
0x12C
Offset

0x130-

756/4691
Reserved
RCC_CICR

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

Reset value

RCC_CCIPR7
RCC_CCIPR6
RCC_CCIPR5
RCC_CCIPR4
RCC_CCIPR3
RCC_CCIPR2
RCC_CCIPR1
Register name

Res. Res. Res. Res. Res. Res. Res. Res. 31

Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. 29
Reset and clock control (RCC)

Res. Res. Res. Res. Res. Res. Res. Res. 28

Res. Res. Res. Res. Res. Res. Res. Res. 27

0
Res. Res. Res. Res. Res. Res. Res. 26
SAI2SEL

0
0
[2:0] Res. Res. LTDCSEL Res. Res. Res. Res. 25
[1:0]

0
0
0
0
0

OTGPHY2CKREFSEL Res. Res. ETH1GTXCLKSEL Res. WKUPFC 24

Res. Res. Res. Res. Res. Res. Res. Res. 23

0
0
Res. Res. Res. Res. Res. Res. 22
SAI1SEL I3C2SEL

0
0
0
0

[2:0] OTGPHY2SEL[1:0] Res. [2:0] Res. Res. DCMIPPSEL Res. 21

[1:0]

0
0
0
0
0

Res. Res. ETH1REFCLKSEL Res. 20

Res. Res. Res. Res. Res. Res. Res. Res. 19

0
0
0

RM0486 Rev 2
Res. Res. Res. Res. Res. 18
MDF1SEL I3C1SEL
ETH1SEL[2:0]

0
0
0
0
0

Res. [2:0] [2:0] Res. Res. HSECSSC 17

0
0
0
0
0
0

OTGPHY1CKREFSEL Res. Res. LSECSSC 16

0
1
0

Res. Res. Res. Res. Res. 15

Reserved

0
1
0
0

Res. MCO2PRE Res. Res. Res. 14

[3:0] I2C4SEL

0
0
1
0
0
0

Res. Res. 13

RTCPRE[5:0]
OTGPHY1SEL[1:0] [2:0] ETH1CLKSEL[1:0]

0
0
1
0
0
0

Res. Res. 12
0
0

Res. Res. Res. Res. Res. Res. PLL4RDYC 11

0
0
0
0

Res. Res. Res. Res. PLL3RDYC 10

ADCPRE[7:0]

MCO2SEL I2C3SEL

1
0
0
0
0
0

RTCSEL XSPI3SEL[1:0] [2:0] [2:0] Res. Res. PLL2RDYC 9

Table 78. RCC register map and reset values (continued)

[1:0]

0
0
0
0
0
0
0

Res. ETH1PWRDOWNACK PLL1RDYC 8

1
0

Res. Res. Res. Res. Res. Res. 7

1
0
0
0

Res. Res. MCO1PRE Res. Res. 6

I2C2SEL ETH1PTPDIV[3:0] ADC12SEL
[3:0]

0
0
1
0
0
0

PSSISE XSPI2SEL[1:0] [2:0] FMCSEL [2:0] Res. 5

L [1:0]

0
0
1
0
0
0
0

HSERDYC 4
0

Res. Res. Res. Res. Res. Res. Res. HSIRDYC 3

0
0
0
0
0

Res. Res. Res. MSIRDYC 2

PERSEL MCO1SEL I2C1SEL ADF1SEL

0
0

0
0
0
0
0

[2:0] XSPI1SEL[1:0] [2:0] [2:0] FDCANSEL ETH1PTPSEL[1:0] [2:0] LSERDYC 1

[1:0]

0
0
0
0
0
0
0

LSIRDYC 0
RM0486
 0x208
0x204
0x178
0x174
0x170
0x164
0x160

0x20C
0x16C
Offset

0x168-

0x17C-
RM0486

Reserved
Reserved

Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value

RCC_CCIPR9
RCC_CCIPR8
Register name

RCC_CCIPR14
RCC_CCIPR13
RCC_CCIPR12

RCC_MEMRSTR
RCC_MISCRSTR
Res. Res. Res. Res. Res. Res. Res. 31

0
Res. Res. Res. Res. Res. Res. 30
UART8SEL[2:0]

0
Res. Res. Res. Res. Res. Res. 29

0
Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. 27

0
0
0
Res. Res. Res. Res. 26
UART7SEL[2:0] LPTIM5SEL[2:0] SPI6SEL[2:0]

0
0
0
Res. Res. Res. Res. 25

0
0
0
Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. 23

0
0
0

Res. Res. Res. Res. 22

USART6SEL[2:0] LPTIM4SEL[2:0] SPI5SEL[2:0]

0
0
0

Res. Res. Res. Res. 21

0
0
0

Res. Res. Res. Res. 20

Res. Res. Res. Res. Res. Res. Res. 19

0
0
0

RM0486 Rev 2
Res. Res. Res. Res. 18
UART5SEL[2:0] LPTIM3SEL[2:0] SPI4SEL[2:0]

0
0
0

Res. Res. Res. Res. 17

0
0
0

Res. Res. Res. Res. 16

Res. Res. Res. Res. Res. Res. Res. 15

Reserved
Reserved

0
0
0

Res. Res. Res. Res. 14

UART4SEL[2:0] LPTIM2SEL[2:0] SPI3SEL[2:0]

0
0
0

Res. Res. Res. Res. 13

0
0
0

0
BOOTROMRST Res. Res. Res. 12

0
VENCRAMRST Res. Res. Res. Res. Res. Res. 11

0
0
0

0
0
CACHEAXIRAMRST Res. Res. 10
LPUART1SEL[2:0] USART3SEL[2:0] LPTIM1SEL[2:0] SPI2SEL[2:0]
0
0
0

0
0
FLEXRAMRST Res. Res. 9
Table 78. RCC register map and reset values (continued)

0
0
0

0
0
0
AXISRAM2RST SDMMC2DLLRS Res. 8

0
0
AXISRAM1RST SDMMC1DLLRS Res. Res. Res. Res. Res. 7
0
0

0
Res. Res. Res. Res. 6
USART10SEL[2:0] USART2SEL[2:0] SPI1SEL[2:0]
0
0

0
0
0
0

AHBSRAM2RST XSPIPHY2RST Res. SDMMC2SEL 5

[1:0]
0
0

0
0
0
0

AHBSRAM1RST XSPIPHY1RST Res. 4

0
AXISRAM6RST Res. Res. Res. Res. Res. Res. 3
0
0

0
0
AXISRAM5RST Res. Res. Res. 2
UART9SEL[2:0] USART1SEL[2:0] SPDIFRX1SEL[2:0]
0
0

0
0
0

AXISRAM4RST Res. Res. SDMMC1SEL 1

[1:0]
0
0

0
0
0
0

AXISRAM3RST DBGRST Res. 0

Reset and clock control (RCC)

757/4691
779
 0x228
0x224
0x220
0x218
0x214
0x210

0x230
0x22C
0x21C
Offset

758/4691
Reserved
Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Register name

RCC_APB2RSTR
RCC_AHB5RSTR
RCC_AHB4RSTR
RCC_AHB3RSTR
RCC_AHB2RSTR
RCC_AHB1RSTR

RCC_APB1LRSTR

RCC_APB1HRSTR
0
0
Res. Res. UART8RST NPURST Res. Res. Res. Res. 31

0
0
Res. Res. UART7RST CACHEAXIRST Res. Res. Res. Res. 30

0
Res. Res. Res. OTG2RST Res. Res. Res. Res. 29
Reset and clock control (RCC)

0
Res. Res. Res. OTGPHY2RST Res. Res. Res. Res. 28

0
Res. Res. Res. OTGPHY1RST Res. Res. Res. Res. 27

0
Res. Res. Res. OTG1RST Res. Res. Res. Res. 26

0
0
Res. Res. I3C2RST ETH1RST Res. Res. Res. Res. 25

0
0
Res. Res. I3C1RST OTG2PHYCTLRST Res. Res. Res. Res. 24

0
0
Res. Res. I2C3RST OTG1PHYCTLRST Res. Res. Res. Res. 23

0
0
SAI2RST Res. I2C2RST Res. Res. Res. Res. Res. 22

0
0
SAI1RST Res. I2C1RST Res. Res. Res. Res. Res. 21

0
0
0
SPI5RST Res. UART5RST GPU2DRST Res. Res. Res. Res. 20

0
0
0
0
TIM9RST Res. UART4RST GFXMMURST CRCRST Res. Res. Res. 19

0
0
0

RM0486 Rev 2
TIM17RST UCPD1RST USART3RST Res. PWRRST Res. Res. Res. 18

0
0
0
0

TIM16RST Res. USART2RST XSPI3RST Res. Res. ADF1RST Res. 17

0
0
0
0

TIM15RST Res. SPDIFRX1RST Res. GPIOQRST Res. MDF1RST Res. 16

0
0
0
TIM18RST Res. SPI3RST Res. GPIOPRST Res. Res. Res. 15

Reserved
0
0

Res. Res. SPI2RST Res. GPIOORST Res. Res. Res. 14

0
0
0
0

SPI4RST Res. TIM11RST XSPIMRST GPIONRST Res. Res. Res. 13

0
0
0
0

SPI1RST Res. TIM10RST XSPI2RST Res. Res. RAMCFGRST Res. 12

0
Res. Res. WWDGRST Res. Res. Res. Res. Res. 11
0

Res. Res. Res. Res. Res. IACRST Res. Res. 10

0
Res. Res. LPTIM1RST Res. Res. Res. Res. Res. 9
Table 78. RCC register map and reset values (continued)

0
0

0
0

Res. FDCANRS TIM14RST SDMMC1RST Res. PKARST Res. Res. 8

0
0
0

USART10RST Res. TIM13RST SDMMC2RST GPIOHRST Res. Res. Res. 7

0
0
0

UART9RST Res. TIM12RST PSSIRST GPIOGRST Res. Res. Res. 6

0
0
0

0
0

USART6RST MDIOSRST TIM7RST XSPI1RST GPIOFRST Res. Res. ADC12RST 5

0
0
0
0
0

USART1RST Res. TIM6RST FMCRST GPIOERST SAESRST Res. GPDMA1RST 4

0
0
0

Res. Res. TIM5RST JPEGRST GPIODRST Res. Res. Res. 3

0
0
0

Res. Res. TIM4RST Res. GPIOCRST CRYPRST Res. Res. 2

0

0
0
0
0

TIM8RST Res. TIM3RST DMA2DRST GPIOBRST HASHRST Res. Res. 1

0

0
0
0
0

TIM1RST Res. TIM2RST HPDMA1RST GPIOARST RNGRST Res. Res. 0

RM0486
 0x254
0x250
0x248
0x244
0x240
0x238
0x234

0x24C
0x23C
Offset
RM0486

Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

RCC_DIVENR

RCC_BUSENR
Register name

RCC_MEMENR
RCC_MISCENR

RCC_AHB2ENR
RCC_AHB1ENR
RCC_APB5RSTR
RCC_APB4LRSTR

RCC_APB4HRSTR
Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. 20

0
Res. Res. Res. Res. Res. IC20EN Res. Res. Res. 19

RM0486 Rev 2
Res. Res. Res. Res. Res. IC19EN Res. Res. Res. 18

0
ADF1EN Res. Res. Res. Res. IC18EN Res. Res. Res. 17
0
0

0
MDF1EN Res. Res. Res. Res. 0 IC17EN Res. Res. RTCRST 16
0

Res. Res. Res. Res. Res. IC16EN Res. Res. VREFBUFRST 15

0

Res. Res. Res. Res. Res. IC15EN Res. Res. Res. 14

0

Res. Res. Res. Res. Res. IC14EN Res. Res. Res. 13

0

1
1
0

RAMCFGEN Res. BOOTROMEN Res. Res. IC13EN Res. Res. LPTIM5RST 12

0

0
0

Res. Res. VENCRAMEN Res. Res. IC12EN Res. Res. LPTIM4RST 11

0

0
0

Res. Res. CACHEAXIRAMEN Res. Res. IC11EN Res. Res. LPTIM3RST 10

0

1
0

Res. Res. FLEXRAMEN Res. Res. IC10EN Res. Res. LPTIM2RST 9

Table 78. RCC register map and reset values (continued)

1
Res. Res. AXISRAM2EN Res. Res. IC9EN Res. Res. Res. 8
0

1
0

Res. Res. AXISRAM1EN Res. Res. IC8EN Res. Res. I2C4RST 7

0

1
0
0

Res. Res. BKPSRAMEN PEREN Res. IC7EN CSIRST Res. Res. 6

0
0

0
1
0

Res. ADC12EN AHBSRAM2EN Res. Res. IC6EN VENCRST Res. SPI6RST 5

0

0
1
0

Res. GPDMA1EN AHBSRAM1EN Res. Res. IC5EN GFXTIMRST Res. Res. 4

0

0
0

Res. Res. AXISRAM6EN 0 XSPIPHYCOMPEN Res. IC4EN Res. Res. LPUART1RST 3

0

0
0

0
0
0

Res. Res. AXISRAM5EN MCO2EN Res. IC3EN DCMIPPRST DTSRST HDPRST 2

0

0
0
1
0

Res. Res. AXISRAM4EN MCO1EN ACLKNCEN IC2EN LTDCRST Res. Res. 1

0

0
0
1
0

Res. Res. AXISRAM3EN DBGEN ACLKNEN IC1EN Res. SYSCFGRST Res. 0

Reset and clock control (RCC)

759/4691
779
 0x278
0x274
0x270
0x268
0x264
0x260
0x258

0x280
0x27C
0x26C
0x25C
Offset

760/4691
Reserved
Reset value
Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Register name

RCC_APB5ENR
RCC_APB3ENR
RCC_APB2ENR
RCC_AHB5ENR
RCC_AHB4ENR
RCC_AHB3ENR

RCC_APB4LENR
RCC_APB1LENR

RCC_APB4HENR
RCC_APB1HENR
0
0
Res. Res. Res. Res. Res. Res. UART8EN NPUEN Res. Res. 31

0
0
Res. Res. Res. Res. Res. Res. UART7EN CACHEAXIEN Res. Res. 30

0
Res. Res. Res. Res. Res. Res. Res. OTG2EN Res. Res. 29
Reset and clock control (RCC)

0
Res. Res. Res. Res. Res. Res. Res. OTGPHY2EN Res. Res. 28

0
Res. Res. Res. Res. Res. Res. Res. OTGPHY1EN Res. Res. 27

0
Res. Res. Res. Res. Res. Res. Res. OTG1EN Res. Res. 26

0
0
Res. Res. Res. Res. Res. Res. I3C2EN ETH1EN Res. Res. 25

0
0
Res. Res. Res. Res. Res. Res. I3C1EN ETH1RXEN Res. Res. 24

0
0
Res. Res. Res. Res. Res. Res. I2C3EN ETH1TXEN Res. Res. 23

0
0

0
Res. Res. Res. Res. SAI2EN Res. I2C2EN ETH1MACEN Res. Res. 22

0
0
Res. Res. Res. Res. SAI1EN Res. I2C1EN Res. Res. Res. 21

0
0
0

Res. Res. Res. Res. SPI5EN Res. UART5EN GPU2DEN Res. Res. 20

0
0
0
0

Res. Res. Res. Res. TIM9EN Res. UART4EN GFXMMUEN CRCEN Res. 19

0
0
0
1

RM0486 Rev 2
Res. Res. Res. Res. TIM17EN UCPD1EN USART3EN MCE4EN PWREN Res. 18

0
0

0
0
Res. Res. RTCAPBEN Res. TIM16EN Res. USART2EN XSPI3EN Res. Res. 17
0
0

0
0
0

Res. Res. RTCEN Res. TIM15EN Res. 0 SPDIFRX1EN MCE3EN GPIOQEN Res. 16
0

0
0
0

Res. Res. VREFBUFEN Res. TIM18EN Res. SPI3EN MCE2EN GPIOPEN Res. 15

Reserved
0
0
0
1

Res. Res. Res. Res. Res. Res. SPI2EN MCE1EN GPIOOEN RISAFEN 14

0
0
0
0

Res. Res. Res. Res. SPI4EN Res. TIM11EN XSPIMEN GPIONEN Res. 13
0
0

0
0
Res. Res. LPTIM5EN Res. SPI1EN Res. TIM10EN XSPI2EN Res. Res. 12
0

0
Res. Res. LPTIM4EN Res. Res. Res. WWDGEN Res. Res. Res. 11

0
1

Res. Res. LPTIM3EN Res. Res. Res. Res. Res. Res. IACEN 10
0

0
1

Res. Res. LPTIM2EN Res. Res. Res. LPTIM1EN Res. Res. RIFSCEN 9
Table 78. RCC register map and reset values (continued)

0
0

0
0

Res. Res. Res. Res. Res. FDCANEN TIM14EN SDMMC1EN Res. PKAEN 8
0
0

0
0
0

Res. Res. I2C4EN Res. USART10EN Res. TIM13EN SDMMC2EN GPIOHEN Res. 7
0
0

0
0

0
CSIEN Res. Res. Res. UART9EN Res. TIM12EN PSSIEN GPIOGEN Res. 6
0
0

0
0
0

0
0

VENCEN Res. SPI6EN Res. USART6EN MDIOSEN TIM7EN XSPI1EN GPIOFEN Res. 5
0
0

0
0

0
0

GFXTIMEN Res. Res. Res. USART1EN Res. TIM6EN FMCEN GPIOEEN SAESEN 4
0
0

0
0

Res. Res. LPUART1EN Res. Res. Res. TIM5EN JPEGEN GPIODEN Res. 3
0

0
0

0
0
0
0

DCMIPPEN DTSEN HDPEN DFTEN Res. Res. TIM4EN Res. GPIOCEN CRYPEN 2
0
0

0
0

0
1
0

LTDCEN BSECEN Res. Res. TIM8EN Res. TIM3EN DMA2DEN GPIOBEN HASHEN 1
0
0

0
0

0
0

Res. SYSCFGEN Res. Res. TIM1EN Res. TIM2EN HPDMA1EN GPIOAEN RNGEN 0
RM0486
 0x298
0x294
0x290
0x288
0x284

0x2A0
0x29C
0x28C
Offset
RM0486

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Register name

RCC_BUSLPENR

RCC_MEMLPENR
RCC_MISCLPENR

RCC_AHB5LPENR
RCC_AHB4LPENR
RCC_AHB3LPENR
RCC_AHB2LPENR
RCC_AHB1LPENR

0
NPULPEN Res. Res. Res. Res. Res. Res. Res. 31

0
CACHEAXILPEN Res. Res. Res. Res. Res. Res. Res. 30

0
OTG2LPEN Res. Res. Res. Res. Res. Res. Res. 29

0
OTGPHY2LPEN Res. Res. Res. Res. Res. Res. Res. 28

0
OTGPHY1LPEN Res. Res. Res. Res. Res. Res. Res. 27

0
OTG1LPEN Res. Res. Res. Res. Res. Res. Res. 26

0
ETH1LPEN Res. Res. Res. Res. Res. Res. Res. 25

0
ETH1RXLPEN Res. Res. Res. Res. Res. Res. Res. 24

0
ETH1TXLPEN Res. Res. Res. Res. Res. Res. Res. 23

0
ETH1MACLPEN Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. 21

0
GPU2DLPEN Res. Res. Res. Res. Res. Res. Res. 20

0
0
GFXMMULPEN CRCLPEN Res. Res. Res. Res. Res. Res. 19

0
1

RM0486 Rev 2
MCE4LPEN PWRLPEN Res. Res. Res. Res. Res. Res. 18

0
0
XSPI3LPEN Res. Res. ADF1LPEN Res. Res. Res. Res. 17

0
0
0
MCE3LPEN GPIOQLPEN Res. MDF1LPEN Res. Res. Res. Res. 16

0
0
MCE2LPEN GPIOPLPEN Res. Res. Res. Res. Res. Res. 15

0
0
0
MCE1LPEN GPIOOLPEN RISAFLPEN Res. Res. Res. Res. Res. 14

0
0
XSPIMLPEN GPIONLPEN Res. Res. Res. Res. Res. Res. 13

0
0
0

XSPI2LPEN Res. Res. RAMCFGLPEN Res. BOOTROMLPEN Res. Res. 12

0

Res. Res. Res. Res. Res. VENCRAMLPEN Res. Res. 11

0

1
Res. Res. IACLPEN Res. Res. CACHEAXIRAMLPEN Res. Res. 10
0

0
Res. Res. RIFSCLPEN Res. Res. FLEXRAMLPEN Res. Res. 9
Table 78. RCC register map and reset values (continued)

0
0

0
SDMMC1LPEN Res. PKALPEN Res. Res. AXISRAM2LPEN Res. Res. 8

0
0
0

SDMMC2LPEN GPIOHLPEN Res. Res. Res. AXISRAM1LPEN Res. Res. 7

0
0
0
0

PSSILPEN GPIOGLPEN Res. Res. Res. BKPSRAMLPEN PERLPEN Res. 6

0
0
0
0

XSPI1LPEN GPIOFLPEN Res. Res. ADC12LPEN AHBSRAM2LPEN Res. Res. 5

0
0
0
0

0
FMCLPEN GPIOELPEN SAESLPEN Res. GPDMA1LPEN AHBSRAM1LPEN Res. Res. 4

0
0
0
0

JPEGLPEN GPIODLPEN Res. Res. Res. AXISRAM6LPEN XSPIPHYCOMPLPEN Res. 3

0
0

0
Res. GPIOCLPEN CRYPLPEN Res. Res. AXISRAM5LPEN Res. Res. 2

0
0
0

0
1

DMA2DLPEN GPIOBLPEN HASHLPEN Res. Res. AXISRAM4LPEN Res. ACLKNCLPEN 1

0
0
0

0
0
1

HPDMA1LPEN GPIOALPEN RNGLPEN Res. Res. AXISRAM3LPEN DBGLPEN ACLKNLPEN 0

Reset and clock control (RCC)

761/4691
779
 0x780
0x448
0x2B8
0x2B4
0x2B0
0x2A8
0x2A4

0x77C
0x44C
Offset

0x2BC
0x2AC

0x450-
0x2C0-

762/4691
Reserved
Reserved

Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value

RCC_RDCR
Register name

RCC_SECCFGR0
RCC_APB5LPENR
RCC_APB3LPENR
RCC_APB2LPENR

RCC_APB4LLPENR
RCC_APB1LLPENR

RCC_APB4HLPENR
RCC_APB1HLPENR
Res. Res. Res. Res. Res. Res. Res. Res. 0
0 UART8LPEN 31
Res. Res. Res. Res. Res. Res. Res. Res. UART7LPEN 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Reset and clock control (RCC)

Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

0
Res. Res. Res. Res. Res. Res. Res. Res. 27

0
Res. Res. Res. Res. Res. Res. Res. Res. 26

0
0

Res. Res. Res. Res. Res. Res. Res. I3C2LPEN 25

EADLY[3:0]

0
0

Res. Res. Res. Res. Res. Res. Res. I3C1LPEN 24

0

Res. Res. Res. Res. Res. Res. Res. Res. I2C3LPEN 23

0
0

Res. Res. Res. Res. Res. Res. SAI2LPEN Res. I2C2LPEN 22

0
0

Res. Res. Res. Res. Res. Res. SAI1LPEN Res. I2C1LPEN 21

0
0
0

Res. Res. Res. Res. Res. SPI5LPEN Res. UART5LPEN 20

0
0
0

Res. Res. Res. Res. Res. TIM9LPEN Res. UART4LPEN 19

0
0
0

RM0486 Rev 2
Res. Res. Res. Res. Res. TIM17LPEN UCPD1LPEN USART3LPEN 18

0
0

0
0

Res. Res. Res. RTCAPBLPEN Res. TIM16LPEN Res. USART2LPEN 17

MRD[4:0]

0
0

0
0

Res. Res. Res. RTCLPEN Res. TIM15LPEN Res. SPDIFRX1LPEN 16

0

0
0

Res. Res. Res. Res. VREFBUFLPEN Res. TIM18LPEN Res. SPI3LPEN 15

Reserved
Reserved
0

Res. Res. Res. Res. Res. Res. Res. Res. SPI2LPEN 14

0
0

Res. Res. Res. Res. Res. Res. SPI4LPEN Res. TIM11LPEN 13

0
0
0

Res. Res. Res. Res. LPTIM5LPEN Res. SPI1LPEN Res. TIM10LPEN 12

0

0
Res. Res. Res. Res. LPTIM4LPEN Res. Res. Res. WWDGLPEN 11

0
Res. Res. Res. Res. LPTIM3LPEN Res. Res. Res. Res. 10
0

0
Res. Res. Res. Res. LPTIM2LPEN Res. Res. Res. LPTIM1LPEN 9
Table 78. RCC register map and reset values (continued)

Res. Res. Res. Res. Res. Res. Res. FDCANLPEN TIM14LPEN 8

0

0
0

Res. Res. Res. Res. I2C4LPEN Res. USART10LPEN Res. TIM13LPEN 7

0

0
Res. Res. CSILPEN Res. Res. Res. UART9LPEN Res. TIM12LPEN 6
0

0
0

0
0

Res. Res. VENCLPEN Res. SPI6LPEN Res. USART6LPEN MDIOSLPEN TIM7LPEN 5

0

0
0
HSESEC Res. GFXTIMLPEN Res. Res. Res. USART1LPEN Res. TIM6LPEN 4
0

0
HSISEC Res. Res. Res. LPUART1LPEN Res. Res. Res. TIM5LPEN 3
0

0
0
0
0

MSISEC Res. DCMIPPLPEN DTSLPEN HDPLPEN DFTLPEN Res. Res. TIM4LPEN 2

0

0
0
LSESEC Res. LTDCLPEN 1 BSECLPEN Res. Res. TIM8LPEN Res. TIM3LPEN 1
0

0
0
LSISEC Res. Res. SYSCFGLPEN Res. Res. TIM1LPEN Res. TIM2LPEN 0
RM0486
 0x798
0x794
0x790
0x788
0x784

0x7A8
0x7A4
0x7A0
0x79C
0x78C
Offset

0x7AC
RM0486

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Register name

RCC_PUBCFGR2
RCC_PUBCFGR1
RCC_PUBCFGR0

RCC_SECCFGR2
RCC_SECCFGR1

RCC_PRIVCFGR2
RCC_PRIVCFGR1
RCC_PRIVCFGR0

RCC_LOCKCFGR2
RCC_LOCKCFGR1
RCC_LOCKCFGR0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20

0
0
0
0
IC20PUB IC20LOCK IC20PRIV IC20SEC Res. Res. Res. Res. Res. Res. Res. 19

0
0
0
0

RM0486 Rev 2
IC19PUB IC19LOCK IC19PRIV IC19SEC Res. Res. Res. Res. Res. Res. Res. 18

0
0
0
0
IC18PUB IC18LOCK IC18PRIV IC18SEC Res. Res. Res. Res. Res. Res. Res. 17

0
0
0
0
IC17PUB IC17LOCK IC17PRIV IC17SEC Res. Res. Res. Res. Res. Res. Res. 16

0
0
0
0
IC16PUB IC16LOCK IC16PRIV IC16SEC Res. Res. Res. Res. Res. Res. Res. 15

0
0
0
0
IC15PUB IC15LOCK IC15PRIV IC15SEC Res. Res. Res. Res. Res. Res. Res. 14

0
0
0
0
IC14PUB IC14LOCK IC14PRIV IC14SEC Res. Res. Res. Res. Res. Res. Res. 13

0
0
0
0
IC13PUB IC13LOCK IC13PRIV IC13SEC Res. Res. Res. Res. Res. Res. Res. 12

0
0
0
0
IC12PUB IC12LOCK IC12PRIV IC12SEC Res. Res. Res. Res. Res. Res. Res. 11

0
0
0
0
IC11PUB IC11LOCK IC11PRIV IC11SEC Res. Res. Res. Res. Res. Res. Res. 10

0
0
0
0
IC10PUB IC10LOCK IC10PRIV IC10SEC Res. Res. Res. Res. Res. Res. Res. 9
Table 78. RCC register map and reset values (continued)

0
0
0
0
IC9PUB IC9LOCK IC9PRIV IC9SEC Res. Res. Res. Res. Res. Res. Res. 8

0
0
0
0
IC8PUB IC8LOCK IC8PRIV IC8SEC Res. Res. Res. Res. Res. Res. Res. 7

0
0
0
0
IC7PUB IC7LOCK IC7PRIV IC7SEC Res. Res. Res. Res. Res. Res. Res. 6

0
0
0
0
IC6PUB IC6LOCK IC6PRIV IC6SEC Res. Res. Res. Res. Res. Res. Res. 5

0
0
0
0
0
0
0

IC5PUB IC5LOCK IC5PRIV IC5SEC Res. Res. Res. Res. HSEPUB HSELOCK HSEPRIV 4

0
0
0
0
0
0
0
0
0
0
0

IC4PUB IC4LOCK IC4PRIV IC4SEC PLL4PUB PLL4LOCK PLL4PRIV PLL4SEC HSIPUB HSILOCK HSIPRIV 3

0
0
0
0
0
0
0
0
0
0
0

IC3PUB IC3LOCK IC3PRIV IC3SEC PLL3PUB PLL3LOCK PLL3PRIV PLL3SEC MSIPUB MSILOCK MSIPRIV 2

0
0
0
0
0
0
0
0
0
0
0

IC2PUB IC2LOCK IC2PRIV IC2SEC PLL2PUB PLL2LOCK PLL2PRIV PLL2SEC LSEPUB LSELOCK LSEPRIV 1

0
0
0
0
0
0
0
0
0
0
0

IC1PUB IC1LOCK IC1PRIV IC1SEC PLL1PUB PLL1LOCK PLL1PRIV PLL1SEC LSIPUB LSILOCK LSIPRIV 0
Reset and clock control (RCC)

763/4691
779
 0x7B8
0x7B4
0x7B0

0x7D0
0x7C8
0x7C4
0x7C0
Offset

0x7FC
0x7BC

0x7CC

0x7D4-

764/4691
Reserved
Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Register name

RCC_PUBCFGR5
RCC_PUBCFGR4
RCC_PUBCFGR3

RCC_SECCFGR4
RCC_SECCFGR3

RCC_PRIVCFGR4
RCC_PRIVCFGR3

RCC_LOCKCFGR4
RCC_LOCKCFGR3
Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Reset and clock control (RCC)

Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. 19

RM0486 Rev 2
Res. Res. Res. Res. Res. Res. Res. Res. Res. 18
Res. Res. Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. Res. Res. 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. 15

Reserved
Res. Res. Res. Res. Res. Res. Res. Res. Res. 14

0
0
0
0
Res. NOCPUB NOCLOCK NOCPRIV NOCSEC Res. Res. Res. Res. 13

0
0
0
Res. APB5PUB APB5LOCK APB5PRIV 0 APB5SEC Res. Res. Res. Res. 12

0
0
0
0
0

VENCRAMPUB APB4PUB APB4LOCK APB4PRIV APB4SEC Res. Res. Res. Res. 11

0
0
0
0
0

CACHEAXIRAMPUB APB3PUB APB3LOCK APB3PRIV APB3SEC Res. Res. Res. Res. 10

0
0
0
0
0

FLEXRAMPUB APB2PUB APB2LOCK APB2PRIV APB2SEC Res. Res. Res. Res. 9

Table 78. RCC register map and reset values (continued)

0
0
0
0
0

AXISRAM2PUB APB1PUB APB1LOCK APB1PRIV APB1SEC Res. Res. Res. Res. 8

0
0
0
0
0

AXISRAM1PUB AHB5PUB AHB5LOCK AHB5PRIV AHB5SEC Res. Res. Res. Res. 7

0
0
0
0
0

BKPSRAMPUB AHB4PUB AHB4LOCK AHB4PRIV AHB4SEC Res. Res. Res. Res. 6

0
0
0
0
0
0
0
0
0

AHBSRAM2PUB AHB3PUB AHB3LOCK AHB3PRIV AHB3SEC RSTPUB RSTLOCK RSTPRIV RSTSEC 5

0
0
0
0
0
0
0
0
0

AHBSRAM1PUB AHB2PUB AHB2LOCK AHB2PRIV AHB2SEC INTPUB INTLOCK INTPRIV INTSEC 4

0
0
0
0
0
0
0
0
0

AXISRAM6PUB AHB1PUB AHB1LOCK AHB1PRIV AHB1SEC PERPUB PERLOCK PERPRIV PERSEC 3

0
0
0
0
0
0
0
0
0

AXISRAM5PUB AHBMPUB AHBMLOCK AHBMPRIV AHBMSEC BUSPUB BUSLOCK BUSPRIV BUSSEC 2

0
0
0
0
0
0
0
0
0

AXISRAM4PUB ACLKNCPUB ACLKNCLOCK ACLKNCPRIV ACLKNCSEC SYSPUB SYSLOCK SYSPRIV SYSSEC 1

0
0
0
0
0
0
0
0
0

AXISRAM3PUB ACLKNPUB ACLKNLOCK ACLKNPRIV ACLKNSEC MODPUB MODLOCK MODPRIV MODSEC 0

RM0486
 0x808
0x800

0x804

0xA18
0xA14
0xA10
0xA08
0xA04
Offset

0xA1C
0xA0C
0x80C-
RM0486

Reserved

Reserved
RCC_CSR

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Register name

RCC_STOPCSR

RCC_MEMRSTSR
RCC_MISCRSTSR

RCC_AHB4RSTSR
RCC_AHB3RSTSR
RCC_AHB2RSTSR
RCC_AHB1RSTSR
Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. 20

0
CRCRSTS Res. Res. Res. Res. Res. Res. Res. 19

RM0486 Rev 2
PWRRSTS Res. Res. Res. Res. Res. Res. Res. 18

0
Res. Res. ADF1RSTS Res. Res. Res. Res. Res. 17

0
0
GPIOQRSTS Res. MDF1RSTS Res. Res. Res. Res. Res. 16

0
GPIOPRSTS Res. Res. Res. Res. Res. Res. Res. 15
Reserved
Reserved

0
GPIOORSTS Res. Res. Res. Res. Res. Res. Res. 14

0
GPIONRSTS Res. Res. Res. Res. Res. Res. Res. 13

0
0
Res. Res. RAMCFGRSTS Res. BOOTROMRSTS Res. Res. Res. 12

0
0

Res. Res. Res. Res. VENCRAMRSTS Res. Res. PLL4ONS 11

0
0
0

Res. IACRSTS Res. Res. CACHEAXIRAMRSTS Res. Res. PLL3ONS 10

0
0

Res. Res. Res. Res. FLEXRAMRSTS Res. Res. PLL2ONS 9

Table 78. RCC register map and reset values (continued)

0
0
0
0

Res. PKARSTS Res. Res. AXISRAM2RSTS SDMMC2DLLRSTS Res. PLL1ONS 8

0
0
0

GPIOHRSTS Res. Res. Res. AXISRAM1RSTS SDMMC1DLLRSTS Res. Res. 7

0
GPIOGRSTS Res. Res. Res. Res. Res. Res. Res. 6

0
0
0
0

GPIOFRSTS Res. Res. ADC12RSTS AHBSRAM2RSTS XSPIPHY2RSTS Res. Res. 5

0
0
0
0
0
0

GPIOERSTS SAESRSTS Res. GPDMA1RSTS AHBSRAM1RSTS XSPIPHY1RSTS Res. HSEONS 4

0
0
0

GPIODRSTS Res. Res. Res. AXISRAM6RSTS Res. Res. HSIONS 3

0
0
0
0

GPIOCRSTS CRYPRSTS Res. Res. AXISRAM5RSTS Res. Res. MSIONS 2

0
0
0
0
0

GPIOBRSTS HASHRSTS Res. Res. AXISRAM4RSTS Res. HSISTOPENS LSEONS 1

0
0
0
0
0
0

GPIOARSTS RNGRSTS Res. Res. AXISRAM3RSTS DBGRSTS MSISTOPENS LSIONS 0

Reset and clock control (RCC)

765/4691
779
 0xA30

0xA40
0xA38
0xA34
0xA28
0xA24
0xA20
Offset

0xA3C
0xA2C

766/4691
Reserved

Reset value
Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Register name

RCC_DIVENSR
RCC_APB5RSTSR
RCC_APB2RSTSR
RCC_AHB5RSTSR

RCC_APB4LRSTSR
RCC_APB1LRSTSR

RCC_APB4HRSTSR
RCC_APB1HRSTSR
0
0
Res. Res. Res. Res. Res. Res. UART8RSTS NPURSTS 31

0
Res. Res. Res. Res. Res. Res. UART7RSTS 0
0 CACHEAXIRSTS 30
Res. Res. Res. Res. Res. Res. Res. OTG2RSTS 29
Reset and clock control (RCC)

Res. Res. Res. Res. Res. Res. Res. OTGPHY2RSTS 28

0

Res. Res. Res. Res. Res. Res. Res. OTGPHY1RSTS 27

0

Res. Res. Res. Res. Res. Res. Res. OTG1RSTS 26

0
0

Res. Res. Res. Res. Res. Res. I3C2RSTS ETH1RSTS 25

0
0

Res. Res. Res. Res. Res. Res. I3C1RSTS OTG2PHYCTLRSTS 24

0
0

Res. Res. Res. Res. Res. Res. I2C3RSTS OTG1PHYCTLRSTS 23

0
0
Res. Res. Res. Res. SAI2RSTS Res. I2C2RSTS Res. 22

0
0

Res. Res. Res. Res. SAI1RSTS Res. I2C1RSTS Res. 21

0
0
0

Res. Res. Res. Res. SPI5RSTS Res. UART5RSTS GPU2DRSTS 20

0
0
0
0

IC20ENS Res. Res. Res. TIM9RSTS Res. UART4RSTS GFXMMURSTS 19

0
0
0

RM0486 Rev 2
IC19ENS Res. Res. Res. TIM17RSTS UCPD1RSTS USART3RSTS Res. 18

0
0
0
0

IC18ENS Res. Res. Res. TIM16RSTS Res. USART2RSTS XSPI3RSTS 17

0
0
0
0

IC17ENS Res. Res. RTCRSTS TIM15RSTS Res. SPDIFRX1RSTS Res. 16

0
0
0
0

IC16ENS Res. Res. VREFBUFRSTS TIM18RSTS Res. SPI3RSTS Res. 15

Reserved

0
0

IC15ENS Res. Res. Res. Res. Res. SPI2RSTS Res. 14

0
0
0
0

IC14ENS Res. Res. Res. SPI4RSTS Res. TIM11RSTS XSPIMRSTS 13

0
0
0

0
0
IC13ENS Res. Res. LPTIM5RSTS SPI1RSTS Res. TIM10RSTS XSPI2RSTS 12

0
0

0
IC12ENS Res. Res. LPTIM4RSTS Res. Res. WWDGRSTS Res. 11

0
0
IC11ENS Res. Res. LPTIM3RSTS Res. Res. Res. Res. 10

0
0

0
IC10ENS Res. Res. LPTIM2RSTS Res. Res. LPTIM1RSTS Res. 9
Table 78. RCC register map and reset values (continued)

0
0
0

IC9ENS Res. Res. Res. Res. FDCANRSTS TIM14RSTS SDMMC1RSTS 8

0
0

0
0
0

IC8ENS Res. Res. I2C4RSTS USART10RSTS Res. TIM13RSTS SDMMC2RSTS 7

0
0

0
0

0
IC7ENS CSIRSTS Res. Res. UART9RSTS Res. TIM12RSTS PSSIRSTS 6

0
0

0
0
0

0
0

IC6ENS VENCRSTS Res. SPI6RSTS USART6RSTS MDIOSRSTS TIM7RSTS XSPI1RSTS 5

0
0

0
0

0
IC5ENS GFXTIMRSTS Res. Res. USART1RSTS Res. TIM6RSTS FMCRSTS 4

0
0
0

IC4ENS Res. Res. 0 LPUART1RSTS Res. Res. TIM5RSTS JPEGRSTS 3

0
0

0
0
IC3ENS DCMIPPRSTS DTSRSTS HDPRSTS Res. Res. TIM4RSTS Res. 2

0
0

0
0

0
IC2ENS LTDCRSTS Res. Res. TIM8RSTS Res. TIM3RSTS DMA2DRSTS 1

0
0

0
0

0
IC1ENS Res. SYSCFGRSTS Res. TIM1RSTS Res. TIM2RSTS HPDMA1RSTS 0
RM0486
 0xA60
0xA58
0xA54
0xA50
0xA48
0xA44
Offset

0xA5C
0xA4C
RM0486

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Register name

RCC_BUSENSR

RCC_MEMENSR
RCC_MISCENSR

RCC_AHB5ENSR
RCC_AHB4ENSR
RCC_AHB3ENSR
RCC_AHB2ENSR
RCC_AHB1ENSR

0
NPUENS Res. Res. Res. Res. Res. Res. Res. 31

0
CACHEAXIENS Res. Res. Res. Res. Res. Res. Res. 30

0
OTG2ENS Res. Res. Res. Res. Res. Res. Res. 29

0
OTGPHY2ENS Res. Res. Res. Res. Res. Res. Res. 28

0
OTGPHY1ENS Res. Res. Res. Res. Res. Res. Res. 27

0
OTG1ENS Res. Res. Res. Res. Res. Res. Res. 26

0
ETH1ENS Res. Res. Res. Res. Res. Res. Res. 25

0
ETH1RXENS Res. Res. Res. Res. Res. Res. Res. 24

0
ETH1TXENS Res. Res. Res. Res. Res. Res. Res. 23

0
ETH1MACENS Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. 21

0
GPU2DENS Res. Res. Res. Res. Res. Res. Res. 20

0
0
GFXMMUENS CRCENS Res. Res. Res. Res. Res. Res. 19

0
0

RM0486 Rev 2
MCE4ENS PWRENS Res. Res. Res. Res. Res. Res. 18

0
0
XSPI3ENS Res. Res. ADF1ENS Res. Res. Res. Res. 17

0
0
0
MCE3ENS GPIOQENS Res. MDF1ENS Res. Res. Res. Res. 16

0
0
MCE2ENS GPIOPENS Res. Res. Res. Res. Res. Res. 15

0
0
0
MCE1ENS GPIOOENS RISAFENS Res. Res. Res. Res. Res. 14

0
0
XSPIMENS GPIONENS Res. Res. Res. Res. Res. Res. 13

0
0
0

XSPI2ENS Res. Res. RAMCFGENS Res. BOOTROMENS Res. Res. 12

0

Res. Res. Res. Res. Res. VENCRAMENS Res. Res. 11

0

0
Res. Res. IACENS Res. Res. CACHEAXIRAMENS Res. Res. 10
0

0
Res. Res. RIFSCENS Res. Res. FLEXRAMENS Res. Res. 9
Table 78. RCC register map and reset values (continued)

0
0

0
SDMMC1ENS Res. PKAENS Res. Res. AXISRAM2ENS Res. Res. 8

0
0
0

SDMMC2ENS GPIOHENS Res. Res. Res. AXISRAM1ENS Res. Res. 7

0
0
0
0

PSSIENS GPIOGENS Res. Res. Res. BKPSRAMENS PERENS Res. 6

0
0
0
0

XSPI1ENS GPIOFENS Res. Res. ADC12ENS AHBSRAM2ENS Res. Res. 5

0
0
0
0
0

FMCENS GPIOEENS SAESENS Res. GPDMA1ENS AHBSRAM1ENS Res. Res. 4

0
0
0
0

JPEGENS GPIODENS Res. Res. Res. AXISRAM6ENS XSPIPHYCOMPENS Res. 3

0
0

0
0

Res. GPIOCENS CRYPENS Res. Res. AXISRAM5ENS MCO2ENS Res. 2

0
0
0

0
0
0

DMA2DENS GPIOBENS HASHENS Res. Res. AXISRAM4ENS MCO1ENS ACLKNCENS 1

0
0
0

0
0
0

HPDMA1ENS GPIOAENS RNGENS Res. Res. AXISRAM3ENS DBGENS ACLKNENS 0

Reset and clock control (RCC)

767/4691
779
 0xA80

0xA84
0xA78
0xA74
0xA70
0xA68
0xA64
Offset

0xA7C
0xA6C

768/4691
Reserved
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Register name

RCC_APB5ENSR
RCC_APB3ENSR
RCC_APB2ENSR

RCC_APB4LENSR
RCC_APB1LENSR

RCC_BUSLPENSR
RCC_APB4HENSR
RCC_APB1HENSR
0
Res. Res. Res. Res. Res. Res. Res. UART8ENS 31
0

Res. Res. Res. Res. Res. Res. Res. UART7ENS 30

Res. Res. Res. Res. Res. Res. Res. Res. 29
Reset and clock control (RCC)

Res. Res. Res. Res. Res. Res. Res. Res. 28

Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. 26
0

Res. Res. Res. Res. Res. Res. Res. I3C2ENS 25

0

Res. Res. Res. Res. Res. Res. Res. I3C1ENS 24

0

Res. Res. Res. Res. Res. Res. Res. I2C3ENS 23

0
0

Res. Res. Res. Res. Res. SAI2ENS Res. I2C2ENS 22

0
0

Res. Res. Res. Res. Res. SAI1ENS Res. I2C1ENS 21

0
0

Res. Res. Res. Res. Res. 0 SPI5ENS Res. UART5ENS 20

0

Res. Res. Res. Res. Res. TIM9ENS Res. UART4ENS 19

0
0

RM0486 Rev 2
Res. Res. Res. Res. Res. TIM17ENS UCPD1ENS USART3ENS 18
0

0
0

Res. Res. Res. RTCAPBENS Res. TIM16ENS Res. USART2ENS 17

0

0
0

Res. Res. Res. RTCENS Res. TIM15ENS Res. SPDIFRX1ENS 16

0

0
0

Res. Res. Res. VREFBUFENS Res. TIM18ENS Res. SPI3ENS 15

Reserved
0

Res. Res. Res. Res. Res. Res. Res. SPI2ENS 14

0
0

Res. Res. Res. Res. Res. SPI4ENS Res. TIM11ENS 13

0

0
0

Res. Res. Res. LPTIM5ENS Res. SPI1ENS Res. TIM10ENS 12

0

0
Res. Res. Res. LPTIM4ENS Res. Res. Res. WWDGENS 11

0
Res. Res. Res. LPTIM3ENS Res. Res. Res. Res. 10
0

Res. Res. Res. 0 LPTIM2ENS Res. Res. Res. LPTIM1ENS 9

Table 78. RCC register map and reset values (continued)

Res. Res. Res. Res. Res. Res. FDCANENS TIM14ENS 8

0

0
0

Res. Res. Res. I2C4ENS Res. USART10ENS Res. TIM13ENS 7

0

0
Res. CSIENS Res. Res. Res. UART9ENS Res. TIM12ENS 6
0

0
0

0
0

Res. VENCENS Res. SPI6ENS Res. USART6ENS MDIOSENS TIM7ENS 5

0

0
Res. GFXTIMENS Res. Res. Res. USART1ENS Res. TIM6ENS 4
0

Res. Res. Res. LPUART1ENS Res. Res. Res. TIM5ENS 3

0

0
0
0

Res. DCMIPPENS DTSENS HDPENS DFTENS Res. Res. TIM4ENS 2

0

0
0
0

ACLKNCLPENS LTDCENS BSECENS Res. Res. TIM8ENS Res. TIM3ENS 1

0

0
0

ACLKNLPENS Res. SYSCFGENS Res. Res. TIM1ENS Res. TIM2ENS 0

RM0486
 0xA98
0xA94
0xA90
0xA88
Offset

0xAA0
0xA9C
0xA8C
RM0486

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Register name

RCC_MEMLPENSR
RCC_MISCLPENSR

RCC_AHB5LPENSR
RCC_AHB4LPENSR
RCC_AHB3LPENSR
RCC_AHB2LPENSR
RCC_AHB1LPENSR

0
NPULPENS Res. Res. Res. Res. Res. Res. 31

0
CACHEAXILPENS Res. Res. Res. Res. Res. Res. 30

0
OTG2LPENS Res. Res. Res. Res. Res. Res. 29

0
OTGPHY2LPENS Res. Res. Res. Res. Res. Res. 28

0
OTGPHY1LPENS Res. Res. Res. Res. Res. Res. 27

0
OTG1LPENS Res. Res. Res. Res. Res. Res. 26

0
ETH1LPENS Res. Res. Res. Res. Res. Res. 25

0
ETH1RXLPENS Res. Res. Res. Res. Res. Res. 24

0
ETH1TXLPENS Res. Res. Res. Res. Res. Res. 23

0
ETH1MACLPENS Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. 21

0
GPU2DLPENS Res. Res. Res. Res. Res. Res. 20

0
0
GFXMMULPENS CRCLPENS Res. Res. Res. Res. Res. 19

0
0

RM0486 Rev 2
MCE4LPENS PWRLPENS Res. Res. Res. Res. Res. 18

0
0
XSPI3LPENS Res. Res. ADF1LPENS Res. Res. Res. 17

0
0
0
MCE3LPENS GPIOQLPENS Res. MDF1LPENS Res. Res. Res. 16

0
0
MCE2LPENS GPIOPLPENS Res. Res. Res. Res. Res. 15

0
0
0
MCE1LPENS GPIOOLPENS RISAFLPENS Res. Res. Res. Res. 14

0
0
XSPIMLPENS GPIONLPENS Res. Res. Res. Res. Res. 13

0
0
0

XSPI2LPENS Res. Res. RAMCFGLPENS Res. BOOTROMLPENS Res. 12

0

Res. Res. Res. Res. Res. VENCRAMLPENS Res. 11

0

0
Res. Res. IACLPENS Res. Res. CACHEAXIRAMLPENS Res. 10
0

0
Res. Res. RIFSCLPENS Res. Res. FLEXRAMLPENS Res. 9
Table 78. RCC register map and reset values (continued)

0
0

0
SDMMC1LPENS Res. PKALPENS Res. Res. AXISRAM2LPENS Res. 8

0
0
0

SDMMC2LPENS GPIOHLPENS Res. Res. Res. AXISRAM1LPENS Res. 7

0
0
0
0

PSSILPENS GPIOGLPENS Res. Res. Res. BKPSRAMLPENS PERLPENS 6

0
0
0
0

XSPI1LPENS GPIOFLPENS Res. Res. ADC12LPENS AHBSRAM2LPENS Res. 5

0
0
0

0
0

FMCLPENS GPIOELPENS SAESLPENS Res. GPDMA1LPENS AHBSRAM1LPENS Res. 4

0
0
0
0

JPEGLPENS GPIODLPENS Res. Res. Res. AXISRAM6LPENS XSPIPHYCOMPLPENS 3

0
0

0
Res. GPIOCLPENS CRYPLPENS Res. Res. AXISRAM5LPENS Res. 2

0
0
0

0
DMA2DLPENS GPIOBLPENS HASHLPENS Res. Res. AXISRAM4LPENS Res. 1

0
0
0

0
0

HPDMA1LPENS GPIOALPENS RNGLPENS Res. Res. AXISRAM3LPENS DBGLPENS 0

Reset and clock control (RCC)

769/4691
779
 0xF88
0xF84
0xF80
Offset

0xAB8
0xAB4
0xAB0
0xAA8
0xAA4

0xABC
0xAAC

0xAC0-

770/4691
RCC_
RCC_

Reserved
Reserved
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Register name

APB4HLPENSR
APB1HLPENSR

RCC_PRIVCFGSR0
RCC_APB5LPENSR
RCC_APB3LPENSR
RCC_APB2LPENSR

RCC_APB4LLPENSR
RCC_APB1LLPENSR

0
Res. Res. Res. Res. Res. Res. Res. UART8LPENS 31
0
Res. Res. Res. Res. Res. Res. Res. UART7LPENS 30
Res. Res. Res. Res. Res. Res. Res. Res. 29
Reset and clock control (RCC)

Res. Res. Res. Res. Res. Res. Res. Res. 28

Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. 26
0

Res. Res. Res. Res. Res. Res. Res. I3C2LPENS 25

0

Res. Res. Res. Res. Res. Res. Res. I3C1LPENS 24

0

Res. Res. Res. Res. Res. Res. Res. I2C3LPENS 23

0
0

Res. Res. Res. Res. Res. SAI2LPENS Res. I2C2LPENS 22

0
0

Res. Res. Res. Res. Res. SAI1LPENS Res. I2C1LPENS 21

0
0

Res. Res. Res. Res. Res. SPI5LPENS Res. UART5LPENS 20

0
0

Res. Res. Res. Res. Res. TIM9LPENS Res. UART4LPENS 19

0
0

RM0486 Rev 2
Res. Res. Res. Res. Res. TIM17LPENS UCPD1LPENS USART3LPENS 18
0

0
0
Res. Res. Res. RTCAPBLPENS Res. TIM16LPENS Res. USART2LPENS 17
0

0
0

Res. Res. Res. RTCLPENS Res. TIM15LPENS Res. SPDIFRX1LPENS 16

0

0
0

Res. Res. Res. VREFBUFLPENS Res. TIM18LPENS Res. SPI3LPENS 15

Reserved
Reserved
0

Res. Res. Res. Res. Res. Res. Res. SPI2LPENS 14

0
0

Res. Res. Res. Res. Res. SPI4LPENS Res. TIM11LPENS 13

0

0
0

Res. Res. Res. LPTIM5LPENS Res. SPI1LPENS Res. TIM10LPENS 12

0

0
Res. Res. Res. LPTIM4LPENS Res. Res. Res. WWDGLPENS 11

0
Res. Res. Res. LPTIM3LPENS Res. Res. Res. Res. 10
0

0
Res. Res. Res. LPTIM2LPENS Res. Res. Res. LPTIM1LPENS 9
Table 78. RCC register map and reset values (continued)

Res. Res. Res. Res. Res. Res. FDCANLPENS TIM14LPENS 8

0

0
0

Res. Res. Res. I2C4LPENS Res. USART10LPENS Res. TIM13LPENS 7

0

0
Res. CSILPENS Res. Res. Res. UART9LPENS Res. TIM12LPENS 6
0

0
0

0
0

Res. VENCLPENS Res. SPI6LPENS Res. USART6LPENS MDIOSLPENS TIM7LPENS 5

0

0
0
HSEPRIVS GFXTIMLPENS Res. Res. Res. USART1LPENS Res. TIM6LPENS 4
0

0
HSIPRIVS Res. Res. LPUART1LPENS Res. Res. Res. TIM5LPENS 3
0

0
0
0
0

MSIPRIVS DCMIPPLPENS DTSLPENS HDPLPENS DFTLPENS Res. Res. TIM4LPENS 2

0

0
0
0
LSEPRIVS LTDCLPENS BSECLPENS Res. Res. TIM8LPENS Res. TIM3LPENS 1
0

0
0
LSIPRIVS Res. SYSCFGLPENS Res. Res. TIM1LPENS Res. TIM2LPENS 0
RM0486
 0xF98
0xF94
0xF90

0xFA8
0xFA4
0xFA0

0xFB8
0xFB4
0xFB0
Offset

0xFC4

0xFC8
0xFC0
0xF9C
0xF8C

0xFAC

0xFBC
RM0486

RCC_
RCC_
RCC_
RCC_

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value

PUBCFGSR3
PUBCFGSR2

PRIVCFGSR4
PRIVCFGSR3
Register name

RCC_PUBCFGSR1
RCC_PUBCFGSR0

RCC_PRIVCFGSR2
RCC_PRIVCFGSR1
Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. 20

0
0
Res. Res. Res. IC20PUBS IC20PRIVS Res. Res. Res. 19

0
0

RM0486 Rev 2
Res. Res. Res. IC19PUBS IC19PRIVS Res. Res. Res. 18

0
0
Res. Res. Res. IC18PUBS IC18PRIVS Res. Res. Res. 17

0
0
Res. Res. Res. IC17PUBS IC17PRIVS Res. Res. Res. 16

0
0
Res. Res. Res. IC16PUBS IC16PRIVS Res. Res. Res. 15

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

0
0
Res. Res. Res. IC15PUBS IC15PRIVS Res. Res. Res. 14

0
0
NOCPRIVS Res. Res. IC14PUBS 0 IC14PRIVS Res. Res. Res. 13

0
0
0
APB5PRIVS Res. Res. IC13PUBS IC13PRIVS Res. Res. Res. 12

0
0
0

APB4PRIVS Res. Res. IC12PUBS IC12PRIVS Res. Res. Res. 11

0
0
0

APB3PRIVS Res. Res. IC11PUBS IC11PRIVS Res. Res. Res. 10

0
0
0

APB2PRIVS Res. Res. IC10PUBS IC10PRIVS Res. Res. Res. 9

Table 78. RCC register map and reset values (continued)

0
0
0

APB1PRIVS Res. Res. IC9PUBS IC9PRIVS Res. Res. Res. 8

0
0
0

AHB5PRIVS Res. Res. IC8PUBS IC8PRIVS Res. Res. Res. 7

0
0
0

0
AHB4PRIVS Res. DFTPRIVS IC7PUBS IC7PRIVS Res. Res. Res. 6

0
0
0

0
0
AHB3PRIVS RSTPUBS RSTPRIVS IC6PUBS IC6PRIVS Res. Res. Res. 5

0
0
0

0
0
0

AHB2PRIVS INTPUBS INTPRIVS IC5PUBS IC5PRIVS Res. Res. HSEPUBS 4

0
0
0

0
0
0
0
0

AHB1PRIVS PERPUBS PERPRIVS IC4PUBS IC4PRIVS PLL4PUBS PLL4PRIVS HSIPUBS 3

0
0
0

0
0
0
0
0

AHBMPRIVS BUSPUBS BUSPRIVS IC3PUBS IC3PRIVS PLL3PUBS PLL3PRIVS MSIPUBS 2

0
0
0

0
0
0
0
0

ACLKNCPRIVS SYSPUBS SYSPRIVS IC2PUBS IC2PRIVS PLL2PUBS PLL2PRIVS LSEPUBS 1

0
0
0

0
0
0
0
0

ACLKNPRIVS MODPUBS MODPRIVS IC1PUBS IC1PRIVS PLL1PUBS PLL1PRIVS LSIPUBS 0

Reset and clock control (RCC)

771/4691
779
 Offset

0xFD0

0xFFC
0xFCC

0xFD4-

0x1004

0x1210
0x1208
0x1204
0x1008
0x1000

0x120C
0x100C-

772/4691
RCC_
RCC_

Reserved
Reserved
Reserved

RCC_CCR
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
PUBCFGSR5
PUBCFGSR4
Register name

RCC_STOPCCR

RCC_MEMRSTCR
RCC_MISCRSTCR

RCC_AHB1RSTCR
Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. 29
Reset and clock control (RCC)

Res. Res. Res. Res. Res. Res. Res. 28

Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. 19

RM0486 Rev 2
Res. Res. Res. Res. Res. Res. Res. 18
Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. 16
Res. Res. Res. Res. Res. Res. Res. 15

Reserved
Reserved
Reserved

Res. Res. Res. Res. Res. Res. Res. 14

0

Res. Res. Res. Res. Res. Res. NOCPUBS 13

0
0

Res. BOOTROMRSTC Res. Res. Res. Res. APB5PUBS 12

0
0
0
0

Res. VENCRAMRSTC Res. Res. PLL4ONC VENCRAMPUBS APB4PUBS 11

0
0
0
0

Res. CACHEAXIRAMRSTC Res. Res. PLL3ONC CACHEAXIRAMPUBS APB3PUBS 10

0
0
0
0

Res. FLEXRAMRSTC Res. Res. PLL2ONC FLEXRAMPUBS APB2PUBS 9

Table 78. RCC register map and reset values (continued)

0
0
0
0
0

Res. AXISRAM2RSTC SDMMC2DLLRSTC Res. PLL1ONC AXISRAM2PUBS APB1PUBS 8

0
0

0
0

Res. AXISRAM1RSTC SDMMC1DLLRSTC Res. Res. AXISRAM1PUBS AHB5PUBS 7

0
0

Res. Res. Res. Res. Res. BKPSRAMPUBS AHB4PUBS 6

0
0
0

0
0

ADC12RSTC AHBSRAM2RSTC XSPIPHY2RSTC Res. Res. AHBSRAM2PUBS AHB3PUBS 5

0
0
0
0
0
0

GPDMA1RSTC AHBSRAM1RSTC XSPIPHY1RSTC Res. HSEONC AHBSRAM1PUBS AHB2PUBS 4

0
0
0
0

Res. AXISRAM6RSTC Res. Res. HSIONC AXISRAM6PUBS AHB1PUBS 3

0
0
0
0

Res. AXISRAM5RSTC Res. Res. MSIONC AXISRAM5PUBS AHBMPUBS 2

0
0
0
0

Res. AXISRAM4RSTC Res. HSISTOPENC LSEONC AXISRAM4PUBS ACLKNCPUBS 1

0
0
0
0
0

Res. AXISRAM3RSTC DBGRSTC MSISTOPENC LSIONC AXISRAM3PUBS ACLKNPUBS 0

RM0486
 Offset

0x1230

0x1234
0x1228
0x1224
0x1220
0x1218
0x1214

0x122C
0x121C
RM0486

Reserved

Reset value
Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Register name

RCC_APB2RSTCR
RCC_AHB5RSTCR
RCC_AHB4RSTCR
RCC_AHB3RSTCR
RCC_AHB2RSTCR

RCC_APB4LRSTCR
RCC_APB1LRSTCR

RCC_APB1HRSTCR
0
0
Res. Res. Res. UART8RSTC NPURSTC Res. Res. Res. 31

0
0
Res. Res. Res. UART7RSTC CACHEAXIRSTC Res. Res. Res. 30

0
Res. Res. Res. Res. OTG2RSTC Res. Res. Res. 29

0
Res. Res. Res. Res. OTGPHY2RSTC Res. Res. Res. 28

0
Res. Res. Res. Res. OTGPHY1RSTC Res. Res. Res. 27

0
Res. Res. Res. Res. OTG1RSTC Res. Res. Res. 26

0
0
Res. Res. Res. I3C2RSTC ETH1RSTC Res. Res. Res. 25

0
0
Res. Res. Res. I3C1RSTC OTG2PHYCTLRSTC Res. Res. Res. 24

0
0
Res. Res. Res. I2C3RSTC OTG1PHYCTLRSTC Res. Res. Res. 23

0
0
Res. SAI2RSTC Res. I2C2RSTC Res. Res. Res. Res. 22

0
0
Res. SAI1RSTC Res. I2C1RSTC Res. Res. Res. Res. 21

0
0
0
Res. SPI5RSTC Res. UART5RSTC GPU2DRSTC Res. Res. Res. 20

0
0
0
0
Res. TIM9RSTC Res. UART4RSTC GFXMMURSTC CRCRSTC Res. Res. 19

0
0
0

RM0486 Rev 2
Res. TIM17RSTC UCPD1RSTC USART3RSTC Res. PWRRSTC Res. Res. 18

0
0
0
0

Res. TIM16RSTC Res. USART2RSTC XSPI3RSTC Res. Res. ADF1RSTC 17

0
0
0
0

RTCRSTC TIM15RSTC Res. SPDIFRX1RSTC Res. GPIOQRSTC Res. MDF1RSTC 16

0
0

0
0

VREFBUFRSTC TIM18RSTC Res. SPI3RSTC Res. GPIOPRSTC Res. Res. 15

Reserved
0
0

Res. Res. Res. SPI2RSTC Res. GPIOORSTC Res. Res. 14

0
0
0
0

Res. SPI4RSTC Res. TIM11RSTC XSPIMRSTC GPIONRSTC Res. Res. 13

0
0
0

0
0

LPTIM5RSTC SPI1RSTC Res. TIM10RSTC XSPI2RSTC Res. Res. RAMCFGRSTC 12

0
LPTIM4RSTC Res. Res. WWDGRSTC Res. Res. Res. Res. 11

0
0

LPTIM3RSTC Res. Res. Res. Res. Res. IACRSTC Res. 10

0
LPTIM2RSTC Res. Res. LPTIM1RSTC Res. Res. Res. Res. 9
Table 78. RCC register map and reset values (continued)

0
0

0
0

Res. Res. FDCANRSTC TIM14RSTC SDMMC1RSTC Res. PKARSTC Res. 8

0
0

0
0
0

I2C4RSTC USART10RSTC Res. TIM13RSTC SDMMC2RSTC GPIOHRSTC Res. Res. 7

0
0
0

Res. UART9RSTC Res. TIM12RSTC PSSIRSTC GPIOGRSTC Res. Res. 6

0
0

0
0
0

0
SPI6RSTC USART6RSTC MDIOSRSTC 0 TIM7RSTC XSPI1RSTC GPIOFRSTC Res. Res. 5

0
0
0
0

Res. USART1RSTC Res. TIM6RSTC FMCRSTC GPIOERSTC SAESRSTC Res. 4

0
0

0
0

LPUART1RSTC Res. Res. TIM5RSTC JPEGRSTC GPIODRSTC Res. Res. 3

0

0
0
0

HDPRSTC Res. Res. TIM4RSTC Res. GPIOCRSTC CRYPRSTC Res. 2

0

0
0
0
0

Res. TIM8RSTC Res. TIM3RSTC DMA2DRSTC GPIOBRSTC HASHRSTC Res. 1

0

0
0
0
0

Res. TIM1RSTC Res. TIM2RSTC HPDMA1RSTC GPIOARSTC RNGRSTC Res. 0

Reset and clock control (RCC)

773/4691
779
 Offset

0x1254
0x1250
0x1248
0x1244
0x1240
0x1238

0x124C
0x123C

774/4691
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Register name

RCC_DIVENCR

RCC_BUSENCR

RCC_MEMENCR
RCC_MISCENCR

RCC_AHB2ENCR
RCC_AHB1ENCR
RCC_APB5RSTCR
RCC_APB4HRSTCR

Res. Res. Res. Res. Res. Res. Res. Res. 31

Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. 29
Reset and clock control (RCC)

Res. Res. Res. Res. Res. Res. Res. Res. 28

Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. 20
0

Res. Res. Res. Res. Res. IC20ENC Res. Res. 19

0

RM0486 Rev 2
Res. Res. Res. Res. Res. IC19ENC Res. Res. 18
0

0
ADF1ENC Res. Res. Res. Res. IC18ENC Res. Res. 17
0

0
MDF1ENC Res. Res. Res. Res. IC17ENC Res. Res. 16
0

Res. Res. Res. Res. Res. IC16ENC Res. Res. 15

0

Res. Res. Res. Res. Res. IC15ENC Res. Res. 14

0

Res. Res. Res. Res. Res. IC14ENC Res. Res. 13

0

0
0
RAMCFGENC Res. BOOTROMENC Res. Res. IC13ENC Res. Res. 12
0

0
Res. Res. VENCRAMENC Res. Res. IC12ENC Res. Res. 11
0

0
Res. Res. CACHEAXIRAMENC Res. Res. IC11ENC Res. Res. 10
0

0
Res. Res. FLEXRAMENC Res. Res. IC10ENC Res. Res. 9
Table 78. RCC register map and reset values (continued)

0
Res. Res. AXISRAM2ENC Res. Res. IC9ENC Res. Res. 8
0

0
Res. Res. AXISRAM1ENC Res. Res. IC8ENC Res. Res. 7
0

0
0
0

Res. Res. BKPSRAMENC PERENC Res. IC7ENC CSIRSTC Res. 6

0

0
0
0

Res. ADC12ENC AHBSRAM2ENC Res. Res. IC6ENC VENCRSTC Res. 5

0

0
0
0

Res. GPDMA1ENC AHBSRAM1ENC Res. Res. IC5ENC GFXTIMRSTC Res. 4

0

0
0

Res. Res. AXISRAM6ENC XSPIPHYCOMPENC Res. IC4ENC Res. Res. 3

0

0
0
0
0

Res. Res. AXISRAM5ENC MCO2ENC Res. IC3ENC DCMIPPRSTC DTSRSTC 2

0

0
0
0
0

Res. Res. AXISRAM4ENC MCO1ENC ACLKNCENC IC2ENC LTDCRSTC Res. 1

0

0
0
0
0

Res. Res. AXISRAM3ENC DBGENC ACLKNENC IC1ENC Res. SYSCFGRSTC 0

RM0486
 Offset

0x1278
0x1274
0x1270
0x1268
0x1264
0x1260
0x1258

0x126C
0x125C
RM0486

Reset value
Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Register name

RCC_APB3ENCR
RCC_APB2ENCR
RCC_AHB5ENCR
RCC_AHB4ENCR
RCC_AHB3ENCR

RCC_APB4LENCR
RCC_APB1LENCR

RCC_APB4HENCR
RCC_APB1HENCR
0
0
Res. Res. Res. Res. Res. UART8ENC NPUENC Res. Res. 31

0
0
Res. Res. Res. Res. Res. UART7ENC CACHEAXIENC Res. Res. 30

0
Res. Res. Res. Res. Res. Res. OTG2ENC Res. Res. 29

0
Res. Res. Res. Res. Res. Res. OTGPHY2ENC Res. Res. 28

0
Res. Res. Res. Res. Res. Res. OTGPHY1ENC Res. Res. 27

0
Res. Res. Res. Res. Res. Res. OTG1ENC Res. Res. 26

0
0
Res. Res. Res. Res. Res. I3C2ENC ETH1ENC Res. Res. 25

0
0
Res. Res. Res. Res. Res. I3C1ENC ETH1RXENC Res. Res. 24

0
0
Res. Res. Res. Res. Res. I2C3ENC ETH1TXENC Res. Res. 23

0
0
0
Res. Res. Res. SAI2ENC Res. I2C2ENC ETH1MACENC Res. Res. 22

0
0
Res. Res. Res. SAI1ENC Res. I2C1ENC Res. Res. Res. 21

0
0
0
Res. Res. Res. SPI5ENC Res. UART5ENC GPU2DENC Res. Res. 20

0
0
0
0

Res. Res. Res. TIM9ENC Res. UART4ENC GFXMMUENC CRCENC Res. 19

0
0
0
0

RM0486 Rev 2
Res. Res. Res. TIM17ENC UCPD1ENC USART3ENC MCE4ENC PWRENC Res. 18

0
0

0
0
Res. RTCAPBENC Res. TIM16ENC Res. USART2ENC XSPI3ENC Res. Res. 17

0
0
0

0
0

Res. RTCENC Res. TIM15ENC Res. SPDIFRX1ENC MCE3ENC GPIOQENC Res. 16

0
0
0

0
0

Res. VREFBUFENC Res. TIM18ENC Res. SPI3ENC MCE2ENC GPIOPENC Res. 15

0
0
0
0

Res. Res. Res. Res. Res. SPI2ENC MCE1ENC GPIOOENC RISAFENC 14

0
0
0
0

Res. Res. Res. SPI4ENC Res. TIM11ENC XSPIMENC GPIONENC Res. 13

0
0

0
0
Res. LPTIM5ENC Res. SPI1ENC Res. TIM10ENC XSPI2ENC Res. Res. 12

0
Res. LPTIM4ENC Res. Res. Res. Res. Res. Res. Res. 11

0
0

Res. LPTIM3ENC Res. Res. Res. Res. Res. Res. IACENC 10

0

0
0

Res. LPTIM2ENC Res. Res. Res. LPTIM1ENC Res. Res. RIFSCENC 9

Table 78. RCC register map and reset values (continued)

0
0

0
0

Res. Res. Res. Res. FDCANENC TIM14ENC SDMMC1ENC Res. PKAENC 8

0
0
0

0
0

Res. I2C4ENC Res. USART10ENC Res. TIM13ENC SDMMC2ENC GPIOHENC Res. 7

0
0
0
0

Res. Res. Res. UART9ENC Res. TIM12ENC PSSIENC GPIOGENC Res. 6

0
0

0
0
0

Res. SPI6ENC Res. USART6ENC MDIOSENC TIM7ENC XSPI1ENC GPIOFENC Res. 5

0
0

0
0
0

Res. Res. Res. USART1ENC Res. TIM6ENC FMCENC GPIOEENC SAESENC 4

0
0

0
0

Res. LPUART1ENC Res. Res. Res. TIM5ENC JPEGENC GPIODENC Res. 3

0

0
0

0
0
0

DTSENC HDPENC DFTENC Res. Res. TIM4ENC Res. GPIOCENC CRYPENC 2

0
0

0
0

0
0

BSECENC Res. Res. TIM8ENC Res. TIM3ENC DMA2DENC GPIOBENC HASHENC 1

0
0

0
0

0
0

SYSCFGENC Res. Res. TIM1ENC Res. TIM2ENC HPDMA1ENC GPIOAENC RNGENC 0

Reset and clock control (RCC)

775/4691
779
 Offset

0x1280

0x1298
0x1294
0x1290
0x1288
0x1284

0x128C
0x127C

776/4691
Reserved

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Register name

RCC_APB5ENCR

RCC_BUSLPENCR

RCC_MEMLPENCR
RCC_MISCLPENCR

RCC_AHB3LPENCR
RCC_AHB2LPENCR
RCC_AHB1LPENCR
Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. 29
Reset and clock control (RCC)

Res. Res. Res. Res. Res. Res. Res. 28

Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. 19

RM0486 Rev 2
Res. Res. Res. Res. Res. Res. Res. 18

0
Res. ADF1LPENC Res. Res. Res. Res. Res. 17

0
Res. MDF1LPENC Res. Res. Res. Res. Res. 16
Res. Res. Res. Res. Res. Res. Res. 15
Reserved

0
RISAFLPENC Res. Res. Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. Res. 13

0
0
Res. RAMCFGLPENC Res. BOOTROMLPENC Res. Res. Res. 12

0
Res. Res. Res. VENCRAMLPENC Res. Res. Res. 11

0
IACLPENC Res. Res. CACHEAXIRAMLPENC Res. Res. Res. 10

0
RIFSCLPENC Res. Res. FLEXRAMLPENC Res. Res. Res. 9
Table 78. RCC register map and reset values (continued)

0
PKALPENC Res. Res. AXISRAM2LPENC Res. Res. Res. 8

0
Res. Res. Res. AXISRAM1LPENC Res. Res. Res. 7
0
0
0

Res. Res. Res. BKPSRAMLPENC PERLPENC Res. CSIENC 6

0
0
0

Res. Res. ADC12LPENC AHBSRAM2LPENC Res. Res. VENCENC 5

0

0
0
0

SAESLPENC Res. GPDMA1LPENC AHBSRAM1LPENC Res. Res. GFXTIMENC 4

0
0

Res. Res. Res. AXISRAM6LPENC XSPIPHYCOMPLPENC Res. Res. 3

0

0
0

CRYPLPENC Res. Res. AXISRAM5LPENC Res. Res. DCMIPPENC 2

0

0
0
0

HASHLPENC Res. Res. AXISRAM4LPENC Res. ACLKNCLPENC LTDCENC 1

0

0
0
0

RNGLPENC Res. Res. AXISRAM3LPENC DBGLPENC ACLKNLPENC Res. 0

RM0486
 Offset

0x12B8
0x12B4
0x12B0
0x12A8
0x12A4
0x12A0
0x129C

0x12AC
RM0486

RCC_
RCC_

Reset value
Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Register name

APB4HLPENCR
APB1HLPENCR

RCC_APB3LPENCR
RCC_APB2LPENCR
RCC_AHB5LPENCR
RCC_AHB4LPENCR

RCC_APB4LLPENCR
RCC_APB1LLPENCR

0
0
Res. Res. Res. Res. Res. UART8LPENC NPULPENC Res. 31

0
0
Res. Res. Res. Res. Res. UART7LPENC CACHEAXILPENC Res. 30

0
Res. Res. Res. Res. Res. Res. OTG2LPENC Res. 29

0
Res. Res. Res. Res. Res. Res. OTGPHY2LPENC Res. 28

0
Res. Res. Res. Res. Res. Res. OTGPHY1LPENC Res. 27

0
Res. Res. Res. Res. Res. Res. OTG1LPENC Res. 26

0
0
Res. Res. Res. Res. Res. I3C2LPENC ETH1LPENC Res. 25

0
Res. Res. Res. Res. Res. I3C1LPENC 0 ETH1RXLPENC Res. 24

0
0
Res. Res. Res. Res. Res. I2C3LPENC ETH1TXLPENC Res. 23

0
0
0

Res. Res. Res. SAI2LPENC Res. I2C2LPENC ETH1MACLPENC Res. 22

0
0
Res. Res. Res. SAI1LPENC Res. I2C1LPENC Res. Res. 21

0
0
0

Res. Res. Res. SPI5LPENC Res. UART5LPENC GPU2DLPENC Res. 20

0
0
0
0

Res. Res. Res. TIM9LPENC Res. UART4LPENC GFXMMULPENC CRCLPENC 19

0
0
0
0

RM0486 Rev 2
Res. Res. Res. TIM17LPENC UCPD1LPENC USART3LPENC MCE4LPENC PWRLPENC 18
0
0

0
0
Res. RTCAPBLPENC Res. TIM16LPENC Res. USART2LPENC XSPI3LPENC Res. 17

0
0
0

0
0

Res. RTCLPENC Res. TIM15LPENC Res. SPDIFRX1LPENC MCE3LPENC GPIOQLPENC 16

0
0
0

0
0

Res. VREFBUFLPENC Res. TIM18LPENC Res. SPI3LPENC MCE2LPENC GPIOPLPENC 15

0
0
0

Res. Res. Res. Res. Res. SPI2LPENC MCE1LPENC GPIOOLPENC 14

0
0
0
0

Res. Res. Res. SPI4LPENC Res. TIM11LPENC XSPIMLPENC GPIONLPENC 13

0
0

0
0
Res. LPTIM5LPENC Res. SPI1LPENC Res. TIM10LPENC XSPI2LPENC Res. 12
0

0
Res. LPTIM4LPENC Res. Res. Res. WWDGLPENC Res. Res. 11

0
Res. LPTIM3LPENC Res. Res. Res. Res. Res. Res. 10
0

0
Res. LPTIM2LPENC Res. Res. Res. LPTIM1LPENC Res. Res. 9
Table 78. RCC register map and reset values (continued)

0
0

Res. Res. Res. Res. FDCANLPENC TIM14LPENC SDMMC1LPENC Res. 8

0
0

0
0
0

Res. I2C4LPENC Res. USART10LPENC Res. TIM13LPENC SDMMC2LPENC GPIOHLPENC 7

0
0

0
0

Res. Res. Res. UART9LPENC Res. TIM12LPENC PSSILPENC GPIOGLPENC 6

0
0

0
0
0

Res. SPI6LPENC Res. USART6LPENC MDIOSLPENC TIM7LPENC XSPI1LPENC GPIOFLPENC 5

0
0

0
0

Res. Res. Res. USART1LPENC Res. TIM6LPENC FMCLPENC GPIOELPENC 4

0
0

0
0

Res. LPUART1LPENC Res. Res. Res. TIM5LPENC JPEGLPENC GPIODLPENC 3

0

0
0

0
0
DTSLPENC HDPLPENC DFTLPENC Res. Res. TIM4LPENC Res. GPIOCLPENC 2
0
0

0
0

0
BSECLPENC Res. Res. TIM8LPENC Res. TIM3LPENC DMA2DLPENC GPIOBLPENC 1
0
0

0
0

0
SYSCFGLPENC Res. Res. TIM1LPENC Res. TIM2LPENC HPDMA1LPENC GPIOALPENC 0
Reset and clock control (RCC)

777/4691
779
 Offset

0x1798
0x1790
0x1788

0x1794
0x1784
0x1780

0x17B8
0x17B0
0x17A8
0x17A0

0x17B4
0x17A4
0x179C
0x178C

0x17AC
0x12BC

0x12C0-

778/4691
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Register name

RCC_PUBCFGCR2
RCC_PUBCFGCR1
RCC_PUBCFGCR0

RCC_PRIVCFGCR3
RCC_PRIVCFGCR2
RCC_PRIVCFGCR1
RCC_PRIVCFGCR0
RCC_APB5LPENCR

Res. Res. Res. Res. Res. Res. Res. Res. 31

Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. 29
Reset and clock control (RCC)

Res. Res. Res. Res. Res. Res. Res. Res. 28

Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. 20

0
0
Res. IC20PUBC IC20PRIVC Res. Res. Res. Res. Res. 19

0
0

RM0486 Rev 2
Res. IC19PUBC IC19PRIVC Res. Res. Res. Res. Res. 18

0
0
Res. IC18PUBC IC18PRIVC Res. Res. Res. Res. Res. 17

0
0
Res. IC17PUBC IC17PRIVC Res. Res. Res. Res. Res. 16

0
0
Res. IC16PUBC IC16PRIVC Res. Res. Res. Res. Res. 15

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

0
0
Res. IC15PUBC IC15PRIVC Res. Res. Res. Res. Res. 14

0
0
Res. IC14PUBC IC14PRIVC Res. Res. Res. Res. Res. 13

0
0
Res. IC13PUBC IC13PRIVC Res. Res. Res. Res. Res. 12

0
0
Res. IC12PUBC IC12PRIVC Res. Res. Res. Res. Res. 11

0
0
Res. IC11PUBC IC11PRIVC Res. Res. Res. Res. Res. 10

0
0
Res. IC10PUBC IC10PRIVC Res. Res. Res. Res. Res. 9
Table 78. RCC register map and reset values (continued)

0
0
Res. IC9PUBC IC9PRIVC Res. Res. Res. Res. Res. 8

0
0
Res. IC8PUBC IC8PRIVC Res. Res. Res. Res. Res. 7

0
0

0
0

DFTPRIVC IC7PUBC IC7PRIVC Res. Res. Res. Res. CSILPENC 6

0
0

0
0

RSTPRIVC IC6PUBC IC6PRIVC Res. Res. Res. Res. VENCLPENC 5

0
0

0
0
0
0

INTPRIVC IC5PUBC IC5PRIVC Res. Res. HSEPUBC HSEPRIVC GFXTIMLPENC 4

0
0

0
0
0
0
0

PERPRIVC IC4PUBC IC4PRIVC PLL4PUBC PLL4PRIVC HSIPUBC HSIPRIVC Res. 3

0
0

0
0
0
0
0
0

BUSPRIVC IC3PUBC IC3PRIVC PLL3PUBC PLL3PRIVC MSIPUBC MSIPRIVC DCMIPPLPENC 2

0
0

0
0
0
0
0
0

SYSPRIVC IC2PUBC IC2PRIVC PLL2PUBC PLL2PRIVC LSEPUBC LSEPRIVC LTDCLPENC 1

0
0

0
0
0
0
0

MODPRIVC IC1PUBC IC1PRIVC PLL1PUBC PLL1PRIVC LSIPUBC LSIPRIVC Res. 0

RM0486
 Offset

0x17D0
0x17C4

0x17C8
0x17C0
0x17BC

0x17CC
RM0486

Reserved
Reserved

Reset value
Reset value

Reset value
Reset value
Register name

RCC_PUBCFGCR5
RCC_PUBCFGCR4
RCC_PUBCFGCR3

RCC_PRIVCFGCR4
Res. Res. Res. Res. 31
Res. Res. Res. Res. 30
Res. Res. Res. Res. 29
Res. Res. Res. Res. 28
Res. Res. Res. Res. 27
Res. Res. Res. Res. 26
Res. Res. Res. Res. 25
Res. Res. Res. Res. 24
Res. Res. Res. Res. 23
Res. Res. Res. Res. 22
Res. Res. Res. Res. 21
Res. Res. Res. Res. 20
Res. Res. Res. Res. 19

RM0486 Rev 2
Res. Res. Res. Res. 18
Res. Res. Res. Res. 17
Res. Res. Res. Res. 16
Res. Res. Res. Res. 15
Reserved
Reserved

Res. Res. Res. Res. 14

0
0

Res. NOCPUBC NOCPRIVC Res. 13

0
0

Res. APB5PUBC APB5PRIVC Res. 12

0
0
0

VENCRAMPUBC APB4PUBC APB4PRIVC Res. 11

0
0
0

CACHEAXIRAMPUBC APB3PUBC APB3PRIVC Res. 10

0
0
0

FLEXRAMPUBC APB2PUBC APB2PRIVC Res. 9

Table 78. RCC register map and reset values (continued)

0
0
0

AXISRAM2PUBC APB1PUBC APB1PRIVC Res. 8

0
0
0

AXISRAM1PUBC AHB5PUBC AHB5PRIVC Res. 7

0
0
0

BKPSRAMPUBC AHB4PUBC AHB4PRIVC Res. 6

0
0
0
0

AHBSRAM2PUBC AHB3PUBC AHB3PRIVC RSTPUBC 5

0
0
0
0

AHBSRAM1PUBC AHB2PUBC AHB2PRIVC INTPUBC 4

0
0
0
0

AXISRAM6PUBC AHB1PUBC AHB1PRIVC PERPUBC 3

0
0
0
0

AXISRAM5PUBC AHBMPUBC AHBMPRIVC BUSPUBC 2

0
0
0
0

AXISRAM4PUBC ACLKNCPUBC ACLKNCPRIVC SYSPUBC 1

0
0
0
0

AXISRAM3PUBC ACLKNPUBC ACLKNPRIVC MODPUBC 0

Reset and clock control (RCC)

779/4691
779
General-purpose I/Os (GPIO) RM0486

15 General-purpose I/Os (GPIO)

15.1 Introduction
Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, and GPIOx_PUPDR), two 32-bit data registers
(GPIOx_IDR and GPIOx_ODR), a 16-bit reset register (GPIOx_BRR), and a 32-bit set/reset
register (GPIOx_BSRR).
In addition, all GPIOs have a 32-bit locking register (GPIOx_LCKR), two couples of 32-bit
advanced configuration registers (GPIOx_DELAYRL/H, GPIOx_ADVCFGRL/H), and two
32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL).
Access to each general-purpose I/O configuration bit can be restricted to secure-only and/or
privileged-only.

15.2 GPIO main features

• Multiple choice of configurations per I/O port:
– Input configuration in floating, pull-up/down, or analog state
– Analog configuration (output buffer and Schmitt trigger input disabled)
– Output configuration, or alternate function configuration, in push-pull or open drain
state, with pull-up or pull-down activated
• Data present on the I/O pin sampled to the input data register GPIOx_IDR
(input configuration) or to the peripheral (alternate function configuration)
• Output buffer on the I/O pin driven by the output data register GPIOx_ODR
(output configuration) or by the peripheral (alternate function configuration)
• I/O data output atomic read/modify through GPIOx_ BSRR and GPIOx_BRR
• Speed selection for each I/O (GPIOx_OSPEEDR)
• Lock mechanism (GPIOx_LCKR) to selectively freeze the I/O port configurations
• Highly-flexible pin multiplexing, enabling the use of I/O pins as GPIOs, or as one of
several possible peripheral functions
• Programmable delay to the input or the output path (GPIOx_DELAYR)
• Double edge selection, clock inversion, and optional retime (GPIOx_ADVCFGR)
• Possibility to restrict each I/O control to secure-only and/or privileged-only

15.3 GPIO functional description

The specific hardware characteristics of each I/O port are detailed in the datasheet.
Each port bit of the GPIO ports can be individually configured by software in several modes:
• input floating
• input pull-up
• input-pull-down
• analog
• output open-drain with pull-up or pull-down capability

780/4691 RM0486 Rev 2

RM0486 General-purpose I/Os (GPIO)

• output push-pull with pull-up or pull-down capability

• alternate function push-pull with pull-up or pull-down capability
• alternate function open-drain with pull-up or pull-down capability
Each I/O port bit is freely programmable, however the I/O port registers must be accessed
as 32-bit words, half-words, or bytes. GPIOx_BSRR and GPIOx_BRR allow atomic
read/modify accesses to any of GPIOx_ODR. In this way, there is no risk of IRQ occurring
between the read and the modify access.
Figure 65 shows the basic structure of a standard I/O port bit.

Figure 65. Basic structure of an I/O port bit

Analog Input driver

To on-chip
peripheral Alternate function input

on/off
Input data

V
VDDIOx DDIOx
register

Read

pull-up
Trigger on/off Protection diode

I/O pin
Bit set/reset
registers

pull-down
Write VDDIOx Output driver
Output data

on/off Protection diode

register

Output P-MOS
control VSS
VSS
Read/write N-MOS

VSS Push-pull
From on-chip Alternate function output open-drain
peripheral or disabled
MSv71156V1

Table 79 gives the possible port bit configurations.

Table 79. Port x bit configurations

Port x bit configurations
I/O configuration(1)
MODEx[1:0] OTx OSPEEDx[1:0] PUPDx[1:0]

0 0 PP
0 1 GP output PP + PU
0
1 0 PP + PD
1 1 Reserved (GP output PP)
01 SPEED[1:0]
0 0 OD
GP output
0 1 OD + PU
1 (open drain)
1 0 OD + PD
1 1 Reserved (GP output OD)

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Table 79. Port x bit configurations (continued)

Port x bit configurations
I/O configuration(1)
MODEx[1:0] OTx OSPEEDx[1:0] PUPDx[1:0]

0 0 PP
0 1 AF PP + PU
0
1 0 PP + PD
1 1 Reserved (AF PP)
10 SPEED[1:0]
0 0 OD
0 1 AF (open drain) OD + PU
1
1 0 OD + PD
1 1 Reserved (AF OD)
x x x 0 0 Floating
x x x 0 1 Input PU
00
x x x 1 0 PD
x x x 1 1 Reserved (input floating)
x x x 0 0 Analog
x x x 0 1 Analog
11 Input/output
x x x 1 0 Analog + PD
x x x 1 1 Analog
1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate function.

15.3.1 General-purpose I/O (GPIO)

During and just after reset, AFs (alternate functions) are not active, and most of the I/O ports
are configured in analog mode, as defined through GPIOx_MODER register.
The debug pins are in AF pull-up/pull-down after reset:
• PA15: JTDI in pull-up
• PA14: JTCK/SWCLK in pull-down
• PA13: JTMS/SWDIO in pull-up
• PB4: NJTRST in pull-up
• PB5: JTDO/TRACESWO in floating state no pull-up/pull-down
When the pin is configured as output, the value written to GPIOx_ODR is output on the I/O
pin. The output driver can be used in push-pull mode or open-drain mode (only the low level
is driven, high level is Hi-Z).
GPIOx_IDR captures the data present on the I/O pin at every AHB clock cycle.
All GPIO pins have weak internal pull-up and pull-down resistors, that can be activated or
not, depending on the value in GPIOx_PUPDR.

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15.3.2 I/O pin AF multiplexer and mapping

The device I/O pins are connected to on-board peripherals/modules through a multiplexer
used to connect only one peripheral AF to an I/O pin at a time. There is no conflict between
peripherals available on the same I/O pin.
Each I/O pin has a multiplexer with up to 16 AF inputs (AF0 to AF15), which can be
configured through GPIOx_AFRL (for pins 0 to 7) and GPIOx_AFRH (for pins 8 to 15):
• During and just after reset, AFs are not active and most of the I/O ports are configured
in analog mode, as defined through GPIOx_MODER. When one AF is active, AF0 is
selected by default.
• Specific AF assignments for each I/O pin are detailed in the device datasheet.
This flexible I/O multiplexing architecture is used to optimize the number of peripherals
available in smaller packages.
To use an I/O in a given configuration, the user must proceed as follows:
• Debug function: after each device reset, these pins are assigned as AF pins
immediately usable by the debugger host.
• GPIO modes: the desired I/O is configured as output, input, or analog
in GPIOx_MODER.
• Peripheral AF:
– For a given peripheral function, the ‘Alternate functions’ table in the datasheet
helps to identify the AF to use with a given I/O. One of GPIOx_AFRL or
GPIOx_AFRH must be used.
– Configure the desired I/O as an AF in GPIOx_MODER. Select the type,
pull-up/pull-down, and output speed via GPIOx_OTYPER, GPIOx_PUPDR, and
GPIOx_OSPEEDR respectively.
• Cortex®-M55 alternate function (EVENTOUT)
– The output EVENTOUT signal can be used by configuring the I/O pin to output at
AF15. An event can be signaled through the configured pin after executing SEV
instruction.
– EVENTOUT signal can be used internally as a trigger for some peripherals (see
Section 17: Peripherals interconnect matrix)
• Additional functions:
– The additional functions listed in the datasheet give the peripheral functions that
directly select/enable its allocated I/O port(s). Typical peripherals are RTC/TAMP,
PWR (WKUPx pins), or RCC (oscillator pins). These functions have priority over
the configuration in standard GPIO registers.
– For ADCs, configure the desired I/O in analog mode in GPIOx_MODER, and
configure the required function in ADC registers.

15.3.3 I/O port control registers

Each GPIO port has four 32-bit memory-mapped control registers to configure up to 16 I/Os:
• GPIOx_MODER is used to select the I/O mode (input, output, AF, analog).
• GPIOx_OTYPER and GPIOx_OSPEEDR are respectively used to select the output
type (push-pull or open-drain) and the speed.
• GPIOx_PUPDR is used to select the pull-up/pull-down whatever the I/O direction.

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15.3.4 I/O port data registers

Each GPIO port has two 16-bit memory-mapped data registers: GPIOx_ODR. These
read/writable register store the data to be output per I/O. Data input through each I/O are
stored into read-only GPIOx_IDR.

15.3.5 I/O data bitwise handling

GPIOx_BSRR is a 32-bit register that allows the application to set/reset each individual bit
in GPIOx_ODR). GPIOx_BSRR has twice the size of GPIOx_ODR.
To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BS(i) and BR(i).
When written to 1, BS(i) sets the corresponding ODR(i). When written to 1, BR(i) resets the
corresponding ODR(i).
Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit
in GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set
action takes priority.
Using GPIOx_BSRR to change the values of individual bits in GPIOx_ODR is a one-shot
effect that does not lock GPIOx_ODR bits: these bits can always be accessed directly.
GPIOx_BSRR provides a way of performing atomic bitwise handling.
The software does not need to disable interrupts when programming GPIOx_ODR at bit
level: one or more bits can be modified in a single atomic AHB write access.

15.3.6 GPIO locking mechanism

GPIO control registers can be frozen by applying a specific write sequence
to GPIOx_LCKR. Indeed, each GPIOx_LCKR bit freezes the corresponding bit in the IO
ports control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
GPIOx_PUPDR, GPIOx_DELAYRL/H, GPIOx_ADVCFGR, and GPIOx_AFRL/H).
To write GPIOx_LCKR, a specific write/read sequence must be applied. When the right lock
sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used to lock the
configuration of the I/Os (during the write sequence the LCKR[15:0] value must be the
same, during the write sequence, only the IOs for which LCKR[15:0] stays to 1 for all the
specific write sequence are locked; other IOs configuration are not (lock sequence aborted).
When the lock sequence is applied to a port bit, the value of the port bit can no longer be
modified until a next device or peripheral reset. Each GPIOx_LCKR bit freezes the
corresponding bit in the control registers (GPIOx_MODER, GPIOx_OTYPER,
GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_DELAYRL/H, GPIOx_ADVCFGR, and
GPIOx_AFRL/H).
The LOCK sequence can be performed only using a word (32-bit long) access to
GPIOx_LCKR, because GPIOx_LCKR bit 16 must be set at the same time as the [15:0] bits.
Note: A lock sequence aborts in the event of an AHB bus error (see Section 15.1), or insufficient
access rights (see Section 15.3.16).
A lock sequence automatically suspends when accessing a different register from
GPIOx_LCKR. It resumes with the next access to GPIOx_LCKR.

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15.3.7 I/O AF input/output

Two registers are provided to select one of the AF inputs/outputs available for each I/O:
GPIOx_AFRL and GPIOx_AFRH. With these registers, the user can connect an AF to some
other pin, as required by the application.
A number of possible peripheral functions are multiplexed on each GPIO using these
registers. The application can select any one of the possible functions for each I/O. As the
AF selection signal is common to the AF input and output, a single channel is selected for
the AF input/output of a given I/O.
To know which functions are multiplexed on each GPIO pin, refer to the datasheet.

15.3.8 External interrupt/wake-up lines

All ports have external interrupt capability. To use external interrupt lines, the ports can be
configured in input, output, or AF mode (the ports must not be configured in analog mode).
Refer to Section 25: Extended interrupts and event controller (EXTI) for more details.

15.3.9 Input configuration

When the I/O port is programmed as input:
• the output buffer is disabled
• the Schmitt trigger input is activated
• the pull-up and pull-down resistors are activated, depending on the value in
GPIOx_PUPDR.
• data present on the I/O pin are sampled into the input data register every AHB clock
cycle
• a read access to the input data register provides the I/O state
Figure 66 shows the input configuration of the I/O port bit.

Figure 66. Input floating/pull-up/pull-down configurations

on/off
Input data

V
VDDIOx DDIOx
register

Read
pull-up

Trigger on/off Protection diode

Input driver
Bit set/reset

I/O pin
registers

pull-down

Write
Output data

on/off Protection diode

register

VSS
Output driver VSS
Read/write
MSv71157V1

15.3.10 Output configuration

When the I/O port is programmed as output:
• The output buffer is enabled:
– open-drain mode: a 0 in the output register activates the N-MOS, whereas a 1 in
the output register leaves the port in Hi-Z (P-MOS never activated).
– push-pull mode: a 0 in the output register activates the N-MOS, whereas a 1 in the
output register activates the P-MOS.

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• The Schmitt trigger input is activated.

• The pull-up and pull-down resistors are activated depending on the value in
GPIOx_PUPDR.
• Data present on the I/O pin are sampled into the input data register every AHB clock
cycle.
• A read access to the input data register gets the I/O state.
• A read access to the output data register gets the last written value.
Figure 67 shows the output configuration of the I/O port bit.

Figure 67. Output configuration

Input driver
on
Input data

V
VDDIOx DDIOx
register

Read

pull-up
Trigger on/off Protection diode

I/O pin
Bit set/reset

pull-down
registers

Write VDDIOx Output driver

on/off Protection diode
Output data
register

Output P-MOS
control VSS
VSS
N-MOS
Read/write
VSS Push-pull or
open-drain
MSv71158V1

15.3.11 AF configuration
When the I/O port is programmed as AF:
• the output buffer can be configured in open-drain or push-pull mode
• the output buffer is driven by the signals coming from the peripheral (transmitter enable
and data)
• the Schmitt trigger input is activated
• the weak pull-up and pull-down resistors are activated or not, depending on the value
in GPIOx_PUPDR
• data present on the I/O pin are sampled into the input data register every AHB clock
cycle
• aread access to the input data register gets the I/O state.

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Figure 68 shows the AF configuration of the I/O port bit.

Figure 68. AF configuration

To on-chip Alternate function input
Input driver
peripheral
on

Input data
V
VDDIOx DDIOx

register
Read

pull-up
Trigger on/off Protection diode

I/O pin
Bit set/reset
registers

pull-down
Write VDDIOx Output driver

Output data
on/off Protection diode

register
Output P-MOS
control VSS
VSS
Read/write N-MOS

From on-chip Alternate function output VSS Push-pull or

open-drain
peripheral
MSv71159V1

15.3.12 Analog configuration

When the I/O port is programmed as analog configuration:
• The output buffer is disabled.
• The Schmitt trigger input is deactivated, providing zero consumption for every analog
value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).
• The weak pull-up resistor is disabled by hardware. The weak pull-down resistor is
activated or not, depending on the value in GPIOx_PUPDR.
• Read access to the input data register gets the value 0.
Figure 69 shows the programmable, analog-input configuration of the I/O port bits.

Figure 69. Programmable analog configuration

To on-chip Analog Input driver

peripheral
off
Input data

VDDIOx
register

Read

Trigger Protection diode

Bit set/reset

I/O pin
registers

pull-down

Write
Output driver
Output data

on/off
register

Protection diode

VSS
VSS
Read/write
Analog
From on-chip peripheral
MSv71160V1

ADC analog configuration

The ADC voltage is 1.8 V. Refer to the product datasheet for more details on the allowed
voltage on ADC input pins.

Warning: Permanent damage to the ADC can occur if the voltage on

input pins exceeds 1.8 V.

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15.3.13 Using HSE or LSE oscillator pins as GPIOs

When the HSE or LSE oscillator is switched off (default state after reset), the related
oscillator pins can be used as normal GPIOs, but only in input mode (output mode is not
supported).
When the HSE or LSE oscillator is switched on (HSEON or LSEON set in RCC_CSR), the
oscillator takes control of its associated pins, and the GPIO configuration of these pins has
no effect.
When the oscillator is configured in a user external clock mode, only the pin is reserved for
clock input (OSC_OUT or OSC32_OUT pins can still be used, in input mode only).

15.3.14 Using GPIO pins in VSW supply domain

The functionality of PC13, PC14, PC15, and PQ7 GPIOs is lost when the core supply
domain is powered off (the device enters Standby mode). If their GPIO configuration is not
bypassed by the RTC/TAMP configuration or by the RCC (LSE), these pins are set in analog
input mode.
For details about I/O control by the RTC, refer to Section 61.3: RTC functional description.

15.3.15 Advanced I/O configurations

I/O compensation cell
The I/O commutation slew rate (tfall/trise) can be adapted by software depending on process,
voltage, and temperature conditions, to reduce the I/O noise on the power supply. Refer to
Section 16: System configuration controller (SYSCFG) for more details.

Input/output path configurable delay

A delay programmed in GPIOx_DELAYRL/H can be applied to either input or output path,
based on DLYPATH in GPIOx_ADVCFGRL/R.

Input/output data double edge selection

Input and output data can be managed as single- or double-edge, according to DE in
GPIOx_ADVCFGRL/R.
Input/output data retiming
When RET is set in GPIOx_ADVCFGRL/R, input and output data are retimed to either rising
or falling clock edge, depending upon INVCLK value.

15.3.16 I/O pin isolation using TrustZone

As TrustZone-aware peripheral, each I/O pin of GPIO port x can be individually configured
as secure through GPIOx_SECCFGR. After reset, all GPIO ports are secure.
The I/Os connected to peripheral functions can be conditioned by the peripheral security
configuration:
• Peripherals for which the I/O pin selection is done through GPIOx_AFRL/H
If the peripheral is configured as secure, it cannot be connected to a nonsecure I/O pin.
If this is not respected, input data to the secure peripheral are forced to 0 (I/O input pin
value ignored), and the output pin value is forced to 0, thus avoiding any secure

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information leak through nonsecure I/Os. TrustZone-aware logic around GPIO ports is
summarized in Table 80.
• Peripherals (like ADC) with embedded analog functions that directly select/enable its
allocated I/O ports using analog switches
If the I/O is secure, this analog switch cannot be controlled by a nonsecure peripheral.
If the peripheral is configured as nonsecure and the I/O is secure, the switch remains
open. This prevents the redirection of secure data to a nonsecure peripheral or I/O
through analog path. Refer to Section 3: System security for the list of peripherals
using this security.
• The list of I/Os without a hardware protection linked to TrustZone is given in Section 3:
System security. More specifically, the listed signals (input and/or outputs) are not
blocked when the I/O is set as secure, and the associated peripheral is non secure. For
each of these listed I/Os, a secure application must decide if a potential effect on data
integrity or confidentiality is critical or not.
Refer to the pins definitions table in the datasheet for more information about AFs and
additional functions mapping.

Table 80. Secure AF between peripherals and allocated I/Os

Security configuration AF logic
Comment
Peripheral Allocated I/O pin Input Output

Secure -
Secure I/O data Peripheral data
Nonsecure Out of reset configuration
Secure Zero Zero
Nonsecure -
Nonsecure I/O data Peripheral data

Table 81 gives a summary of the I/O port y secured bits, following the setting of SECy
in GPIOx_SECCFGR. The following is valid for each register in the table:
• When a bit is secured, read/write operations are only allowed by a secure access.
Non-secure read or write accesses on secured bits are RAZ/WI, with no illegal access
event generated.
• When a bit is nonsecure, there is no TrustZone restriction. Read/write operations are
allowed by both secure and nonsecure accesses.

Table 81. GPIO secured bits

Secured bitfield(s) Register name Nonsecure access on secure bits

MODEy[1:0] GPIOx_MODER
OTy GPIOx_OTYPER
OSPEEDy[1:0] GPIOx_OSPEEDR
PUPDy[1:0] GPIOx_PUPDR RAZ/WI
IDy GPIOx_IDR
ODy GPIOx_ODR
BSy and BRy GPIOx_BSRR

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Table 81. GPIO secured bits (continued)

Secured bitfield(s) Register name Nonsecure access on secure bits

BRy GPIOx_BRR
LCKy GPIOx_LCKR
GPIOx_AFRH
AFSELy[3:0]
GPIOx_AFRL
RAZ/WI
GPIOx_DELAYRL
DELAYy[3:0]
GPIOx_DELAYRH

RETy, INVCLKy, DEy, GPIOx_ADVCFGRL

and DLYPATHy GPIOx_ADVCFGRH

Note: GPIOx_SECCFGR is readable by any application. Each bit in this register is write-locked
until the next device reset, when setting the corresponding bit in GPIOx_RCFGLOCKR.

15.3.17 I/O pin isolation using privilege

As RIF-aware peripheral, each I/O pin of GPIO port x can be individually configured as
privileged through GPIOx_PRIVCFGR. After reset, all GPIO registers can be read and
written by privileged and unprivileged accesses, if security is enough and the CPU is
allowed.
Table 81 gives a summary of the I/O port y protected bits, following the setting of PRIVy
in GPIOx_PRIVCFGR. The following is valid for each register in the table:
• When a bit is privileged, read/write operations are only allowed by a privileged access.
Unprivileged read or write accesses on privileged bits are RAZ/WI, with no illegal
access event generated.
• When a bit is unprivileged, there is no privilege restriction. Read and write operations
are allowed by both privileged and unprivileged accesses.
Note: GPIOx_PRIVCFGR is readable by any application, writable by only privileged applications.
Each bit in GPIOx_PRIVCFGR is write locked until next device reset, when setting the
corresponding bit in GPIOx_RCFGLOCKR.

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15.4 GPIO registers

GPIO registers are accessible through 32-bit word, half-word, or byte single access.
Double-word and instruction fetch accesses trigger an AHB bus error. Byte or half-word
writes to GPIOx_LCKR are silently ignored (no bus error).

15.4.1 GPIO port x mode register (GPIOx_MODER) (x = A to H, N to Q)

Address offset:0x00
Reset value: Port A: 0xABFF EFFF
Reset value: Port B: 0xFFFF FAFF
Reset value: 0xFFFF FFFF (for the other ports)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODE15[1:0] MODE14[1:0] MODE13[1:0] MODE12[1:0] MODE11[1:0] MODE10[1:0] MODE9[1:0] MODE8[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODE7[1:0] MODE6[1:0] MODE5[1:0] MODE4[1:0] MODE3[1:0] MODE2[1:0] MODE1[1:0] MODE0[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MODEy[1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O mode.
00: General-purpose input mode
01: General-purpose output mode
10: Alternate function mode (refer to device datasheet for available options)
11: Analog mode (reset state)
Note: Each bitfield is reserved and must be kept to reset value when the corresponding I/O is
not available on the selected package.
Successful read or write to MODEy must be secure if SECy = 1 in GPIOx_SECCFGR, and
must be privileged if PRIVy = 1 in GPIOx_PRIVCFGR.

15.4.2 GPIO port x output type register (GPIOx_OTYPER)

(x =A to H, N to Q)
Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15 OT14 OT13 OT12 OT11 OT10 OT9 OT8 OT7 OT6 OT5 OT4 OT3 OT2 OT1 OT0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

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Bits 15:0 OTy: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O output type.
0: Output push-pull (reset state)
1: Output open-drain
Note: Each bit is reserved and must be kept to reset value when the corresponding I/O is not
available on the selected package.
Successful read or write to OTy must be secure if SECy = 1 in GPIOx_SECCFGR, and must
be privileged if PRIVy = 1 in GPIOx_PRIVCFGR.

15.4.3 GPIO port x output speed register (GPIOx_OSPEEDR)

(x =A to H, N to Q)
Address offset: 0x08
Reset value: Port A: 0x0C00 0000
Reset value: Port B: 0x0000 0C00
Reset value: 0x0000 0000 (for the other ports)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEED15[1:0] OSPEED14[1:0] OSPEED13[1:0] OSPEED12[1:0] OSPEED11[1:0] OSPEED10[1:0] OSPEED9[1:0] OSPEED8[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEED7[1:0] OSPEED6[1:0] OSPEED5[1:0] OSPEED4[1:0] OSPEED3[1:0] OSPEED2[1:0] OSPEED1[1:0] OSPEED0[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 OSPEEDy[1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O output speed.
00: Low speed
01: Medium speed
10: High speed
11: Very high speed
Note: Refer to the device datasheet for frequency specifications, power supply, and load
conditions for each speed. Each bitfield is reserved and must be kept to reset value
when the corresponding I/O is not available on the selected package.
Successful read or write to OSPEEDy must be secure if SECy = 1 in GPIOx_SECCFGR,
and must be privileged if PRIVy = 1 in GPIOx_PRIVCFGR.

15.4.4 GPIO port x pull-up/pull-down register (GPIOx_PUPDR)

(x= A to H, N to Q)
Address offset: 0x0C
Reset value: Port A: 0x6400 0000
Reset value: Port B: 0x0000 0100
Reset value: 0x0000 0000 (for the other ports)

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPD15[1:0] PUPD14[1:0] PUPD13[1:0] PUPD12[1:0] PUPD11[1:0] PUPD10[1:0] PUPD9[1:0] PUPD8[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPD7[1:0] PUPD6[1:0] PUPD5[1:0] PUPD4[1:0] PUPD3[1:0] PUPD2[1:0] PUPD1[1:0] PUPD0[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 PUPDy[1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O pull-up or pull-down
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved
Note: Each bitfield is reserved and must be kept to reset value when the corresponding I/O is
not available on the selected package.
Successful read or write to PUPDy must be secure if SECy = 1 in GPIOx_SECCFGR, and
must be privileged if PRIVy = 1 in GPIOx_PRIVCFGR.

15.4.5 GPIO port x input data register (GPIOx_IDR) (x = A to H, N to Q)

Address offset: 0x10
Reset value: 0x0000 XXXX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 IDy: Port x input data I/O pin y (y = 15 to 0)
These bits are read-only. They contain the input value of the corresponding I/O port.
Note: Each bit is reserved and must be kept to reset value when the corresponding I/O is not
available on the selected package.
Successful read to IDy must be secure if SECy = 1 in GPIOx_SECCFGR, and must be
privileged if PRIVy = 1 in GPIOx_PRIVCFGR.

15.4.6 GPIO port x output data register (GPIOx_ODR) (x = A to H, N to Q)

Address offset: 0x14
Reset value: 0x0000 0000

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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ODy: Port x output data I/O pin y (y = 15 to 0)
These bits can be read and written by software.
Note: For atomic bit set/reset, OD bits can be individually set and/or reset by writing
to GPIOx_BSRR or GPIOx_BRR. Each bit is reserved and must be kept to reset value
when the corresponding I/O is not available on the selected package.
Successful read or write to ODy must be secure if SECy= 1 in GPIOx_SECCFGR, and must
be privileged if PRIVy = 1 in GPIOx_PRIVCFGR.

15.4.7 GPIO port x bit set/reset register (GPIOx_BSRR) (x = A to H, N to Q)

Address offset: 0x18
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0
w w w w w w w w w w w w w w w w

Bits 31:16 BRy: Port x reset I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns 0x0000.
0: No action on the corresponding ODy bit
1: Resets the corresponding ODy bit
Note: If both BSy and BRy are set, BSy has priority.
Each bit is reserved and must be kept to reset value when the corresponding I/O is not
available on the selected package.
Successful write to BRy must be secure if SECy = 1 in GPIOx_SECCFGR, and must be
privileged if PRIVy = 1 in GPIOx_PRIVCFGR.
Bits 15:0 BSy: Port x set I/O pin y (y = 15 to 0)
These bits are write-only. A read to these bits returns 0x0000.
0: No action on the corresponding ODx bit
1: Sets the corresponding ODx bit
Note: Each bit is reserved and must be kept to reset value when the corresponding I/O is not
available on the selected package.
Successful write to BSy must be secure if SECy = 1 in GPIOx_SECCFGR, and must be
privileged if PRIVy = 1 in GPIOx_PRIVCFGR.

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RM0486 General-purpose I/Os (GPIO)

15.4.8 GPIO port x configuration lock register (GPIOx_LCKR)

(x = A to H, N to Q)
Address offset: 0x1C
Reset value: 0x0000 0000
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the GPIO configuration.
During the lock sequence, only bit port unlock can be changed.
Note: Only word access (32-bit long) is allowed during this locking sequence.
Byte or half-word writes are silently ignored (no bus error, no abort to lock sequence).
When the LOCK sequence has been applied on a port bit, the value of this port bit can no
longer be modified until the next MCU reset or peripheral reset. Each lock bit freezes a
specific configuration register (control and AF registers). See Section 15.3.6 for details.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 LCKK: Lock key
This bit can be read any time. It can only be modified using the lock key write sequence.
0: Port configuration lock key not active
1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU
reset or peripheral reset.
Lock key write sequence:
WR LCKR[16] = 1 + LCKR[15:0]
WR LCKR[16] = 0 + LCKR[15:0]
WR LCKR[16] = 1 + LCKR[15:0]
RD LCKR
RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active)
Note: Any error in the sequence aborts the lock. After the first lock sequence on any bit of the
port, any read access on LCKK bit returns 1 until the next device or peripheral reset.
Bits 15:0 LCKy: Port x lock I/O pin y (y = 15 to 0)
These bits are read/write but can only be written when LCKK = 0.
0: Port configuration not locked
1: Port configuration locked
Note: Each bit is reserved and must be kept to reset value when the corresponding I/O is not
available on the selected package.
Successful read or write to LCKy must be secure if SECy = 1 in GPIOx_SECCFGR, and
must be privileged if PRIVy = 1 in GPIOx_PRIVCFGR.

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15.4.9 GPIO port x AF low register (GPIOx_AFRL) (x = A to H, N to Q)

Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 AFSELy[3:0]: AF selection for port x I/O pin y (y = 7 to 0)

These bits are written by software to configure AF I/Os.
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15
Note: Each bitfield is reserved and must be kept to reset value when the corresponding I/O is
not available on the selected package.
Successful read or write to the bitfield AFSELy must be secure if SECy = 1
in GPIOx_SECCFGR, and must be privileged if PRIVy =1 in GPIOx_PRIVCFGR.

15.4.10 GPIO port x AF high register (GPIOx_AFRH) (x = A to H, N to Q)

Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15[3:0] AFSEL14[3:0] AFSEL13[3:0] AFSEL12[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11[3:0] AFSEL10[3:0] AFSEL9[3:0] AFSEL8[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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RM0486 General-purpose I/Os (GPIO)

Bits 31:0 AFSELy[3:0]: AF selection for port x I/O pin y (y = 15 to 8)

These bits are written by software to configure AF I/Os (see GPIOx_AFRL for details).
Note: Each bitfield is reserved and must be kept to reset value when the corresponding I/O is
not available on the selected package.
Successful read or write to the bitfield AFRHy must be secure if SECy = 1 in
GPIOx_SECCFGR, and must be privileged if PRIVy = 1 in GPIOx_PRIVCFGR.

15.4.11 GPIO port x bit reset register (GPIOx_BRR) (x = A to H, N to Q)

Address offset: 0x28
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0
w w w w w w w w w w w w w w w w

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 BRy: Port x reset IO pin y (y = 15 to 0)
These bits are write-only. A read to these bits returns 0x0000.
0: No action on the corresponding ODx bit
1: Reset the corresponding ODx bit
Note: Each bit is reserved and must be kept to reset value when the corresponding I/O is not
available on the selected package.
Successful write to BRy must be secure if SECy = 1 in GPIOx_SECCFGR, and must be
privileged if PRIVy = 1 in GPIOx_PRIVCFGR.

15.4.12 GPIO port x secure configuration register (GPIOx_SECCFGR)

(x = A to H, N to Q)
Address offset: 0x30
Reset value: Port A: 0x0000 FFFF
Reset value: Port B: 0x0000 FFFF
Reset value: Port C: 0x0000 FFFF
Reset value: Port D: 0x0000 FFFF
Reset value: Port E: 0x0000 FFFF
Reset value: Port F: 0x0000 FFFF
Reset value: Port G: 0x0000 FFFF
Reset value: Port H: 0x0000 03FF
Reset value: Port N: 0x0000 1FFF
Reset value: Port O: 0x0000 003F
Reset value: Port P: 0x0000 FFFF

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General-purpose I/Os (GPIO) RM0486

Reset value: Port Q: 0x0000 00FF

This register is used to configure a selected I/O as secure. Nonsecure or unprivileged writes
to this register are ignored, while any read is allowed.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15 SEC14 SEC13 SEC12 SEC11 SEC10 SEC9 SEC8 SEC7 SEC6 SEC5 SEC4 SEC3 SEC2 SEC1 SEC0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 SECy: I/O pin y of Port x security configuration (y = 15 to 0)
0: The I/O pin y is nonsecure. Secure access is also possible.
1: The I/O pin y is secure (see Table 81 for all corresponding secure bits).
Note: Each bit is reserved and must be kept to reset value when the corresponding I/O is not
available on the selected package.

15.4.13 GPIO port x privileged configuration register (GPIOx_PRIVCFGR)

(x = A to H, N to Q)
Address offset: 0x34
Reset value: Port A: 0x0000 FFFF
Reset value: Port B: 0x0000 FFFF
Reset value: Port C: 0x0000 FFFF
Reset value: Port D: 0x0000 FFFF
Reset value: Port E: 0x0000 FFFF
Reset value: Port F: 0x0000 FFFF
Reset value: Port G: 0x0000 FFFF
Reset value: Port H: 0x0000 03FF
Reset value: Port N: 0x0000 1FFF
Reset value: Port O: 0x0000 003F
Reset value: Port P: 0x0000 FFFF
Reset value: Port Q: 0x0000 00FF
Unprivileged writes to this register are ignored, while any read is allowed.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIV15 PRIV14 PRIV13 PRIV12 PRIV11 PRIV10 PRIV9 PRIV8 PRIV7 PRIV6 PRIV5 PRIV4 PRIV3 PRIV2 PRIV1 PRIV0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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RM0486 General-purpose I/Os (GPIO)

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PRIVy: I/O pin y of Port x privilege configuration (y = 15 to 0)
0: The I/O pin y is unprivileged. Privileged access is also possible.
1: The I/O pin y is privileged only (see Table 81 for all corresponding protected bits).
If the corresponding SECy = 1 in GPIOx_SECCFGR, PRIVy can only be written by a secure
privileged application.
Note: Each bit is reserved and must be kept to reset value when the corresponding I/O is not
available on the selected package.

15.4.14 GPIO port x resource configuration lock register

(GPIOx_RCFGLOCKR) (x = A to H, N to Q)
Address offset: 0x38
Reset value: 0x0000 0000
Secure privileged write access only. Write only by trusted domain CID. Any read access is
allowed on this register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RLOCK15

RLOCK14

RLOCK13

RLOCK12

RLOCK10
RLOCK11

RLOCK9

RLOCK8

RLOCK7

RLOCK6

RLOCK5

RLOCK4

RLOCK3

RLOCK2

RLOCK1

RLOCK0
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 RLOCKy: I/O pin y of port x resource lock (y = 15 to 0)
This bit is set to lock this I/O resource. It is cleared by default, and once set, it cannot be
cleared until the GPIOx is reset.
0: SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are writable.
1: Writes to SECy in GPIOx_SECCFGR and PRIVy in GPIOx_PRIVCFGR are ignored.
Note: Each bit is reserved and must be kept to reset value when the corresponding I/O is not
available on the selected package.

15.4.15 GPIO port x delay low register (GPIOx_DELAYRL)

(x = A to H, N to Q)
Address offset: 0x40
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLY7[3:0] DLY6[3:0] DLY5[3:0] DLY4[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLY3[3:0] DLY2[3:0] DLY1[3:0] DLY0[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:0 DLYy[3:0]: Port x IO pin y delay setup (y = 7 to 0)

Configure delay applied to the input (data IN from the pin) or the output path (data OUT to
the pin), depending on the value of the corresponding DLYPATHy in GPIOx_ADVCFGRL.
0000: No delay
0001: Delay 0.3 ns
0010: Delay 0.5 ns
0011: Delay 0.75 ns
0100: Delay 1.0 ns
0101: Delay 1.25 ns
0110: Delay 1.5 ns
0111: Delay 1.75 ns
1000: Delay 2.0 ns
1001: Delay 2.25 ns
1010: Delay 2.5 ns
1011: Delay 2.75 ns
1100: Delay 3.0 ns
1101: Delay 3.25 ns
1110 to 1111: Delay 3.25 ns (maximum)
Note: Each bitfield is reserved and must be kept to reset value when the corresponding I/O is
not available on the selected package.
Successful read or write to DELAYy must be secure if SECy = 1 in GPIOx_SECCFGR, and
must be privileged if PRIVy = 1 in GPIOx_PRIVCFGR.

15.4.16 GPIO port x delay high register (GPIOx_DELAYRH)

(x = A to H, N to Q)
Address offset: 0x44
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLY15[3:0] DLY14[3:0] DLY13[3:0] DLY12[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLY11[3:0] DLY10[3:0] DLY9[3:0] DLY8[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 DLYy[3:0]: Port x I/O pin y delay setup (y = 15 to 8)

Configure delay on input or output data prior to retiming (see GPIOx_DELAYRL for details).
Note: Each bitfield is reserved and must be kept to reset value when the corresponding I/O is
not available on the selected package.
Successful read or write to DELAYy must be secure if SECy = 1 in GPIOx_SECCFGR, and
must be privileged if PRIVy = 1 in GPIOx_PRIVCFGR.

15.4.17 GPIO port x advanced configuration low register (GPIOx_ADVCFGRL)

(x = A to H, N to Q)
Address offset: 0x48
Reset value: 0x0000 0000

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RM0486 General-purpose I/Os (GPIO)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INV DLY INV DLY INV DLY INV DLY
RET7 DE7 RET6 DE6 RET5 DE5 RET4 DE4
CLK7 PATH7 CLK6 PATH6 CLK5 PATH5 CLK4 PATH4
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INV DLY INV DLY INV DLY INV DLY
RET3 DE3 RET2 DE2 RET1 DE1 RET0 DE0
CLK3 PATH3 CLK2 PATH2 CLK1 PATH1 CLK0 PATH0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31, 27, 23, 19, RETy: Data retime selection (y = 7 to 0)

15, 11, 7, 3 0: Input and output data are not synchronized or retimed on clock edges.
1: Input and output data are retimed to rising or falling clock edge, depending upon value of
INVCLKy.
Bits 30, 26, 22, 18, INVCLKy: Clock inversion selection (y = 7 to 0)
14, 10, 6, 2 0: I/O clocks are not inverted. Input and output data are retimed to rising clock edge.
1: I/O clocks are inverted. Input and output data are retimed to falling clock edge
Bits 29, 25, 21, 17, DEy: Input/Output data double edge selection (cfg_double_edge) (y = 7 to 0)
13, 9, 5, 1 0: Input and output data is single-edge (changing on rising or falling clock edge, but not both)
1: Input and output data is double-edge (changing on both rising and falling clock edges)
Bits 28, 24, 20, 16, DLYPATHy: Clock inversion selection (y = 7 to 0)
12, 8, 4, 0 Controls which path contains the configurable delay, input or output
0: Delay is switched into the output path, while the input path is set as pass through.
1: Delay is switched into the input path, while the output path is set as pass through.

15.4.18 GPIO port x advanced configuration high register (GPIOx_ADVCFGRH)

(x =A to H, N to Q)
Address offset: 0x4C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLY DLY DLY DLY
INV INV INV INV
RET15 DE15 PATH RET14 DE14 PATH RET13 DE13 PATH RET12 DE12 PATH
CLK15 CLK14 CLK13 CLK12
15 14 13 12
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLY DLY DLY DLY
INV INV INV INV
RET11 DE11 PATH RET10 DE10 PATH RET9 DE9 PATH RET8 DE8 PATH
CLK11 CLK10 CLK9 CLK8
11 10 9 8
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31, 27, 23, 19, RETy: Data retime selection (y = 15 to 8)

15, 11, 7, 3 0: Input and output data are not synchronized or retimed on clock edges.
1: Input and output data are retimed to rising or falling clock edge, depending upon value of
INVCLKy.
Bits 30, 26, 22, 18, INVCLKy: Clock inversion selection (y = 15 to 8)
14, 10, 6, 2 0: I/O clocks are not inverted. Input and output data are retimed to rising clock edge.
1: I/O clocks are inverted. Input and output data are retimed to falling clock edge

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Bits 29, 25, 21, 17, DEy: Input/Output data double edge selection (cfg_double_edge) (y = 15 to 8)
13, 9, 5, 1 0: Input and output data is single-edge (changing on rising or falling clock edge, but not both)
1: Input and output data is double-edge (changing on both rising and falling clock edges)
Bits 28, 24, 20, 16, DLYPATHy: Clock inversion selection (y = 15 to 8)
12, 8, 4, 0 Controls which path contains the configurable delay, input or output
0: Delay is switched into the output path, while the input path is set as pass through.
1: Delay is switched into the input path, while the output path is set as pass through.

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RM0486 General-purpose I/Os (GPIO)

15.4.19 GPIO register map

Table 82. GPIO register map and reset values

Offset Register name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
MODE15

MODE14

MODE13

MODE12

MODE10
MODE11

MODE9

MODE8

MODE7

MODE6

MODE5

MODE4

MODE3

MODE2

MODE1

MODE0
GPIOx_MODER
[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]
(x = A to H, N to Q)
0x000
Reset value port A 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reset value port B 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1
Reset value others 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

GPIOx_OTYPER

OT15
OT14
OT13
OT12

OT10
OT11
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

OT9
OT8
OT7
OT6
OT5
OT4
OT3
OT2
OT1
OT0
0x004 (x = A to H, N to Q)

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OSPEED15

OSPEED14

OSPEED13

OSPEED12

OSPEED10
OSPEED11

OSPEED9

OSPEED8

OSPEED7

OSPEED6

OSPEED5

OSPEED4

OSPEED3

OSPEED2

OSPEED0
OSPEED
GPIOx_OSPEEDR

1[1:0]
[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]
(x = A to H, N to Q)
0x008
Reset value port A 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reset value port B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
Reset value others 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PUPD15

PUPD14

PUPD13

PUPD12

PUPD10
PUPD11

PUPD9

PUPD8

PUPD7

PUPD6

PUPD5

PUPD4

PUPD3

PUPD2

PUPD1

PUPD0
GPIOx_PUPDR
[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]

[1:0]
(x = A to H, N to Q)
0x00C
Reset value port A 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reset value port B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Reset value others 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_IDR
ID15
ID14
ID13
ID12

ID10
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ID11

ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0x010 (x = A to H, N to Q)
Reset value X X X X X X X X X X X X X X X X
GPIOx_ODR
OD15
OD14
OD13
OD12

OD10
OD11

OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

0x014 (x = A to H, N to Q)
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_BSRR
BR15
BR14
BR13
BR12

BR10

BS15
BS14
BS13
BS12

BS10
BR11

BS11
BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0

BS9
BS8
BS7
BS6
BS5
BS4
BS3
BS2
BS1
BS0
0x018 (x = A to H, N to Q)
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LCK15
LCK14
LCK13
LCK12

LCK10
LCK11

GPIOx_LCKR
LCKK

LCK9
LCK8
LCK7
LCK6
LCK5
LCK4
LCK3
LCK2
LCK1
LCK0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

0x01C (x = A to H, N to Q)

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_AFRL
AFRL7[3:0] AFRL6[3:0] AFRL5[3:0] AFRL4[3:0] AFRL3[3:0] AFRL2[3:0] AFRL1[3:0] AFRL0[3:0]
0x020 (x = A to H, N to Q)
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_AFRH
AFRH15[3:0] AFRH14[3:0] AFRH13[3:0] AFRH12[3:0] AFRH11[3:0] AFRH10[3:0] AFRH9[3:0] AFRH8[3:0]
0x024 (x = A to H, N to Q)
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_BRR
BR15
BR14
BR13
BR12

BR10
BR11
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0

0x028 (x = A to H, N to Q)
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x02C Reserved Reserved

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805
General-purpose I/Os (GPIO) RM0486

Table 82. GPIO register map and reset values (continued)

Offset Register name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
SEC15
SEC14
SEC13
SEC12

SEC10
SEC11

SEC9
SEC8
SEC7
SEC6
SEC5
SEC4
SEC3
SEC2
SEC1
SEC0
GPIOx_SECCFGR

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
(x = A to H, N to Q)

Reset value port A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Reset value port B 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reset value port C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reset value port D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reset value port E 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0x030
Reset value port F 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reset value port G 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reset value port H 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
Reset value port N 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Reset value port O 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
Reset value port P 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Reset value port Q 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

PRIV15
PRIV14
PRIV13
PRIV12

PRIV10
PRIV11

PRIV9
PRIV8
PRIV7
PRIV6
PRIV5
PRIV4
PRIV3
PRIV2
PRIV1
PRIV0
GPIOx_PRIVCFGR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
(x = A to H, N to Q)

Reset value port A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Reset value port B 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reset value port C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reset value port D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reset value port E 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0x034
Reset value port F 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reset value port G 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reset value port H 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
Reset value port N 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Reset value port O 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
Reset value port P 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Reset value port Q 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
RLOCK15
RLOCK14
RLOCK13
RLOCK12

RLOCK10
RLOCK11

RLOCK9
RLOCK8
RLOCK7
RLOCK6
RLOCK5
RLOCK4
RLOCK3
RLOCK2
RLOCK1
RLOCK0
GPIOx_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

RCFGLOCKR
0x038 (x = A to H, N to Q)

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x03C Reserved Reserved
GPIOx_DELAYRL
DLY7[3:0] DLY6[3:0] DLY5[3:0] DLY4[3:0] DLY3[3:0] DLY2[3:0] DLY1[3:0] DLY0[3:0]
0x040 (x = A to H, N to Q)
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIOx_DELAYRH
DLY15 [3:0] DLY14 [3:0] DLY13 [3:0] DLY12 [3:0] DLY11 [3:0] DLY10 [3:0] DLY9[3:0] DLY8[3:0]
0x044 (x = A to H, N to Q)
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DLYPATH7

DLYPATH6

DLYPATH5

DLYPATH4

DLYPATH3

DLYPATH2

DLYPATH1

DLYPATH0
INVCLK7

INVCLK6

INVCLK5

INVCLK4

INVCLK3

INVCLK2

INVCLK1

INVCLK0

GPIOx_ADVCFGRL
RET7

RET6

RET5

RET4

RET3

RET2

RET1

RET0
DE7

DE6

DE5

DE4

DE3

DE2

DE1

DE0

0x048 (x = A to H, N to Q)

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DLYPATH15

DLYPATH14

DLYPATH13

DLYPATH12

DLYPATH10
DLYPATH11

DLYPATH9

DLYPATH8
INVCLK15

INVCLK14

INVCLK13

INVCLK12

INVCLK10
INVCLK11

INVCLK9

INVCLK8
RET15

RET14

RET13

RET12

RET10
RET11

GPIOx_ADVCFGRH
RET9

RET8
DE15

DE14

DE13

DE12

DE10
DE11

DE9

DE8

0x04C (x = A to H, N to Q)

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

804/4691 RM0486 Rev 2

RM0486 General-purpose I/Os (GPIO)

Refer to Section 2.3 for the register boundary addresses.

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System configuration controller (SYSCFG) RM0486

16 System configuration controller (SYSCFG)

STM32N6x7xx devices feature a set of configuration registers. The SYSCFG manages:

• Cortex-M55 internal settings (such as TCM, CACHE, or vectors)
• interconnect, security, and memory settings
• compensation cells

16.0.1 I/O compensation cell

The I/O compensation cell generates an 8-bit value for the I/O buffer (4 bits for N-MOS and
4 bits for P-MOS), that depends on PVT operating conditions (process, voltage,
temperature).
These bits are used to control the current slew-rate and output impedance in the I/O buffer.
Five compensation cells are embedded: one for I/Os supplied by VDD, and four for I/Os
supplied by VDDIO2,VDDIO3,VDDIO4, and VDDIO5.
By default, the compensation cells are disabled, and a fixed code is applied to all I/Os.
When enabled, the compensation cell tracks the PVT, and the 4-bit APSRC and ANSRC
values are available in SYSCFG_xCCSR (with x = VDD, VDDIO2, VDDIO3, VDDIO4, or VDDIO5)
once the corresponding READY is set in SYSCFG_xCCSR.
If CS is cleared in SYSCFG_xCCCR, and READY is set, I/Os receive the APSRC and
ANSRC values that result from the compensation cell.
To optimize the trimming, these values can be adjusted using RAPSRC and RANSRC
in SYSCFG_xCCCR (see Figure 70).
To reduce the power consumption, it is recommended to copy the values from
SYSCFG_xCCSR to SYSCFG_xCCCR. When the result is ready, set CS and disable
the compensation cell.

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RM0486 System configuration controller (SYSCFG)

Figure 70. I/O compensation cell control overview

BSEC SYSCFG_xCCCR / SYSCFG_xCCSR registers

OTP
fuses APSRC[3:0] RAPSRC[3:0]
READY CS EN
ANSRC[3:0] RANSRC[3:0]
COMPCELL[3:0]

4 4+4 4+4
RESTRIM

EN

READY

I/O
4+4

4+4
Compensation Level
4+4

RAxSRC I/O I/O I/O I/O

measurement 10 shifter
AxSRC

I/O compensation cell Padring section X

MSv67474V1

16.1 SYSCFG registers

16.1.1 SYSCFG boot pin control register (SYSCFG_BOOTCR)

Address offset: 0x000
Reset value: 0x0000 0000
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOT1 BOOT0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
_PD _PD
rw rw

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 BOOT1_PD: BOOT1 pin pull-down disable
This is used to save power when BOOT1 pin is connected to VDD.
0:Pull-down enabled. The BOOT1 pin can be left open and takes a value of 0 if open.
1: Pull-down disabled. The BOOT1 pin must not be left open.
Bit 0 BOOT0_PD: BOOT0 pin pull-down disable
This is used to save power when BOOT0 pin is connected to VDD.
0: Pull-down enabled. The BOOT0 pin can be left open and takes a value of 0 if open.
1: Pull-down disabled. The BOOT0 pin must not be left open.

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System configuration controller (SYSCFG) RM0486

16.1.2 SYSCFG Cortex-M55 control register (SYSCFG_CM55CR)

Address offset: 0x004
Reset value: 0x0000 0000
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCKS
LOCKD LOCKS LOCKN LOCKS LOCKN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VTAIR
CAIC AU SMPU MPU SVTOR
CR
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FPU_IT_EN[5:0]
rw rw rw rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 LOCKDCAIC: Disable access to the instruction cache direct cache access registers DCAICLR
and DCAICRR.
Bit 20 LOCKSAU: Prevent changes to secure SAU memory regions already programmed.
Bit 19 LOCKNSMPU: Prevent changes to nonsecure MPU memory regions already programmed.
Bit 18 LOCKSMPU: Prevent changes to programmed secure MPU memory regions.
Bit 17 LOCKNSVTOR: Prevent changes to the nonsecure vector table base address.
Bit 16 LOCKSVTAIRCR: Prevent changes to:
- the secure vector table base address
- handling of secure interrupt priority
- BusFault, HardFault, and NMI security target settings in the processor
Bits 15:6 Reserved, must be kept at reset value.
Bits 5:0 FPU_IT_EN[5:0]: Enable FPU exception
bit 5: Input abnormal interrupt enable
bit 4: Inexact interrupt enable
bit 3: Underflow operation interrupt enable
bit 2: Overflow interrupt enable
bit 1: Divide-by-zero interrupt enable
bit 0: Invalid operation interrupt enable

16.1.3 SYSCFG Cortex-M55 TCM control register

(SYSCFG_CM55TCMCR)
Address offset: 0x008
Reset value: 0x0000 0087
Reset on pwr_vsw_rstn.

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RM0486 System configuration controller (SYSCFG)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTCM ITCMW
LOCKD LOCKI LOCKT
Res. Res. Res. Res. Res. Res. Res. WSDIS SDISA Res. Res. Res. Res.
TGU TGU CM
ABLE BLE
rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. CFGDTCMSZ[3:0] CFGITCMSZ[3:0]
rwo rwo rwo rwo rwo rwo rwo rwo

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 DTCMWSDISABLE: Disable wait-state applied by default on extended DTCM memory.
Bit 23 ITCMWSDISABLE: Disable wait-state applied by default on extended ITCM memory.
Bits 22:19 Reserved, must be kept at reset value.
Bit 18 LOCKDTGU: Disable writes to registers associated with the DTCM interface security gating.
Bit 17 LOCKITGU: Disable writes to registers associated with the ITCM interface security gating.
Bit 16 LOCKTCM: Disable writes to registers associated with the TCM region
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:4 CFGDTCMSZ[3:0]: Select DTCM memory size
0x8: 128 Kbytes (default value)
0x9: 256 Kbytes
Others: Reserved
Bits 3:0 CFGITCMSZ[3:0]: Select ITCM memory size
0x7: 64 Kbytes (default value)
0x8: 128 Kbytes
0x9: 256 Kbytes
Others: Reserved
Note: CFGDTCMSZ and CFGITCMSZ must be written in the same data access, because they
are write-once bitfields locked together. Writing only one of them blocks write-access to
the other up to the next power-on reset.

16.1.4 SYSCFG Cortex-CM55 memory RW margin register

(SYSCFG_CM55RWMCR)
Address offset: 0x00C
Reset value: 0x0000 1020
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BC2_C BC1_C RME_C BC2_T BC1_T RME_T
Res. Res. RM_CACHE[3:0] RM_TCM[3:0]
ACHE ACHE ACHE CM CM CM
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:14 Reserved, must be kept at reset value.

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System configuration controller (SYSCFG) RM0486

Bit 13 BC2_CACHE: Biasing level adjust input recommended for Vnom + 10%
Its setting gives a higher value of rise on VSS-core voltage to give enough head room for
retention.
Bit 12 BC1_CACHE: Biasing level adjust input recommended for Vnom.
Its setting gives a smaller value of rise on VSS-core voltage to give enough head room for
retention.
Bits 11:8 RM_CACHE[3:0]: External read/write (RW) margin inputs for caches memories
Bit 7 RME_CACHE: RW margin enable input for caches memories
0: Default RW margin settings
1: Use external pin RW margin setting
Bit 6 BC2_TCM: Biasing level adjust input recommended for Vnom + 10%
Its setting gives a higher value of rise on VSS-core voltage to give enough head room for
retention.
Bit 5 BC1_TCM: Biasing level adjust input recommended for Vnom
Its setting gives a smaller value of rise on VSS-core voltage to give enough head room for
retention.
Bits 4:1 RM_TCM[3:0]: External RW margin inputs for TCM memories
Bit 0 RME_TCM: RW margin enable input for TCM memories
0: Default RW margin settings
1: Use external pin RW margin setting

16.1.5 SYSCFG Cortex-M55 SVTOR control register

(SYSCFG_INITSVTORCR)
Address offset: 0x010
Reset value: 0x1800 0000
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SVTOR_ADDR[24:9]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SVTOR_ADDR[8:0] Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw rw rw rw rw rw

Bits 31:7 SVTOR_ADDR[24:0]: Secure vector table base address

Bits 6:0 Reserved, must be kept at reset value.

16.1.6 SYSCFG Cortex-M55 NSVTOR control register

(SYSCFG_INITNSVTORCR)
Address offset: 0x014
Reset value: 0x0800 0000
Reset by system reset.

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RM0486 System configuration controller (SYSCFG)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSVTOR_ADDR[24:9]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSVTOR_ADDR[8:0] Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw rw rw rw rw rw

Bits 31:7 NSVTOR_ADDR[24:0]: Nonsecure vector table base address

Bits 6:0 Reserved, must be kept at reset value.

16.1.7 SYSCFG Cortex-M55 reset type control register

(SYSCFG_CM55RSTCR)
Address offset: 0x018
Reset value: 0x0000 0000
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCKU LOCKU CORE_
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. P_NMI P_RST RESET
_EN _EN _TYPE
rw rw rw

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 LOCKUP_NMI_EN: Select action to perform on a lockup state on the core
0: Lockup state must be recovered from NVIC interrupt (default value)
1: Lockup generates a NMI on the core.
Bit 1 LOCKUP_RST_EN: Select action to perform on a lockup state on the core
0: Lockup state must be recovered from interrupt (default value)
1: Lockup requests a warm reset to the RCC.
Bit 0 CORE_RESET_TYPE: Select reset to apply on core upon SYSRESETREQ
0: Warm reset (default value)
1: Power-on reset

16.1.8 SYSCFG Cortex-M55 P-AHB write posting control register

(SYSCFG_CM55PAHBWPR)
Address offset: 0x01C
Reset value: 0x0000 0000
Reset by system reset.

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825
System configuration controller (SYSCFG) RM0486

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAHB_
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ERRO
R_ACK
rw

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 PAHB_ERROR_ACK: Error capture in write posting buffer
0: Error capture
1: Clean error

16.1.9 SYSCFG VENCRAM control register (SYSCFG_VENCRAMCR)

Address offset: 0x020
Reset value: 0x0000 0000
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VENCR
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
AM_EN
rw

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 VENCRAM_EN: VENCRAM allocation VENC if active, or to system (if VENC inactive)
0: VENCRAM reserved for the VENC
1: VENCRAM available for the system (VENC inactive)

16.1.10 SYSCFG potential tamper reset register

(SYSCFG_POTTAMPRSTCR)
Address offset: 0x024
Reset value: 0x0000 0000
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POTTA
MPER
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SETMA
SK
rw

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RM0486 System configuration controller (SYSCFG)

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 POTTAMPERSETMASK:
This bit can be set by software to mask PKA, SAES, CRYP, and HASH reset, in case
of potential tamper.
0: PKA, SAES, CRYP, and HASH reset in case of potential tamper
1: PKA, SAES, CRYP, and HASH not reset in case of potential tamper

16.1.11 SYSCFG NPUNIC QoS control register

(SYSCFG_NPUNICQOSCR)
Address offset: 0x028
Reset value: 0x0000 0000
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. CPUSS_AWQOS[3:0] CPUSS_ARQOS[3:0]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPU2_AWQOS[3:0] NPU2_ARQOS[3:0] NPU1_AWQOS[3:0] NPU1_ARQOS[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:20 CPUSS_AWQOS[3:0]: NPUNIC write QoS information for master port from CPUSS
Bits 19:16 CPUSS_ARQOS[3:0]: NPUNIC read QoS information for master port from CPUSS
Bits 15:12 NPU2_AWQOS[3:0]: NPUNIC write QoS information for NPU2 master port
Bits 11:8 NPU2_ARQOS[3:0]: NPUNIC read QoS information for NPU2 master port
Bits 7:4 NPU1_AWQOS[3:0]: NPUNIC write QoS information for NPU1 master port
Bits 3:0 NPU1_ARQOS[3:0]: NPUNIC read QoS information for NPU1 master port

16.1.12 SYSCFG AHB-AXI bridge early write response control

register (SYSCFG_ICNEWRCR)
Address offset: 0x034
Reset value: 0x0000 0000
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMM SDMM
USB2_ USB1_
C2_EA C1_EA
EARLY EARLY
RLY_W RLY_W
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. _WR_R _WR_R
R_RSP R_RSP
SP_EN SP_EN
_ENAB _ENAB
ABLE ABLE
LE LE
rw rw rw rw

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825
System configuration controller (SYSCFG) RM0486

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 USB2_EARLY_WR_RSP_ENABLE:
0: Early-write response disabled. The last AHB write data beat receives the AXI buffered
response for the complete AHB transaction.
1: Early-write response enabled. AHB-Lite write data beats receive an automatic OK
response from the AHB-to-AXI bridge, whatever the B-channel AXI response.
Bit 2 USB1_EARLY_WR_RSP_ENABLE:
0: Early-write response disabled. The last AHB write data beat receives the AXI buffered
response for the complete AHB transaction.
1: Early-write response enabled. AHB-Lite write data beats receive an automatic OK
response from the AHB-to-AXI bridge, whatever the B-channel AXI response.
Bit 1 SDMMC2_EARLY_WR_RSP_ENABLE:
0: Early-write response disabled. The last AHB write data beat receives the AXI buffered
response for the complete AHB transaction.
1: Early-write response enabled. AHB-Lite write data beats receive an automatic OK
response from the AHB-to-AXI bridge, whatever the B-channel AXI response.
Bit 0 SDMMC1_EARLY_WR_RSP_ENABLE:
0: Early-write response disabled. The last AHB write data beat receives the AXI buffered
response for the complete AHB transaction.
1: Early-write response enabled. AHB-Lite write data beats receive an automatic OK
response from the AHB-to-AXI bridge, whatever the B-channel AXI response.

16.1.13 SYSCFG ICN clock gating control register (SYSCFG_ICNCGCR)

Address offset: 0x038
Reset value: 0x0000 0000
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_N CPU_N NPU_N
OC_C IC_CG OC_C
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
G_DIS _DISA G_DIS
ABLE BLE ABLE
rw rw rw

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 CPU_NOC_CG_DISABLE: CPU_NOC clock gating disable
0: CPU_NOC clock gating enabled (default value)
1: CPU_NOC clock gating disabled
Bit 1 CPU_NIC_CG_DISABLE: CPU_NIC clock gating disable
0: CPU_NIC clock gating enabled (default value)
1: CPU_NIC clock gating disabled
Bit 0 NPU_NOC_CG_DISABLE: NPU_NOC clock gating disable
0: NPU_NOC clock gating enabled (default value)
1: NPU_NOC clock gating disabled

814/4691 RM0486 Rev 2

RM0486 System configuration controller (SYSCFG)

16.1.14 SYSCFG VDDIOx compensation cell control register

(SYSCFG_VDDIOxCCCR)
Address offset: 0x044 + 0x8 * (x - 2), (x = 2 to 5)
Reset value: 0x0000 0078
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. CS EN RAPSRC[3:0] RANSRC[3:0]
rw rw rw rw rw rw rw rw rw rw

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 CS: Selects the code to be applied for the compensation cell of I/Os supplied by VDDIOx.
0: VDDIOx I/O code from the cell (available in the SYSCFG_VDDIOxCCSR)
1: VDDIOx I/O code from RANSRC[3:0] and RAPSRC[3:0] in this register
Note: CS = 0 is not taken into account until READY = 1. Whenever CS, RANSRC[3:0], and
RAPSRC[3:0] are used for I/O compensation when the compensation cell is not enabled
(EN = 0, which is the case after a reset).
Bit 8 EN: Enables the compensation cell of I/Os supplied by VDDIOx.
0: VDDIOx I/O compensation cell disabled
1: VDDIOx I/O compensation cell enabled
Note: The HSI oscillator must be enabled and ready (controlled in RCC) before EN can be
set to 1. The HSI oscillator can be disabled only if EN is set to 0.
Bits 7:4 RAPSRC[3:0]: These bits are written by software to define an I/O compensation code for
PMOS transistors. This code is applied to the I/O compensation cell when CS = 1.
Bits 3:0 RANSRC[3:0]: These bits are written by software to define an I/O compensation code for
NMOS transistors. This code is applied to the I/O compensation cell when the CS = 1.

16.1.15 SYSCFG VDDIOx compensation cell status register

(SYSCFG_VDDIOxCCSR)
Address offset: 0x048 + 0x8 * (x - 2), (x = 2 to 5)
Reset value: 0x0000 0000
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. READY APSRC[3:0] ANSRC[3:0]
r r r r r r r r r

Bits 31:9 Reserved, must be kept at reset value.

RM0486 Rev 2 815/4691

825
System configuration controller (SYSCFG) RM0486

Bit 8 READY: Provides the compensation cell status of I/Os supplied by VDDIOx
0: VDDIOx I/O compensation cell not ready
1: VDDIOx I/O compensation cell ready
Bits 7:4 APSRC[3:0]: This value is provided by the cell, and can be used by the CPU to compute
an I/O compensation cell code for PMOS transistors.
This code is applied to the I/O compensation cell when the CS = 0
in SYSCFG_VDDIOxCCCR, and READY = 1 in this register.
Bits 3:0 ANSRC[3:0]: This value is provided by the cell, and can be used by the CPU to compute
an I/O compensation cell code for NMOS transistors.
This code is applied to the I/O compensation cell when the CS = 0
in SYSCFG_VDDIOxCCCR, and READY = 1 in this register.

16.1.16 SYSCFG VDD compensation cell control register

(SYSCFG_VDDCCCR)
Address offset: 0x064
Reset value: 0x0000 0078
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. CS EN RAPSRC[3:0] RANSRC[3:0]
rw rw rw rw rw rw rw rw rw rw

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 CS: Selects the code to be applied for the compensation cell of I/Os supplied by VDD.
0: VDD I/O code from the cell (available in the SYSCFG_VDDCCSR)
1: VDD I/O code from RANSRC[3:0] and RAPSRC[3:0]
Note: CS = 0 is not taken into account until READY = 1. Whenever CS, RANSRC[3:0] and
RAPSRC[3:0] are used for I/O compensation when the compensation cell is not enabled
(EN = 0, which is the case after a reset).
Bit 8 EN: Enables the compensation cell of I/Os supplied by VDD.
0: VDD I/O compensation cell disabled
1: VDD I/O compensation cell enabled
Note: The HSI oscillator must be enabled and ready (controlled in RCC) before EN can be
set to 1. The HSI oscillator can be disabled only if EN is set to 0.
Bits 7:4 RAPSRC[3:0]: These bits are written by software to define an I/O compensation code for
PMOS transistors. This code is applied to the I/O compensation cell when CS = 1.
Bits 3:0 RANSRC[3:0]: These bits are written by software to define an I/O compensation code for
NMOS transistors. This code is applied to the I/O compensation cell when CS = 1.

816/4691 RM0486 Rev 2

RM0486 System configuration controller (SYSCFG)

16.1.17 SYSCFG VDD compensation cell status register

(SYSCFG_VDDCCSR)
Address offset: 0x068
Reset value: 0x0000 0000
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. READY APSRC[3:0] ANSRC[3:0]
r r r r r r r r r

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 READY: Provides the compensation cell status of I/Os supplied by VDD
0: VDD I/O compensation cell not ready
1: VDD I/O compensation cell ready
Bits 7:4 APSRC[3:0]: This value is provided by the cell, and can be used by the CPU to compute
an I/O compensation cell code for PMOS transistors.
This code is applied to the I/O compensation cell when CS = 0 in SYSCFG_VDDCCCR, and
READY = 1.
Bits 3:0 ANSRC[3:0]: This value is provided by the cell, and can be used by the CPU to compute
an I/O compensation cell code for NMOS transistors.
This code is applied to the I/O compensation cell when CS = 0 in SYSCFG_VDDCCCR, and
READY = 1.

16.1.18 SYSCFG control timer break register (SYSCFG_CBR)

Address offset: 0x06C
Reset value: 0x0000 0000
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CM55T CM55C BKPRA
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PVDEN Res. CM55L
CML ACHEL ML
rw rw rw rw rw

Bits 31:11 Reserved, must be kept at reset value.

RM0486 Rev 2 817/4691

825
System configuration controller (SYSCFG) RM0486

Bit 10 CM55TCML: Cortex-M55 TCM double ECC error lock

This bit is set by software and cleared only by a system reset. It can be used to enable and
lock the Cortex-M55 TCM double ECC error signal connection to TIM1/8/15/16/17 break
inputs.
0: Cortex-M55 TCM double ECC error signal disconnected from TIM1/8/15/16/17 break
inputs
1: Cortex-M55 TCM double ECC error signal connected to TIM1/8/15/16/17 break inputs
Bit 9 CM55CACHEL: Cortex-M55 cache double ECC error lock
This bit is set by software and cleared only by a system reset. It can be used to enable and
lock the Cortex-M55 cache double ECC error signal connection to TIM1/8/15/16/1break
inputs.
0: Cortex-M55 cache double ECC error signal disconnected from TIM1/8/15/16/17 break
inputs
1: Cortex-M55 cache double ECC error signal connected to TIM1/8/15/16/17 break inputs
Bit 8 BKPRAML: Backup SRAM double ECC error lock
This bit is set by software and cleared only by a system reset. It can be used to enable and
lock the backup SRAM double ECC error signal connection to TIM1/8/15/16/17 break inputs.
0: Backup SRAM double ECC error signal disconnected from TIM1/8/15/16/17 break inputs
1: Backup SRAM double ECC error signal connected to TIM1/8/15/16/17 break inputs
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 PVDEN: PVD lock enable
This bit is set by software and cleared only by a system reset. It can be used to enable and
lock the PVD connection to TIM1/8/15/16/17 break input, as well as the PVDE in PWR_CR2.
0: PVD interrupt disconnected from TIM1/8/15/16/17 break input. PVDE bits can be
programmed by the application.
1: PVD interrupt connected to TIM1/8/15/16/17 break input. PVDE and bits are read only.
Bit 1 Reserved, must be kept at reset value.
Bit 0 CM55L: CM55 lockup lock enable
This bit is set by software and cleared only by a system reset. It can be used to enable and
lock the Cortex-M55 lockup (HardFault) output connection to TIM1/8/15/16/17 break input.
0: Cortex-M55 lockup output disconnected from TIM1/8/15/16/17 break inputs
1: Cortex-M55 lockup output disconnected from TIM1/8/15/16/17 break inputs

16.1.19 SYSCFG DMA CID secure control register (SYSCFG_SEC_AIDCR)

Address offset: 0x070
Reset value: 0x0000 0001
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMACID_SEC[2:0]
rw rw rw

Bits 31:3 Reserved, must be kept at reset value.

818/4691 RM0486 Rev 2

RM0486 System configuration controller (SYSCFG)

Bits 2:0 DMACID_SEC[2:0]: Secure user accesses to the DMA present this programmed CID.

16.1.20 SYSCFG FMC retiming logic control register

(SYSCFG_FMC_RETIMECR)
Address offset: 0x074
Reset value: 0x0000 0000
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG_R CFG_R
SDFBC
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETIME ETIME
LK_180
_TX _RX
rw rw rw

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 SDFBCLK_180: Delay on feedback clock
0: No delay on the feedback clock
1: Half a cycle delay on the feedback clock
Bit 1 CFG_RETIME_TX: Retiming on Tx path
0: No retiming on Tx path
1: Retiming on Tx path
Bit 0 CFG_RETIME_RX: Retiming on Rx path
0: No retiming on Rx path
1: Retiming on Rx path

16.1.21 SYSCFG NPU RAM interleaving control register

(SYSCFG_NPU_ICNCR)
Address offset: 0x078
Reset value: 0x0000 0000
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTER
LEAVIN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
G_ACT
IVE
rw

Bits 31:1 Reserved, must be kept at reset value.

RM0486 Rev 2 819/4691

825
System configuration controller (SYSCFG) RM0486

Bit 0 INTERLEAVING_ACTIVE: Control interleaving on NPU RAMs

0: Interleaving disabled
1: Interleaving enabled

16.1.22 SYSCFG boot pin status register (SYSCFG_BOOTSR)

Address offset: 0x100
Reset value: 0x0000 0000
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BOOT1 BOOT0
r r

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 BOOT1: BOOT1 pin value
0: BOOT1 pin connected to VSS (or left open if BOOT1_PD = 0 in SYSCFG_BOOTCR)
1: BOOT1 pin connected to VDD
Bit 0 BOOT0: BOOT0 pin value
0: BOOT0 pin connected to VSS (or left open if BOOT0_PD = 0)
1: BOOT0 pin connected to VDD

16.1.23 SYSCFG AHB write posting address error register

(SYSCFG_AHBWP_ERROR_SR)
Address offset: 0x104
Reset value: 0x0000 0000
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAHB_ERROR_ADDR[31:16]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAHB_ERROR_ADDR[15:0]
r r r r r r r r r r r r r r r r

Bits 31:0 PAHB_ERROR_ADDR[31:0]: Reports address of the first error in P-AHB write-posting buffer

820/4691 RM0486 Rev 2

RM0486 System configuration controller (SYSCFG)

16.1.24 SYSCFG SMPS observable signals through HDP selection

configuration register (SYSCFG_SMPSHDPCR)
Address offset: 0x400
Reset value: 0x0000 0000
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SMPSHDPSEL[3:0]
rw rw rw rw

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 SMPSHDPSEL[3:0]:
0000: Standard run mode (no HDP)
1100: Analyze fsm mode analysis
1101: Analyze fsm mos analysis
1110: Analyze fsm rampe analysis
1111: Analyze fsm mode analysis
Others: Reserved

16.1.25 SYSCFG DMA CID nonsecure control register

(SYSCFG_SECPRIV_AIDCR)
Address offset: 0x800
Reset value: 0x0000 0001
Reset by system reset.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMACID_SECPRIV[2:0]
rw rw rw

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 DMACID_SECPRIV[2:0]: Secure privilege accesses to the DMA present this programmed
CID.

RM0486 Rev 2 821/4691

825
System configuration controller (SYSCFG) RM0486

16.1.26 SYSCFG device ID register (SYSCFG_DEVICEID)

Address offset: 0x0FF0
Reset value: 0xXXXX 6XXX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REV_ID[15:0]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. DEV_ID[11:0]
r r r r r r r r r r r r

Bits 31:16 REV_ID[15:0]: Silicon revision

0x1000: Revision A
0x2000: Revision B
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 DEV_ID[11:0]: Device identifier
0x486: STM32N6x7xx

16.1.27 SYSCFG register map

Table 83. SYSCFG register map and reset values

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11
Offset Register name

9
8
7
6
5
4
3
2
1
0
BOOT1
BOOT0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SYSCFG_BOOTCR
0x000

Reset value 0 0
LOCKSVTAIRCR
LOCKNSVTOR
LOCKNSMPU
LOCKDCAIC

LOCKSMPU
LOCKSAU
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

SYSCFG_CM55CR FPU_IT_EN[5:0]
0x004

Reset value 0 0 0 0 0 0 0 0 0 0 0 0
DTCMWSDISABLE
ITCMWSDISABLE

CFGDTCMSZ

CFGITCMSZ
LOCKDTGU
LOCKITGU
LOCKTCM

SYSCFG_
[3:0]

[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

0x008 CM55TCMCR

Reset value 0 0 0 0 0 1 0 0 0 0 1 1 1
RME_CACHE
BC2_CACHE
BC1_CACHE

RM_CACHE

RME_TCM
BC2_TCM
BC1_TCM

RM_TCM

SYSCFG_
[3:0]

[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

0x00C CM55RWMCR

Reset value 0 1 0 0 0 0 0 0 1 0 0 0 0 0
SYSCFG_
Res.
Res.
Res.
Res.
Res.
Res.
Res.

_INITSVTORCR
SVTOR_ADDR[24:0]
0x010
Reset value 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

822/4691 RM0486 Rev 2

 0x030
0x028
0x024
0x020
0x018
0x014

0x01C
Offset
RM0486

Reserved
SYSCFG_
SYSCFG_
SYSCFG_
SYSCFG_
SYSCFG_
SYSCFG_

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

CM55RSTCR

VENCRAMCR

NPUNICQOSCR
CM55PAHBWPR
_INITNSVTORCR

POTTAMPRSTCR
Register name

Res. Res. Res. Res. Res.

31
Res. Res. Res. Res. Res.
30
Res. Res. Res. Res. Res.
29
Res. Res. Res. Res. Res.
28
Res. Res. Res. Res. Res.
27
Res. Res. Res. Res. Res.
26
Res. Res. Res. Res. Res.
25
Res. Res. Res. Res. Res.
24
Res. Res. Res. Res.
23
Res. Res. Res. Res.
22
Res. Res. Res. Res.

[3:0]
21

AWQOS
CPUSS_
Res. Res. Res. Res.
20
Res. Res. Res. Res.
19

RM0486 Rev 2
Res. Res. Res. Res.
18
Res. Res. Res. Res.

[3:0]
17

ARQOS
CPUSS_
Res. Res. Res. Res.
16
NSVTOR_ADDR[24:0]

Res. Res. Res. Res.

15

Reserved
Res. Res. Res. Res.
14
Res. Res. Res. Res.

[3:0]
13

NPU2_
AWQOS
Res. Res. Res. Res.
12
Res. Res. Res. Res.
11
Res. Res. Res. Res.
10
Res. Res. Res. Res.

[3:0]
9

NPU2_
ARQOS
Res. Res. Res. Res.
Table 83. SYSCFG register map and reset values (continued)

8
Res. Res. Res. Res.
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

7
Res. Res. Res. Res. Res.
6
Res. Res. Res. Res. Res.

[3:0]
5

NPU1_
AWQOS
Res. Res. Res. Res. Res.
4
Res. Res. Res. Res. Res.
3
Res. Res. Res. LOCKUP_NMI_EN Res.
2
Res. Res. Res. LOCKUP_RST_EN Res.

[3:0]
1
NPU1_
ARQOS
POTTAMPERSETMASK VENCRAM_EN PAHB_ERROR_ACK CORE_RESET_TYPE Res.

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0 0 0
System configuration controller (SYSCFG)

823/4691
0

825
 0x070
0x068
0x064
0x040
0x038
0x034

0x06C
0x03C-

0x048 +
0x044 +
Offset

(x=2 to 5)
(x=2 to 5)

0x8*(x-2),
0x8*(x-2),

824/4691
Reserved

SYSCFG_
SYSCFG_
SYSCFG_
SYSCFG_

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
ICNEWRCR

SEC_AIDCR
VDDIOxCCSR
VDDIOxCCCR

SYSCFG_CBR
Register name

SYSCFG_ICNCGCR

SYSCFG_VDDCCSR
SYSCFG_VDDCCCR
Res. Res. Res. Res. Res. Res. Res. Res.
31
Res. Res. Res. Res. Res. Res. Res. Res.
30
Res. Res. Res. Res. Res. Res. Res. Res.
29
Res. Res. Res. Res. Res. Res. Res. Res.
28
Res. Res. Res. Res. Res. Res. Res. Res.
27
Res. Res. Res. Res. Res. Res. Res. Res.
26
Res. Res. Res. Res. Res. Res. Res. Res.
25
Res. Res. Res. Res. Res. Res. Res. Res.
System configuration controller (SYSCFG)

24
Res. Res. Res. Res. Res. Res. Res. Res.
23
Res. Res. Res. Res. Res. Res. Res. Res.
22
Res. Res. Res. Res. Res. Res. Res. Res.
21
Res. Res. Res. Res. Res. Res. Res. Res.
20
Res. Res. Res. Res. Res. Res. Res. Res.
19

RM0486 Rev 2
Res. Res. Res. Res. Res. Res. Res. Res.
18
Res. Res. Res. Res. Res. Res. Res. Res.
17
Res. Res. Res. Res. Res. Res. Res. Res.
16
Res. Res. Res. Res. Res. Res. Res. Res.
15

Reserved
Res. Res. Res. Res. Res. Res. Res. Res.
14
Res. Res. Res. Res. Res. Res. Res. Res.
13
Res. Res. Res. Res. Res. Res. Res. Res.
12
Res. Res. Res. Res. Res. Res. Res. Res.
11
Res. Res. Res. Res. Res. Res. Res. Res.
10
Res. Res. Res. CS Res. CS Res. Res.
9
Res. Res. READY EN READY EN Res. Res.
Table 83. SYSCFG register map and reset values (continued)

8
Res. Res. Res. Res.
7
Res. CM55TCML Res. Res.
6
Res. CM55CACHEL Res. Res.

0 0
[3:0]
[3:0]
[3:0]
[3:0]

APSRC
APSRC

RAPSRC
RAPSRC

Res. Res. Res. Res.

4
Res. BKPRAML Res. USB2_EARLY_WR_RSP_ENABLE
3
PVDL_LOCK CPU_NOC_CG_DISABLE USB1_EARLY_WR_RSP_ENABLE

0 0
DMACID_SEC 2
Res. CPU_NIC_CG_DISABLE SDMMC2_EARLY_WR_RSP_ENABLE

[3:0]
[3:0]
[3:0]
[3:0]

[2:0] 1

ANSRC
ANSRC

RANSRC
RANSRC

CM55L 0 0 0 1 1 1 1 0 0 0 NPU_NOC_CG_DISABLE SDMMC1_EARLY_WR_RSP_ENABLE

0 0 0 1 1 1 1 0 0 0

0 0 1
0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0
0 0 0 0
RM0486

0
 0x800
0x400
0x104
0x100
0x078
0x074

0x7FC
0x3FC
0x0FC
0x080-

0x804 -
0x404 -
0x108 -

0xHFF0
Offset

0xHFEC
RM0486

Reserved
Reserved
Reserved
Reserved

SYSCFG_

SYSCFG_
SYSCFG_
SYSCFG_
SYSCFG_

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

NPU_ICNCR

SMPSHDPCR
FMC_RETIMECR

SECPRIV_AIDCR
Register name

SYSCFG_BOOTSR

SYSCFG_DEVICEID
AHBWP_ERROR_SR
Res. Res. Res. Res. Res.
31
Res. Res. Res. Res. Res.
30
Res. Res. Res. Res. Res.
29
Res. Res. Res. Res. Res.
28
Res. Res. Res. Res. Res.
27
Res. Res. Res. Res. Res.
26
Res. Res. Res. Res. Res.
25
Res. Res. Res. Res. Res.
24
Res. Res. Res. Res. Res.
23
Res. Res. Res. Res. Res.
22

REV_ID[15:0]
Res. Res. Res. Res. Res.
21
Res. Res. Res. Res. Res.
20
Res. Res. Res. Res. Res.
19

RM0486 Rev 2
Res. Res. Res. Res. Res.
18
Res. Res. Res. Res. Res.
17
Res. Res. Res. Res. Res.

X X X X X X X X X X X X X X X X
16
Res. Res. Res. Res. Res. Res.
15

Reserved
Reserved
Reserved
Reserved

Res. Res. Res. Res. Res. Res.

Refer to Section 2.3 for the register boundary addresses.

14
Res. Res. Res. Res. Res. Res.
13
Res. Res. Res. Res. Res. Res.
12
Res. Res. Res. Res. Res. Res.
PAHB_ERROR_ADDR[31:0]
11
Res. Res. Res. Res. Res.
10
Res. Res. Res. Res. Res.
9
Res. Res. Res. Res. Res.
Table 83. SYSCFG register map and reset values (continued)

8
Res. Res. Res. Res. Res.
7
Res. Res. Res. Res. Res.
6
Res. Res. Res. Res. Res.
5
Res. Res. Res. Res. Res.
4
Res. Res. Res. Res.

DEV_ID[11:0]
3
SMPSHDPSEL Res. Res. SDFBCLK_180
DMACID_SECPRIV 2
[3:0] BOOT1 Res. CFG_RETIME_TX
[2:0] 1
BOOT0 INTERLEAVING_ACTIVE CFG_RETIME_RX
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 1
0 0 0 0
0 0
0
0 0 0

X X X X X X X X X X X
System configuration controller (SYSCFG)

825/4691
0

825
Peripherals interconnect matrix RM0486

17 Peripherals interconnect matrix

17.1 Introduction
Several peripherals have direct connections between them. This allows autonomous
communication and or synchronization between peripherals, saving CPU resources, thus
power supply consumption. In addition, these hardware connections remove software
latency, and improve the predictability of the system design.
Depending on peripherals, these interconnections can operate in various power modes:
Run, Standby, Sleep, and Stop modes.

17.2 Connection summary

The table below summarizes which master can access which memory-mapped resource.

Table 84. Connectivity matrix

CACHE AXI RAM

AXISRAM3/4/5/6
AHBSRAM1/2

AXISRAM1/2

AHBx/APBx
BKPSRAM

VENCRAM
FLEXRAM

BootROM
XSPI1/2/3
GFXMMU

DTCM
ITCM
FMC
STM

Resource

CPU M-AXI X X X X X X X X X X X X X(1) X(1) X

CPU P-AHB - - - - - - - - - - - - - - X(2)
AXI_AP X X X X X X X X X X - X - - X
TRACE - - - - X X X X - X - - - - -
NPU - - - - X X X X X - - X - X -
GPU_M0/1 X - - - X X X X X X - X - - -
GPU_CL - - - - X X X X X X - X - - -
ETH1 - - - - X X X X X X - X - - -
HPDMA1 AXI - - X X X X X X X X - X X X X
HPDMA1 AHB - - X X X X X X X X - X - - X
GPDMA1 - - X X X X X X X X - X - - X
SDMMC1/2 - - - - X X X X X X - X - - -
OTG1/2 - - - - X X X X X X - X - - -
DCMIPP - - - - X X X X X X - X - - -
DMA2D X - - - X X X X X X - X - - -
LTDC X - - - X X X X X X - X - - -
VENC - - - - X X X X X - - X - - -
GFXMMU - - - - X X X X X X - X - - -
1. The CPU accesses internally to its DTCM and ITCM. The DAP uses the CPU internal to reach TCMs.
2. By default, the CPU uses P-AHB master port to reach the AHBx/APBx target.

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RM0486 High-performance direct memory access controller (HPDMA)

18 High-performance direct memory access controller

(HPDMA)

18.1 HPDMA introduction

The high-performance direct memory access (HPDMA) controller is a bus master and
system peripheral.
The HPDMA is used to perform programmable data transfers between memory-mapped
peripherals, and/or memories via linked-lists, upon the control of an off-loaded CPU.

18.2 HPDMA main features

• Single bidirectional AXI master and single bidirectional AHB master
• Memory-mapped data transfers from a source to a destination:
– Peripheral-to-memory
– Memory-to-peripheral
– Memory-to-memory
– Peripheral-to-peripheral
Transfer arbitration based on a 4-grade programmed priority at channel level:
– One high-priority traffic class, for time-sensitive channels (queue 3)
– Three low-priority traffic classes, with a weighted round-robin allocation for non
time-sensitive channels (queues 0, 1, 2)
• Per channel event generation, on any of the following events: transfer complete, half
transfer complete, data transfer error, user setting error, link transfer error, completed
suspension, and trigger overrun
• Per channel interrupt generation, with separately programmed interrupt enable per
event
• 16 concurrent HPDMA channels:
– Per channel FIFO for queuing source and destination transfers
(see Section 18.3.1)
– Intra-channel HPDMA transfers chaining via programmable linked-list into
memory, supporting two execution modes: run-to-completion and link step mode
– Intra-channel and inter-channel HPDMA transfers chaining via programmable
HPDMA input triggers connection to HPDMA task completion events
• Per linked-list item within a channel:
– Separately programmed source and destination transfers
– Programmable data handling between source and destination: byte-based
reordering, packing or unpacking, padding or truncation, sign extension and
left/right realignment
– Programmable number of data bytes to be transferred from the source, defining
the block level
– Linear source and destination addressing: either fixed or contiguously
incremented addressing, programmed at block level, between successive
burst transfers

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High-performance direct memory access controller (HPDMA) RM0486

– 2D source and destination addressing: programmable signed address offsets

between successive burst transfers (non-contiguous addressing within a block,
combined with programmable signed address offsets between successive blocks,
at a second 2D/repeated block level, for a reduced set of channels
(see Section 18.3.1)
– Support for scatter-gather (multi-buffer transfers), data interleaving and
deinterleaving via 2D addressing
– Selection of programmable HPDMA request and trigger
– Generation of programmable HPDMA half-transfer and transfer-complete event
– Pointer to the next linked-list item and its data structure in memory, with automatic
update of the HPDMA linked-list control registers
– Channel abort and restart
• Debug:
– Channel suspend and resume support
– Channel status reporting, including FIFO level, and event flags
• TrustZone support:
– Support for secure and nonsecure HPDMA transfers, independently at a first
channel level, and independently at a source/destination and link sublevels
– Secure and nonsecure interrupts reporting, resulting from any of the respectively
secure and nonsecure channels
– TrustZone-aware AHB slave port, protecting any HPDMA secure resource
(register, bitfield) from a nonsecure access
• Privileged/unprivileged support:
– Support for privileged and unprivileged HPDMA transfers, independently at
channel level
– Privileged-aware AHB slave port
• Channel isolation support:
– Support for compartmented DMA transfers, independently at channel level, via
compartment IDs (named CIDs)
– CID-aware interrupts reporting
– CID-aware AHB slave port, with integrated semaphores for a concurrent control,
from any of the CPUs

18.3 HPDMA implementation

18.3.1 HPDMA channels

A given HPDMA channel x is implemented with the following features and intended use.
To make the best use of the HPDMA performance, the following table lists some general
recommendations, allowing the user to select and allocate a channel, given its implemented
FIFO size and the requested HPDMA transfer.

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RM0486 High-performance direct memory access controller (HPDMA)

Table 85. Implementation of HPDMA1 channels

Hardware parameters
Channel x Features
dma_fifo_ dma_
size[x] addressing[x]

Channel x (x = 0 to 11) is implemented with:

– a FIFO of 16 bytes, 4 words, 2 double-words
x = 0 to 11 3 0 – fixed/contiguously incremented addressing
These channels can be used for HPDMA transfers between an APB or
AHB peripheral, an AHB/AXI SRAM, or CPU TCM.
Channel x (x = 12 to 15) is implemented with:
– a FIFO of 64 bytes, 8 double-words
x = 12 to 15 5 1 – 2D addressing
These channels can be also used for HPDMA transfers, including AXI
external memories.

18.3.2 HPDMA allowed AXI maximum burst length

For a data transfer, the user has to program:
– the source (and destination) burst length that a given channel x ideally performs, via SBL_1[5:0]
(and respectively DBL_1[5:0]) field in HPDMA_CxTR1.
– the allocated master port, AXI or AHB, on which this source (or destination) data transfer must be
performed, via SAP (or respectively DAP) field in HPDMA_CxTR1.
Caution: The maximum allowed AXI burst length is restricted to 16:
1. if SAP = 0 (AXI allocated port): the maximum allowed value of SBL_1[5:0] is 15.
2. if DAP = 0 (AXI allocated port): the maximum allowed value of DBL_1[5:0] is 15.

18.3.3 HPDMA in low-power modes

The HPDMA wake-up feature is implemented in the device low-power modes as per the
table below.

Table 86. HPDMA1 in low-power modes

Feature Low-power modes

Wake-up HPDMA1 in Sleep mode

18.3.4 HPDMA requests

An HPDMA request from a peripheral can be assigned to a HPDMA channel x,
via REQSEL[7:0] in HPDMA_CxTR2, provided that SWREQ = 0.

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High-performance direct memory access controller (HPDMA) RM0486

The HPDMA requests mapping is specified in the table below.

Table 87. Programmed HPDMA1 request

HPDMA_CxTR2.REQSEL[7:0] Selected HPDMA request

0 jpeg_rx_dma
1 jpeg_tx_dma
2 xspi1_dma
3 xspi2_dma
4 xspi3_dma
5 fmc2_txrx_dma
6 fmc2_bch_dma
7 adc1_dma
8 adc2_dma
9 cryp_in_dma
10 cryp_out_dma
11 saes_out_dma
12 saes_in_dma
13 hash_in_dma
14 tim1_cc1_dma
15 tim1_cc2_dma
16 tim1_cc3_dma
17 tim1_cc4_dma
18 tim1_upd_dma
19 tim1_trg_dma
20 tim1_com_dma
21 tim2_cc1_dma
22 tim2_cc2_dma
23 tim2_cc3_dma
24 tim2_cc4_dma
25 tim2_upd_dma
26 tim2_trg_dma
27 tim3_cc1_dma
28 tim3_cc2_dma
29 tim3_cc3_dma
30 tim3_cc4_dma
31 tim3_upd_dma
32 tim3_trg_dma

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RM0486 High-performance direct memory access controller (HPDMA)

Table 87. Programmed HPDMA1 request (continued)

HPDMA_CxTR2.REQSEL[7:0] Selected HPDMA request

33 tim4_cc1_dma
34 tim4_cc2_dma
35 tim4_cc3_dma
36 tim4_cc4_dma
37 tim4_upd_dma
38 tim4_trg_dma
39 tim5_cc1_dma
40 tim5_cc2_dma
41 tim5_cc3_dma
42 tim5_cc4_dma
43 tim5_upd_dma
44 tim5_trg_dma
45 tim6_upd_dma
46 tim7_upd_dma
47 tim8_cc1_dma
48 tim8_cc2_dma
49 tim8_cc3_dma
50 tim8_cc4_dma
51 tim8_upd_dma
52 tim8_trg_dma
53 tim8_com_dma
54 -
55 -
56 tim15_cc1_dma
57 tim15_cc2_dma
58 tim15_upd_dma
59 tim15_trg_dma
60 tim15_com_dma
61 tim16_cc1_dma
62 tim16_upd_dma
63 tim16_com_dma
64 tim17_cc1_dma
65 tim17_upd_dma
66 tim17_com_dma
67 tim18_cc1_dma

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High-performance direct memory access controller (HPDMA) RM0486

Table 87. Programmed HPDMA1 request (continued)

HPDMA_CxTR2.REQSEL[7:0] Selected HPDMA request

68 tim18_upd_dma
69 tim18_com_dma
70 lptim1_ic1_dma
71 lptim1_ic2_dma
72 lptim1_ue_dma
73 lptim2_ic1_dma
74 lptim2_ic2_dma
75 lptim2_ue_dma
76 lptim3_ic1_dma
77 lptim3_ic2_dma
78 lptim3_ue_dma
79 spi1_rx_dma
80 spi1_tx_dma
81 spi2_rx_dma
82 spi2_tx_dma
83 spi3_rx_dma
84 spi3_tx_dma
85 spi4_rx_dma
86 spi4_tx_dma
87 spi5_rx_dma
88 spi5_tx_dma
89 spi6_rx_dma
90 spi6_tx_dma
91 sai1_a_dma
92 sai1_b_dma
93 sai2_a_dma
94 sai2_b_dma
95 i2c1_rx_dma
96 i2c1_tx_dma
97 i2c2_rx_dma
98 i2c2_tx_dma
99 i2c3_rx_dma
100 i2c3_tx_dma
101 i2c4_rx_dma
102 i2c4_tx_dma

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RM0486 High-performance direct memory access controller (HPDMA)

Table 87. Programmed HPDMA1 request (continued)

HPDMA_CxTR2.REQSEL[7:0] Selected HPDMA request

103 i3c1_rx_dma
104 i3c1_tx_dma
105 i3c2_rx_dma
106 i3c2_tx_dma
107 usart1_rx_dma
108 usart1_tx_dma
109 usart2_rx_dma
110 usart2_tx_dma
111 usart3_rx_dma
112 usart3_tx_dma
113 uart4_rx_dma
114 uart4_tx_dma
115 uart5_rx_dma
116 uart5_tx_dma
117 usart6_rx_dma
118 usart6_tx_dma
119 uart7_rx_dma
120 uart7_tx_dma
121 uart8_rx_dma
122 uart8_tx_dma
123 uart9_rx_dma
124 uart9_tx_dma
125 usart10_rx_dma
126 usart10_tx_dma
127 lpuart1_rx_dma
128 lpuart1_tx_dma
129 spdifrx_cs_dma
130 spdifrx_dt_dma
131 adf1_flt0_dma
132 mdf1_flt0_dma
133 mdf1_flt1_dma
134 mdf1_flt2_dma
135 mdf1_flt3_dma
136 mdf1_flt4_dma
137 mdf1_flt5_dma

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High-performance direct memory access controller (HPDMA) RM0486

Table 87. Programmed HPDMA1 request (continued)

HPDMA_CxTR2.REQSEL[7:0] Selected HPDMA request

138 ucpd_tx_dma
139 ucpd_rx_dma
140 cci_dma
141 i3c1_tc_dma
142 i3c1_rs_dma
143 i3c2_tc_dma
144 i3c2_rs_dma

18.3.5 HPDMA block requests

Some HPDMA requests must be programmed as a block request, and not as a burst
request. Then BREQ in HPDMA_CxTR2 must be set for a correct HPDMA execution of the
requested peripheral transfer at the hardware level.

Table 88. Programmed HPDMA1 request as a block request

HPDMA block requests

lptim1/2/3_ue

18.3.6 HPDMA channels with peripheral early termination

An HPDMA channel, if implemented with this feature, can support the early termination of
the data transfer from the peripheral which does also support this feature.

Table 89. HPDMA1 channel with peripheral early termination

HPDMA channel x with peripheral early termination

x = 0, x = 1, and x = 15

This HPDMA support is activated when the channel x is programmed with

HPDMA_CxTR2.PFREQ = 1. Then, the peripheral itself can initiate and request a data
transfer completion, before that the HPDMA has transferred the whole block
(see Section 18.4.14 for more details).

Table 90. Programmed HPDMA1 request with peripheral early termination

Programmed HPDMA channel x request with peripheral early termination

i3c1_rx_dma
i3c2_rx_dma
jpeg_tx_dma

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RM0486 High-performance direct memory access controller (HPDMA)

18.3.7 HPDMA triggers

An HPDMA trigger can be assigned to an HPDMA channel x, via TRIGSEL[6:0]
in HPDMA_CXTR2, provided that TRIGPOL[1:0] defines a rising or a falling edge of the
selected trigger (TRIGPOL[1:0] = 01 or TRIGPOL[1:0] = 10).

Table 91. Programmed HPDMA1 trigger

HPDMA_CxTR2.TRIGSEL[7:0] Selected HPDMA trigger

0 dcmipp_p1_frameend_evt
1 dcmipp_p1_lineend_evt
2 dcmipp_p1_hsync_evt
3 dcmipp_p1_vsync_evt
4 dcmipp_p1_frameend_evt
5 dcmipp_p1_lineend_evt
6 dcmipp_p1_hsync_evt
7 dcmipp_p1_vsync_evt
8 dcmipp_p2_frameend_evt
9 dcmipp_p2_lineend_evt
10 dcmipp_p2_hsync_evt
11 dcmipp_p2_vsync_evt
12 dma2d_ctc_flag
13 dma2d_tc_flag
14 dma2d_tw_flag
15 jpeg_eoc_flag
16 jpeg_ifnf_flag
17 jpeg_ift_flag
18 jpeg_ofne_flag
19 jpeg_oft_flag
20 lcd_li_flag
21 gpu2d1_gp_flag[0]
22 gpu2d1_gp_flag[1]
23 gpu2d1_gp_flag[2]
24 gpu2d1_gp_flag[3]
25 gfxtim1_0_gfxtim_evt[3]
26 gfxtim1_0_gfxtim_evt[2]
27 gfxtim1_0_gfxtim_evt[1]
28 gfxtim1_0_gfxtim_evt[0]
29 -
30 lptim1_ch1

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High-performance direct memory access controller (HPDMA) RM0486

Table 91. Programmed HPDMA1 trigger (continued)

HPDMA_CxTR2.TRIGSEL[7:0] Selected HPDMA trigger

31 lptim1_ch2
32 lptim2_ch1
33 lptim2_ch2
34 lptim3_ch1
35 lptim3_ch2
36 lptim4_out
37 lptim5_out
38 -
39 rtc_wkup
40 lpuart1_it_r_wup_async
41 lpuart1_it_t_wup_async
42 spi6_it_or_spi6_ait_sync
43 -
44 tim1_trgo_cktim
45 tim1_trgo2_cktim
46 tim2_trgo_cktim
47 tim3_trgo_cktim
48 tim4_trgo_cktim
49 tim5_trgo_cktim
50 tim6_trgo_cktim
51 tim7_trgo_cktim
52 tim8_trgo_cktim
53 tim8_trgo2_cktim
54 -
55 -
56 -
57 tim12_trgo_cktim
58 tim15_trgo_cktim
59 -
60 hpdma1_ch0_tc
61 hpdma1_ch1_tc
62 hpdma1_ch2_tc
63 hpdma1_ch3_tc
64 hpdma1_ch4_tc
65 hpdma1_ch5_tc

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RM0486 High-performance direct memory access controller (HPDMA)

Table 91. Programmed HPDMA1 trigger (continued)

HPDMA_CxTR2.TRIGSEL[7:0] Selected HPDMA trigger

66 hpdma1_ch6_tc
67 hpdma1_ch7_tc
68 hpdma1_ch8_tc
69 hpdma1_ch9_tc
70 hpdma1_ch10_tc
71 hpdma1_ch11_tc
72 hpdma1_ch12_tc
73 hpdma1_ch13_tc
74 hpdma1_ch14_tc
75 hpdma1_ch15_tc
76 gpdma1_ch0_tc
77 gpdma1_ch1_tc
78 gpdma1_ch2_tc
79 gpdma1_ch3_tc
80 gpdma1_ch4_tc
81 gpdma1_ch5_tc
82 gpdma1_ch6_tc
83 gpdma1_ch7_tc
84 gpdma1_ch8_tc
85 gpdma1_ch9_tc
86 gpdma1_ch10_tc
87 gpdma1_ch11_tc
88 gpdma1_ch12_tc
89 gpdma1_ch13_tc
90 gpdma1_ch14_tc
91 gpdma1_ch15_tc
92 -
93 extit0_sync
94 extit1_sync
95 extit2_sync
96 extit3_sync
97 extit4_sync
98 extit5_sync
99 extit6_sync
100 extit7_sync

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High-performance direct memory access controller (HPDMA) RM0486

Table 91. Programmed HPDMA1 trigger (continued)

HPDMA_CxTR2.TRIGSEL[7:0] Selected HPDMA trigger

101 extit8_sync
102 extit9_sync
103 extit10_sync
104 extit11_sync
105 extit12_sync
106 extit13_sync
107 extit14_sync
108 extit15_sync

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RM0486 High-performance direct memory access controller (HPDMA)

18.4 HPDMA functional description

18.4.1 HPDMA block diagram

Figure 71. HPDMA block diagram

HPDMA

64-bit AXI bus

Channel datapath and Transfer output control AXI master
transfer input control port 0
DMA interface
Data transfer
requests
Channel x (1) generation
... Arbitration

32-bit AHB bus

DMA
triggers Channel 1 AHB master
Link transfer port 1
Channel 0 generation interface

DMA channel
DMA
Interrupt generation interrupt
clock
DMA channel registers
DMA channel
Events generation
Stop DMA transfer complete
channel in Channel x (1) (hpdma_chx_tc)
DMA global Channel state
debug mode ...
registers management DMA channel state
Channel 1 Security and privilege (vs privilege, security
management and compartment)
Channel 0
DMA illegal event
Compartment isolation
(vs privilege, security
management
and compartment)
AHB slave interface
Clock management DMA clock request

(1) Refer to the device implementation table for the number of channels.
32-bit AHB bus MSv66925V2

18.4.2 HPDMA channel state and direct programming without

any linked-list
After an HPDMA reset, an HPDMA channel x is in idle state. When the software writes 1 into
the HPDMA_CxCR.EN enable control bit, the channel takes into account the value of the
different channel configuration registers (HPDMA_CxXXX), switches to the active/non-idle
state, and starts to execute the corresponding requested data transfers.
After enabling/starting an HPDMA channel transfer by writing 1 into HPDMA_CxCR.EN,
an HPDMA channel interrupt on a complete transfer notifies the software that the HPDMA
channel is back in idle state (EN is then deasserted by hardware), and that the channel is
ready to be reconfigured then enabled again.

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High-performance direct memory access controller (HPDMA) RM0486

The figure below illustrates this HPDMA direct programming without any linked-list
(HPDMA_CxLLR = 0).

Figure 72. HPDMA channel direct programming without linked-list (HPDMA_CxLLR = 0)

Channel state = Idle

Initialize DMA channel Reconfigure DMA channel
(keeping DMA_CxLLR[31:0] = 0) (keeping DMA_CxLLR[31:0] = 0)

Enable DMA channel

Channel state = Active

Valid user
setting ? N

Y
Setting USEF = 1
Disabling DMA channel
Executing the data transfer
from the register file

No transfer
N
error ?

Y Setting DTEF = 1
Disabling DMA channel

Setting TCF = 1
Disabling DMA channel

End

MSv62626V1

18.4.3 HPDMA channel suspend and resume

The software can suspend on its own a channel still active, with the following sequence:
1. The software writes 1 into the HPDMA_CxCR.SUSP bit.
2. The software polls the suspended flag HPDMA_CxSR.SUSPF until SUSPF = 1, or
waits for an interrupt previously enabled by writing 1 to HPDMA_CxCR.SUSPIE.
Wait for the channel to be effectively in suspended state means wait for the completion
of any ongoing HPDMA transfer over its master ports. Then the software can observe,
in a steady state, any read register or bitfield that is hardware modifiable.

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Note: An ongoing HPDMA transfer can be a data transfer (a source/destination burst

transfer,) or a link transfer for the internal update of the linked-list register file from the
next linked-list item.
3. The software safely resumes the suspended channel by writing 0 to
[Link].

Figure 73. HPDMA channel suspend and resume sequence

Channel state = Active

Suspend the DMA channel

(write 1 to [Link])
or

N
SUSPF=1 ?

Channel state = Suspended and Idle Y

Receiving
suspended
interrupt

Resume the DMA channel

(write 0 to [Link])

Channel state = Active

MSv62627V1

Note: A suspend and resume sequence does not impact the HPDMA_CxCR.EN bit. Suspending a
channel (transfer) does not suspend a started trigger detection.

18.4.4 HPDMA channel abort and restart

Alternatively, like for aborting a continuous HPDMA transfer with a circular buffering or a
double buffering, the software can abort, on its own, a still active channel with the following
sequence:
1. The software writes 1 into the HPDMA_CxCR.SUSP bit.
2. The software polls suspended flag HPDMA_CxSR.SUSPF until SUSPF = 1, or waits
for an interrupt previously enabled by writing 1 to HPDMA_CxCR.SUSPIE. Wait for the
channel to be effectively in suspended state means wait for the completion of any
ongoing HPDMA transfer over its master port.
3. The software resets the channel by writing 1 to HPDMA_CxCR.RESET. This causes
the reset of the FIFO, the reset of the channel internal state, the reset of the
HPDMA_CxCR.EN bit, and the reset of the HPDMA_CxCR.SUSP bit.
4. The software safely reconfigures the channel. The software must reprogram
hardware-modified HPDMA_CxBR1, HPDMA_CxSAR, and HPDMA_CxDAR.

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5. In order to restart the aborted then reprogrammed channel, the software enables it
again by writing 1 to the HPDMA_CxCR.EN bit.

Figure 74. HPDMA channel abort and restart sequence

Channel state = Active

Suspend the DMA channel

(write 1 to [Link])
or

N
SUSPF=1 ?

Y
Channel state = Suspended
Receiving (and Idle)
suspended
interrupt

Reset the DMA channel

(write 1 to [Link])

Channel state = Idle

Reconfigure the DMA channel

Enable the DMA channel

Channel state = Active

MSv62628V1

18.4.5 HPDMA linked-list data structure

Alternatively to the direct programming mode, a channel can be programmed by a list of
transfers, known as a list of linked-list items (LLI). Each LLI is defined by its data structure.
For a channel x, the base address in memory of the data structure of a next LLIn+1 is the
sum of the following:
• the link base address of the channel x (in HPDMA_CxLBAR)
• the link address offset LA[15:2] bitfield in HPDMA_CxLLR, that is the updated result
from the data structure of the previous LLIn of the channel x
The data structure for each LLI can be specific.
A linked-list data structure is addressed following the value of UT1, UT2, UB1, USA, UDA,
and ULL bits, plus UB2 and UT3 when present, in HPDMA_CxLLR.
In linked-list mode, each HPDMA linked-list register (HPDMA_CxTR1, HPDMA_CxTR2,
HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR or HPDMA_CxLLR,

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RM0486 High-performance direct memory access controller (HPDMA)

plus HPDMA_CxTR3 or HPDMA_CxBR2 when present) is conditionally and automatically

updated from the next linked-list data structure in the memory, following the current value
of HPDMA_CxLLR that was conditionally updated from the linked-list data structure of the
previous LLI.

Static linked-list data structure

For example, when the update bits (UT1, UT2, UB1, USA, UDA, and ULL, plus UB2 and
UT3 when present) in HPDMA_CxLLR are all asserted, the linked-list data structure in the
memory is maximal with:
• channel x, x = 0 to 11, six contiguous 32-bit locations, including HPDMA_CxTR1,
HPDMA_CxTR2, HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR, and
HPDMA_CxLLR (see Figure 75) and including the first linked-list register file (LLI0),
and the next LLIs (LLI1, LLI2,...) in the memory
• channel x, x = 12 to 15, eight contiguous 32-bit locations, including HPDMA_CxTR1,
HPDMA_CxTR2, HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR, and
HPDMA_CxLLR, plus HPDMA_CxTR3 and HPDMA_CxBR2 (see Figure 76), including
the first linked-list register file (LLI0), and the next LLIs (LLI1, LLI2,...) in the memory

Figure 75. Static linked-list data structure (all Uxx = 1) of a linear addressing channel x
DMA register file Memory from link base address
DMA_CxLBAR
Channel x linked-list register file
(LLI0) LLI1
DMA_CxTR1 All Uxx=1 DMA_CxTR1

DMA_CxTR2 DMA_CxTR2

DMA_CxBR1 DMA_CxBR1

DMA_CxSAR DMA_CxSAR

DMA_CxDAR DMA_CxDAR

DMA_CxLLR DMA_CxLLR
All Uxx=1

Channel x other registers LLI2

DMA_CxTR1
Other channels registers DMA_CxTR2

Global registers DMA_CxBR1

DMA_CxSAR
DMA_CxDAR
DMA_CxLLR

MSv62629V1

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Figure 76. Static linked-list data structure (all Uxx = 1) of a 2D addressing channel x
DMA register file Memory from link base address
DMA_CxLBAR
Channel x linked-list register file
(LLI0) LLI1
DMA_CxTR1 DMA_CxTR1
All Uxx=1
DMA_CxTR2 DMA_CxTR2

DMA_CxBR1 DMA_CxBR1

DMA_CxSAR DMA_CxSAR

DMA_CxDAR DMA_CxDAR

DMA_CxTR3 DMA_CxTR3

DMA_CxBR2 DMA_CxBR2

DMA_CxLLR DMA_CxLLR
All Uxx=1

Channel x other registers

LLI2

Other channels registers DMA_CxTR1

DMA_CxTR2
Global registers
DMA_CxBR1
DMA_CxSAR
DMA_CxDAR
DMA_CxTR3
DMA_CxBR2
DMA_CxLLR

MSv63645V1

Dynamic linked-list data structure

Alternatively, the memory organization for the full list of LLIs can be compacted with specific
data structure for each LLI.
If UT1 = 0 and UT2 = 1, the link address offset of HPDMA_CxLLR points to the updated
value of HPDMA_CxTR2, instead of HPDMA_CxTR1 which is not to be modified
(see Figure 77).
Example: if UT1 = UB1 = USA = 0, and if UT3 = UB2 = 0 when channel x is with 2D
addressing, and if UT2 = UDA = ULL = 1, the next LLI does not contain an (updated) value
for HPDMA_CxTR1, nor HPDMA_CxBR1, nor HPDMA_CxSAR, nor HPDMA_CxTR3, nor
HPDMA_CxBR2 when channel x is with 2D addressing. The next LLI contains an updated
value for HPDMA_CxTR2, HPDMA_CxDAR, and HPDMA_CxLLR, as shown in Figure 78.

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Figure 77. HPDMA dynamic linked-list data structure of linear addressing channel x
LLIn
All Uxx = 1
DMA_CxTR1
DMA_CxTR2
UT1 = UB1 = USA = 0 LLIn+1
DMA_CxBR1 UT2 = UDA = ULL = 1
DMA_CxTR2
DMA_CxSAR
DMA_CxDAR
DMA_CxDAR
DMA_CxLLR
DMA_CxLLR
MSv62630V1

Figure 78. HPDMA dynamic linked-list data structure of a 2D addressing channel x

LLIn
All Uxx = 1
DMA_CxTR1
UT1 = UB1 = USA = 0
DMA_CxTR2
UT3 = UB2 = 0 LLIn+1
DMA_CxBR1 UT2 = UDA = ULL = 1
DMA_CxTR2
DMA_CxSAR
DMA_CxDAR
DMA_CxDAR
DMA_CxLLR
DMA_CxTR3
DMA_CxBR2
DMA_CxLLR
MSv63646V1

The user must program HPDMA_CxLLR for each LLIn to be 32-bit aligned, and not to
exceed the 64-Kbyte addressable space pointed by HPDMA_CxLBAR.

18.4.6 Linked-list item transfer execution

An LLIn transfer is the sequence of:
1. a data transfer: the HPDMA executes the data transfer as described by the HPDMA
internal register file (this data transfer can be void/null for LLI0).
2. a conditional link transfer: the HPDMA automatically and conditionally updates its
internal register file by the data structure of the next LLIn+1, as defined by the
HPDMA_CxLLR value of the LLIn.
Note: The initial data transfer, as defined by the internal register file (LLI0), can be null
(HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxTR2.PFREQ = 0), provided that UB1 is
set in HPDMA_CxLLR (meaning there is a non-null data transfer described by the next LLI1
in the memory to be executed).
Depending on the intended HPDMA use, an HPDMA channel x can be executed as
described by the full linked-list (run-to-completion mode, HPDMA_CxCR.LSM = 0), or can
be programmed for a single execution of a LLI (link step mode, HPDMA_CxCR.LSM = 1),
as described in the next sections.

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18.4.7 HPDMA channel state and linked-list programming

in run-to-completion mode
When HPDMA_CxCR.LSM = 0 (in full-list execution mode, execution of the full sequence of
LLIs, named run-to-completion mode), an HPDMA channel x is initially programmed, started
by writing 1 to HPDMA_CxCR.EN, and after completed at channel level.
The channel transfer is:
• configured with at least the following:
– the first LLI0, internal linked-list register file: HPDMA_CxTR1, HPDMA_CxTR2,
HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR, and HPDMA_CxLLR, plus
HPDMA_CxTR3 and HPDMA_CxBR2 when present
– the last LLIN described by the linked-list data structure in memory, as defined
by HPDMA_CxLLR reflecting the before last LLIN-1
• completed when HPDMA_CxLLR[31:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0,
if BRC[10:0] is present and HPDMA_CxBR1.BNDT[15:0] = 0, at the end of the last
LLIN-1 transfer
HPDMA_CxLLR[31:0] = 0 is the condition of a linked-list based channel completion, and
means the following:
• The 16 low significant bits HPDMA_CxLLR.LA[15:0] of the next link address are null.
• All bits HPDMA_CxLLR.Uxx are null (UT1, UT2, UB1, USA, UDA, and ULL, plus UB2
and UT3 when present).
The channel may never be completed when HPDMA_CxLLR.LSM = 0:
• If the last LLIN is recursive, pointing to itself as a next LLI, in one of the following:
– HPDMA_CxLLR.ULL = 1 and HPDMA_CxLLR.LA[15:2] is updated by the same
value.
– HPDMA_CxLLR.ULL = 0
• If LLIN points to a previous LLI
In the regular data transfer completion at a block level, HPDMA_CxBR1.BNDT[15:0] = 0
and HPDMA_CxBR1.BRC[10:0] = 0 (if present). Alternatively, a block transfer may be early
completed by a peripheral (such as an I3C in Rx mode), and then BNDT[15:0] is not null
(see Section 18.4.14 for more details).
In the typical run-to-completion mode, the allocation of an HPDMA channel, including its fine
programming, is done once during the HPDMA initialization. In order to have a reserved
data communication link and HPDMA service during run-time, for continuously repeated
transfers (from/to a peripheral respectively to/from memory or for memory-to-memory
transfers). This reserved data communication link can consist of a channel, or the channel
can be shared and a repeated transfer consists of a sequence of LLIs.
Figure 79 depicts the HPDMA channel execution and its registers programming in run-to-
completion mode.
Note: Figure 79 is not intended to illustrate how often a TCEF can be raised, depending on the
programmed value of TCEM[1:0] in HPDMA_CxTR2. It can be raised at (each) block
completion, at (each) 2D block completion, at (each) LLI completion, or only at channel

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completion. In run-to-completion mode, whatever is the value of TCEM[1:0], at the channel

completion, the hardware always set TCEF = 1 and disables the channel.
In Figure 79, BNDT ≠ 0 is the typical condition for starting the first data transfer. This
condition becomes (BNDT ≠ 0 and PFREQ = 1) if the peripheral requests a data transfer
with early termination (see Section 18.3.6).

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Figure 79. HPDMA channel execution and linked-list programming

in run-to-completion mode (HPDMA_CxCR.LSM = 0)
Channel state = Idle

Initialize DMA channel

Reconfigure DMA channel

Enable DMA channel

Channel state = Active

Valid user
setting ? N

Y
Setting USEF = 1
N Disabling DMA channel
BNDT0 ?

Executing once the data

transfer from the register file

No transfer
N
error ?

Y
Setting DTEF = 1
Disabling DMA channel
N LLR 0 ?

Loading next LLI

into the register file

No transfer
N
error ?

Y Setting ULEF = 1
Disabling DMA channel
Valid user
N
setting ?
Y
Setting USEF = 1
Setting TCF = 1 Disabling DMA channel
Disabling DMA channel

End

MSv62631V1

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Run-time inserting a LLIn via an auxiliary channel, in run-to-completion mode

The start of the link transfer of the LLIn-1 (start of the LLIn loading) can be conditioned by the
occurrence of a trigger, when programming the following bitfields of HPDMA_CxTR2 in the
data structure of the LLIn-1:
• TRIGM[1:0] = 10 (link transfer triggering mode)
• TRIGPOL[1:0] = 01 or 10 (rising or falling edge)
• TRIGSEL[6:0] (see Section 18.3.7 for the trigger selection details)
Another auxiliary channel y can be used to store the channel x LLIn in the memory, and to
generate a transfer complete event hpdma_chy_tc. By selecting this event as the input
trigger of the link transfer of the LLIn-1 of the channel x, the software can pause the primary
channel x after its LLIn-1 data transfer, until it is indeed written the LLIn.
Figure 80 depicts such a dynamic elaboration of a linked-list of a primary channel x,
via another auxiliary channel y.
Caution: This use case is restricted to an application with an LLIn-1 data transfer that does not need
a trigger. The triggering mode of this LLIn-1 is used to load the next LLIn.

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Figure 80. Inserting a LLIn with an auxiliary HPDMA channel y

DMA primary channel x DMA auxiliary channel y CPU

Executing LLIn-2 data transfer

LLIn-1 transfer

Loading LLIn-1
(with DMA_CxTR2: TRIGM[1:0] = 10
TRIGPOL[1:0] = 01
TRIGSEL= dma_chy_tc
and TCEM[1:0] = 01)

Executing LLIn-1 data transfer

Transfer complete interrupt
Build new LLIn
Configure channel Y
LLIn transfer

Executing data transfer

(Memcopy of new LLIn)
dma_chy_tc

Loading new LLIn

Executing LLIn data transfer

transfer
LLIn+1

Loading LLIn+1

MSv62632V2

18.4.8 HPDMA channel state and linked-list programming

in link step mode
When HPDMA_CxCR.LSM = 1 (in link step execution mode, single execution of one LLI),
a channel transfer is executed and completed after each single execution of a LLI, including
its (conditional) data transfer and its (conditional) link transfer.
An HPDMA channel transfer can be programmed at an LLI level, started by writing 1 into
HPDMA_CxCR.EN, and after completed at LLI level:
• The current LLIn transfer is described with the following:
– HPDMA_CxTR1 defines the source/destination elementary single/burst transfers.
– HPDMA_CxBR1 defines the number of bytes at a block level (BNDT[15:0]), for
channel x = 12 to 15, the number of blocks at a 2D/repeated block level
(BRC[10:0]+1), and the incrementing/decrementing mode for address offsets.

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– HPDMA_CxTR2 defines the input control (request, trigger), and the output control
(transfer-complete event) of the transfer.
– HPDMA_CxSAR and HPDMA_CxDAR define the source/destination transfer
start address.
– HPDMA_CxTR3 (for channel x = 12 to 15) defines the source/destination
additional address offset between burst transfers.
– HPDMA_CxBR2 (for channel x = 12 to 15) defines the source/destination
additional address offset between blocks at a 2D/repeated block level.
– HPDMA_CxLLR defines the data structure, and the address offset of the next
LLIn+1 in the memory.
• The current LLIn transfer is completed after the single execution of the current LLIn:
– after the (conditional) data transfer completion (when
HPDMA_CxBR1.BRC[10:0] = 0 if BRC[10:0] is present, and
HPDMA_CxBR1.BNDT[15:0] = 0)
– after the (conditional) update of the HPDMA link register file from the data
structure of the next LLIn+1 in memory
Note: If an LLI is recursive (pointing to itself as a next LLI, either HPDMA_CxLLR.ULL = 1 and
HPDMA_CxLLR.LA[15:2] is updated by the same value, or HPDMA_CxLLR.ULL = 0),
a channel in link step mode is completed after each repeated single execution of this LLI.
In the regular data transfer completion at a block level, HPDMA_CxBR1.BNDT[15:0] = 0
and HPDMA_CxBR1.BRC[10:0] = 0 (if present). Alternatively, a block transfer can be early
completed by a peripheral (such as an I3C in Rx mode), and then BNDT[15:0] is not null
(see Section 18.4.14 for more details).
The link step mode can be used to elaborate dynamically LLIs in memory during run-time.
The software can be facilitated by using a static data structure for any LLIn (all update bits of
HPDMA_CxLLR have a static value, [Link] = [Link] + constant).
Figure 81 depicts the HPDMA channel execution mode, and its programming in link step
mode.
Note: Figure 81 is not intended to illustrate how often a TCEF can be raised, depending on the
programmed value of TCEM[1:0] in HPDMA_CxTR2. It can be raised at (each) block
completion, at (each) 2D block completion, at (each) LLI completion, or only at the last LLI
data transfer completion. In link step mode, the channel is disabled after each single
execution of a LLI, and depending on the value of TCEM[1:0] a TCEF is raised or not.
In Figure 81, BNDT ≠ 0 is the typical condition for starting the first data transfer.
This condition becomes BNDT ≠ 0 and PFREQ = 1 if the peripheral requests a data transfer
with early termination (see Section 18.3.6).

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Figure 81. HPDMA channel execution and linked-list programming

in link step mode (HPDMA_CxCR.LSM = 1)
Channel state = Idle

Initialize DMA channel

Reconfigure DMA channel

Enable DMA channel

Channel state = Active

Valid user
setting ? N

Y
Setting USEF = 1
N Disabling DMA channel
BNDT  0 ?

Executing once the data

transfer from the register file

No transfer
N
error ?

Y
Setting DTEF = 1
Disabling DMA channel
N LLR 0 ?

Loading next LLI

into the register file

No transfer
N
error ?

Y Setting ULEF = 1
Disabling DMA channel
Valid user
N
setting ?
Y
Setting USEF = 1
Setting TCF = 1 Disabling DMA channel
Disabling DMA channel

End

MSv62633V1

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Run-time adding a LLIn+1 in link step mode

During run-time, the software can defer the elaboration of the LLIn+1 (and next LLIs),
until/after the HPDMA executed the transfer from the LLIn-1 and loaded the LLIn from the
memory, as shown in the figure below.

Figure 82. Building LLIn+1: HPDMA dynamic linked-lists in link step mode

LSM = 1 with 2-stage linked-list programming:

DMA executes LLIn-1 and loads LLIn while CPU builds LLIn+1

DMA Channel CPU

LLIn-2
transfer

Transfer complete interrupt

Enable DMA channel

Executing LLIn-1 data transfer

transfer
LLIn-1

Build and store LLIn+1

Loading LLIn

Transfer complete interrupt

Enable DMA channel

LLIn
transfer

MSv62634V1

Run-time replacing an LLIn with a new LLIn’ in link step mode (in linked-list
register file)
In this link step mode, during run-time, the software can build and insert a new LLIn’, after
the HPDMA executed the transfer from the LLIn-1, and loaded a formerly elaborated LLIn
from the memory by overwriting directly the linked-list register file with the new LLIn’, as
shown in Figure 83.

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Figure 83. Replace with a new LLIn’ in register file in link step mode

LSM = 1 with 1-stage linked-list programming:

Overwriting the (pre)loaded LLIn linked-list register file with
a new LLIn’ directly in linked-list register file.
DMA executes LLIn-1 and load LLIn, then CPU builds and overwrites LLIn'

DMA channel CPU

Executing LLIn-1 data transfer

transfer
LLIn-1

Loading LLIn

Transfer complete interrupt

Build LLIn' and overwrite

linked-list register file

Enable DMA channel

Executing LLIn' data transfer

transfer
LLIn'

Loading LLIn+1’

Transfer complete interrupt

Build LLIn+1’' and overwrite

linked-list register file

Enable DMA channel

LLIn+1"
transfer

Transfer complete interrupt

MSv62635V1

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Run-time replacing an LLIn with a new LLIn’ in link step mode (in the memory)
The software can build and insert a new LLIn’ and LLIn+1’ in the memory, after HPDMA
executed the transfer from the LLIn-1, and loaded a formerly elaborated LLIn from the
memory, by overwriting partly the linked-list register file (HPDMA_CxBR1.BNDT[15:0] to be
null, and HPDMA_CxLLR to point to new LLIn) as shown in Figure 84.

Figure 84. Replace with a new LLIn’ and LLIn+1’ in memory in link step mode (option 1)

LSM = 1 with 1-stage linked-list programming:

Overwriting the (pre)loaded LLIn linked-list register file with a new LLIn' and LLIn+1' in memory and
overwrite partly linked-list register file
(DMA_CxBR1.BNDT = 0 and DMA_CxLLR to point to new LLIn')
DMA executes LLIn-1 and load LLIn then CPU builds (LLIn' and LLIn+1') and overwrite (BR1 and LLR)

DMA Channel CPU

Executing LLIn-1 data transfer

transfer
LLIn-1

Loading LLIn

Transfer complete interrupt

Build LLIn' and LLIn+1' in memory

Write DMA_CxBR1.BNDT = 0
Write DMA_CxLLR to point to new LLIn'

Enable DMA channel

transfer
LLIn'

Loading LLIn’

Transfer complete interrupt

Enable DMA channel

Executing LLIn+1' data transfer

transfer
LLIn+1'

Loading LLIn+1'

Transfer complete interrupt

MSv62636V1

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Run-time replacing a LLIn with a new LLIn’ in link step mode

Other software implementations exist. Meanwhile the HPDMA executes the transfer from
the LLIn-1 and loads a formerly elaborated LLIn from the memory (or even earlier),
the software can do the following:
1. Disable the NVIC for not being interrupted by the interrupt handling.
2. Build a new LLIn’ and a new LLIn+1’.
3. Enable again the NVIC for the channel interrupt (transfer complete) notification.
The software in the interrupt handler for LLIn-1 is then restricted to overwrite
HPDMA_CxBR1.BNDT[15:0] to be null and HPDMA_CxLLR to point to new LLIn’, as shown
in the figure below.

Figure 85. Replace with a new LLIn’ and LLIn+1’ in memory in link step mode (option 2)

LSM = 1 with 1-stage linked-list programming:

Overwriting the (pre)loaded LLIn linked-list register file by building new LLIn' and LLIn+1' in memory
while disabling (temporary) channel interrupt at NVIC level, and overwriting DMA_CxBR1.BNDT = 0
and DMA_CxLLR to point to new LLIn'
DMA executes LLIn-1 and loading LLIn while CPU builds (LLIn' and LIn+1'), then CPU overwrites
(BR1 and LLR)

DMA channel CPU

Disable NVIC DMA irq channel

Executing LLIn-1 data transfer
transfer
LLIn-1

Build LLIn' & LLIn+1' in memory

Loading LLIn
Enable NVIC DMA irq channel
Transfer complete interrupt
Write DMA_CxBR1.BNDT = 0
Write DMA_CxLLR to point to new LLIn'

Enable DMA channel

transfer
LLIn'

Loading LLIn’

Transfer complete interrupt

Enable DMA channel

Executing LLIn+1' data transfer

transfer
LLIn+1'

Loading LLIn+1'
Transfer complete interrupt MSv62637V1

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18.4.9 HPDMA channel state and linked-list programming

The software can reconfigure a channel when the channel is disabled
(HPDMA_CxCR.EN = 0), and update the execution mode (HPDMA_CxCR.LSM) to change
from/to run-to-completion mode to/from link step mode.
In any execution mode, the software can:
• reprogram LLIn+1 in the memory to finally complete the channel by this LLIn+1 (clear the
HPDMA_CxLLR of this LLIn+1), before this LLIn+1 is loaded/used by the HPDMA
channel
• abort and reconfigure the channel with an LSM update (see Section 18.4.4.)
In link step mode, the software can clear LSM after each a single execution of any LLI,
during LLIn-1.
Figure 86 shows the overall and unified HPDMA linked-list programming, whatever is the
execution mode.
Note: Figure 86 is not intended to illustrate how often a TCEF can be raised, depending on the
programmed value of TCEM[1:0] in HPDMA_CxTR2. It can be raised at (each) block
completion, at (each) 2D block completion, at (each) LLI completion, or only at the last LLI
data transfer completion. In run-to-completion mode, whatever is the value of TCEM[1:0], at
the channel completion the hardware always set TCEF = 1 and disables the channel. In link
step mode, the channel is disabled after each single execution of a LLI, and depending on
the value of TCEM[1:0] a TCEF is raised or not.
In Figure 86, BNDT ≠ 0 is the typical condition for starting the first data transfer.
This condition becomes BNDT ≠ 0 and PFREQ = 1 if the peripheral requests a data transfer
with early termination (see Section 18.3.6).

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Figure 86. HPDMA channel execution and linked-list programming

Channel state = Idle

Initialize DMA channel

Reconfigure DMA channel

Enable DMA channel

Channel state = Active

Valid user
setting ? N

Setting USEF = 1
BNDT  0 ? N Disabling DMA channel

Executing once the data

transfer from the register file

No transfer
N
error ?

Y
Setting DTEF = 1
N LLR 0 ? Disabling DMA channel

Loading next LLI

into the register file

No transfer
N
error ?

Y Setting ULEF = 1
Disabling DMA channel

Valid user
N
setting ?
Y Setting USEF = 1
Disabling DMA channel
N LSM = 1 ?
Y
Setting TCF = 1
Disabling DMA channel

End

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18.4.10 HPDMA FIFO-based transfers

There is a single transfer operation mode: the FIFO mode. There are FIFO-based transfers.
Any channel x is implemented with a dedicated FIFO whose size is defined
by dma_fifo_size[x] (see Section 18.3.1 for more details).

HPDMA burst
A programmed transfer at the lowest level is an HPDMA burst.
An HPDMA burst is a burst of data received from the source, or a burst of data sent to the
destination. A source (and destination) burst is programmed with a burst length
by SBL_1[5:0] (respectively DBL_1[5:0]), and with a data width defined by SDW_LOG2[1:0]
(respectively DDW_LOG2[1:0]) in HPDMA_CxTR1.
The addressing mode after each data (named beat) of an HPDMA burst is defined by SINC
and DINC in HPDMA_CxTR1, for source and destination respectively: either a fixed
addressing or an incremented addressing with contiguous data.
The start and next addresses of an HPDMA source/destination burst (defined by
HPDMA_CxSAR and HPDMA_CxDAR) must be aligned with the respective data width.
The table below lists the main characteristics of an HPDMA burst.

Table 92. Programmed HPDMA source/destination burst

Burst Next Next
SAP/DAP Data Burst
SDW_LOG2[1:0] SBL_1[5:0] length data/ burst
(allocated width SINC/DINC address
DDW_LOG2[1:0] DBL_1[5:0] (data/ beat addres
port) (bytes) alignment
beats) address s

00 1 1
0: AXI
01 2 2
1: AHB 0 (fixed) +0 +0
10 4 4
0: AXI 11 8 8
00 1 +1 + (n + 1) 1
n = 0 to 63(1)(2) n+1
+2*
0: AXI 01 2 +2 2
1 (n + 1)
1: AHB
(contiguously +4*
10 4 incremented) +4 4
(n + 1)
+8*
0: AXI 11 8 +8 8
(n + 1)
0: AHB 11 forbidden user setting, causing USEF generation and none burst to be issued.
1. When S/DBL_1[5:0] = 0, burst is of length 1. Then burst can be also named as single.
2. As highlighted in Section 18.3.2, the maximum allowed AXI burst length is 16. The user must set SBL_1[5:0] lower or equal
to 15 if the source allocated port is AXI (if SAP = 0). The user must set DBL_1[5:0] lower or equal to 15 if the destination
allocated port is AXI (if DAP = 0).

The next burst address in the above table is the next source/destination default address
pointed by HPDMA_CxSAR or HPDMA_CxDAR, once the programmed source/destination
burst is completed. This default value refers to the fixed/contiguously incremented address.

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HPDMA burst with 2D addressing (channel x = 12 to 15)

When the channel has additional 2D addressing feature, this default value refers to the
value without taking into account the two programmed incremented or decremented offsets.
These two additional offsets (with a null default value) are applied:
• after each completed source/destination burst, as defined respectively by
HPDMA_CxTR2.SAO[12:0]/DAO[12:0] and HPDMA_CxBR1.SDEC/DDEC
• after each completed block, as defined respectively by
HPDMA_CxBR2.BRSAO[15:0]/BRDAO[15:0] and
HPDMA_CxBR1.BRSDEC/BRDDEC)
Then, a 2D/repeated block can be addressed with a first programmed address jump after
each completed burst, and with a second programmed address jump after each block, as
depicted by Figure 87 with a 2D destination buffer.

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Figure 87. Programmed 2D addressing

Memory

32b
Cx_DAR Data0
Data1
... Burst0
DataI-1
+ DAO
Data0
Data1
... Burst1
DataI-1
+ DAO Block0

+ DAO
Data0
Data1
... BurstJ-1
DataI-1
Memory-mapped + DAO
Peripheral

+ BRDAO
32b
Cx_SAR Data Register Burst0
...

(fixed addressing, + DAO

SINC=0)
... Burst1
Restore Cx_DAR 2D/repeated block
+ DAO Blockk
LLIL

+ DAO

... BurstJ-1

+ DAO

+ BRDAO

Data0
Data1
... Burst0
DataI-1
+ DAO
Data0
Data1
... Burst1
DataI-1
+ DAO BlockK-1

+ DAO
Data0
Data1
... BurstJ-1
Programmable address jumps 1) after burst and 2) after DataI-1
+ DAO
block.
Example:
burst: I * words (DBL_1=I-1; DDW_LOG2=’b10) + BRDAO
block: J * bursts (BNDT=J*I*4)
LLI: K * blocks (BRC=K-1)

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HPDMA FIFO-based burst

In FIFO-mode, a transfer generally consists of two pipelined and separated burst transfers:
• one burst from the source to the FIFO over the allocated source master port, as defined
by HPDMA_CxTR1.SAP
• one burst from the FIFO to the destination over the allocated destination master port,
as defined by HPDMA_CxTR1.DAP

HPDMA source burst

The requested source burst transfer to the FIFO can be scheduled as early as possible over
the allocated port, depending on the current FIFO level versus the programmed burst size
(when the FIFO is ready to get one new burst from the source):
when FIFO level ≤ 2dma_fifo_size[x] - (SBL_1[5:0]+1) * 2SDW_LOG2[1:0]
where:
• FIFO level is the current filling level of the FIFO, in bytes.
• 2dma_fifo_size[x] is the channel x FIFO size, in bytes (see Section 18.3.1 for the
implementation details and dma_fifo_size[x] value).
• (SBL_1[5:0]+1) * 2SDW_LOG2[1:0] is the size of the programmed source burst transfer,
in bytes.
Based on the channel priority (HPDMA_CxCR.PRIO[1:0]), this ready FIFO-based source
transfer is internally arbitrated versus the other requested and active channels.

HPDMA destination burst

The requested destination burst transfer from the FIFO can be scheduled as early as
possible over the allocated port, depending on the current FIFO level versus the
programmed burst size (when the FIFO is ready to push one new burst to the destination):
when FIFO level ≥ (DBL_1[5:0]+1) * 2DDW_LOG2[1:0]
where:
• FIFO level is the current filling level of the FIFO, in bytes.
• (DBL_1[5:0]+1) * 2DDW_LOG2[1:0] is the size of the programmed destination burst
transfer, in bytes.
Based on the channel priority, this ready FIFO-based destination transfer is internally
arbitrated versus the other requested and active channels.

HPDMA burst versus source block size, 1- or 4-Kbyte address boundary and
FIFO size
The programmed source/destination HPDMA burst is implemented with an AHB/AXI burst
as is, unless one of the following conditions is met:
• When half of the FIFO size of the channel x is lower than the programmed
source/destination burst size, the programmed source/destination HPDMA burst is
implemented with a series of singles or bursts of a lower size, each transfer being of a
size that is lower or equal than half of the FIFO size, without any user constraint.
• if the source block size (HPDMA_CxBR1.BNDT[15:0]) is not a multiple of the source
burst size but is a multiple of the data width of the source burst
(HPDMA_CxTR1.SDW_LOG2[1:0]), the HPDMA modifies and shortens bursts into

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singles or bursts of lower length, in order to transfer exactly the source block size,
without any user constraint.
• if the source/destination burst transfer have crossed the 1- or 4-Kbyte address
boundary on, respectively, an AHB or AXI transfer, the HPDMA modifies and shortens
the programmed burst into singles or bursts of lower length, to be compliant with the
AHB/AXI protocol, without any user constraint.
• If the source/destination burst length exceeds 16 on a AHB transfer, or if the
source/destination burst on an AXI transfer is both with fixed addressing and with a
burst length which exceeds 16, the HPDMA modifies and shortens the programmed
burst into singles or bursts of lower length, to be compliant with the AHB/AXI protocol,
without any user constraint.
In any case, the HPDMA keeps ensuring source/destination data (and address) integrity
without any user constraint. The current FIFO level (software readable in HPDMA_CxSR)
is compared to and updated with the effective transfer size, and the HPDMA re-arbitrates
between each AHB/AXI single or burst transfer, possibly modified.
Based on the channel priority, each single or burst of a lower burst size versus the
programmed burst, is internally arbitrated versus the other requested and active channels.
Note: In linked-list mode, the HPDMA read transfers related to the update of the linked-list
parameters from the memory to the internal HPDMA registers, are scheduled over the link
allocated port, as programmed by HPDMA_CxCR.LAP.

HPDMA data handling: byte-based reordering, packing/unpacking,

padding/truncation, sign extension, and left/right alignment
The data handling is controlled by HPDMA_CxTR1. The source/destination data width of
the programmed burst is byte, half-word, word, or double-word, as per SDW_LOG2[1:0] and
DDW_LOG2[1:0] (see Table 93).
The user can configure the data handling between transferred data from the source and
transfer to the destination. More specifically, programmed data handling is orderly
performed with:
1. Byte-based source reordering
– If SBX = 1 and if the source data width is a word or a double-word (for AXI source
bus, SAP = 0), the two bytes of the unaligned half-word at the middle of each
source data word are exchanged.
2. Data-width conversion by packing, unpacking, padding, or truncation, if destination
data width is different than the source data width, depending on PAM[1:0]:
– If destination data width > source data width, the post SBX source data is either
right-aligned and padded with 0s, or sign extended up to the destination data
width, or is FIFO queued and packed up to the destination data width.
– If destination data width < source data width, the post SBX data is either
right-aligned and left-truncated down to the destination data width, or is FIFO
queued and unpacked and streamed down to the destination data width.

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3. Byte-based destination re-ordering:

– If DBX = 1 and if the destination data width is not a byte, the two bytes are
exchanged within the aligned post PAM[1:0] half-words.
– If DHX = 1 and if the destination data width is neither a byte nor a half-word, the
two aligned half-words are exchanged within the aligned post PAM[1:0] words.
– If DWX = 1and if the destination data width is a double-word and the destination
bus is AXI (DAP = 0), the two aligned words are exchanged within aligned
(post PAM[1:0]) double-words).
Note: Left-alignment with 0s-padding can be achieved by programming both a right-alignment with
a 0s-padding, and a destination byte-based re-ordering.
The table below lists the possible data handling from the source to the destination.

Table 93. Programmed data handling

Destination
SDW_ DDW_
Source Source data Destination data

DWX
DBX

DHX
data
SBX

LOG2 LOG2 PAM[1:0](2)

data stream(1) stream(1)
[1:0] [1:0]

B7,B6,B5,B4,B3,B2,B1,
00 Byte xx x
B0
0 0B3,0B2,0B1,0B0
00 (RA, 0P)(3)(4)
1 B30,B20,B10,B00
x
Half- 0 SB3,SB2,SB1,SB0
01 01 (RA, SE)(3)(4)
word 1 B3S,B2S,B1S,B0S
0 B7B6,B5B4,B3B2,B1B0
1x (PACK)
1 B6B7,B4B5,B2B3,B0B1
0 000B1,000B0
0
1 00B10,00B00
B7,B6,B5,B4,B3 00 (RA, 0P)(3)(4)
00 Byte x x
,B2,B1,B0 0 0B100,0B000
1
1 B1000,B0000
0 SSSB1,SSSB0
0
1 SSB1S,SSB0S
10 Word 01 (RA, SE)(3)(4)
0 SB1SS,SB0SS
1
1 B1SSS,B0SSS
0 B7B6B5B4,B3B2B1B0
0
1 B6B7B4B5,B2B3B0B1
1x (PACK)
0 B5B4B7B6,B1B0B3B2
1
1 B4B5B6B7,B0B1B2B3

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Table 93. Programmed data handling (continued)

Destination
SDW_ DDW_
Source Source data Destination data

DWX
DBX

DHX
SBX

data
LOG2 LOG2 PAM[1:0](2)
data stream(1) stream(1)
[1:0] [1:0]

0 0000000B0
0
1 000000B00
0
0 00000B000
1
1 0000B0000
00 (RA, 0P)(3)(4)
0 000B00000
0
1 00B000000
1
0 0B0000000
1
1 B00000000
0 SSSSSSSB0
0
1 SSSSSSB0S
0
0 SSSSSB0SS
1
B7,B6,B5,B4,B3 Double- 1 SSSSB0SSS
00 Byte x 11(5) 01 (RA, SE)(3)(4)
,B2,B1,B0 word 0 SSSB0SSSS
0
1 SSB0SSSSS
1
0 SB0SSSSSS
1
1 B0SSSSSSS
0 B7B6B5B4B3B2B1B0
0
1 B6B7B4B5B2B3B0B1
0
0 B5B4B7B6B1B0B3B2
1
1 B4B5B6B7B0B1B2B3
1x (PACK)
0 B3B2B1B0B7B6B5B4
0
1 B2B3B0B1B6B7B4B5
1
0 B1B0B3B2B5B4B7B6
1
1 B0B1B2B3B4B5B6B7

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Table 93. Programmed data handling (continued)

Destination
SDW_ DDW_
Source Source data Destination data

DWX
DBX

DHX
SBX

data
LOG2 LOG2 PAM[1:0](2)
data stream(1) stream(1)
[1:0] [1:0]

00 (RA, LT)(3) B6,B4,B2,B0

01 (LA, RT)(3) B7,B5,B3,B1
00 Byte x
B7,B6,B5,B4,B3,B2,B1,
1x (UNPACK) x
B0

Half- 0 B7B6,B5B4,B3B2,B1B0
01 xx
word 1 B6B7,B4B5,B2B3,B0B1
0 00B3B2,00B1B0
0
1 B3B200,B1B000
00 (RA, 0P)(3)(4)
0 B2B300,B0B100
Half- B7B6,B5B4, 1
01 x x
word B3B2,B1B0 1 00B2B3,00B0B1
0 SSB3B2,SSB1B0
0
1 B3B2SS,B1B0SS
10 Word 01 (RA, SE)(3)(4)
0 B2B3SS,B0B1SS
1
1 SSB2B3,SSB0B1
0 B7B6B5B4,B3B2B1B0
0
1 B6B7B4B5,B2B3B0B1
1x (PACK)
0 B5B4B7B6,B1B0B3B2
1
1 B4B5B6B7,B0B1B2B3

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Table 93. Programmed data handling (continued)

Destination
SDW_ DDW_
Source Source data Destination data

DWX
DBX

DHX
SBX

data
LOG2 LOG2 PAM[1:0](2)
data stream(1) stream(1)
[1:0] [1:0]

0 000000B1B0
0
1 000000B0B1
0
0 0000B1B000
1
1 0000B1B000
00 (RA, 0P)(3)(4)
0 00B1B00000
0
1 00B0B10000
1
0 B1B0000000
1
1 B0B1000000
- SSSSSSB1B0
0
1 SSSSSSB0B1
0
0 SSSSB1B0SS
1
Half- B7B6,B5B4, Double- 1 SSSSB1B0SS
01 x 11(5) 01 (RA, SE)(3)(4)
word B3B2,B1B0 word 0 SSB1B0SSSS
0
1 SSB0B1SSSS
1
0 B1B0SSSSSS
1
1 B0B1SSSSSS
0 B7B6B5B4B3B2B1B0
0
1 B6B7B4B5B2B3B0B1
0
0 B5B4B7B6B1B0B3B2
1
1 B4B5B6B7B0B1B2B3
1x (PACK)
0 B3B2B1B0B7B6B5B4
0
1 B2B3B0B1B6B7B4B5
1
0 B1B0B3B2B5B4B7B6
1
1 B0B1B2B3B4B5B6B7

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Table 93. Programmed data handling (continued)

Destination
SDW_ DDW_
Source Source data Destination data

DWX
DBX

DHX
SBX

data
LOG2 LOG2 PAM[1:0](2)
data stream(1) stream(1)
[1:0] [1:0]

00 (RA, LT)(3) - B12,B8,B4,B0

01 (LA, RT)(3) - B15,B11,B7,B3
00 Byte
B7,B6,B5,B4,B3,B2,B1,
1x (UNPACK) x
B0
0 B5B4,B1B0
00 (RA, LT)(3) x
1 B4B5,B0B1

Half- 0 B7B6,B3B2
B7B6B5B4, 01 01 (LA, RT)(3)
10 Word 0 word x
B3B2B1B0 1 B6B7,B2B3
0 B7B6,B5B4,B3B2,B1B0
1x (UNPACK)
1 B6B7,B4B5,B2B3,B0B1
0 B7B6B5B4,B3B2B1B0
0
1 B6B7B4B5,B2B3B0B1
10 Word xx
0 B5B4B7B6,B1B0B3B2
1
1 B4B5B6B7,B0B1B2B3

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Table 93. Programmed data handling (continued)

Destination
SDW_ DDW_
Source Source data Destination data

DWX
DBX

DHX
SBX

data
LOG2 LOG2 PAM[1:0](2)
data stream(1) stream(1)
[1:0] [1:0]

0 B7B6B5B4B3B2B1B0
0
1 B6B7B4B5B2B3B0B1
0
0 B5B4B7B6B1B0B3B2
1
1 B4B5B6B7B0B1B2B3
1x (PACK)
0 B3B2B1B0B7B6B5B4
0
1 B2B3B0B1B6B7B4B5
1
0 B1B0B3B2B5B4B7B6
1
1 B0B1B2B3B4B5B6B7
0 0000B3B2B1B0
0
1 0000B2B3B0B1
0
0 0000B1B0B3B2
1
B7B6B5B4, Double- 1 0000B0B1B2B3
10 Word 0 11(5) 00 (RA, 0P)(3)(4)
B3B2B1B0 word 0 B3B2B1B00000
0
1 B1B0B3B20000
1
0 B3B2B1B00000
1
1 B0B1B2B30000
0 SSSSB3B2B1B0
0
1 SSSSB2B3B0B1
0
0 SSSSB1B0B3B2
1
1 SSSSB0B1B2B3
01 (RA, SE)(3)(4)
0 B3B2B1B0SSSS
0
1 B1B0B3B2SSSS
1
0 B3B2B1B0SSSS
1
1 B0B1B2B3SSSS

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Table 93. Programmed data handling (continued)

Destination
SDW_ DDW_
Source Source data Destination data

DWX
DBX

DHX
SBX

data
LOG2 LOG2 PAM[1:0](2)
data stream(1) stream(1)
[1:0] [1:0]

00 (RA, LT)(3) - B12,B8,B4,B0

01 (LA, RT)(3) - B15,B11,B7,B3
00 Byte
B7,B5,B6,B4,B3,B1,B2,
1x (UNPACK) x
B0
0 B6B4,B2B0
00 (RA, LT)(3) x
1 B4B6,B0B2

Half- 0 B7B5,B3B1
B7B6B5B4, 01 01 (LA, RT)(3)
10 Word 1 word x
B3B2B1B0 1 B5B7,B1B3
0 B7B5,B6B4,B3B1,B2B0
1x (UNPACK)
1 B5B7,B4B6,B1B3,B0B2
0 B7B5B6B4,B3B1B2B0
0
1 B5B7B4B6,B1B3B0B2
10 Word xx
0 B6B4B7B5,B2B0B3B1
1
1 B4B6B5B7,B0B2B1B3

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Table 93. Programmed data handling (continued)

Destination
SDW_ DDW_
Source Source data Destination data

DWX
DBX

DHX
SBX

data
LOG2 LOG2 PAM[1:0](2)
data stream(1) stream(1)
[1:0] [1:0]

0 0000B3B1B2B0
0
1 0000B1B3B0B2
0
0 0000B2B0B3B1
1
1 0000B0B2B1B3
00 (RA, 0P)(3)(4)
0 B3B1B2B00000
0
1 B1B3B0B20000
1
0 B2B0B3B10000
1
1 B0B2B1B30000
0 SSSSB3B1B2B0
0
1 SSSSB1B3B0B2
0
0 SSSSB2B0B3B1
1
B7B6B5B4, Double- 1 SSSSB0B2B1B3
10 Word 1 11(5) 01 (RA, SE)(3)(4)
B3B2B1B0 word 0 B3B1B2B0SSSS
0
1 B1B3B0B2SSSS
1
0 B2B0B3B1SSSS
1
1 B0B2B1B3SSSS
0 B7B5B6B4B3B1B2B0
0
1 B5B7B4B6B1B3B0B2
0
0 B6B4B7B5B2B0B3B1
1
1 B4B6B5B7B0B2B1B3
1x (PACK)
0 B3B1B2B0B7B5B6B4
0
1 B1B3B0B2B5B7B4B6
1
0 B2B0B3B1B6B4B7B5
1
1 B0B2B1B3B4B6B5B7

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Table 93. Programmed data handling (continued)

Destination
SDW_ DDW_
Source Source data Destination data

DWX
DBX

DHX
SBX

data
LOG2 LOG2 PAM[1:0](2)
data stream(1) stream(1)
[1:0] [1:0]

00 (RA, LT)(3) - B24,B16,B8,B0

01 (LA, RT)(3) - B31,B23,B15,B7
00 Byte
B7,B6,B5,B4,B3,B2,B1,
1x (UNPACK) x
B0
0 B9B8,B1B0
00 (RA, LT)(3) x
1 B8B9,B0B1

Half- 0 B15B14,B7B6
01 01 (LA, RT)(3)
word 1 B14B15,B6B7
0 B7B6,B5B4,B3B2,B1B0
1x (UNPACK)
1 B6B7,B4B5,B2B3,B0B1
B11B10B9B8,
0
B3B2B1B0
0
B10B11B8B9,
1
B2B3B0B1
Double B7B6B5B4B3B2 00 (RA, LT)(3)
11(6) 0 x B9B8B11B10,
-word B1B0 0
B1B0B3B2
1
B8B9B10B11,
1
B0B1B2B3
B15B14B13B12,
0
B7B6B5B4
0
10 Word B14B15B12B13,
1
B6B7B4B5
01 (LA, RT)(3)
B13B12B15B14,
0
B5B4B7B6
1
B12B13B14B15,
1
B4B5B6B7
0 B7B6B5B4,B3B2B1B0
0
1 B6B7B4B5,B2B3B0B1
1x (UNPACK)
0 B5B4B7B6,B1B0B3B2
1
1 B4B5B6B7,B0B1B2B3

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Table 93. Programmed data handling (continued)

Destination
SDW_ DDW_
Source Source data Destination data

DWX
DBX

DHX
SBX

data
LOG2 LOG2 PAM[1:0](2)
data stream(1) stream(1)
[1:0] [1:0]

0 B7B6B5B4B3B2B1B0
0
1 B6B7B4B5B2B3B0B1
0
0 B5B4B7B6B1B0B3B2
1
Double- 1 B4B5B6B7B0B1B2B3
0 11(5) xx
word 0 B3B2B1B0B7B6B5B4
0
1 B2B3B0B1B6B7B4B5
1
0 B1B0B3B2B5B4B7B6
1
1 B0B1B2B3B4B5B6B7
Double B7B6B5B4B3B2 00 (RA, LT)(3) B24,B16,B8,B0
11(6)
-word B1B0
01 (LA, RT)(3) B31,B23,B15,B7
00 Byte x
B7,B5,B6,B4,B3,B1,B2,
1x (UNPACK)
B0
0 B10B8,B2B0
1 00 (RA, LT)(3) x x
1 B8B10,B0B2

Half- 0 B15B13,B7B5
01 01 (LA, RT)(3)
word 1 B13B15,B5B7
0 B7B5,B6B4,B3B1,B2B0
1x (UNPACK)
1 B5B7,B4B6,B1B3,B0B2

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Table 93. Programmed data handling (continued)

Destination
SDW_ DDW_
Source Source data Destination data

DWX
DBX

DHX
SBX

data
LOG2 LOG2 PAM[1:0](2)
data stream(1) stream(1)
[1:0] [1:0]

0 B11B9B10B8,B3B1B2B0
0
1 B9B11B8B10,B1B3B0B2
00 (RA, LT)(3)
0 B10B8B11B9,B2B0B3B1
1
1 B8B10B9B11,B0B2B1B3
B15B13B14B12,
0
B7B5B6B4
0
B13B15B12B14,
1
B5B7B4B6
10 Word 01 (LA, RT)(3) x
B14B12B15B13,
0
B6B4B7B5
1
B12B14B13B15,
1
B4B6B5B7
Double B7B6B5B4B3B2 0 B7B5B6B4,B3B1B2B0
11(6) 1
-word B1B0 0
1 B5B7B4B6,B1B3B0B2
1x (UNPACK)
0 B6B4B7B5,B2B0B3B1
1
1 B4B6B5B7,B0B2B1B3
0 B7B5B6B4B3B1B2B0
0
1 B5B7B4B6B1B3B0B2
0
0 B6B4B7B5B2B0B3B1
1
Double- 1 B4B6B5B7B0B2B1B3
11(5) xx
word 0 B3B1B2B0B7B5B6B4
0
1 B1B3B0B2B5B7B4B6
1
0 B2B0B3B1B6B4B7B5
1
1 B0B2B1B3B4B6B5B7
1. Data stream is timely ordered starting from the byte with the lowest index (B0).
2. RA= right aligned, LA = left aligned, RT = right truncated, LT = left truncated, 0P = zero bit padding up to the destination data
width, SE = sign bit extended up to the destination data width.
3. RA= right aligned. LA = left aligned. RT = right truncated. LT = left truncated.
4. 0P= zero-bit padding up to the destination data width. SE = sign bit extended up to the destination data width.
5. if DDW_LOG2[1:0] = 11 and if DAP = 0 (destination allocated port is AXI). Else if DDW_LOG2[1:0] = 11 and
DAP = 1 (AHB), a user setting error (USEF) is reported.
6. if SDW_LOG2[1:0] = 11 and if SAP = 0 (source allocated source port is AXI). Else if SDW_LOG2[1:0] = 11 and
SAP = 1 (AHB), a user setting error (USEF) is reported.

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18.4.11 HPDMA transfer request and arbitration

HPDMA transfer request
As defined by HPDMA_CxTR2, a programmed HPDMA data transfer is requested with one
of the following:
• a software request if the control bit SWREQ = 1: This is used typically by the CPU for
a data transfer from a memory-mapped address to another memory mapped address
(memory-to-memory, GPIO to/from memory)
• an input hardware request coming from a peripheral if SWREQ = 0: The selection of
the HPDMA hardware peripheral request is driven by REQSEL[7:0]
(see Section 18.3.5). The selected hardware request can be one of the following:
– an hardware request from a peripheral configured in HPDMA mode (for a transfer
from/to the peripheral data register respectively to/from the memory)
– an hardware request from a peripheral for its control register update from
the memory
– an hardware request from a peripheral for a read of its status registers transferred
to the memory
Caution: The user must not assign the same input hardware peripheral HPDMA request
via HPDMA_CxTR.REQSEL[7:0] to two different channels, if at a given time this request is
asserted by the peripheral, and each channel is ready to execute this requested data
transfer. There is no user setting error reporting.

HPDMA transfer request for arbitration

A ready FIFO-based HPDMA source single/burst transfer (from the source address to the
FIFO) to be scheduled over the allocated master port (HPDMA_CxTR1.SAP) is arbitrated
based on the channel priority (HPDMA_CxCR.PRIO[1:0]) versus the other simultaneous
requested HPDMA transfers to the same master port.
A ready FIFO-based HPDMA destination single/burst transfer (from the FIFO to the
destination address) to be scheduled over the allocated master port (HPDMA_CxTR1.DAP)
is arbitrated based on the channel priority (HPDMA_CxCR.PRIO[1:0]) versus the other
simultaneous requested HPDMA transfers to the same master port.
An arbitrated HPDMA requested link transfer consists of one 32-bit read from the linked-list
data structure in the memory to one of the linked-list registers (HPDMA_CxTR1,
HPDMA_CxTR2, HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR, HPDMA_CxTR3,
HPDMA_CxBR2 or HPDMA_CxLLR). Each 32-bit read from the memory is arbitrated with
the same channel priority as for data transfers, in order to be scheduled over the allocated
master port (HPDMA_CxCR.LAP).
Whatever the requested data transfer is programmed with a software request for a
memory-to- memory transfer (HPDMA_CxTR2.SWREQ = 1), or with a hardware request
(HPDMA_CxTR2.SWREQ = 0) for a memory-to-peripheral transfer or a peripheral-to-
memory transfer and whatever is the hardware request type, re-arbitration occurs after each
granted single/burst transfer.
When an hardware request is programmed from a destination peripheral
(HPDMA_CxTR2.SWREQ = 0 and HPDMA_CxTR2.DREQ = 1), the first memory read of a
(possibly 2D/repeated) block (the first ready FIFO-based source burst request), is gated by
the occurrence of the corresponding and selected hardware request. This first read request

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to memory is not taken into account earlier by the arbiter (not as soon as the block transfer
is enabled and executable).

HPDMA arbitration
The HPDMA arbitration is directed from the 4-grade assigned channel priority
(HPDMA_CxCR.PRIO[1:0]). The arbitration policy, as illustrated in Figure 88, is defined by:
• one high-priority traffic class (queue 3), dedicated to the assigned channels with
priority 3, for time-sensitive channels
This traffic class is granted via a fixed-priority arbitration against any other low-priority
traffic class. Within this class, requested single/burst transfers are round-robin
arbitrated.
• three low-priority traffic classes (queues 0, 1 or 2) for non time-sensitive channels with
priority 0, 1 or 2
Each requested single/burst transfer within this class is round-robin arbitrated, with a
weight that is monotonically driven from the programmed priority:
– Requests with priority 0 are allocated to the queue 0.
– Requests with priority 1 are allocated and replicated to the queue 0 and queue 1.
– Requests with priority 2 are allocated and replicated to the queue 0, queue 1, and
queue 2.
– Any queue 0, 1 or 2 equally grants any of its active input requests in a round-robin
manner, provided there are simultaneous requests.
– Additionally, there is a second stage for the low-traffic with a round-robin arbiter
that fairly alternates between simultaneous selected requests from queue 0,
queue 1 and queue 2.

Figure 88. HPDMA arbitration policy

Request from any channel x

Queue 0
being assigned with HPDMA_CxCR.PRIO = 0 RRA

Request from any channel x Low FPA

Queue 1
RRA
Granted
being assigned with HPDMA_CxCR.PRIO = 1 RRA request
Request from any channel x Queue 2 High
being assigned with HPDMA_CxCR.PRIO = 2 RRA

Request from any channel x Queue 3

being assigned with HPDMA_CxCR.PRIO = 3 RRA

HPDMA arbitration
RRA = round-robin arbitration, FPA = fixed-priority arbitration MSv66927V1

HPDMA arbitration and bandwidth

With this arbitration policy, the following is guaranteed:
• equal maximum bandwidth between requests with same priority
• reserved bandwidth (noted as BQ3) to the time-sensitive requests (with priority 3)
• residual weighted bandwidth between different low-priority requests (priority 0 versus
priority 1 versus priority 2).

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The two following examples highlight that the weighted round-robin arbitration is driven by
the programmed priorities:
• Example 1: basic application with two non time-sensitive HPDMA requests: req0 and
req1. There are the following programming possibilities:
– If they are assigned with same priority, the allocated bandwidth by the arbiter to
req0 (Breq0) is equal to the allocated bandwidth to req1(Breq1).
Breq0 = Breq1 = 1/2 * (1 - BQ3)
– If req0 is assigned to priority 0 and req1 to priority 1, the allocated bandwidth to
req0 (BP0) is 3 times less than the allocated bandwidth to req1 (BP1).
Breq0 = BP0 = 1/2 * 1/2 * (1 - BQ3) = 1/4 * (1 - BQ3)
Breq1 = BP1 = (1/2 + 1) * 1/2 * (1 - BQ3) = 3/4 * (1 - BQ3)
– If req0 is assigned to priority 0 and req1 to priority 2, the allocated bandwidth to
req0 (BP0) is 5 times less than the allocated bandwidth to req1 (BP2).
Breq0 = BP0 = 1/2 * 1/3 * (1 - BQ3) = 1/6 * (1 - BQ3)
Breq1 = BP2 = (1/2 + 1 +1) * 1/3 * (1 - BQ3) = 5/6 * (1 - BQ3)
The above computed bandwidth calculation is based on a theoretical input request,
always active for any HPDMA clock cycle. This computed bandwidth from the arbiter
must be weighted by the frequency of the request given by the application, that cannot
be always active and may be quite much variable from one HPDMA client (example
I2C at 400 kHz) to another one (PWM at 1 kHz) than the above x3 and x5 ratios.
• Example 2: application where the user distributes a same non-null N number of
HPDMA requests to every non time-sensitive priority 0, 1 and 2. The bandwidth
calculation is then the following:
– The allocated bandwidth to the set of requests of priority 0 (BP0) is
BP0 = 1/3 * 1/3 * (1 - BQ3) = 1/9 * (1 - BQ3)
– The allocated bandwidth to the set of requests of priority 1(BP1) is
BP1 = (1/3 + 1/2) * 1/3 * (1 - BQ3) = 5/18 * (1 - BQ3)
– The allocated bandwidth to the set of requests of priority 2(BP2) is
BP2 = (1/3 + 1/2 + 1) * 1/3 * (1 - BQ3) = 11/18 * (1 - BQ3)
– The allocated bandwidth to any request n (Bn) among the N requests of that
priority Pi (i = 0 to 2) is Bn = 1/N * BPi
– The allocated bandwidth to any request n of priority 0i (Bn, Pi) is
Bn, P0 = 1/N *1/9 * (1 - BQ3)
Bn, P1 = 1/N *5/18 * (1 - BQ3)
Bn, P2 = 1/N *11/18 * (1 - BQ3)
In this example, when the master port bus bandwidth is not totally consumed by the
time-sensitive queue 3, the residual bandwidth is such that 2.5 times less bandwidth
is allocated to any request of priority 0 versus priority 1, and 5.5 times less bandwidth
is allocated to any request of priority 0 versus priority 2.

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More generally, assume that the following requests are present:

• I requests (I ≥ 0) assigned to priority 0
If I > 0, these requests are noted from i = 0 to I-1.
• J requests (J ≥ 0) assigned to priority 1
If J > 0, these requests are noted from j = 0 to J-1.
• K requests (K > 0) assigned to priority 2
These requests are noted from k = 0 to K-1
• L requests (L ≥ 0) assigned to priority 3
If L > 0, these requests are noted from l = 0 to L-1.
As BQ3 is the reserved bandwidth to time-sensitive requests, the bandwidth for each request
L with priority 3 is:
• Bl = BQ3 / L for L > 0 (else: Bl = 0)
The bandwidth for each non-time sensitive queue is:
• BQ0 = 1/3 * (1 - BQ3)
• BQ1 = 1/3 * (1 - BQ3)
• BQ2 = 1/3 * (1 - BQ3)
The bandwidth for the set of requests with priority 0 is:
• BP0 = I / (I + J + K) * BQ0
The bandwidth for each request i with priority 0 is:
• Bi = BP0 / I for L > 0 (else BP0 = 0)
The bandwidth for the set of requests with priority 1 and routed to queue 0 is:
• BP1,Q0 = J / (I + J + K) * BQ0
The bandwidth for the set of requests with priority 1 and routed to queue 1 is:
• BP1,Q1 = J / (J + K) * BQ1
The total bandwidth for the set of requests with priority 1 is:
• BP1 = BP1,Q0 + BP1,Q1
The bandwidth for each request j with priority 1 is:
• Bj = BP1 / J for J > 0 (else Bj = 0)
The bandwidth for the set of requests with priority 2 and routed to queue 0 is:
• BP2,Q0 = K / (I + J + K) * BQ0
The bandwidth for the set of requests with priority 2 and routed to queue 1 is:
• BP2,Q1 = K / (J + K) * BQ1
The bandwidth for the set of requests with priority 2 and routed to queue 2 is:
• BP2,Q2 = BQ2
The total bandwidth for the set of requests with priority 2 is:
• BP2 = BP2,Q0 + BP2,Q1+ BP2,Q2
The bandwidth for each request k with priority 2 is:
• Bk = BP2 / K (K>0 in the general case)

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Thus finally the maximum allocated residual bandwidths for any i, j, k non-time sensitive
request are:
• in the general case (when there is at least one request k with a priority 2 (K > 0)):
– Bi = 1/I * 1/3 * I/(I + J + K) * (1 - BQ3)
– Bj = 1/J * 1/3 *[J/(I + J + K) + J/(J + K)] * (1 - BQ3)
– Bk = 1/K * 1/3 *[K/(I + J + K) + K/(J + K) + 1] * (1 - BQ3)
• in the specific case (when there is no request k with a priority 2 (K = 0)):
– Bi = 1/I * 1/2 * I/(I + J) * (1 - BQ3)
– Bj = 1/J * 1/2 *[J/(I + J) + 1] * (1 - BQ3)
Consequently, the HPDMA arbiter can be used as a programmable weighted bandwidth
limiter, for each queue and more generally for each request/channel. The different weights
are monotonically resulting from the programmed channel priorities.

18.4.12 HPDMA triggered transfer

A programmed HPDMA transfer can be triggered by a rising/falling edge of a selected input
trigger event, as defined by HPDMA_CxTR2.TRIGPOL[1:0] and
HPDMA_CxTR2.TRIGSEL[6:0] (see Section 18.3.7 for the trigger selection).
The triggered transfer, as defined by the trigger mode in HPDMA_CxTR2.TRIGM[1:0], can
be at LLI data transfer level, to condition the first burst read of a block, the first burst read of
a 2D/repeated block (for channel x = 12 to 15), or each programmed burst read/write.
The trigger mode can also be programmed to condition the LLI link transfer
(see TRIGM[1:0] in HPDMA channel x transfer register 2 (HPDMA_CxTR2) for more
details).

Trigger hit memorization and trigger overrun flag generation

The HPDMA monitoring of a trigger for a channel x is started when the channel is
enabled/loaded with a new active trigger configuration: rising or falling edge on a selected
trigger (respectively TRIGPOL[1:0] = 01 or TRIGPOL[1:0] = 10).
The monitoring of this trigger is kept active during the triggered and uncompleted (data or
link) transfer. If a new trigger is detected, this hit is internally memorized to grant the next
transfer, as long as the defined rising/falling edge and TRIGSEL[6:0] are not modified, and
the channel is enabled.
Transferring a next LLIn+1, that updates HPDMA_CxTR2 with a new value for any of
TRIGSEL[6:0] or TRIGPOL[1:0], resets the monitoring, trashing the possible memorized hit
of the formerly defined LLIn trigger.
Caution: After a first new trigger, hitn+1 is memorized. If another trigger hitn+2 is detected, and if
the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized. A trigger
overrun flag is reported (HPDMA_CxSR.TOF = 1) and an interrupt is generated if enabled
(if HPDMA_CxCR.TOIE = 1). The channel is not automatically disabled by hardware due to
a trigger overrun.

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The figure below illustrates the trigger hit, memorization, and overrun in the configuration
example with a block-level trigger mode and a rising edge trigger polarity.

Figure 89. Trigger hit, memorization and overrun waveform

Channel state IDLE ACTIVE

Trigger

Peripheral
request

DMA transfer block transfer block transfer block transfer

Trigger monitoring
Idle Active (monitoring) Active Active Active Active Active Active
state

Trigger monitoring Hit and Hit and Fire Hit and Hit and Fire
action fire memorize memorize trash

Trigger overrun

Hit and trash Hit and fire (or fire alone) Hit and memorize
MSv66923V1

Note: The user can assign the same input trigger event to different channels. This can be used
to trigger different channels on a broadcast trigger event.

18.4.13 HPDMA circular buffering with linked-list programming

HPDMA circular buffering for memory-to-peripheral and
peripheral-to-memory transfers, with a linear addressing channel
For a circular buffering, with a continuous memory-to-peripheral (or peripheral-to-memory)
transfer, the software must set up a channel with half-transfer and complete-transfer
event/interrupt generation (HPDMA_CxCR.HTIE = 1 and HPDMA_CxCR.TCIE = 1),
in order to enable a concurrent buffer software processing.
LLI0 is configured for the first block transfer with the linear addressing channel.
A continuously-executed LLI1 is needed to restore the memory source (or destination) start
address for the memory-to-peripheral transfer (respectively the peripheral-to-memory).
The HPDMA automatically reloads the initially programmed HPDMA_CxBR1.BNDT[15:0]
when a block transfer is completed, and there is no need to restore HPDMA_CxBR1.

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The figure below illustrates this programming with a linear addressing HPDMA channel and
a source circular buffer.

Figure 90. HPDMA circular buffer programming: update of the memory start address
with a linear addressing channel

Req=PERIPH_TX Req=PERIPH_TX

Reset
Restore
Init/LLI0
SAR/LLI1

Channel x
Ht+ tcf Ht+ tcf

Linked-list register file

LLI0
DMA_CxTR1 Memory
CxLBA (LA = 0)
DMA_CxTR2 USA = 1
LLI1
DMA_CxBR1 others Uxx = 0
DMA_CxSAR
DMA_CxSAR
DMA_CxDAR
DMA_CxLLR
MSv62640V1

Note: With a 2D addressing channel, a single LLI can be used with

HPDMA_CxBR1.BRC[10:0] = 1. The user can program a negative memory block address
offset with HDMA_CxBR2 and HDMA_CxBR1, in order to jump back to the memory source
or destination start address.
If the circular buffering must be executed after some other transfers over the shared
HPDMA channel x, the before-last LLIN-1 in the memory is needed to configure the first
block transfer. The last LLIN restores the memory source (or destination) start address
in memory-to-peripheral transfer (respectively in peripheral-to-memory).

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The figure below illustrates this programming with a linear addressing shared HPDMA
channel, and a source circular buffer.

Figure 91. Shared HPDMA channel with circular buffering: update of the memory
start address with a linear addressing channel
Req=PERIPH_TX Req=PERIPH_TX

Reset
Init/LLI0 LLI1 ... LLIN-1 LLIN

Channel X Ht+ tcf Ht+ tcf

Memory
LLIN-2 LLIN-1
All Uxx=1
DMA_Cx... DMA_CxTR1

DMA_Cx... DMA_CxTR2
DMA_Cx... DMA_CxBR1

DMA_CxLLR LLIN DMA_CxSAR

DMA_CxDAR
DMA_CxLLR

USA = 1, others Uxx = 0 LA+ = 0xC MSv62641V1

18.4.14 HPDMA transfer in peripheral flow-control mode

A peripheral with the peripheral flow-control mode feature can decide to early terminate
an HPDMA block transfer, provided that the allocated channel is implemented with this
feature (see Section 18.3.6).
If the related HPDMA channel x is also programmed in peripheral flow-control mode
(HPDMA_CxTR2.PFREQ = 1):
• The HPDMA block transfer starts as follows:
– If HPDMA_CxBR1.BNDT[15:0] ≠ 0, the programmed value is internally taken into
account by the HPDMA hardware.
– If HPDMA_CxBR1.BNDT[15:0] = 0, the HPDMA hardware internally considers
a 64-Kbyte value for the maximum source block size to be transferred.
• The HPDMA block transfer is completed as soon as the first occurrence of any of the
following condition occurs:
– when HPDMA_CxBR1.BNDT[15:0] = 0
– when the peripheral early terminates the block. The complete transfer event is
generated if programmed, depending on HPDMA_CxTR2. Then the software can
read the current number of transferred bytes from the source
(HPDMA_CxBR1.BNDT[15:0]), and/or read the current source or destination
address of the buffer in memory (HPDMA_CxSAR[31:0] or
HPDMA_CxDAR[31:0]).

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In peripheral flow-control mode:

• a destination peripheral with an hardware requested transfer is not supported:
memory-to-peripheral transfer is not supported.
• Data packing from a source peripheral is not supported.
• 2D/repeated block is not supported.
• HPDMA_CxBR1.BNDT[15:0] must be programmed as a multiple of the source
(peripheral) burst size.

18.4.15 HPDMA secure/nonsecure channel

The HPDMA controller is compliant with the TrustZone hardware architecture at channel
level, partitioning all its resources so that they exist in one of the secure and nonsecure
worlds at any given time.
Any channel x is a secure or nonsecure hardware resource, as configured
by HPDMA_SECCFGR.SECx.
When a channel x is configured in secure state by a secure and privileged agent,
the following access control rules are applied:
• A nonsecure read access to a bitfield of this channel is forced to return 0, except for
HPDMA_SECCFGR, HPDMA_PRIVCFGR, HPDMA_RCFGLOCKR, and
HPDMA_CxSEMCR that are readable by a nonsecure agent.
• A nonsecure write access to a bitfield of this channel has no impact.
When a channel x is configured in secure state, a secure agent can configure separately
as secure or nonsecure the HPDMA data transfer from the source (HPDMA_CxTR1.SSEC),
and to the destination (HPDMA_CxTR1.DSEC).
When a channel x is configured in secure state and in linked-list mode, the loading of the
next linked-list data structure from the HPDMA memory into its register file, is automatically
performed with secure transfers via the HPDMA_CxCR.LAP allocated master port.
The HPDMA generates a secure bus that reflects HPDMA_SECCFGR, to keep the other
peripherals informed of the secure/nonsecure state of each HPDMA channel x.
The HPDMA also generates a security illegal access pulse signal on an illegal nonsecure
access to a secure HPDMA register. This signal is routed to the TrustZone interrupt
controller.
When the secure software must switch a channel from a secure state to a nonsecure state,
the secure software must abort the channel or wait until the secure channel is completed
before switching. This is needed to dynamically re-allocate a channel to a next nonsecure
transfer as a nonsecure software is not allowed to do so, and must have
HPDMA_CxCR.EN = 0 before the nonsecure software can reprogram HPDMA_CxCR for
a next transfer. The secure software can reset not only the channel x
(HPDMA_CxCR.RESET = 1), but also the full channel x register file to its reset value.

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18.4.16 HPDMA privileged/unprivileged channel

Any channel x is a privileged or unprivileged hardware resource, as configured by a
privileged agent via HPDMA_PRIVCFGR.PRIVx.
When a channel x is configured in a privileged state by a privileged agent, the following
access control rules are applied:
• An unprivileged read access to a bitfield of this channel is forced to return 0, except for
HPDMA_PRIVCFGR, HPDMA_SECCFGR, HPDMA_CxCIDCFGR and
HPDMA_CxSEMCR that are readable by an unprivileged agent.
• An unprivileged write access to a bitfield of this channel has no impact.
When a channel is configured in a privileged (or unprivileged) state, the source and
destination data transfers are privileged (respectively unprivileged) transfers over
the AHB/AXI master port.
When a channel is configured in a privileged (or unprivileged) state and in linked-list mode,
the loading of the next linked-list data structure from the HPDMA memory into its register
file, is automatically performed with privileged (respectively unprivileged) transfers,
via the HPDMA_CxCR.LAP allocated master port.
The HPDMA generates a privileged bus that reflects HPDMA_PRIVCFGR, to keep the other
peripherals informed of the privileged/unprivileged state of each HPDMA channel x.
Additionally, the HPDMA generates a privileged illegal access pulse signal on an illegal
unprivileged access to a privileged HPDMA register. This signal can be used or not,
depending on the product (see the system security section for more details).
When the privileged software must switch a channel from a privileged state to
an unprivileged state, the privileged software must abort the channel, or wait until the
privileged channel is completed before switching. This is needed to dynamically re-allocate
a channel to a next unprivileged transfer, as an unprivileged software is not allowed to do
so, and must have HPDMA_CxCR.EN = 0 before the unprivileged software can reprogram
the HPDMA_CxCR for a next transfer. The privileged software can reset not only the
channel x (HPDMA_CxCR.RESET = 1), but also the full channel x register file to its reset
value.

HPDMA compartmented channel

The HPDMA controller performs bus transfers over its master port, under the control of
a resource isolation domain identification named compartment identification (CID),
at a channel level. For more details about resource isolation and CID, refer to the RIF
section in the product reference manual.

18.4.17 HPDMA error management

The HPDMA can manage and report to the user a transfer error, as follows, depending on
the root cause.

Data transfer error

On a bus access (as an AHB/AXI single or a burst) to the source or the destination
• The source or destination target reports an AHB/AXI error.
• The programmed channel transfer is stopped (HPDMA_CxCR.EN cleared by the
HPDMA hardware). The channel status register reports an idle state
(HPDMA_CxSR.IDLEF = 1) and the data error (HPDMA_CxSR.DTEF = 1).

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• After an HPDMA data transfer error, the user must perform a debug session, taking
care of the product-defined memory mapping of the source and destination, including
the protection attributes.
• After an HPDMA data transfer error, the user must issue a channel reset
(set HPDMA_CxCR.RESET) to reset the hardware HPDMA channel data path and the
FIFO content, before the user enables again the same channel for a next transfer.

Link transfer error

On a tentative update of a HPDMA channel register from the programmed LLI in the
memory:
• The linked-list memory reports an AHB/AXI error.
• The programmed channel transfer is stopped (HPDMA_CxCR.EN cleared by the
HPDMA hardware), the channel status register reports an idle state
HPDMA_CxSR.IDLEF = 1), and the link error (HPDMA_CxSR.ULEF = 1).
• After an HPDMA link error, the user must perform a debug session, taking care of the
product-defined memory mapping of the linked-list data structure (HPDMA_CxLBAR
and HPDMA_CxLLR), including the protection attributes.
• After an HPDMA link error, the user must explicitly write the linked-list register file
(HPDMA_CxTR1, HPDMA_CxTR2, HPDMA_CxBR1, HPDMA_CxSAR,
HPDMA_CxDAR, and HPDMA_CxLLR, plus HPDMA_CxTR3 and HPDMA_CxBR2
when present), before the user enables again the same channel for a next transfer.

User setting error

On a tentative execution of an HPDMA transfer with an unauthorized user setting:
• The programmed channel transfer is disabled (HPDMA_CxCR.EN forced and cleared
by the HPDMA hardware), preventing the next unauthorized programmed data transfer
from being executed. The channel status register reports an idle state
(HPDMA_CxSR.IDLEF = 1), and a user setting error (HPDMA_CxSR.USEF = 1).
• After an HPDMA user setting error, the user must perform a debug session, taking care
of the HPDMA channel programming. A user setting error can be caused by one of the
following:
– a programmed null source block size without a programmed update of this value
from the next LLI1 (HPDMA_CxBR1.BNDT[15:0] = 0 and
HPDMA_CxLLR.UB1 = 0)
– a programmed non-null source block size being not a multiple of the programmed
data width of a source burst transfer (HPDMA_CxBR1.BNDT[2:0] versus
HPDMA_CxTR1.SDW_LOG2[1:0])
– when in packing/unpacking mode (if PAM[1] = 1), a programmed non-null source
block size being not a multiple of the programmed data width of a destination burst
transfer (HPDMA_CxBR1.BNDT[2:0] versus HPDMA_CxTR1.DDW_LOG2[1:0])
– when in packing/unpacking mode (if PAM[1] = 1), a programmed non-null source
block size being not a multiple of the programmed data width of a destination burst
transfer (HPDMA_CxBR1.BNDT[2:0] versus HPDMA_CxTR1.DDW_LOG2[1:0])
– a programmed unaligned source start address being not a multiple of
the programmed data width of a source burst transfer (HPDMA_CxSAR[2:0]
versus HPDMA_CxTR1.SDW_LOG2[1:0])

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– for channel x =12 to 15, a programmed unaligned source address offset being not
a multiple of the programmed data width of a source burst transfer
(HPDMA_CxTR3.SAO[2:0] versus HPDMA_CxTR1.SDW_LOG2[1:0])
– for channel x =12 to 15, a programmed unaligned block repeated source address
offset being not a multiple of the programmed data width of a source burst transfer
(HPDMA_CxBR2.BRSAO[2:0] versus HPDMA_CxTR1.SDW_LOG2[1:0])
– a programmed unaligned destination start address, being not a multiple of the
programmed data width of a destination burst transfer (HPDMA_CxDAR[2:0]
versus HPDMA_CxTR1.DDW_LOG2[1:0])
– for channel x =12 to 15, a programmed unaligned destination address offset being
not a multiple of the programmed data width of a destination burst transfer
(HPDMA_CxTR3.DAO[2:0] versus HPDMA_CxTR1.DDW_LOG2[1:0])
– for channel x =12 to 15, a programmed unaligned block repeated destination
address offset being not a multiple of the programmed data width of a destination
burst transfer (HPDMA_CxBR2.BRDAO[2:0] versus
HPDMA_CxTR1.DDW_LOG2[1:0])
– a programmed double-word source data width and a programmed AHB source
allocated port (HPDMA_CxTR1.SDW_LOG2[1:0] = 11 and
HPDMA_CxTR1.SAP = 1)
– a programmed double-word destination data width and a programmed AHB
destination allocated port (HPDMA_CxTR1.DDW_LOG2[1:0] = 11 and
HPDMA_CxTR1.DAP = 1)
– a programmed linked-list item LLIn+1 with a null data transfer
(HPDMA_CxLLR.UB1 = 1 and HPDMA_CxBR1. BNDT = 0)

18.5 HPDMA in debug mode

When the device enters debug mode (core halted), any channel x can be individually either
continued (default) or suspended, depending on the programmable control bit
in the DBGMCU module.
Note: In debug mode, HPDMA_CxSR.SUSPF is not altered by a suspension from the
programmable control bit in the DBGMCU module. In this case, HPDMA_CxSR.IDLEF can
be checked to know the completion status of the channel suspension.

18.6 HPDMA in low-power modes

Table 94. Effect of low-power modes on HPDMA
Mode Description

Sleep No effect. HPDMA interrupts cause the device to exit Sleep mode.
(1)
Stop The content of HPDMA registers is kept when entering Stop mode.
Standby The HPDMA is powered down, and must be reinitialized after exiting Standby mode.
1. Refer to Section 18.3.3 to know which Stop mode is supported.

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18.7 HPDMA interrupts

There is one HPDMA interrupt line for each channel, and separately for each CPU
(if several ones in the devices).

Table 95. HPDMA interrupt requests

Interrupt Interrupt
Interrupt enable Event flag Event clear method
acronym event

Transfer
HPDMA_CxCR.TCIE HPDMA_CxSR.TCF Writes 1 to HPDMA_CxFCR.TCF
complete
Half transfer HPDMA_CxCR.HTIE HPDMA_CxSR.HTF Writes 1 to HPDMA_CxFCR.HTF
Data transfer
HPDMA_CxCR.DTEIE HPDMA_CxSR.DTEF Writes 1 to HPDMA_CxFCR.DTEF
error
HPDMA_CHx

Update link
HPDMA_CxCR.ULEIE HPDMA_CxSR.ULEF Writes 1 to HPDMA_CxFCR.ULEF
error
User setting
HPDMA_CxCR.USEIE HPDMA_CxSR.USEF Writes 1 to HPDMA_CxFCR.USEF
error
Suspended HPDMA_CxCR.SUSPIE HPDMA_CxSR.SUSPF Writes 1 to HPDMA_CxFCR.SUSPF
Trigger
HPDMA_CxCR.TOFIE HPDMA_CxSR.TOF Writes 1 to HPDMA_CxFCR.TOF
overrun

An HPDMA channel x event can be:

• a transfer complete
• an half-transfer complete
• a transfer error, due to either:
– a data transfer error
– an update link error
– a user setting error completed suspension
• a trigger overrun
Note: When a channel x transfer complete event occurs, the output signal hpdma_chx_tc is
generated as a high pulse of one clock cycle.
An interrupt is generated following any xx event, provided that both:
• the corresponding interrupt event xx is enabled (HPDMA_CxCR.xxIE = 1)
• the corresponding event flag is cleared (HPDMA_CxSR.xxF = 0). This means that,
after a previous same xx event occurrence, a software agent must have written 1 into
the corresponding xx flag clear control bit (write 1 into HPDMA_CxFCR.xxF).
TCF (transfer complete) and HTF (half transfer) events generation is controlled by
HPDMA_CxTR2.TCEM[1:0] as follows:
• A transfer-complete event is a block transfer complete, a 2D/repeated block transfer
complete, or a LLI transfer complete including the upload of the next LLI if any, or the
full linked-list completion, depending on the transfer complete event mode
HPDMA_CxTR2.TCEM[1:0].
• A half-transfer event is an half-block transfer, or a half 2D/repeated block transfer,
depending on the transfer complete event mode HPDMA_CxTR2.TCEM[1:0].

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An half-block transfer occurs when half of the source block size bytes (rounded-up
integer of HPDMA_CxBR1.BNDT[15:0] / 2) is transferred to the destination.
An half 2D/repeated block transfer occurs when half of the repeated blocks
(rounded-up integer of (HPDMA_CxBR1.BRC[10:0] + 1) / 2) is transferred to the
destination.
See HPDMA channel x transfer register 2 (HPDMA_CxTR2) for more details.
Note: The interrupt mode must be used (not the polling mode) to be notified on an half transfer
when the write data transaction has been completed over the AXI destination allocated port
(written at the destination memory-mapped address), and not just before when has been
issued, at HPDMA level, this AXI burst transaction.
A transfer error rises in one of the following situations:
• during a single/burst data transfer from the source or to the destination (DTEF)
• during an update of an HPDMA channel register from the programmed LLI in memory
(ULEF)
• during a tentative execution of an HPDMA channel with an unauthorized setting
(USEF)
The user must perform a debug session to correct the HPDMA channel programming
versus the USEF root causes list (see Section 18.4.17).
A trigger overrun is described in Trigger hit memorization and trigger overrun flag
generation.

18.8 HPDMA registers

The HPDMA registers must be accessed with an aligned 32-bit word data access.

18.8.1 HPDMA secure configuration register (HPDMA_SECCFGR)

Address offset: 0x000
Reset value: 0x0000 0000
A write access to this register must be secure and privileged. A read access is secure or
nonsecure, privileged, or unprivileged, and with any CID.
A write access is ignored at bit level if the corresponding channel x is locked
(HPDMA_RCFGLOCKR.LOCKx = 1).
This register can mix information from different CIDs. If a channel x is configured as CID
filtered (HPDMA_CxCIDCFGR.CFEN = 1), the SECx bit can be written only by an
authorized CID (and secure and privileged) agent. If the debug domain feature is activated,
an access to this register is granted to the debug domain CID, regardless of any CID
filtering.

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This register must be written when HPDMA_CxCR.EN = 0.

This register is read-only when HPDMA_CxCR.EN = 1.
This register must be programmed at a bit level, at the initialization/closure of an HPDMA
channel (when HPDMA_CxCR.EN = 0), to securely allocate individually any channel x to
the secure or nonsecure world.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15 SEC14 SEC13 SEC12 SEC11 SEC10 SEC9 SEC8 SEC7 SEC6 SEC5 SEC4 SEC3 SEC2 SEC1 SEC0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 SECx: Secure state of channel x (x = 15 to 0)
0: Nonsecure
1: Secure

18.8.2 HPDMA privileged configuration register (HPDMA_PRIVCFGR)

Address offset: 0x004
Reset value: 0x0000 0000
A write access to this register must be privileged. A read access can be privileged or
unprivileged, secure or nonsecure, and with any CID.
This register can mix secure and nonsecure information. If a channel x is configured as
secure (HPDMA_SECCFGR.SECx = 1), the PRIVx bit can be written only by a secure
(and privileged) agent.
This register can mix information from different CIDs. If a channel x is configured as CID
filtered (HPDMA_CxCIDCFGR.CFEN = 1), the PRIVx bit can be written only by an
authorized CID (and privileged) agent. If the debug domain feature is activated, an access
to this register is granted to the debug domain CID, regardless of any CID filtering.
A write access is ignored at bit level if the corresponding channel x is locked
(HPDMA_RCFGLOCKR.LOCKx = 1).
This register must be written when HPDMA_CxCR.EN = 0.
This register is read-only when HPDMA_CxCR.EN = 1.
This register must be programmed at a bit level, at the initialization/closure of a HPDMA
channel (HPDMA_CxCR.EN = 0), to individually allocate any channel x to the privileged or
unprivileged world.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIV15 PRIV14 PRIV13 PRIV12 PRIV11 PRIV10 PRIV9 PRIV8 PRIV7 PRIV6 PRIV5 PRIV4 PRIV3 PRIV2 PRIV1 PRIV0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PRIVx: Privileged state of channel x (x = 15 to 0)
0: Unprivileged
1: Privileged

18.8.3 HPDMA configuration lock register (HPDMA_RCFGLOCKR)

Address offset: 0x008
Reset value: 0x0000 0000
This register can be written by a software agent with secure privileged and trusted domain
CID attributes in order to individually lock, for example at boot time, the secure privileged
and CID attributes of any HPDMA channel/resource (to lock the setting of
HPDMA_SECCFGR, HPDMA_PRIVCFGR, and HPDMA_CxCIDCFGR for any channel x
at, for example at boot time).
A read access may be privileged or unprivileged, secure or nonsecure, and with any CID.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK1 LOCK1 LOCK1 LOCK1 LOCK1 LOCK1
LOCK9 LOCK8 LOCK7 LOCK6 LOCK5 LOCK4 LOCK3 LOCK2 LOCK1 LOCK0
5 4 3 2 1 0
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 LOCKx: Lock of the configuration of HPDMA_SECCFGR.SECx, HPDMA_PRIVCFGR.PRIVx,
and HPDMA_CxCIDCFGR until a global HPDMA reset (x = 15 to 0)
This bit is cleared after reset and, once set, it cannot be reset until a global HPDMA reset.
0: Secure privilege and CID configuration of the channel x is writable.
1: Secure privilege and CID configuration of the channel x is not writable.

18.8.4 HPDMA nonsecure masked interrupt status register

(HPDMA_MISR)
Address offset: 0x00C
Reset value: 0x0000 0000
This register is a read register.
This is a nonsecure register, containing the masked interrupt status bit MISx for each
non-secure channel x (channel x configured with HPDMA_SECCFGR.SECx = 0). It is a
logical OR of all the flags of HPDMA_CxSR, each source flag being enabled by the
corresponding interrupt enable bit of HPDMA_CxCR.
Every bit is deasserted by hardware when writing 1 to the corresponding flag clear bit in
HPDMA_CxFCR.
If a channel x is in secure state (HPDMA_SECCFGR.SECx = 1), a read access to the
masked interrupt status bit MISx of this channel x returns zero.

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This register can mix privileged and unprivileged information, depending on the privileged
state of each channel HPDMA_PRIVCFGR.PRIVx. A privileged software can read the full
nonsecure interrupt status. An unprivileged software is restricted to read the status of
unprivileged (and nonsecure) channels, other privileged bitfields returning zero.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIS15 MIS14 MIS13 MIS12 MIS11 MIS10 MIS9 MIS8 MIS7 MIS6 MIS5 MIS4 MIS3 MIS2 MIS1 MIS0
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 MISx: Masked interrupt status of channel x (x = 15 to 0)
0: No interrupt occurred on channel x.
1: An interrupt occurred on channel x.

18.8.5 HPDMA secure masked interrupt status register (HPDMA_SMISR)

Address offset: 0x010
Reset value: 0x0000 0000
This is a secure read register, containing the masked interrupt status bit MISx for each
secure channel x (HPDMA_SECCFGR.SECx = 1). It is a logical OR of all the
HPDMA_CxSR flags, each source flag being enabled by the corresponding HPDMA_CxCR
interrupt enable bit.
Every bit is deasserted by hardware when securely writing 1 to the corresponding
HPDMA_CxFCR flag clear bit.
This register does not contain any information about a nonsecure channel.
This register can mix privileged and unprivileged information, depending on the privileged
state of each channel HPDMA_PRIVCFGR.PRIVx. A privileged software can read the full
secure interrupt status. An unprivileged software is restricted to read the status of
unprivileged and secure channels, other privileged bitfields returning zero.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIS15 MIS14 MIS13 MIS12 MIS11 MIS10 MIS9 MIS8 MIS7 MIS6 MIS5 MIS4 MIS3 MIS2 MIS1 MIS0
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 MISx: Masked interrupt status of the secure channel x (x = 15 to 0)
0: No interrupt occurred on the secure channel x.
1: An interrupt occurred on the secure channel x.

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18.8.6 HPDMA channel x linked-list base address register

(HPDMA_CxLBAR)
Address offset: 0x050 + 0x80 * x (x = 0 to 15)
Reset value: 0x0000 0000
This register must be written by a privileged software. It is either privileged readable or not,
depending on the privileged state of the channel x HPDMA_PRIVCFGR.PRIVx.
This register is either secure or nonsecure depending on the secure state of the channel x
(HPDMA_SECCFGR.SECx).
This register is CID-filtered depending on the CID configuration of the channel x
(HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, an access to
this register is granted to the debug domain CID, regardless of any CID filtering.
This register must be written when HPDMA_CxCR.EN = 0.
This register is read-only when HPDMA_CxCR.EN = 1.
This channel-based register is the linked-list base address of the memory region, for a given
channel x, from which the LLIs describing the programmed sequence of the HPDMA
transfers, are conditionally and automatically updated.
This 64-Kbyte aligned channel x linked-list base address is offset by the 16-bit
HPDMA_CxLLR register that defines the word-aligned address offset for each LLI.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LBA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:16 LBA[31:16]: Linked-list base address of HPDMA channel x

Bits 15:0 Reserved, must be kept at reset value.

18.8.7 HPDMA channel x CID register (HPDMA_CxCIDCFGR)

Address offset: 0x054+ 0x80 * x (x = 0 to 15)
Reset value: 0x0000 0000
This channel-based register can be written by the secure, privileged, and trusted domain
CID, in order to individually configure the CID allocation of any HPDMA channel x. If the
debug domain feature is activated, a read/write access to this register is granted to the
debug domain CID, regardless of any CID filtering.
This register must be written when the resource configuration of the channel x is unlocked
(HPDMA_RCFGLOCKR.LOCKx = 0) and when the channel is disabled
(HPDMA_CxCR.EN = 0).

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A read access may be privileged or unprivileged, secure or nonsecure, and with any CID.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEM_ SEM_ SEM_ SEM_ SEM_ SEM_ SEM_
Res. Res. Res. Res. Res. Res. Res. Res. Res. WLIST WLIST WLIST WLIST WLIST WLIST WLIST
_CID6 _CID5 _CID4 _CID3 _CID2 _CID1 _CID0
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEM_E
Res. Res. Res. Res. Res. Res. Res. Res. Res. SCID[2:0] Res. Res. CFEN
N
rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 SEM_WLIST_CID6: White-listed CID6 in the CID allocation pool (for when the channel x
in semaphore mode)
0: CID6 black-listed in the semaphore-based CID allocation pool
1: CID6 white-listed in the semaphore-based CID allocation pool
Bit 21 SEM_WLIST_CID5: White-listed CID5 in the CID allocation pool (for when the channel x
in semaphore mode)
0: CID5 black-listed in the semaphore-based CID allocation pool
1: CID5 white-listed in the semaphore-based CID allocation pool
Bit 20 SEM_WLIST_CID4: White-listed CID4 in the CID allocation pool (for when the channel x
in semaphore mode)
0: CID4 black-listed in the semaphore-based CID allocation pool
1: CID4 white-listed in the semaphore-based CID allocation pool
Bit 19 SEM_WLIST_CID3: White-listed CID3 in the CID allocation pool (for when the channel x
in semaphore mode)
0: CID3 black-listed in the semaphore-based CID allocation pool
1: CID3 white-listed in the semaphore-based CID allocation pool
Bit 18 SEM_WLIST_CID2: White-listed CID2 in the CID allocation pool (for when the channel x
in semaphore mode)
0: CID2 black-listed in the semaphore-based CID allocation pool
1: CID2 white-listed in the semaphore-based CID allocation pool
Bit 17 SEM_WLIST_CID1: White-listed CID1 in the CID allocation pool (for when the channel x
in semaphore mode)
0: CID1 black-listed in the semaphore-based CID allocation pool
1: CID1 white-listed in the semaphore-based CID allocation pool
Bit 16 SEM_WLIST_CID0: White-listed CID0 in the CID allocation pool (for when the channel x
in semaphore mode)
0: CID0 black-listed in the semaphore-based CID allocation pool
1: CID0 white-listed in the semaphore-based CID allocation pool
Bits 15:7 Reserved, must be kept at reset value.

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Bits 6:4 SCID[2:0]: Allocation of a static/single CID to the channel x (for when the channel x CID
configuration is not in semaphore mode)
000: CID0 allocated to the channel x
001: CID1 allocated to the channel x
010: CID2 allocated to the channel x
011: CID3 allocated to the channel x
100: CID4 allocated to the channel x
101: CID5 allocated to the channel x
110: CID6 allocated to the channel x
111: Reserved (write ignored)
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 SEM_EN: Semaphore mode enable (for the CID allocation policy to the channel x)
0: Semaphore mode disabled. CID allocation policy to the channel x is defined by SCID[1:0].
1: Semaphore mode enabled. CID allocation policy to the channel x is defined by
the white-listed allocation pool SEM_WLIST_CIDx and HPDMA_CxSEMCR.SEM_MUTEX.
Note: If SEM_EN = 1 and if a trusted domain or debug domain CID agent clears this bit, then
the HPDMA hardware automatically clears the HPDMA_CxSEMCR.SEM_MUTEX.
Bit 0 CFEN: CID filtering enable of the channel x
0: CID filtering disabled for when accessing a channel x register/bitfield
1: CID filtering enabled for when accessing a channel x register/bitfield
Note: If CFEN = 1 and if a trusted domain or debug domain CID agent clears this bit, then the
HPDMA hardware automatically clears the HPDMA_CxSEMCR.SEM_MUTEX.

18.8.8 HPDMA channel x semaphore control register

(HPDMA_CxSEMCR)
Address offset: 0x058+ 0x80 * x (x = 0 to 15)
Reset value: 0x0000 0000
When the secure, privileged and trusted domain has set up the channel x in semaphore
mode (HPDMA_CxCIDCFGR.SEM_EN = 1), this register is used during run-time by an
authorized white-listed CID agent, in order to take and after possibly release the control of
the channel x.
A read access may be privileged or unprivileged, secure or nonsecure, and with any CID.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEM_
Res. Res. Res. Res. Res. Res. Res. Res. Res. SEM_CCID[2:0] Res. Res. Res.
MUTEX
r r r rw

Bits 31:7 Reserved, must be kept at reset value.

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Bits 6:4 SEM_CCID[2:0]: Current CID allocated to the channel x (in semaphore mode)
This read-only bitfield is internally updated when a white-listed CID took the control of
the channel x, in semaphore mode. If SEM_MUTEX = 0, this same CID also released it.
000: CID0 is the last white-listed CID that took the control of the channel x.
001: CID1 is the last white-listed CID that took the control of the channel x.
010: CID2 is the last white-listed CID that took the control of the channel x.
011: CID3 is the last white-listed CID that took the control of the channel x.
100: CID4 is the last white-listed CID that took the control of the channel x.
101: CID5 is the last white-listed CID that took the control of the channel x.
110: CID6 is the last white-listed CID that took the control of the channel x.
111: Reserved
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 SEM_MUTEX: Mutual exclusion semaphore for the CID allocation of the channel x
(in semaphore mode)
If the channel x is in secure state (HPDMA_SECCFGR.SECx = 1), this bit can only be written
by a secure agent. If the channel x is in privileged state (HPDMA_PRIVCFGR.PRIVx = 1),
this bit can only be written by a privileged agent.
If the channel x is CID-filtered (HPDMA_CxCIDCFGR.CFEN = 1) and in semaphore mode
(HPDMA_CIDCFGR.SEM_EN = 1), this bit can only be written either by an authorized
(white-listed) CID agent to take the control, or by the same (white-listed) CID agent to
release the control.

Condition: write
0: Release the control of the channel x (in semaphore mode) to any white-listed CID.
1: Take the control of the channel x (in semaphore mode), from one of the white-listed
CID pool.
Condition: read
0: Channel x CID-free (not currently under the control of any white-listed CID)
1: Channel x CID-allocated (currently taken and under the control of one white-listed CID)

Note: This bit must be written when HPDMA_CxCR.EN = 0. This bit is read-only when
HPDMA_CxCR.EN = 1.
When SEM_EN or CFEN bit is cleared in HPDMA_CxSEMCR, the HPDMA hardware
automatically clears this SEM_MUTEX bit.

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18.8.9 HPDMA channel x flag clear register (HPDMA_CxFCR)

Address offset: 0x05C+ 0x80 * x (x = 0 to 15)
Reset value: 0x0000 0000
This is a write register, secure or nonsecure depending on the secure state of channel x
(HPDMA_SECCFGR.SECx) and privileged or unprivileged, depending on the privileged
state of the channel x (HPDMA_PRIVCFGR.PRIVx).
This register is CID-filtered depending on the CID configuration of the channel x
(HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, an access to
this register is granted to the debug domain CID, regardless of any CID filtering.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. TOF SUSPF USEF ULEF DTEF HTF TCF Res. Res. Res. Res. Res. Res. Res. Res.
w w w w w w w

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 TOF: Trigger overrun flag clear
0: No effect
1: Corresponding TOF flag cleared
Bit 13 SUSPF: Completed suspension flag clear
0: No effect
1: Corresponding SUSPF flag cleared
Bit 12 USEF: User setting error flag clear
0: No effect
1: Corresponding USEF flag cleared
Bit 11 ULEF: Update link transfer error flag clear
0: No effect
1: Corresponding ULEF flag cleared
Bit 10 DTEF: Data transfer error flag clear
0: No effect
1: Corresponding DTEF flag cleared
Bit 9 HTF: Half transfer flag clear
0: No effect
1: Corresponding HTF flag cleared
Bit 8 TCF: Transfer complete flag clear
0: No effect
1: Corresponding TCF flag cleared
Bits 7:0 Reserved, must be kept at reset value.

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18.8.10 HPDMA channel x status register (HPDMA_CxSR)

Address offset: 0x060 + 0x80 * x (x = 0 to 15)
Reset value: 0x0000 0001
This is a read register, reporting the channel status.
This register is secure or nonsecure, depending on the secure state of channel x
(HPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged
state of the channel (HPDMA_PRIVCFGR.PRIVx).
This register is CID-filtered depending on the CID configuration of the channel x
(HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, an access to
this register is granted to the debug domain CID, regardless of any CID filtering.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. FIFOL[8:0]
r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. TOF SUSPF USEF ULEF DTEF HTF TCF Res. Res. Res. Res. Res. Res. Res. IDLEF
r r r r r r r r

Bits 31:25 Reserved, must be kept at reset value.

Bits 24:16 FIFOL[8:0]: Monitored FIFO level
Number of available write beats in the FIFO, in units of the programmed destination data
width (see Section 18.8.12: HPDMA channel x transfer register 1 (HPDMA_CxTR1)
DDW_LOG2[1:0], in units of bytes, half-words, words or double-words).
Note: After having suspended an active transfer, the user may need to read FIFOL[8:0],
additionally to HPDMA_CxBR1.BDNT[15:0] and HPDMA_CxBR1.BRC[10:0], to know
how many data have been transferred to the destination. Before reading, the user may
wait for the transfer to be suspended (HPDMA_CxSR.SUSPF = 1).
Bit 15 Reserved, must be kept at reset value.
Bit 14 TOF: Trigger overrun flag
0: No trigger overrun event
1: A trigger overrun event occurred.
Bit 13 SUSPF: Completed suspension flag
0: No completed suspension event
1: A completed suspension event occurred.
Bit 12 USEF: User setting error flag
0: No user setting error event
1: A user setting error event occurred.
Bit 11 ULEF: Update link transfer error flag
0: No update link transfer error event
1: A master bus error event occurred while updating a linked-list register from memory.
Bit 10 DTEF: Data transfer error flag
0: No data transfer error event
1: A master bus error event occurred on a data transfer.

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Bit 9 HTF: Half transfer flag

0: No half transfer event
1: An half transfer event occurred.
An half transfer event is either an half block transfer or an half 2D/repeated block transfer,
depending on the transfer complete event mode (HPDMA_CxTR2.TCEM[1:0]).
An half block transfer occurs when half of the bytes of the source block size (rounded up
integer of HPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination.
An half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up
integer of (HPDMA_CxBR1.BRC[10:0]+1)/2)) has been transferred to the destination.
Bit 8 TCF: Transfer complete flag
0: No transfer complete event
1: A transfer complete event occurred.
A transfer complete event is either a block transfer complete, a 2D/repeated block transfer
complete, a LLI transfer complete including the upload of the next LLI if any, or the full linked-
list completion, depending on the transfer complete event mode
(HPDMA_CxTR2.TCEM[1:0]).
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 IDLEF: Idle flag
0: Channel not in idle state
1: Channel in idle state
This idle flag is deasserted by hardware when the channel is enabled
(HPDMA_CxCR.EN = 1) with a valid channel configuration (no USEF to be immediately
reported).
This idle flag is asserted after hard reset or by hardware when the channel is back in idle
state (in suspended or disabled state).

18.8.11 HPDMA channel x control register (HPDMA_CxCR)

Address offset: 0x064 + 0x80 * x (x = 0 to 15)
Reset value: 0x0000 0000
This register is secure or nonsecure depending on the secure state of channel x
(HPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged
state of the channel x (HPDMA_PRIVCFGR.PRIVx).
This register is CID-filtered depending on the CID configuration of the channel x
(HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, an access to
this register is granted to the debug domain CID, regardless of any CID filtering.
This register is used to control a channel (activate, suspend, abort or disable it).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. PRIO[1:0] Res. Res. Res. Res. LAP LSM
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSPI
Res. TOIE USEIE ULEIE DTEIE HTIE TCIE Res. Res. Res. Res. Res. SUSP RESET EN
E
rw rw rw rw rw rw rw rw w rw

Bits 31:24 Reserved, must be kept at reset value.

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Bits 23:22 PRIO[1:0]: Priority level of the channel x HPDMA transfer versus others
00: Low priority, low weight
01: Low priority, mid weight
10: Low priority, high weight
11: High priority
Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
Bits 21:18 Reserved, must be kept at reset value.
Bit 17 LAP: lLnked-list allocated port
This bit is used to allocate the master port for the update of the HPDMA linked-list registers
from the memory.
0: Port 0 (AXI) allocated
1: Port 1 (AHB) allocated
Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
Bit 16 LSM: Link step mode
0: Channel executed for the full linked-list and completed at the end of the last LLI
(HPDMA_CxLLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0)
and all the update bits are null (UT1 = UB1 = UT2 = USA = UDA = ULL = 0 and
UT3 = UB2 = 0 if present). Then HPDMA_CxBR1.BNDT[15:0] = 0 and
HPDMA_CxBR1.BRC[10:0] = 0 if present.
1: Channel executed once for the current LLI
First the (possible 1D/repeated) block transfer is executed as defined by the current internal
register file until HPDMA_CxBR1.BNDT[15:0] = 0 and HPDMA_CxBR1.BRC[10:0] = 0,
if present. Secondly the next linked-list data structure is conditionally uploaded from memory
as defined by HPDMA_CxLLR. Then channel execution is completed.
Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
Bit 15 Reserved, must be kept at reset value.
Bit 14 TOIE: Trigger overrun interrupt enable
0: Interrupt disabled
1: Interrupt enabled
Bit 13 SUSPIE: cCmpleted suspension interrupt enable
0: Interrupt disabled
1: Interrupt enabled
Bit 12 USEIE: User setting error interrupt enable
0: Interrupt disabled
1: Interrupt enabled
Bit 11 ULEIE: Update link transfer error interrupt enable
0: Interrupt disabled
1: Interrupt enabled
Bit 10 DTEIE: Data transfer error interrupt enable
0: Interrupt disabled
1: Interrupt enabled
Bit 9 HTIE: Half transfer complete interrupt enable
0: Interrupt disabled
1: Interrupt enabled
Bit 8 TCIE: Transfer complete interrupt enable
0: Interrupt disabled
1: Interrupt enabled

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Bits 7:3 Reserved, must be kept at reset value.

Bit 2 SUSP: Suspend
Writing 1 to RESET in this register causes the hardware to deassert this SUSP bit, whatever
is written into this SUSP. Else:
Software must write 1 in order to suspend an active channel (a channel with an ongoing
HPDMA transfer over its master ports).
The software must write 0 in order to resume a suspended channel, following the
programming sequence detailed in Figure 73.
0: Write: resume channel, read: channel not suspended
1: Write: suspend channel, read: channel suspended
Bit 1 RESET: Reset
This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the
FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2
and bit 0).
The reset is effective when the channel is in steady state, meaning one of the following:
- active channel in suspended state (HPDMA_CxSR.SUSPF = 1 and
HPDMA_CxSR.IDLEF = HPDMA_CxCR.EN = 1)
- channel in disabled state (HPDMA_CxSR.IDLEF = 1 and HPDMA_CxCR.EN = 0).
After writing a RESET, to continue using this channel, the user must explicitly reconfigure the
channel including the hardware-modified configuration registers (HPDMA_CxBR1,
HPDMA_CxSAR and HPDMA_CxDAR) before enabling again the channel (see the
programming sequence in Figure 74).
0: No channel reset
1: Channel reset
Bit 0 EN: Enable
Writing 1 to RESET in this register causes the hardware to deassert this EN bit, whatever is
written into this bit 0. Else:
This bit is deasserted by hardware when there is a transfer error (master bus error or user
setting error) or when there is a channel transfer complete (channel ready to be configured,
for example if LSM = 1 at the end of a single execution of the LLI).
Else, this bit can be asserted by software.
Writing 0 into this EN bit is ignored.
0: Write: ignored, read: channel disabled
1: Write: enable channel, read: channel enabled

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18.8.12 HPDMA channel x transfer register 1 (HPDMA_CxTR1)

Address offset: 0x090 + 0x80 * x (x = 0 to 15)
Reset value: 0x0000 0000
This register is secure or nonsecure depending on the secure state of channel x
(HPDMA_SECCFGR.SECx) except for secure DSEC and SSEC, privileged or unprivileged,
depending on the privileged state of the channel x in HPDMA_PRIVCFGR.PRIVx.
This register is CID-filtered depending on the CID configuration of the channel x
(HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, an access to
this register is granted to the debug domain CID, regardless of any CID filtering.
This register controls the transfer of a channel x.
This register must be written when HPDMA_CxCR.EN = 0.
This register is read-only when HPDMA_CxCR.EN = 1.
This register must be written when the channel is completed. Then the hardware has
de-asserted HPDMA_CxCR.EN). A channel transfer can be completed and programmed at
different levels: block, 2D/repeated block, LLI, or full linked-list.
In linked-list mode, during the link transfer, this register is automatically updated by HPDMA
from the memory if HPDMA_CxLLR.UT1 = 1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSEC DAP Res. DWX DHX DBX DBL_1[5:0] DINC Res. DDW_LOG2[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSEC SAP SBX PAM[1:0] Res. SBL_1[5:0] SINC Res. SDW_LOG2[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 DSEC: Security attribute of the HPDMA transfer to the destination

If HPDMA_SECCFGR.SECx = 1 and the access is secure:
0: HPDMA transfer nonsecure
1: HPDMA transfer secure
This is a secure register bit. This bit can only be read by a secure software. This bit must be
written by a secure software when HPDMA_SECCFGR.SECx = 1. A secure write is ignored
when HPDMA_SECCFGR.SECx = 0.
When HPDMA_SECCFGR.SECx is deasserted, this DSEC bit is also deasserted by
hardware (on a secure reconfiguration of the channel as nonsecure), and the HPDMA
transfer to the destination is nonsecure.
Bit 30 DAP: Destination allocated port
This bit is used to allocate the master port for the destination transfer
0: Port 0 (AXI) allocated
1: Port 1 (AHB) allocated
Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
Bit 29 Reserved, must be kept at reset value.

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Bit 28 DWX: Destination word exchange

If the destination data size is not a double-word, this bit is ignored.
If the destination data size is a double-word and if destination bus is AXI (DAP = 0):
0: No word-based exchanged within double-word
1: The two consecutive (post PAM) words are exchanged in each destination double-word.
Bit 27 DHX: Destination half-word exchange
If the destination data size is shorter than a word, this bit is ignored.
If the destination data size is a word or double-word and if destination bus is AXI (DAP = 0):
0: No half-word-based exchanged within word
1: The two consecutive (post PAM) half-words are exchanged in each destination word.
Bit 26 DBX: Destination byte exchange
If the destination data size is a byte, this bit is ignored.
If the destination data size is not a byte:
0: No byte-based exchange within half-word
1: The two consecutive (post PAM) bytes are exchanged in each destination half-word.
Bits 25:20 DBL_1[5:0]: Destination burst length minus 1, between 0 and 63
The burst length unit is one data named beat within a burst. If DBL_1[5:0] = 0, the burst can
be named as single. Each data/beat has a width defined by the destination data width
DDW_LOG2[1:0].
Caution: As highlighted in Section 18.3.2, the maximum allowed AXI burst length is 16. The
user must set DBL_1[5:0] lower or equal to 15 if the destination allocated port is AXI
(if DAP = 0).
Note: If a burst transfer crossed a 1- or 4-Kbyte address boundary on respectively an AHB or
AXI transfer, the HPDMA modifies and shortens the programmed burst into singles or
bursts of lower length, to be compliant with the AHB/AXI protocol.
If the burst length exceeds 16 on an AHB transfer, or if the burst on an AXI transfer is
both with fixed addressing (DINC = 0) and with a burst length which exceeds 16, the
HPDMA modifies and shortens the programmed burst into bursts of lower length, to be
compliant with the AHB or AXI protocol.
If a burst transfer is of length greater than the FIFO size of the channel x, the HPDMA
modifies and shortens the programmed burst into singles or bursts of lower length, to be
compliant with the FIFO size. Transfer performance is lower, with HPDMA re-arbitration
between effective and lower singles/bursts, but the data integrity is guaranteed.
Bit 19 DINC: Destination incrementing burst
0: Fixed burst
1: Contiguously incremented burst
The destination address, pointed by HPDMA_CxDAR, is kept constant after a burst
beat/single transfer, or is incremented by the offset value corresponding to a contiguous data
after a burst beat/single transfer.
Bit 18 Reserved, must be kept at reset value.

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Bits 17:16 DDW_LOG2[1:0]: Binary logarithm of the destination data width of a burst, in bytes
00: Byte
01: Half-word (2 bytes)
10: Word (4 bytes)
11: If DAP = 0 (AXI), double-word (8 bytes)
if DAP = 1, user setting error reported and no transfer issued
Note: A destination burst transfer must have an aligned address with its data width (start
address HPDMA_CxDAR[2:0] and if present address offset HPDMA_CxTR3.DAO[2:0],
versus DDW_LOG2[1:0]). Otherwise a user setting error is reported and no transfer is
issued.
When configured in packing mode (PAM[1] = 1 and destination data width different from
source data width), a source block size must be a multiple of the destination data width
(see HPDMA_CxBR1.BNDT[2:0] versus DDW_LOG2[1:0]). Else a user setting error is
reported and none transfer is issued.
A burst with a double-word data width must be allocated to the AXI master port, else a
user setting error is reported and none transfer is issued.
Bit 15 SSEC: Security attribute of the HPDMA transfer from the source
If HPDMA_SECCFGR.SECx = 1 and the access is secure:
0: HPDMA transfer nonsecure
1: HPDMA transfer secure
This is a secure register bit. This bit can only be read by a secure software. This bit must be
written by a secure software when HPDMA_SECCFGR.SECx = 1. A secure write is ignored
when HPDMA_SECCFGR.SECx = 0.
When HPDMA_SECCFGR.SECx is deasserted, this SSEC bit is also deasserted by
hardware (on a secure reconfiguration of the channel as nonsecure), and the HPDMA
transfer from the source is nonsecure.
Bit 14 SAP: Source allocated port
This bit is used to allocate the master port for the source transfer
0: Port 0 (AXI) allocated
1: Port 1 (AHB) allocated
Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.
Bit 13 SBX: Source byte exchange within the unaligned half-word of each source word
If the source data width is shorter than a word, this bit is ignored.
If the source data width is a word or a double-word, and if source bus is AXI (SAP = 0):
0: No byte-based exchange within the unaligned half-word of each source word
1: The two consecutive bytes within the unaligned half-word of each source word
are exchanged.

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Bits 12:11 PAM[1:0]: Padding/alignment mode

If DDW_LOG2[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is
equal to the data width of a burst source transfer, these bits are ignored.
Else, in the following enumerated values, the condition PAM_1 is when destination data width
is higher than source data width, and the condition PAM_2 is when source data width is
higher than destination data width.
Condition: PAM_1
00: Source data is transferred as right aligned, padded with 0s up to the destination data
width
01: Source data is transferred as right aligned, sign extended up to the destination data width
10-11: Successive source data are FIFO queued and packed at the destination data width, in
a left (LSB) to right (MSB) order (named little endian), before a destination transfer
Condition: PAM_2
00: Source data is transferred as right aligned, left-truncated down to the destination data
width
01: Source data is transferred as left-aligned, right-truncated down to the destination data
width
10-11: Source data is FIFO queued and unpacked at the destination data width, to be
transferred in a left (LSB) to right (MSB) order (named little endian) to the destination
Note: If the transfer from the source peripheral is configured with peripheral flow-control mode
(SWREQ = 0 and PFREQ = 1 and DREQ = 0), and if the destination data width > the
source data width, packing is not supported.
Bit 10 Reserved, must be kept at reset value.
Bits 9:4 SBL_1[5:0]: Source burst length minus 1, between 0 and 63
The burst length unit is one data named beat within a burst. If SBL_1[5:0] = 0, the burst can
be named as single. Each data/beat has a width defined by the destination data width
SDW_LOG2[1:0].
Caution: As highlighted in Section 18.3.2, the maximum allowed AXI burst length is 16. The
user must set SBL_1[5:0] lower or equal to 15 if the source allocated port is AXI
(if SAP = 0).
Note: If a burst transfer crossed a 1- or 4-Kbyte address boundary on respectively an AHB or
an AXI transfer, the HPDMA modifies and shortens the programmed burst into singles
or bursts of lower length, to be compliant with the AHB protocol.
If the burst length exceeds 16 on a AHB transfer, or if the burst on a AXI transfer is both
with fixed addressing (SINC = 0) and with a burst length which exceeds 16, the HPDMA
modifies and shortens the programmed burst into singles or bursts of lower length, to be
compliant with the FIFO size. Transfer performance is lower, with HPDMA re-arbitration
between effective and lower singles/bursts, but the data integrity is guaranteed.
Bit 3 SINC: Source incrementing burst
0: Fixed burst
1: Contiguously incremented burst
The source address, pointed by HPDMA_CxSAR, is kept constant after a burst beat/single
transfer or is incremented by the offset value corresponding to a contiguous data after a burst
beat/single transfer.
Bit 2 Reserved, must be kept at reset value.

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Bits 1:0 SDW_LOG2[1:0]: Binary logarithm of the source data width of a burst in bytes
00: Byte
01: Half-word (2 bytes)
10: Word (4 bytes)
11: If SAP = 0 (AXI), double-word (8 bytes)
if SAP = 1, user setting error reported and no transfer issued
Note: A source block size must be a multiple of the source data width
(HPDMA_CxBR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error
is reported and no transfer is issued.
A source burst transfer must have an aligned address with its data width (start address
HPDMA_CxSAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is
reported and none transfer is issued.
A burst with a double-word data width must be allocated to the AXI master port, else a
user setting error is reported and none transfer is issued.

18.8.13 HPDMA channel x transfer register 2 (HPDMA_CxTR2)

Address offset: 0x094 + 0x80 * x (x = 0 to 15)
Reset value: 0x0000 0000
This register is secure or nonsecure depending on the secure state of channel x
(HPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged
state of channel x (HPDMA_PRIVCFGR.PRIVx).
This register is CID-filtered depending on the CID configuration of the channel x
(HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, a write access
to this register is granted to the debug domain CID, regardless of any CID filtering.
This register controls the transfer of a channel x.
This register must be written when HPDMA_CxCR.EN = 0.
This register is read-only when HPDMA_CxCR.EN = 1.
This register must be written when the channel is completed (the hardware deasserted
HPDMA_CxCR.EN). A channel transfer can be completed and programmed at different
levels: block, 2D/repeated block, LLI, or full linked-list.
In linked-list mode, during the link transfer, this register is automatically updated by HPDMA
from the memory, if HPDMA_CxLLR.UT2 = 1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCEM[1:0] Res. Res. Res. Res. TRIGPOL[1:0] Res. TRIGSEL[6:0]
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRE
TRIGM[1:0] Res. PFREQ BREQ DREQ Res. REQSEL[7:0]
Q
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:30 TCEM[1:0]: Transfer complete event mode

These bits define the transfer granularity for the transfer complete and half transfer complete
events generation.
00: At block level (when HPDMA_CxBR1.BNDT[15:0] = 0): The complete (and the half)
transfer event is generated at the (respectively half of the) end of a block.
Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register
file with HPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor
the half transfer event is generated.
01: Channel x = 0 to 11, same as 00; channel x = 12 to 15, at 2D/repeated block level
(when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete
(and the half) transfer event is generated at the end (respectively half of the end) of
the 2D/repeated block.
Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register
file with HPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor
the half transfer event is generated.
10: At LLI level: The complete transfer event is generated at the end of the LLI transfer,
including the update of the LLI if any. The half transfer event is generated at the half of the
LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer
for channel x = 12 to 15), if any data transfer.
Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register
file with HPDMA_CxBR1.BNDT[15:0] = 0), then the half transfer event is not generated,
and the transfer complete event is generated when is completed the loading of the LLI1.
11: At channel level: The complete transfer event is generated at the end of the last LLI
transfer. The half transfer event is generated at the half of the data transfer of the last LLI.
The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the
HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if
present). If the channel transfer is continuous/infinite, no event is generated.
Bits 29:26 Reserved, must be kept at reset value.
Bits 25:24 TRIGPOL[1:0]: Trigger event polarity
These bits define the polarity of the selected trigger event input defined by TRIGSEL[6:0].
00: No trigger (masked trigger event)
01: Trigger on the rising edge
10: Trigger on the falling edge
11: Same as 00
Bit 23 Reserved, must be kept at reset value.
Bits 22:16 TRIGSEL[6:0]: Trigger event input selection
These bits select the trigger event input of the HPDMA transfer (as per Section 18.3.7),
with an active trigger event if TRIGPOL[1:0] ≠ 00.

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Bits 15:14 TRIGM[1:0]: Trigger mode

These bits define the transfer granularity for its conditioning by the trigger.
If the channel x is enabled (HPDMA_CxCR.EN asserted) with TRIGPOL[1:0] = 00 or 11,
these TRIGM[1:0] bits are ignored.
Else, an HPDMA transfer is conditioned by at least one trigger hit:
00: at block level: the first burst read of each block transfer is conditioned by one hit trigger
(channel x = 12 to 15, for each block if a 2D/repeated block is configured with
HPDMA_CxBR1.BRC[10:0] ≠ 0).
01: channel x = 0 to 11, same as 00; channel x = 12 to 15, at 2D/repeated block level, the first
burst read of a 2D/repeated block transfer is conditioned by one hit trigger.
10: at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer
(if any) is not conditioned.
11: at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by
one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected
peripheral, is conditioned by one hit trigger.
– If the peripheral is programmed as a source (DREQ = 0) of the LLI data transfer, each
programmed burst read is conditioned.
– If the peripheral is programmed as a destination (DREQ = 1) of the LLI data transfer, each
programmed burst write is conditioned. The first memory burst read of a (possibly
2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the
occurrence of both the hardware request and the first trigger hit.
The HPDMA monitoring of a trigger for channel x is started when the channel is
enabled/loaded with a new active trigger configuration: rising or falling edge on a selected
trigger (TRIGPOL[1:0] = 01 or respectively TRIGPOL[1:0] = 10).
The monitoring of this trigger is kept active during the triggered and uncompleted (data or
link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the
next transfer, as long as the defined rising or falling edge is not modified, and the
TRIGSEL[5:0] is not modified, and the channel is enabled.
Transferring a next LLIn+1 that updates the HPDMA_CxTR2 with a new value for any of
TRIGSEL[6:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the
formerly defined LLIn trigger.
After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if
the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized. A trigger
overrun flag is reported (HPDMA_CxSR.TOF = 1), and an interrupt is generated if enabled
(HPDMA_CxCR.TOIE = 1). The channel is not automatically disabled by hardware due to a
trigger overrun.
Note: When the source block size is not a multiple of the source burst size and is a multiple of
the source data width, then the last programmed source burst is not completed and is
internally shorten to match the block size. In this case, if TRIGM[1:0] = 11 and
(SWREQ = 1 or (SWREQ = 0 and DREQ = 0)), the shortened burst transfer (by singles
or/and by bursts of lower length) is conditioned once by the trigger.
When the programmed destination burst is internally shortened by singles or/and by
bursts of lower length (versus FIFO size, versus block size, 1/4-Kbyte boundary address
crossing maximum burst length versus AHB/AXI protocol): if the trigger is conditioning
the programmed destination burst (if TRIGM[1:0] = 11 and SWREQ = 0 and DREQ = 1),
this shortened destination burst transfer is conditioned once by the trigger.
Bit 13 Reserved, must be kept at reset value.

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Bit 12 PFREQ: Hardware request in peripheral flow control mode

Important: If a given channel x is not implemented with this feature, this bit is reserved and
PFREQ is not present (see Section 18.3.6 for the list of the implemented channels with this
feature.
If the channel x is activated (HPDMA_CxCR.EN asserted) with SWREQ = 1 (software
request for a memory-to-memory transfer), this bit is ignored. Else:
0: The selected hardware request is driven by a peripheral with a hardware
request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with
HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block
transfer completion.
1: The selected hardware request is driven by a peripheral with a hardware
request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be
early completed by the peripheral itself (see Section 18.3.6 for more details).
Note: In peripheral flow control mode, there are the following restrictions:
- no 2D/repeated block support (HPDMA_CxBR1.BRC[10:0] must be set to 0 if present)
- the peripheral must be set as the source of the transfer (DREQ = 0).
- data packing to a wider destination width is not supported (if destination width > source
data width, HPDMA_CxTR1.PAM[1] must be set to 0).
- HPDMA_CxBR1.BNDT[15:0] must be set as a multiple of the source (peripheral) burst
size.
Bit 11 BREQ: Block hardware request
If the channel x is activated (HPDMA_CxCR.EN asserted) with SWREQ = 1 (software
request for a memory-to-memory transfer), this bit is ignored. Else:
0: The selected hardware request is driven by a peripheral with a hardware
request/acknowledge protocol at a burst level.
1: The selected hardware request is driven by a peripheral with a hardware
request/acknowledge protocol at a block level (see Section 18.3.5).
Bit 10 DREQ: Destination hardware request
This bit is ignored if channel x is activated (HPDMA_CxCR.EN asserted) with SWREQ = 1
(software request for a memory-to-memory transfer). Else:
0: Selected hardware request driven by a source peripheral (request signal taken into
account by the HPDMA transfer scheduler over the source/read port)
1: Selected hardware request driven by a destination peripheral (request signal taken into
account by the HPDMA transfer scheduler over the destination/write port)
Note: If the channel x is activated (HPDMA_CxCR.EN is asserted) with SWREQ = 0 and
PFREQ = 1 (peripheral hardware request with peripheral flow-control mode), any
software assertion to this DREQ bit is ignored: in peripheral flow-control mode, only a
peripheral-to-memory transfer is supported.
Bit 9 SWREQ: Software request
This bit is internally taken into account when HPDMA_CxCR.EN is asserted.
0: No software request. The selected hardware request REQSEL[7:0] is taken into account.
1: Software request for a memory-to-memory transfer. The default selected hardware request
as per REQSEL[7:0] is ignored.
Bit 8 Reserved, must be kept at reset value.

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Bits 7:0 REQSEL[7:0]: Hardware request selection

These bits are ignored if channel x is activated (HPDMA_CxCR.EN asserted) with
SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected
hardware request is internally taken into account as per Section 18.3.4.
Caution: The user must not assign a same input hardware request (same REQSEL[7:0]
value) to different active HPDMA channels (HPDMA_CxCR.EN = 1 and
HPDMA_CxTR2.SWREQ = 0 for these channels). The HPDMA is not intended to
hardware support the case of simultaneous enabled channels incorrectly configured
with a same hardware peripheral request signal, and there is no user setting error
reporting.

18.8.14 HPDMA channel x block register 1 (HPDMA_CxBR1)

Address offset: 0x098 + 0x80 * x (x = 0 to 11)
Reset value: 0x0000 0000
This register is secure or nonsecure depending on the secure state of channel x
(HPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged
state of channel x (HPDMA_PRIVCFGR.PRIVx).
This register is CID-filtered depending on the CID configuration of the channel x
(HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, a write access
to this register is granted to the debug domain CID, regardless of any CID filtering.
This register controls the transfer of a channel x at a block level.
This register must be written when HPDMA_CxCR.EN = 0.
This register is read-only when HPDMA_CxCR.EN = 1.
This register must be written when channel x is completed (then the hardware has
de-asserted HPDMA_CxCR.EN). A channel transfer can be completed and programmed at
different levels: block, 2D/repeated block, LLI, or full linked-list.
In linked-list mode, during the link transfer:
• if HPDMA_CxLLR.UB1 = 1, this register is automatically updated by the HPDMA from
the next LLI in memory.
• If HPDMA_CxLLR.UB1 = 0 and if there is at least one linked-list register to be updated
from the next LLI in memory, this register is automatically and internally restored with
the programmed value for the bitfield BNDT[15:0].
• If all the update bits HPDMA_CxLLR.Uxx are null and if HPDMA_CxLLR.LA[15:0] ≠ 0,
the current LLI is the last one and is continuously executed: this register is
automatically and internally restored with the programmed value for BNDT[15:0] after
each execution of this final LLI
• If HPDMA_CxLLR = 0, this register and BNDT[15:0] are kept as null, channel x is
completed.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 BNDT[15:0]: Block number of data bytes to transfer from the source
Block size transferred from the source. When the channel is enabled, this bitfield becomes
read-only and is decremented, indicating the remaining number of data items in the current
source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum
source block size is 64 Kbytes -1.
Once the last data transfer is completed (BNDT[15:0] = 0):
- if HPDMA_CxLLR.UB1 = 1, this bitfield is updated by the LLI in the memory.
- if HPDMA_CxLLR.UB1 = 0 and if there is at least one non null Uxx update bit, this bitfield is
internally restored to the programmed value.
- if all HPDMA_CxLLR.Uxx = 0 and if HPDMA_CxLLR.LA[15:0] = 0, this bitfield is internally
restored to the programmed value (infinite/continuous last LLI).
- if HPDMA_CxLLR = 0, this bitfield is kept as zero following the last LLI data transfer.
Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0]
versus HPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no
transfer is issued.
When configured in packing mode (HPDMA_CxTR1.PAM[1] = 1 and destination data
width different from source data width), a non-null source block size must be a multiple
of the destination data width (BNDT[2:0] versus HPDMA_CxTR1.DDW_LOG2[1:0]).
Else a user setting error is reported and no transfer is issued.

18.8.15 HPDMA channel x alternate block register 1 (HPDMA_CxBR1)

Address offset: 0x098 + 0x80 * x (x = 12 to 15)
Reset value: 0x0000 0000
This register is secure or nonsecure depending on the secure state of channel x
(HPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged
state of channel x (HPDMA_PRIVCFGR.PRIVx).
This register is CID-filtered depending on the CID configuration of the channel x
(HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, a write access
to this register is granted to the debug domain CID, regardless of any CID filtering.
This register controls the transfer of a channel x at a block level.
This register must be written when HPDMA_CxCR.EN = 0.
This register is read-only when HPDMA_CxCR.EN = 1.
This register must be written when channel x is completed (then the hardware has
de-asserted HPDMA_CxCR.EN). A channel transfer can be completed and programmed at
different levels: block, 2D/repeated block, LLI, or full linked-list.
In linked-list mode, during the link transfer:
• if HPDMA_CxLLR.UB1 = 1, this register is automatically updated by the HPDMA from
the next LLI in memory.
• If HPDMA_CxLLR.UB1 = 0 and if there is at least one linked-list register to be updated
from the next LLI in memory, this register is automatically and internally restored with
the programmed value for the bitfields BNDT[15:0] and BRC[10:0].
• If all the update bits HPDMA_CxLLR.Uxx are null and if HPDMA_CxLLR.LA[15:0] ≠ 0,
the current LLI is the last one and is continuously executed: this register is
automatically and internally restored with the programmed value for the bitfields
BNDT[15:0] and BRC[10:0] after each execution of this final LLI

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• If HPDMA_CxLLR = 0, BNDT[15:0] and BRC[10:0] are kept as null, channel x is

completed.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRDDE BRSDE
DDEC SDEC Res. BRC[10:0]
C C
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 BRDDEC: Block repeat destination address decrement

0: At the end of a block transfer, the HPDMA_CxDAR register is updated by adding the
programmed offset HPDMA_CxBR2.BRDAO to the current HPDMA_CxDAR value (current
destination address)
1: At the end of a block transfer, the HPDMA_CxDAR register is updated by subtracting the
programmed offset HPDMA_CxBR2.BRDAO from the current HPDMA_CxDAR value
(current destination address)
Note: On top of this increment/decrement (depending on BRDDEC), HPDMA_CxDAR is in the
same time also updated by the increment/decrement (depending on DDEC) of the
HPDMA_CxTR3.DAO value, as it is usually done at the end of each programmed burst
transfer.
Bit 30 BRSDEC: Block repeat source address decrement
0: At the end of a block transfer, the HPDMA_CxSAR register is updated by adding the
programmed offset HPDMA_CxBR2.BRSAO to the current HPDMA_CxSAR value (current
source address)
1: At the end of a block transfer, the HPDMA_CxSAR register is updated by subtracting the
programmed offset HPDMA_CxBR2.BRSAO from the current HPDMA_CxSAR value
(current source address)
Note: On top of this increment/decrement (depending on BRSDEC), HPDMA_CxSAR is in the
same time also updated by the increment/decrement (depending on SDEC) of the
HPDMA_CxTR3.SAO value, as it is done after any programmed burst transfer.
Bit 29 DDEC: destination address decrement
0: At the end of a programmed burst transfer to the destination, the HPDMA_CxDAR register
is updated by adding the programmed offset HPDMA_CxTR3.DAO to the current
HPDMA_CxDAR value (current destination address)
1: At the end of a programmed burst transfer to the destination, the HPDMA_CxDAR register
is updated by subtracting the programmed offset HPDMA_CxTR3.DAO to the current
HPDMA_CxDAR value (current destination address)
Bit 28 SDEC: source address decrement
0: At the end of a programmed burst transfer from the source, the HPDMA_CxSAR register is
updated by adding the programmed offset HPDMA_CxTR3.SAO to the current
HPDMA_CxSAR value (current source address)
1: At the end of a programmed burst transfer from the source, the HPDMA_CxSAR register is
updated by subtracting the programmed offset HPDMA_CxTR3.SAO to the current
HPDMA_CxSAR value (current source address)
Bit 27 Reserved, must be kept at reset value.

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Bits 26:16 BRC[10:0]: Block repeat counter

This bitfield contains the number of repetitions of the current block (0 to 2047).
When the channel is enabled, this bitfield becomes read-only. After decrements, this bitfield
indicates the remaining number of blocks, excluding the current one. This counter is
hardware decremented for each completed block transfer.
Once the last block transfer is completed (BRC[10:0] = BNDT[15:0] = 0):
– If HPDMA_CxLLR.UB1 = 1, all HPDMA_CxBR1 bitfields are updated by the next LLI
in the memory.
– If HPDMA_CxLLR.UB1 = 0 and if there is at least one not null Uxx update bit, this bitfield is
internally restored to the programmed value.
– if all HPDMA_CxLLR.Uxx = 0 and if HPDMA_CxLLR.LA[15:0] ≠ 0, this bitfield is internally
restored to the programmed value (infinite/continuous last LLI).
– if HPDMA_CxLLR = 0, this bitfield is kept as zero following the last LLI and data transfer.
Bits 15:0 BNDT[15:0]: Block number of data bytes to transfer from the source
Block size transferred from the source. When the channel is enabled, this bitfield becomes
read-only and is decremented, indicating the remaining number of data items in the current
source block to be transferred.
BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1.
Once the last data transfer is completed (BNDT[15:0] = 0):
- if HPDMA_CxLLR.UB1 = 1, this bitfield is updated by the LLI in the memory.
- if HPDMA_CxLLR.UB1 = 0 and if there is at least one not null Uxx update bit, this bitfield is
internally restored to the programmed value.
- if all HPDMA_CxLLR.Uxx = 0 and if HPDMA_CxLLR.LA[15:0] ≠ 0, this bitfield is internally
restored to the programmed value (infinite/continuous last LLI).
- if HPDMA_CxLLR = 0, this bitfield is kept as zero following the last LLI data transfer.
Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0]
versus HPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and no
transfer is issued.
When configured in packing mode (HPDMA_CxTR1.PAM[1] = 1 and destination data
width different from source data width), a non-null source block size must be a multiple
of the destination data width (BNDT[2:0] versus HPDMA_CxTR1.DDW_LOG2[1:0]).
Else a user setting error is reported and no transfer is issued.

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18.8.16 HPDMA channel x source address register (HPDMA_CxSAR)

Address offset: 0x09C + 0x80 * x (x = 0 to 15)
Reset value: 0x0000 0000
This register is secure or nonsecure depending on the secure state of channel x
(HPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged
state of channel x (HPDMA_PRIVCFGR.PRIVx).
This register is CID-filtered depending on the CID configuration of the channel x
(HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, an access to
this register is granted to the debug domain CID, regardless of any CID filtering.
This register configures the source start address of a transfer.
This register must be written when HPDMA_CxCR.EN = 0.
This register is read-only when HPDMA_CxCR.EN = 1, and continuously updated by
hardware, in order to reflect the address of the next burst transfer from the source.
This register must be written when the channel is completed (then the hardware has
deasserted HPDMA_CxCR.EN). A channel transfer can be completed and programmed at
different levels: block, 2D/repeated block, LLI, or full linked-list.
In linked-list mode, during the link transfer, this register is automatically updated by the
HPDMA from the memory if HPDMA_CxLLR.USA = 1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:0 SA[31:0]: Source address

This bitfield is the pointer to the address from which the next data is read.
During the channel activity, depending on the source addressing mode
(HPDMA_CxTR1.SINC), this bitfield is kept fixed or incremented by the data width
(HPDMA_CxTR1.SDW_LOG2[1:0]) after each burst source data, reflecting the next address
from which data is read.
During the channel activity, this address is updated after each completed source burst,
consequently to:
– the programmed source burst; either in fixed addressing mode or in contiguous-data
incremented mode. If contiguously incremented (HPDMA_CxTR1.SINC = 1), then the
additional address offset value is the programmed burst size, as defined by
HPDMA_CxTR1.SBL_1[5:0] and HPDMA_CxTR1.SDW_LOG2[1:0]
– the additional source incremented/decremented offset value as programmed by
HPDMA_CxBR1.SDEC and HPDMA_CxTR3.SAO[12:0]
– once/if completed source block transfer, for a channel x with 2D addressing capability
(x = 12 to 15). additional block repeat source incremented/decremented offset value as
programmed by HPDMA_CxBR1.BRSDEC and HPDMA_CxBR2.BRSAO[15:0]
In linked-list mode, after a LLI data transfer is completed, this register is automatically
updated by HPDMA from the memory, provided the LLI is set with HPDMA_CxLLR.USA = 1.
Note: A source address must be aligned with the programmed data width of a source burst
(SA[2:0] versus HPDMA_CxTR1.SDW_LOG2[1:0]). Else, a user setting error is
reported and no transfer is issued.
When the source block size is not a multiple of the source burst size and is a multiple of
the source data width, the last programmed source burst is not completed and is
internally shorten to match the block size. In this case, the additional
HPDMA_CxTR3.SAO[12:0] is not applied.

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18.8.17 HPDMA channel x destination address register (HPDMA_CxDAR)

Address offset: 0x0A0 + 0x80 * x (x = 0 to 15)
Reset value: 0x0000 0000
This register is secure or nonsecure depending on the secure state of channel x
(HPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged
state of channel x (HPDMA_PRIVCFGR.PRIVx).
This register is CID-filtered depending on the CID configuration of the channel x
(HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, an access to
this register is granted to the debug domain CID, regardless of any CID filtering.
This register configures the destination start address of a transfer.
This register must be written when HPDMA_CxCR.EN = 0.
This register is read-only when HPDMA_CxCR.EN = 1, and continuously updated by
hardware, in order to reflect the address of the next burst transfer to the destination.
This register must be written when the channel is completed (then the hardware has
deasserted HPDMA_CxCR.EN). A channel transfer can be completed and programmed at
different levels: block, 2D/repeated block, LLI, or full linked-list.
In linked-list mode, during the link transfer, this register is automatically updated by HPDMA
from the memory if HPDMA_CxLLR.UDA = 1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:0 DA[31:0]: destination address

This bitfield is the pointer to the address from which the next data is written.
During the channel activity, depending on the destination addressing mode
(HPDMA_CxTR1.DINC), this bitfield is kept fixed or incremented by the data width
(HPDMA_CxTR1.DDW_LOG2[1:0]) after each burst destination data, reflecting the next
address from which data is written.
During the channel activity, this address is updated after each completed destination burst,
consequently to:
– the programmed destination burst; either in fixed addressing mode or in contiguous-data
incremented mode. If contiguously incremented (HPDMA_CxTR1.DINC = 1), then the
additional address offset value is the programmed burst size, as defined by
HPDMA_CxTR1.DBL_1[5:0] and HPDMA_CxTR1.DDW_LOG2[1:0]
– the additional destination incremented/decremented offset value as programmed by
HPDMA_CxBR1.DDEC and HPDMA_CxTR3.DAO[12:0]
– once/if completed destination block transfer, for a channel x with 2D addressing capability
(x = 12 to 15), the additional block repeat destination incremented/decremented offset value
as programmed by HPDMA_CxBR1.BRDDEC and HPDMA_CxBR2.BRDAO[15:0]
In linked-list mode, after a LLI data transfer is completed, this register is automatically
updated by the HPDMA from the memory, provided the LLI is set with
HPDMA_CxLLR.UDA = 1.
Note: A destination address must be aligned with the programmed data width of a destination
burst (DA[2:0] versus HPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user setting error is
reported and no transfer is issued.

916/4691 RM0486 Rev 2

RM0486 High-performance direct memory access controller (HPDMA)

18.8.18 HPDMA channel x transfer register 3 (HPDMA_CxTR3)

Address offset: 0x0A4 + 0x80 * x (x = 12 to 15)
Reset value: 0x0000 0000
This register is secure or nonsecure depending on the secure state of channel x
(HPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged
state of channel x (HPDMA_PRIVCFGR.PRIVx).
This register is CID-filtered depending on the CID configuration of the channel x
(HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, a write access
to this register is granted to the debug domain CID, regardless of any CID filtering.
This register controls the transfer of a channel x.
This register must be written when HPDMA_CxCR.EN = 0.
This register is read-only when HPDMA_CxCR.EN = 1.
This register must be written when the channel is completed (then the hardware has
deasserted HPDMA_CxCR.EN). A channel transfer can be completed and programmed at
different levels: block, 2D/repeated block, LLI, or full linked-list.
In linked-list mode, during the link transfer, this register is automatically updated by the
HPDMA from the memory if HPDMA_CxLLR.UT3 = 1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. DAO[12:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. SAO[12:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:16 DAO[12:0]: Destination address offset increment
The destination address, pointed by HPDMA_CxDAR, is incremented or decremented
(depending on HPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed
destination burst. This offset is not including and is added to the programmed burst size
when the completed burst is addressed in incremented mode (HPDMA_CxTR1.DINC = 1).
Note: A destination address offset must be aligned with the programmed data width of a
destination burst (DAO[2:0] versus HPDMA_CxTR1.DDW_LOG2[1:0]). Else, a user
setting error is reported and no transfer is issued.
Bits 15:13 Reserved, must be kept at reset value.

RM0486 Rev 2 917/4691

924
High-performance direct memory access controller (HPDMA) RM0486

Bits 12:0 SAO[12:0]: Source address offset increment

The source address, pointed by HPDMA_CxSAR, is incremented or decremented
(depending on HPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed
source burst. This offset is not including and is added to the programmed burst size when the
completed burst is addressed in incremented mode (HPDMA_CxTR1.SINC = 1).
Note: A source address offset must be aligned with the programmed data width of a source
burst (SAO[2:0] versus HPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is
reported and none transfer is issued.
When the source block size is not a multiple of the destination burst size and is a
multiple of the source data width, then the last programmed source burst is not
completed and is internally shorten to match the block size. In this case, the additional
HPDMA_CxTR3.SAO[12:0] is not applied.

18.8.19 HPDMA channel x block register 2 (HPDMA_CxBR2)

Address offset: 0x0A8 + 0x80 * x (x = 12 to 15)
Reset value: 0x0000 0000
This register is secure or nonsecure depending on the secure state of channel x
(HPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged
state of channel x (HPDMA_PRIVCFGR.PRIVx).
This register is CID-filtered depending on the CID configuration of the channel x
(HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, a write access
to this register is granted to the debug domain CID, regardless of any CID filtering.
This register controls the transfer of a channel x at a 2D/repeated block level.
This register must be written when HPDMA_CxCR.EN = 0.
This register is read-only when HPDMA_CxCR.EN = 1.
This register must be written when the channel is completed (then the hardware has
deasserted HPDMA_CxCR.EN). A channel transfer can be completed and programmed at
different levels: block, 2D/repeated block, LLI, or full linked-list.
In linked-list mode, during the link transfer, this register is automatically updated by the
HPDMA from the memory if HPDMA_CxLLR.UB2 = 1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRDAO[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRSAO[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

918/4691 RM0486 Rev 2

RM0486 High-performance direct memory access controller (HPDMA)

Bits 31:16 BRDAO[15:0]: Block repeated destination address offset

For a channel with 2D addressing capability, this bitfield is used to update (by addition or
subtraction depending on HPDMA_CxBR1.BRDDEC) the current destination address
(HPDMA_CxDAR) at the end of a block transfer.
Note: A block repeated destination address offset must be aligned with the programmed data
width of a destination burst (BRDAO[2:0] versus HPDMA_CxTR1.DDW_LOG2[1:0]).
Else a user setting error is reported and no transfer is issued.
BRDAO[15:0] must be set to 0 in peripheral flow-control mode
(if HPDMA_CxTR2.PFREQ = 1).
Bits 15:0 BRSAO[15:0]: Block repeated source address offset
For a channel with 2D addressing capability, this bitfield is used to update (by addition or
subtraction depending on HPDMA_CxBR1.BRSDEC) the current source address
(HPDMA_CxSAR) at the end of a block transfer.
Note: A block repeated source address offset must be aligned with the programmed data
width of a source burst (BRSAO[2:0] versus HPDMA_CxTR1.SDW_LOG2[1:0]). Else a
user setting error is reported and no transfer is issued.
BRSAO[15:0] must be set to 0 in peripheral flow-control mode
(if HPDMA_CxTR2.PFREQ = 1).

18.8.20 HPDMA channel x linked-list address register (HPDMA_CxLLR)

Address offset: 0x0CC + 0x80 * x (x = 0 to 11)
Reset value: 0x0000 0000
This register is secure or nonsecure depending on the secure state of channel x
(HPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged
state of channel x (HPDMA_PRIVCFGR.PRIVx).
This register is CID-filtered depending on the CID configuration of the channel x
(HPDMA_CxCIDCFGR.CFEN = 1). If the debug domain feature is activated, a write access
to this register is granted to the debug domain CID, regardless of any CID filtering.
This register configures the data structure of the next LLI in the memory and its address
pointer. A channel transfer is completed when this register is null.
This register must be written when HPDMA_CxCR.EN = 0.
This register is read-only when HPDMA_CxCR.EN = 1.
This register must be written when the channel is completed (then the hardware has
deasserted HPDMA_CxCR.EN). A channel transfer can be completed and programmed at
different levels: block, 2D/repeated block, LLI, or full linked-list.
In linked-list mode, during the link transfer, this register is automatically updated by the
HPDMA from the memory if HPDMA_CxLLR.ULL = 1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UT1 UT2 UB1 USA UDA Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ULL
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LA[15:2] Res. Res.
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0486 Rev 2 919/4691

924
High-performance direct memory access controller (HPDMA) RM0486

Bit 31 UT1: Update HPDMA_CxTR1 from memory

This bit controls the update of HPDMA_CxTR1 from the memory during the link transfer.
0: No HPDMA_CxTR1 update
1: HPDMA_CxTR1 update
Bit 30 UT2: Update HPDMA_CxTR2 from memory
This bit controls the update of HPDMA_CxTR2 from the memory during the link transfer.
0: No HPDMA_CxTR2 update
1: HPDMA_CxTR2 update
Bit 29 UB1: Update HPDMA_CxBR1 from memory
This bit controls the update of HPDMA_CxBR1 from the memory during the link transfer.
If UB1 = 0 and if HPDMA_CxLLR ≠ 0, the linked-list is not completed.
HPDMA_CxBR1.BNDT[15:0] is then restored to the programmed value after data transfer is
completed and before the link transfer.
0: No HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any
link transfer)
1: HPDMA_CxBR1 update
Bit 28 USA: Update HPDMA_CxSAR from memory
This bit controls the update of HPDMA_CxSAR from the memory during the link transfer.
0: No HPDMA_CxSAR update
1: HPDMA_CxSAR update
Bit 27 UDA: Update HPDMA_CxDAR register from memory
This bit is used to control the update of HPDMA_CxDAR from the memory during the link
transfer.
0: No HPDMA_CxDAR update
1: HPDMA_CxDAR update
Bits 26:17 Reserved, must be kept at reset value.
Bit 16 ULL: Update HPDMA_CxLLR register from memory
This bit is used to control the update of HPDMA_CxLLR from the memory during the link
transfer.
0: No HPDMA_CxLLR update
1: HPDMA_CxLLR update
Bits 15:2 LA[15:2]: Pointer (16-bit low-significant address) to the next linked-list data structure
If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:2] = 0, the current LLI is the last
one. The channel transfer is completed without any update of the linked-list HPDMA
register file.
Else, this bitfield is the pointer to the memory address offset from which the next linked-list
data structure is automatically fetched from, once the data transfer is completed, in order to
conditionally update the linked-list HPDMA internal register file (HPDMA_CxTR1,
HPDMA_CxTR2, HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR, and
HPDMA_CxLLR).
Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are
write ignored.
Bits 1:0 Reserved, must be kept at reset value.

920/4691 RM0486 Rev 2

RM0486 High-performance direct memory access controller (HPDMA)

18.8.21 HPDMA channel x alternate linked-list address register

(HPDMA_CxLLR)
Address offset: 0x0CC + 0x80 * x (x = 12 to 15)
Reset value: 0x0000 0000
This register is secure or nonsecure depending on the secure state of channel x
(HPDMA_SECCFGR.SECx), and privileged or unprivileged, depending on the privileged
state of channel x (HPDMA_PRIVCFGR.PRIVx).
This register configures the data structure of the next LLI in the memory and its address
pointer. A channel transfer is completed when this register is null.
This register must be written when HPDMA_CxCR.EN = 0.
This register is read-only when HPDMA_CxCR.EN = 1.
This register must be written when the channel is completed (then the hardware has
deasserted HPDMA_CxCR.EN). A channel transfer can be completed and programmed at
different levels: block, 2D/repeated block, LLI, or full linked-list.
In linked-list mode, during the link transfer, this register is automatically updated by the
HPDMA from the memory if HPDMA_CxLLR.ULL = 1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UT1 UT2 UB1 USA UDA UT3 UB2 Res. Res. Res. Res. Res. Res. Res. Res. ULL
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LA[15:2] Res. Res.
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 UT1: Update HPDMA_CxTR1 from memory

This bit controls the update of HPDMA_CxTR1 from the memory during the link transfer.
0: No HPDMA_CxTR1 update
1: HPDMA_CxTR1 update
Bit 30 UT2: Update HPDMA_CxTR2 from memory
This bit controls the update of HPDMA_CxTR2 from the memory during the link transfer.
0: No HPDMA_CxTR2 update
1: HPDMA_CxTR2 update
Bit 29 UB1: Update HPDMA_CxBR1 from memory
This bit controls the update of HPDMA_CxBR1 from the memory during the link transfer.
If UB1 = 0 and if HPDMA_CxLLR ≠ 0, the linked-list is not completed.
HPDMA_CxBR1.BNDT[15:0] is then restored to the programmed value after data transfer is
completed and before the link transfer.
0: No HPDMA_CxBR1 update from memory (HPDMA_CxBR1.BNDT[15:0] restored if any
link transfer)
1: HPDMA_CxBR1 update
Bit 28 USA: Update HPDMA_CxSAR from memory
This bit controls the update of HPDMA_CxSAR from the memory during the link transfer.
0: No HPDMA_CxSAR update
1: HPDMA_CxSAR update

RM0486 Rev 2 921/4691

924
High-performance direct memory access controller (HPDMA) RM0486

Bit 27 UDA: Update HPDMA_CxDAR register from memory

This bit is used to control the update of HPDMA_CxDAR from the memory during the link
transfer.
0:No HPDMA_CxDAR update
1: HPDMA_CxDAR update
Bit 26 UT3: Update HPDMA_CxTR3 from memory
This bit controls the update of HPDMA_CxTR3 from the memory during the link transfer.
0: No HPDMA_CxTR3 update
1: HPDMA_CxTR3 update
Bit 25 UB2: Update HPDMA_CxBR2 from memory
This bit controls the update of HPDMA_CxBR2 from the memory during the link transfer.
0: No HPDMA_CxBR2 update
1: HPDMA_CxBR2 update
Bits 24:17 Reserved, must be kept at reset value.
Bit 16 ULL: Update HPDMA_CxLLR register from memory
This bit is used to control the update of HPDMA_CxLLR from the memory during the link
transfer.
0: No HPDMA_CxLLR update
1: HPDMA_CxLLR update
Bits 15:2 LA[15:2]: Pointer (16-bit low-significant address) to the next linked-list data structure
If UT1 = UT2 = UB1 = USA = UDA = ULL= 0 and if LA[15:2] = 0, the current LLI is the last
one. The channel transfer is completed without any update of the linked-list HPDMA register
file.
Else, this bitfield is the pointer to the memory address offset from which the next linked-list
data structure is automatically fetched from, once the data transfer is completed, in order to
conditionally update the linked-list HPDMA internal register file (HPDMA_CxTR1,
HPDMA_CxTR2, HPDMA_CxBR1, HPDMA_CxSAR, HPDMA_CxDAR and
HPDMA_CxLLR).
Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are
write ignored.
Bits 1:0 Reserved, must be kept at reset value.

18.8.22 HPDMA register map

Table 96. HPDMA register map and reset values

Offset Register name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
SEC15
SEC14
SEC13
SEC12

SEC10
SEC11

SEC9
SEC8
SEC7
SEC6
SEC5
SEC4
SEC3
SEC2
SEC1
SEC0

HPDMA_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

0x000 SECCFGR

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PRIV15
PRIV14
PRIV13
PRIV12

PRIV10
PRIV11

PRIV9
PRIV8
PRIV7
PRIV6
PRIV5
PRIV4
PRIV3
PRIV2
PRIV1
PRIV0

HPDMA_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

0x004 PRIVCFGR

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LOCK15
LOCK14
LOCK13
LOCK12

LOCK10
LOCK11

LOCK9
LOCK8
LOCK7
LOCK6
LOCK5
LOCK4
LOCK3
LOCK2
LOCK1
LOCK0

HPDMA_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

0x008 RCFGLOCKR

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

922/4691 RM0486 Rev 2

 0x010

0x04C
0x00C

0x098+
0x014 -

0x098 +
0x094 +
0x090 +
0x064 +
0x060 +
0x058 +
0x054 +
0x050 +

0x80 * x
0x80 * x
0x80 * x
Offset

0x09C +
0x05C +

0x080 * x
0x080 * x
0x080 * x
0x080 * x
0x080 * x
0x080 * x
0x080 * x
0x080 * x

(x=0 to 11)

(x=0 to 15)
(x=0 to 15)
(x=0 to 15)
(x=0 to 15)
(x=0 to 15)
(x=0 to 15)
RM0486

(x = 0 to 15)
(x = 0 to 15)
(x = 0 to 15)

(x=12 to 15)
HPDMA_
HPDMA_
Reserved

CxSEMCR

Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

CxCIDCFGR
HPDMA_MISR

HPDMA_CxSR

HPDMA_CxCR

HPDMA_CxTR2
HPDMA_CxTR1

HPDMA_CxBR1
HPDMA_CxBR1
HPDMA_SMISR

HPDMA_CxSAR
HPDMA_CxFCR
HPDMA_CxLBAR
Register name

0
0
0
0
0
BRDDEC Res. DSEC Res. Res. Res. Res. Res. Res. Res. 31
TCEM[1:0]

0
0
0
0
0
BRSDEC Res. DAP Res. Res. Res. Res. Res. Res. Res. 30

0
0
0
DDEC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29

0
0
0
0
SDEC Res. Res. DWX Res. Res. Res. Res. Res. Res. Res. 28

0
0
0
Res. Res. Res. DHX Res. Res. Res. Res. Res. Res. Res. 27

0
0
0
0
Res. Res. DBX Res. Res. Res. Res. Res. Res. Res. 26

0
0
0
0
Res. Res. Res. Res. Res. Res. 0 Res. Res. 25
TRIGPOL[1:0]

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 24

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 23

PRIO[1:0]
LBA[31:16]

0
0
0
0
0
0
0

0
Res. Res. Res. SEM_WLIST_CID6 Res. Res. 22

DBL_1[5:0]

0
0
0
0
0
0

0
Res. Res. Res. Res. SEM_WLIST_CID5 Res. Res. 21

0
0
0
0
0
0

0
Res. Res. Res. Res. SEM_WLIST_CID4 Res. Res. 20

BRC[10:0]

0
0
0
0
0
0

Res. DINC Res. Res. Res. 0 SEM_WLIST_CID3 Res. Res. 19

FIFOL[8:0]

0
0
0
0
0

0
Res. Res. Res. Res. Res. SEM_WLIST_CID2 Res. Res. 18

RM0486 Rev 2
TRIGSEL[6:0]

0
0
0
0
0

0
0
0

Res. LAP Res. Res. SEM_WLIST_CID1 Res. Res. 17

DDW_LOG2[1:0]

0
0
0
0
0

0
0
0

Res. LSM Res. Res. SEM_WLIST_CID0 Res. Res. 16

0
0
0
0

0
0
0

SSEC Res. Res. Res. Res. Res. Res. MIS15 MIS15 15

SA[31:0]
Reserved

TRIGM[1:0]

0
0
0
0

0
0
0
0
0
0

SAP TOIE TOF TOF Res. Res. Res. MIS14 MIS14 14

0
0
0

0
0
0
0
0
0

Res. SBX SUSPIE SUSPF SUSPF Res. Res. Res. MIS13 MIS13 13

0
0
0
0

0
0
0
0
0
0

PFREQ USEIE USEF USEF Res. Res. Res. MIS12 MIS12 12

PAM[1:0]

0
0
0
0

0
0
0
0
0
0

BREQ ULEIE ULEF ULEF Res. Res. Res. MIS11 MIS11 11

0
0
0

0
0
0
0
0
0

DREQ Res. DTEIE DTEF DTEF Res. Res. Res. MIS10 MIS10 10

0
0
0
0

0
0
0
0
0
0

SWREQ HTIE HTF HTF Res. Res. Res. MIS9 MIS9 9

0
0
0

0
0
0
0
0
0
Table 96. HPDMA register map and reset values (continued)

Res. TCIE TCF TCF Res. Res. Res. MIS8 MIS8 8

0
0
0

0
0
0
0

Res. Res. Res. Res. Res. Res. MIS7 MIS7 7

BNDT[15:0]
BNDT[15:0]

0
0
0

0
0
0
0
0

Res. Res. Res. Res. MIS6 MIS6 6

SEM_CCID

SBL_1[5:0]

0
0
0

0
0
0
0
0

Res. Res. Res. SCID[2:0] Res. MIS5 MIS5 5

[2:0]

0
0
0

0
0
0
0
0

Res. Res. Res. Res. MIS4 MIS4 4

0
0
0

0
0
0
0

SINC Res. Res. Res. Res. Res. Res. MIS3 MIS3 3

0
0
0
0
0
0
0

Res. SUSP Res. Res. Res. Res. Res. MIS2 MIS2

REQSEL[7:0]
2

0
0
0
0
0
0
0
0
0

RESET Res. Res. Res. SEM_EN Res. MIS1 MIS1 1

SDW_LOG2[1:0]

0
0
0
0
0
0
1
0
0
0

0
High-performance direct memory access controller (HPDMA)

923/4691
EN IDLEF Res. SEM_MUTEX CFEN Res. MIS0 MIS0 0

924
High-performance direct memory access controller (HPDMA) RM0486

Table 96. HPDMA register map and reset values (continued)

Offset Register name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
0x0A0 + HPDMA_CxDAR DA[31:0]
0x080 * x
(x=0 to 15) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x0A4 + HPDMA_
Res.
Res.
Res.

Res.
Res.
Res.
DAO[12:0] SAO[12:0]
0x080 * x CxTR3
(x = 12 to
15) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x0A8 + HPDMA_CxBR2 BRDAO[15:0] BRSAO[15:0]
0x080 * x
(x=12 to 15) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
UDA
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
USA
UB1

0x0CC +
UT1
UT2

ULL
HPDMA_CxLLR LA[15:2]
0x080 * x
(x=0 to 11) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
UDA
USA

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
UB1

UB2
0x0CC +
UT1
UT2

UT3

ULL
HPDMA_CxLLR LA[15:2]
0x080 * x
(x=12 to 15) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.3 for the register boundary addresses.

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RM0486 General purpose direct memory access controller (GPDMA)

19 General purpose direct memory access controller

(GPDMA)

19.1 GPDMA introduction

The general purpose direct memory access (GPDMA) controller is a bus master and system
peripheral.
The GPDMA is used to perform programmable data transfers between memory-mapped
peripherals and/or memories via linked-lists, upon the control of an off-loaded CPU.

19.2 GPDMA main features

• Dual bidirectional AHB master
• Memory-mapped data transfers from a source to a destination:
– Peripheral-to-memory
– Memory-to-peripheral
– Memory-to-memory
– Peripheral-to-peripheral
Transfer arbitration based on a 4-grade programmed priority at channel level:
– One high-priority traffic class, for time-sensitive channels (queue 3)
– Three low-priority traffic classes, with a weighted round-robin allocation for non
time-sensitive channels (queues 0, 1, 2)
• Per channel event generation, on any of the following events: transfer complete, half
transfer complete, data transfer error, user setting error, link transfer error, completed
suspension, and trigger overrun
• Per channel interrupt generation, with separately programmed interrupt enable per
event
• 16 concurrent GPDMA channels:
– Per channel FIFO for queuing source and destination transfers
(see Section 19.3.1)
– Intra-channel GPDMA transfers chaining via programmable linked-list into
memory, supporting two execution modes: run-to-completion and link step mode
– Intra-channel and inter-channel GPDMA transfers chaining via programmable
GPDMA input triggers connection to GPDMA task completion events
• Per linked-list item within a channel:
– Separately programmed source and destination transfers
– Programmable data handling between source and destination: byte-based
reordering, packing or unpacking, padding or truncation, sign extension and
left/right realignment
– Programmable number of data bytes to be transferred from the source, defining
the block level
– Linear source and destination addressing: either fixed or contiguously
incremented addressing, programmed at a block level, between successive burst
transfers

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– 2D source and destination addressing: programmable signed address offsets

between successive burst transfers (non-contiguous addressing within a block,
combined with programmable signed address offsets between successive blocks,
at a second 2D/repeated block level, for a reduced set of channels
(see Section 19.3.1)
– Support for scatter-gather (multi-buffer transfers), data interleaving and
deinterleaving via 2D addressing
– Programmable GPDMA request and trigger selection
– Programmable GPDMA half transfer and transfer complete events generation
– Pointer to the next linked-list item and its data structure in memory, with automatic
update of the GPDMA linked-list control registers
– Channel abort and restart
• Debug:
– Channel suspend and resume support
– Channel status reporting, including FIFO level, and event flags
• TrustZone support:
– Support for secure and nonsecure GPDMA transfers, independently at a first
channel level, and independently at a source/destination and link sublevels
– Secure and nonsecure interrupts reporting, resulting from any of the respectively
secure and nonsecure channels
– TrustZone-aware AHB slave port, protecting any GPDMA secure resource
(register, register field) from a nonsecure access
• Privileged/unprivileged support:
– Support for privileged and unprivileged GPDMA transfers, independently at a
channel level
– Privileged-aware AHB slave port

19.3 GPDMA implementation

19.3.1 GPDMA channels

A given GPDMA channel x is implemented with the following features and intended usage.
To make the best use of the GPDMA performances, the table below lists some general
recommendations, allowing the user to select and allocate a channel, given its implemented
FIFO size and the requested GPDMA transfer.

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Table 97. GPDMA1 channel implementation

Hardware parameters
Channel x Features
dma_fifo_ dma_
size[x] addressing[x]

Channel x (x = 0 to 11) is implemented with:

– a FIFO of 8 bytes, 2 words
x = 0 to 11 2 0 – fixed/contiguously incremented addressing
These channels must be typically allocated for GPDMA transfers
between an APB or AHB peripheral and SRAM.
Channel x (x = 12 to 15) is implemented with:
– a FIFO of 32 bytes, 8 words
– 2D addressing
x = 12 to 15 4 1
These channels may be also used for GPDMA transfers, between a
demanding AHB peripheral and SRAM, or for transfers from/to external
memories.

19.3.2 GPDMA in low-power modes

The GPDMA wake-up feature is implemented in the device low-power modes as per the
table below.

Table 98. GPDMA1 wake-up in low-power modes

Feature Low-power modes

Wake-up GPDMA1 in Sleep mode

19.3.3 GPDMA requests

A GPDMA request from a peripheral can be assigned to a GPDMA channel x, via
REQSEL[7:0] in GPDMA_CxTR2, provided that SWREQ = 0.
The GPDMA requests mapping is specified in the table below.

Table 99. Programmed GPDMA1 request

GPDMA_CxTR2.REQSEL[7:0] Selected GPDMA request

0 jpeg_rx_dma
1 jpeg_tx_dma
2 xspi1_dma
3 xspi2_dma
4 xspi3_dma
5 fmc_txrx_dma
6 fmc_bch_dma
7 adc1_dma
8 adc2_dma

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Table 99. Programmed GPDMA1 request (continued)

GPDMA_CxTR2.REQSEL[7:0] Selected GPDMA request

9 cryp_in_dma
10 cryp_out_dma
11 saes_out_dma
12 saes_in_dma
13 hash_in_dma
14 tim1_cc1_dma
15 tim1_cc2_dma
16 tim1_cc3_dma
17 tim1_cc4_dma
18 tim1_upd_dma
19 tim1_trg_dma
20 tim1_com_dma
21 tim2_cc1_dma
22 tim2_cc2_dma
23 tim2_cc3_dma
24 tim2_cc4_dma
25 tim2_upd_dma
26 tim2_trg_dma
27 tim3_cc1_dma
28 tim3_cc2_dma
29 tim3_cc3_dma
30 tim3_cc4_dma
31 tim3_upd_dma
32 tim3_trg_dma
33 tim4_cc1_dma
34 tim4_cc2_dma
35 tim4_cc3_dma
36 tim4_cc4_dma
37 tim4_upd_dma
38 tim4_trg_dma
39 tim5_cc1_dma
40 tim5_cc2_dma
41 tim5_cc3_dma
42 tim5_cc4_dma
43 tim5_upd_dma

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Table 99. Programmed GPDMA1 request (continued)

GPDMA_CxTR2.REQSEL[7:0] Selected GPDMA request

44 tim5_trg_dma
45 tim6_upd_dma
46 tim7_upd_dma
47 tim8_cc1_dma
48 tim8_cc2_dma
49 tim8_cc3_dma
50 tim8_cc4_dma
51 tim8_upd_dma
52 tim8_trg_dma
53 tim8_com_dma
54 -
55 -
56 tim15_cc1_dma
57 tim15_cc2_dma
58 tim15_upd_dma
59 tim15_trg_dma
60 tim15_com_dma
61 tim16_cc1_dma
62 tim16_upd_dma
63 tim16_com_dma
64 tim17_cc1_dma
65 tim17_upd_dma
66 tim17_com_dma
67 tim18_cc1_dma
68 tim18_upd_dma
69 tim18_com_dma
70 lptim1_ic1_dma
71 lptim1_ic2_dma
72 lptim1_ue_dma
73 lptim2_ic1_dma
74 lptim2_ic2_dma
75 lptim2_ue_dma
76 lptim3_ic1_dma
77 lptim3_ic2_dma
78 lptim3_ue_dma

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Table 99. Programmed GPDMA1 request (continued)

GPDMA_CxTR2.REQSEL[7:0] Selected GPDMA request

79 spi1_rx_dma
80 spi1_tx_dma
81 spi2_rx_dma
82 spi2_tx_dma
83 spi3_rx_dma
84 spi3_tx_dma
85 spi4_rx_dma
86 spi4_tx_dma
87 spi5_rx_dma
88 spi5_tx_dma
89 spi6_rx_dma
90 spi6_tx_dma
91 sai1_a_dma
92 sai1_b_dma
93 sai2_a_dma
94 sai2_b_dma
95 i2c1_rx_dma
96 i2c1_tx_dma
97 i2c2_rx_dma
98 i2c2_tx_dma
99 i2c3_rx_dma
100 i2c3_tx_dma
101 i2c4_rx_dma
102 i2c4_tx_dma
103 i3c1_rx_dma
104 i3c1_tx_dma
105 i3c2_rx_dma
106 i3c2_tx_dma
107 usart1_rx_dma
108 usart1_tx_dma
109 usart2_rx_dma
110 usart2_tx_dma
111 usart3_rx_dma
112 usart3_tx_dma
113 uart4_rx_dma

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Table 99. Programmed GPDMA1 request (continued)

GPDMA_CxTR2.REQSEL[7:0] Selected GPDMA request

114 uart4_tx_dma
115 uart5_rx_dma
116 uart5_tx_dma
117 usart6_rx_dma
118 usart6_tx_dma
119 uart7_rx_dma
120 uart7_tx_dma
121 uart8_rx_dma
122 uart8_tx_dma
123 uart9_rx_dma
124 uart9_tx_dma
125 usart10_rx_dma
126 usart10_tx_dma
127 lpuart1_rx_dma
128 lpuart1_tx_dma
129 spdifrx_cs_dma
130 spdifrx_dt_dma
131 adf1_flt0_dma
132 mdf1_flt0_dma
133 mdf1_flt1_dma
134 mdf1_flt2_dma
135 mdf1_flt3_dma
136 mdf1_flt4_dma
137 mdf1_flt5_dma
138 ucpd1_tx_dma
139 ucpd1_rx_dma
140 dcmi_dma or pssi_dma(1)
141 i3c1_tc_dma
142 i3c1_rs_dma
143 i3c2_tc_dma
144 i3c2_rs_dma
1. Depends on which exclusive function is used.

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19.3.4 GPDMA block requests

Some GPDMA requests must be programmed as a block request, and not as a burst
request. Then BREQ in GPDMA_CxTR2 must be set for a correct GPDMA execution of the
requested peripheral transfer at the hardware level.

Table 100. Programmed GPDMA1 request as a block request

GPDMA block requests

lptim1_ue_dma
lptim2_ue_dma
lptim3_ue_dma

19.3.5 GPDMA channels with peripheral early termination

A GPDMA channel, if implemented with this feature, can support the early termination of
the data transfer from the peripheral which does also support this feature.

Table 101. GPDMA1 channel with peripheral early termination

GPDMA channel x with peripheral early termination

x = 0, x = 1, and x = 15

This GPDMA support is activated when the channel x is programmed with

GPDMA_CxTR2.PFREQ = 1. Then, the peripheral itself can initiate and request a data
transfer completion, before that the GPDMA has transferred the whole block
(see Section 19.4.14 for more details).

Table 102. Programmed GPDMA1 request with peripheral early termination

Programmed GPDMA channel x request with peripheral early termination

i3c1_rx_dma
i3c2_rx_dma
jpeg_tx_dma

19.3.6 GPDMA triggers

A GPDMA trigger can be assigned to a GPDMA channel x, via TRIGSEL[6:0]
in GPDMA_CxTR2, provided that TRIGPOL[1:0] defines a rising or a falling edge of the
selected trigger (TRIGPOL[1:0] = 01 or TRIGPOL[1:0] = 10).

Table 103. Programmed GPDMA1 trigger

GPDMA_CxTR2.TRIGSEL[7:0] Selected GPDMA trigger

0 dcmipp_p1_frameend_evt
1 dcmipp_p1_lineend_evt
2 dcmipp_p1_hsync_evt

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Table 103. Programmed GPDMA1 trigger (continued)

GPDMA_CxTR2.TRIGSEL[7:0] Selected GPDMA trigger

3 dcmipp_p1_vsync_evt
4 dcmipp_p1_frameend_evt
5 dcmipp_p1_lineend_evt
6 dcmipp_p1_hsync_evt
7 dcmipp_p1_vsync_evt
8 dcmipp_p2_frameend_evt
9 dcmipp_p2_lineend_evt
10 dcmipp_p2_hsync_evt
11 dcmipp_p2_vsync_evt
12 dma2d_ctc_flag
13 dma2d_tc_flag
14 dma2d_tw_flag
15 jpeg_eoc_flag
16 jpeg_ifnf_flag
17 jpeg_ift_flag
18 jpeg_ofne_flag
19 jpeg_oft_flag
20 lcd_li_flag
21 gpu2d1_gp_flag[0]
22 gpu2d1_gp_flag[1]
23 gpu2d1_gp_flag[2]
24 gpu2d1_gp_flag[3]
25 gfxtim1_0_gfxtim_evt[3]
26 gfxtim1_0_gfxtim_evt[2]
27 gfxtim1_0_gfxtim_evt[1]
28 gfxtim1_0_gfxtim_evt[0]
29 -
30 lptim1_ch1
31 lptim1_ch2
32 lptim2_ch1
33 lptim2_ch2
34 lptim3_ch1
35 lptim3_ch2
36 lptim4_out
37 lptim5_out

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Table 103. Programmed GPDMA1 trigger (continued)

GPDMA_CxTR2.TRIGSEL[7:0] Selected GPDMA trigger

38 -
39 rtc_wkup
40 lpuart1_it_r_wup_async
41 lpuart1_it_t_wup_async
42 spi6_it_or_spi6_ait_sync
43 -
44 tim1_trgo_cktim
45 tim1_trgo2_cktim
46 tim2_trgo_cktim
47 tim3_trgo_cktim
48 tim4_trgo_cktim
49 tim5_trgo_cktim
50 tim6_trgo_cktim
51 tim7_trgo_cktim
52 tim8_trgo_cktim
53 tim8_trgo2_cktim
54 -
55 -
56 -
57 tim12_trgo_cktim
58 tim15_trgo_cktim
59 -
60 hpdma1_ch0_tc
61 hpdma1_ch1_tc
62 hpdma1_ch2_tc
63 hpdma1_ch3_tc
64 hpdma1_ch4_tc
65 hpdma1_ch5_tc
66 hpdma1_ch6_tc
67 hpdma1_ch7_tc
68 hpdma1_ch8_tc
69 hpdma1_ch9_tc
70 hpdma1_ch10_tc
71 hpdma1_ch11_tc
72 hpdma1_ch12_tc

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Table 103. Programmed GPDMA1 trigger (continued)

GPDMA_CxTR2.TRIGSEL[7:0] Selected GPDMA trigger

73 hpdma1_ch13_tc
74 hpdma1_ch14_tc
75 hpdma1_ch15_tc
76 gpdma1_ch0_tc
77 gpdma1_ch1_tc
78 gpdma1_ch2_tc
79 gpdma1_ch3_tc
80 gpdma1_ch4_tc
81 gpdma1_ch5_tc
82 gpdma1_ch6_tc
83 gpdma1_ch7_tc
84 gpdma1_ch8_tc
85 gpdma1_ch9_tc
86 gpdma1_ch10_tc
87 gpdma1_ch11_tc
88 gpdma1_ch12_tc
89 gpdma1_ch13_tc
90 gpdma1_ch14_tc
91 gpdma1_ch15_tc
92 -
93 extit0_sync
94 extit1_sync
95 extit2_sync
96 extit3_sync
97 extit4_sync
98 extit5_sync
99 extit6_sync
100 extit7_sync
101 extit8_sync
102 extit9_sync
103 extit10_sync
104 extit11_sync
105 extit12_sync
106 extit13_sync

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Table 103. Programmed GPDMA1 trigger (continued)

GPDMA_CxTR2.TRIGSEL[7:0] Selected GPDMA trigger

107 extit14_sync
108 extit15_sync

19.4 GPDMA functional description

19.4.1 GPDMA block diagram

Figure 92. GPDMA block diagram

GPDMA

32-bit AHB bus

Channel datapath and Transfer output control AHB master
transfer input control port 0
DMA interface
Data transfer
requests
Channel x (1) generation
DMA ... Arbitration

32-bit AHB bus

triggers
Channel 1 AHB master
Link transfer port 1
Channel 0 generation interface

DMA DMA channel

clock Interrupt generation interrupt

DMA channel registers

DMA channel
Stop DMA Events generation transfer complete
channel in Channel x (1) (gpdma_chx_tc)
debug mode DMA global Channel state
... DMA channel state
registers management
Channel 1 (vs privilege
and security)
Channel 0 Security and privilege
management
DMA illegal event
(vs security)
AHB slave interface Clock management
DMA clock request

(1) Refer to the device implementation table for the number of channels.
32-bit AHB bus MSv63644V2

19.4.2 GPDMA channel state and direct programming without any linked-list
After a GPDMA reset, a GPDMA channel x is in idle state. When the software writes 1 in
GPDMA_CxCR.EN, the channel takes into account the value of the different channel
configuration registers (GPDMA_CxXXX), switches to the active/non-idle state and starts to
execute the corresponding requested data transfers.
After enabling/starting a GPDMA channel transfer by writing 1 in GPDMA_CxCR.EN, a
GPDMA channel interrupt on a complete transfer notifies the software that the GPDMA

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channel is back in idle state (EN is then deasserted by hardware) and that the channel is
ready to be reconfigured then enabled again.
Figure 93 illustrates this GPDMA direct programming without any linked-list
(GPDMA_CxLLR = 0).

Figure 93. GPDMA channel direct programming without linked-list (GPDMA_CxLLR = 0)

Channel state = Idle

Initialize DMA channel Reconfigure DMA channel
(keeping DMA_CxLLR[31:0] = 0) (keeping DMA_CxLLR[31:0] = 0)

Enable DMA channel

Channel state = Active

Valid user
setting ? N

Y
Setting USEF = 1
Disabling DMA channel
Executing the data transfer
from the register file

No transfer
N
error ?

Y Setting DTEF = 1
Disabling DMA channel

Setting TCF = 1
Disabling DMA channel

End

MSv62626V1

19.4.3 GPDMA channel suspend and resume

The software can suspend on its own a channel still active, with the following sequence:
1. The software writes 1 into the GPDMA_CxCR.SUSP bit.
2. The software polls the suspended flag GPDMA_CxSR.SUSPF until SUSPF = 1, or
waits for an interrupt previously enabled by writing 1 to GPDMA_CxCR.SUSPIE. Wait
for the channel to be effectively in suspended state means wait for the completion of

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any ongoing GPDMA transfer over its master ports. Then the software can observe, in
a steady state, any read register or register field that is hardware modifiable.
Note: An ongoing GPDMA transfer can be a data transfer (a source/destination burst transfer) or a
link transfer for the internal update of the linked-list register file from the next linked-list item.
3. The software safely resumes the suspended channel by writing 0 to
GPDMA_CxCR.SUSP.

Figure 94. GPDMA channel suspend and resume sequence

Channel state = Active

Suspend the DMA channel

(write 1 to [Link])
or

N
SUSPF=1 ?

Channel state = Suspended and Idle Y

Receiving
suspended
interrupt

Resume the DMA channel

(write 0 to [Link])

Channel state = Active

MSv62627V1

Note: A suspend and resume sequence does not impact the GPDMA_CxCR.EN bit. Suspending a
channel (transfer) does not suspend a started trigger detection.

19.4.4 GPDMA channel abort and restart

Alternatively, like for aborting a continuous GPDMA transfer with a circular buffering or a
double buffering, the software can abort, on its own, a still active channel with the following
sequence:
1. The software writes 1 into the GPDMA_CxCR.SUSP bit.
2. The software polls suspended flag GPDMA_CxSR.SUSPF until SUSPF = 1, or waits
for an interrupt previously enabled by writing 1 to GPDMA_CxCR.SUSPIE. Wait for the
channel to be effectively in suspended state means wait for the completion of any
ongoing GPDMA transfer over its master port.
3. The software resets the channel by writing 1 to GPDMA_CxCR.RESET. This causes
the reset of the FIFO, the reset of the channel internal state, the reset of the
GPDMA_CxCR.EN bit, and the reset of the GPDMA_CxCR.SUSP bit.

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4. The software safely reconfigures the channel. The software must reprogram the
hardware-modified GPDMA_CxBR1, GPDMA_CxSAR, and GPDMA_CxDAR
registers.
5. In order to restart the aborted then reprogrammed channel, the software enables it
again by writing 1 to the GPDMA_CxCR.EN bit.

Figure 95. GPDMA channel abort and restart sequence

Channel state = Active

Suspend the DMA channel

(write 1 to [Link])
or

N
SUSPF=1 ?

Y
Channel state = Suspended
Receiving (and Idle)
suspended
interrupt

Reset the DMA channel

(write 1 to [Link])

Channel state = Idle

Reconfigure the DMA channel

Enable the DMA channel

Channel state = Active

MSv62628V1

19.4.5 GPDMA linked-list data structure

Alternatively to the direct programming mode, a channel can be programmed by a list of
transfers, known as a list of linked-list items (LLI). Each LLI is defined by its data structure.
The base address in memory of the data structure of a next LLIn+1 of a channel x is the sum
of the following:
• the link base address of the channel x (in GPDMA_CxLBAR)
• the link address offset (LA[15:2] field in GPDMA_CxLLR). The linked-list register
GPDMA_CxLLR is the updated result from the data structure of the previous LLIn of
the channel x.
The data structure for each LLI may be specific.

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A linked-list data structure is addressed following the value of the UT1, UT2, UB1, USA,
UDA and ULL bits, plus UB2 and UT3, in GPDMA_CxLLR.
In linked-list mode, each GPDMA linked-list register (GPDMA_CxTR1, GPDMA_CxTR2,
GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR or GPDMA_CxLLR, plus
GPDMA_CxTR3 or GPDMA_CxBR2) is conditionally and automatically updated from the
next linked-list data structure in the memory, following the current value of the
GPDMA_CxLLR register that was conditionally updated from the linked-list data structure of
the previous LLI.

Static linked-list data structure

For example, when the update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UB2 and
UT3) in GPDMA_CxLLR are all asserted, the linked-list data structure in the memory is
maximal with:
• channel x (x = 0 to 11) contiguous 32-bit locations, including GPDMA_CxTR1,
GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and
GPDMA_CxLLR (see Figure 96) and including the first linked-list register file (LLI0) and
the next LLIs (such as LLI1, LLI2) in the memory
• channel x (x = 12 to 15), contiguous 32-bit locations, including GPDMA_CxTR1,
GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR, and
GPDMA_CxLLR, plus GPDMA_CxTR3 and GPDMA_CxBR2 (see Figure 97), and
including the first linked-list register file (LLI0) and the next LLIs (such as LLI1, LLI2) in
the memory

Figure 96. Static linked-list data structure (all Uxx = 1)

of a linear addressing channel x
DMA register file Memory from link base address
DMA_CxLBAR
Channel x linked-list register file
(LLI0) LLI1
DMA_CxTR1 All Uxx=1 DMA_CxTR1

DMA_CxTR2 DMA_CxTR2

DMA_CxBR1 DMA_CxBR1

DMA_CxSAR DMA_CxSAR

DMA_CxDAR DMA_CxDAR

DMA_CxLLR DMA_CxLLR
All Uxx=1

Channel x other registers LLI2

DMA_CxTR1
Other channels registers DMA_CxTR2

Global registers DMA_CxBR1

DMA_CxSAR
DMA_CxDAR
DMA_CxLLR

MSv62629V1

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Figure 97. Static linked-list data structure (all Uxx = 1)

of a 2D addressing channel x
DMA register file Memory from link base address
DMA_CxLBAR
Channel x linked-list register file
(LLI0) LLI1
DMA_CxTR1 DMA_CxTR1
All Uxx=1
DMA_CxTR2 DMA_CxTR2

DMA_CxBR1 DMA_CxBR1

DMA_CxSAR DMA_CxSAR

DMA_CxDAR DMA_CxDAR

DMA_CxTR3 DMA_CxTR3

DMA_CxBR2 DMA_CxBR2

DMA_CxLLR DMA_CxLLR
All Uxx=1

Channel x other registers

LLI2

Other channels registers DMA_CxTR1

DMA_CxTR2
Global registers
DMA_CxBR1
DMA_CxSAR
DMA_CxDAR
DMA_CxTR3
DMA_CxBR2
DMA_CxLLR

MSv63645V1

Dynamic linked-list data structure

Alternatively, the memory organization for the full list of LLIs can be compacted with specific
data structure for each LLI.
If UT1 = 0 and UT2 = 1, the link address offset of the register GPDMA_CxLLR is pointing to
the updated value of the GPDMA_CxTR2 instead of the GPDMA_CxTR1 which is not to be
modified (see Figure 98).
Example: if UT1 = UB1 = USA = 0 and if UT3 = UB2 = 0, when channel x is with 2D
addressing, and if UT2 = UDA = ULL = 1, the next LLI does not contain an (updated) value
for GPDMA_CxTR1, nor GPDMA_CxBR1, nor GPDMA_CxSAR, nor GPDMA_CxTR3, nor
GPDMA_CxBR2 when channel x is with 2D addressing. The next LLI contains an updated
value for GPDMA_CxTR2, GPDMA_CxDAR, and GPDMA_CxLLR, as shown in Figure 99.

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Figure 98. GPDMA dynamic linked-list data structure

of a linear addressing channel x
LLIn
All Uxx = 1
DMA_CxTR1
DMA_CxTR2
UT1 = UB1 = USA = 0 LLIn+1
DMA_CxBR1 UT2 = UDA = ULL = 1
DMA_CxTR2
DMA_CxSAR
DMA_CxDAR
DMA_CxDAR
DMA_CxLLR
DMA_CxLLR
MSv62630V1

Figure 99. GPDMA dynamic linked-list data structure

of a 2D addressing channel x
LLIn
All Uxx = 1
DMA_CxTR1
UT1 = UB1 = USA = 0
DMA_CxTR2
UT3 = UB2 = 0 LLIn+1
DMA_CxBR1 UT2 = UDA = ULL = 1
DMA_CxTR2
DMA_CxSAR
DMA_CxDAR
DMA_CxDAR
DMA_CxLLR
DMA_CxTR3
DMA_CxBR2
DMA_CxLLR
MSv63646V1

The user must program GPDMA_CxLLR for each LLIn to be 32-bit aligned and not to
exceed the 64-Kbyte addressable space pointed by GPDMA_CxLBAR.

19.4.6 Linked-list item transfer execution

A LLIn transfer is the sequence of:
1. a data transfer: GPDMA executes the data transfer as described by the GPDMA
internal register file (this data transfer can be void/null for LLI0)
2. a conditional link transfer: GPDMA automatically and conditionally updates its internal
register file by the data structure of the next LLIn+1, as defined by the GPDMA_CxLLR
value of the LLIn.
Note: The initial data transfer as defined by the internal register file (LLI0) can be null
(GPDMA_CxBR1.BNDT[15:0] = 0 and GPDMA_CxTR2.PFREQ = 0) provided that the
conditional update bit UB1 in GPDMA_CxLLR is set (meaning there is a non-null data
transfer described by the next LLI1 in the memory to be executed).
Depending on the intended GPDMA usage, a GPDMA channel x can be executed as
described by the full linked-list (run-to-completion mode, GPDMA_CxCR.LSM = 0) or a
GPDMA channel x can be programmed for a single execution of a LLI (link step mode,
GPDMA_CxCR.LSM = 1), as described in the next sections.

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19.4.7 GPDMA channel state and linked-list programming

in run-to-completion mode
When GPDMA_CxCR.LSM = 0 (in full list execution mode, execution of the full sequence of
LLIs, named run-to-completion mode), a GPDMA channel x is initially programmed, started
by writing 1 to GPDMA_CxCR.EN, and after completed at channel level. The channel
transfer is:
• configured with at least the following:
– the first LLI0, internal linked-list register file: GPDMA_CxTR1, GPDMA_CxTR2,
GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR, and GPDMA_CxLLR, plus
GPDMA_CxTR3 and GPDMA_CxBR2
– the last LLIN, described by the linked-list data structure in memory, as defined by
the GPDMA_CxLLR reflecting the before last LLIN-1
• completed when GPDMA_CxLLR[31:0] = 0, GPDMA_CxBR1.BRC[10:0] = 0, and
GPDMA_CxBR1.BNDT[15:0] = 0, at the end of the last LLIN-1 transfer
GPDMA_CxLLR[31:0] = 0 is the condition of a linked-list based channel completion and
means the following:
• The 16 low significant bits GPDMA_CxLLR.LA[15:0] of the next link address are null.
• All the update bits GPDMA_CxLLR.Uxx are null (UT1, UT2, UB1, USA, UDA and ULL,
plus UB2 and UT3).
The channel may never be completed when GPDMA_CxLLR.LSM = 0:
• If the last LLIN is recursive, pointing to itself as a next LLI:
– either GPDMA_CxLLR.ULL = 1 and GPDMA_CxLLR.LA[15:2] is updated by the
same value
– or GPDMA_CxLLR.ULL = 0
• If LLIN is pointing to a previous LLI
In the regular data transfer completion at a block level, GPDMA_CxBR1.BNDT[15:0] = 0
and GPDMA_CxBR1.BRC[10:0] = 0 (if present). Alternatively, a block transfer may be early
completed by a peripheral (such as an I3C in Rx mode), and then BNDT[15:0] is not null
(see Section 19.4.14 for more details).
In the typical run-to-completion mode, the allocation of a GPDMA channel, including its fine
programming, is done once during the GPDMA initialization. In order to have a reserved
data communication link and GPDMA service during run-time, for continuously repeated
transfers (from/to a peripheral respectively to/from memory or for memory-to-memory
transfers). This reserved data communication link can consist of a channel, or the channel
can be shared and a repeated transfer consists of a sequence of LLIs.
Figure 100 depicts the GPDMA channel execution and its registers programming in run-to-
completion mode.
Note: Figure 100 is not intended to illustrate how often a TCEF can be raised, depending on the
programmed value of TCEM[1:0] in GPDMA_CxTR2. It can be raised at (each) block
completion, at (each) 2D block completion, at (each) LLI completion, or only at channel
completion. In run-to-completion mode, whatever is the value of TCEM[1:0], at the channel
completion, the hardware always set TCEF = 1 and disables the channel.
In Figure 100, BNDT ≠ 0 is the typical condition for starting the first data transfer in this
figure. This condition becomes (BNDT ≠ 0 and PFREQ = 1) if the peripheral requests a data
transfer with early termination (see Section 19.3.5).

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Figure 100. GPDMA channel execution and linked-list programming

in run-to-completion mode (GPDMA_CxCR.LSM = 0)
Channel state = Idle

Initialize DMA channel

Reconfigure DMA channel

Enable DMA channel

Channel state = Active

Valid user
setting ? N

Y
Setting USEF = 1
N Disabling DMA channel
BNDT0 ?

Executing once the data

transfer from the register file

No transfer
N
error ?

Y
Setting DTEF = 1
Disabling DMA channel
N LLR 0 ?

Loading next LLI

into the register file

No transfer
N
error ?

Y Setting ULEF = 1
Disabling DMA channel
Valid user
N
setting ?
Y
Setting USEF = 1
Setting TCF = 1 Disabling DMA channel
Disabling DMA channel

End

MSv62631V1

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Run-time inserting a LLIn via an auxiliary channel, in run-to-completion mode

The start of the link transfer of the LLIn-1 (start of the LLIn loading) can be conditioned by the
occurrence of a trigger, when programming the following fields of the GPDMA_CxTR2 in the
data structure of the LLIn-1:
• TRIGM[1:0] = 10 (link transfer triggering mode)
• TRIGPOL[1:0] = 01 or 10 (rising or falling edge)
• TRIGSEL[6:0] (see Section 19.3.6 for the trigger selection details)
Another auxiliary channel y can be used to store the channel x LLIn in the memory and to
generate a transfer complete event gpdma_chy_tc. By selecting this event as the input
trigger of the link transfer of the LLIn-1 of the channel x, the software can pause the primary
channel x after its LLIn-1 data transfer, until it is indeed written the LLIn.
Figure 101 depicts such a dynamic elaboration of a linked-list of a primary channel x, via
another auxiliary channel y.
Caution: This use case is restricted to an application with a LLIn-1 data transfer that does not need a
trigger. The triggering mode of this LLIn-1 is used to load the next LLIn.

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Figure 101. Inserting a LLIn with an auxiliary GPDMA channel y

DMA primary channel x DMA auxiliary channel y CPU

Executing LLIn-2 data transfer

LLIn-1 transfer

Loading LLIn-1
(with DMA_CxTR2: TRIGM[1:0] = 10
TRIGPOL[1:0] = 01
TRIGSEL= dma_chy_tc
and TCEM[1:0] = 01)

Executing LLIn-1 data transfer

Transfer complete interrupt
Build new LLIn
Configure channel Y
LLIn transfer

Executing data transfer

(Memcopy of new LLIn)
dma_chy_tc

Loading new LLIn

Executing LLIn data transfer

transfer
LLIn+1

Loading LLIn+1

MSv62632V2

19.4.8 GPDMA channel state and linked-list programming in link step mode
When GPDMA_CxCR.LSM = 1 (in link step execution mode, single execution of one LLI), a
channel transfer is executed and completed after each single execution of a LLI, including
its (conditional) data transfer and its (conditional) link transfer.
A GPDMA channel transfer can be programmed at LLI level, started by writing 1 into
GPDMA_CxCR.EN, and after completed at LLI level:
• The current LLIn transfer is described with:
– GPDMA_CxTR1 defines the source/destination elementary single/burst transfers.
– GPDMA_CxBR1 defines the number of bytes at a block level (BNDT[15:0]) and,
for channel x (x = 12 to 15), the number of blocks at a 2D/repeated block level
(BRC[10:0]+1) and the incrementing/decrementing mode for address offsets.

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– GPDMA_CxTR2 defines the input control (request, trigger) and the output control
(transfer complete event) of the transfer.
– GPDMA_CxSAR/GPDMA_CxDAR define the source/destination transfer start
address.
– GPDMA_CxTR3 for channel x (x = 12 to 15) defines the source/destination
additional address offset between burst transfers.
– GPDMA_CxBR2 for channel x (x = 12 to 15) defines the source/destination
additional address offset between blocks at a 2D/repeated block level.
– GPDMA_CxLLR defines the data structure and the address offset of the next
LLIn+1 in the memory.
• The current LLIn transfer is completed after the single execution of the current LLIn:
– after the (conditional) data transfer completion (when
GPDMA_CxBR1.BRC[10:0] = 0, and GPDMA_CxBR1.BNDT[15:0] = 0
– after the (conditional) update of the GPDMA link register file from the data
structure of the next LLIn+1 in memory
Note: If a LLI is recursive (pointing to itself as a next LLI, either GPDMA_CxLLR.ULL = 1 and
GPDMA_CxLLR.LA[15:2] is updated by the same value, or GPDMA_CxLLR.ULL = 0), a
channel in link step mode is completed after each repeated single execution of this LLI.
In the regular data transfer completion at a block level, GPDMA_CxBR1.BNDT[15:0] = 0
and GPDMA_CxBR1.BRC[10:0] = 0. Alternatively, a block transfer may be early completed
by a peripheral (such as an I3C in Rx mode), and then BNDT[15:0] is not null
(see Section 19.4.14 for more details).
The link step mode can be used to elaborate dynamically LLIs in memory during run-time.
The software can be facilitated by using a static data structure for any LLIn (all update bits of
GPDMA_CxLLR have a static value, [Link] = [Link] + constant).
Figure 102 depicts the GPDMA channel execution mode, and its programming in link step
mode.
Note: Figure 102 is not intended to illustrate how often a TCEF can be raised, depending on the
programmed value of TCEM[1:0] in GPDMA_CxTR2. It can be raised at (each) block
completion, at (each) 2D block completion, at (each) LLI completion, or only at the last LLI
data transfer completion. In link step mode, the channel is disabled after each single
execution of a LLI, and depending on the value of TCEM[1:0] a TCEF is raised or not.
In Figure 102, BNDT ≠ 0 is the typical condition for starting the first data transfer. This
condition becomes (BNDT ≠ 0 and PFREQ = 1) if the peripheral requests a data transfer
with early termination (see Section 19.3.5).

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Figure 102. GPDMA channel execution and linked-list programming

in link step mode (GPDMA_CxCR.LSM = 1)
Channel state = Idle

Initialize DMA channel

Reconfigure DMA channel

Enable DMA channel

Channel state = Active

Valid user
setting ? N

Y
Setting USEF = 1
N Disabling DMA channel
BNDT  0 ?

Executing once the data

transfer from the register file

No transfer
N
error ?

Y
Setting DTEF = 1
Disabling DMA channel
N LLR 0 ?

Loading next LLI

into the register file

No transfer
N
error ?

Y Setting ULEF = 1
Disabling DMA channel
Valid user
N
setting ?
Y
Setting USEF = 1
Setting TCF = 1 Disabling DMA channel
Disabling DMA channel

End

MSv62633V1

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Run-time adding a LLIn+1 in link step mode

During run-time, the software can defer the elaboration of the LLIn+1 (and next LLIs),
until/after GPDMA executed the transfer from the LLIn-1 and loaded the LLIn from the
memory, as shown in Figure 103.

Figure 103. Building LLIn+1: GPDMA dynamic linked-lists in link step mode

LSM = 1 with 2-stage linked-list programming:

DMA executes LLIn-1 and loads LLIn while CPU builds LLIn+1

DMA Channel CPU

LLIn-2
transfer

Transfer complete interrupt

Enable DMA channel

Executing LLIn-1 data transfer

transfer
LLIn-1

Build and store LLIn+1

Loading LLIn

Transfer complete interrupt

Enable DMA channel

LLIn
transfer

MSv62634V1

Run-time replacing a LLIn with a new LLIn’ in link step mode (in linked-list
register file)
In this link step mode, during run-time, the software can build and insert a new LLIn’, after
GPDMA executed the transfer from the LLIn-1 and loaded a formerly elaborated LLIn from
the memory by overwriting directly the linked-list register file with the new LLIn’, as shown in
Figure 104.

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Figure 104. Replace with a new LLIn’ in register file in link step mode

LSM = 1 with 1-stage linked-list programming:

Overwriting the (pre)loaded LLIn linked-list register file with
a new LLIn’ directly in linked-list register file.
DMA executes LLIn-1 and load LLIn, then CPU builds and overwrites LLIn'

DMA channel CPU

Executing LLIn-1 data transfer

transfer
LLIn-1

Loading LLIn

Transfer complete interrupt

Build LLIn' and overwrite

linked-list register file

Enable DMA channel

Executing LLIn' data transfer

transfer
LLIn'

Loading LLIn+1’

Transfer complete interrupt

Build LLIn+1’' and overwrite

linked-list register file

Enable DMA channel

LLIn+1"
transfer

Transfer complete interrupt

MSv62635V1

Run-time replacing a LLIn with a new LLIn’ in link step mode (in the memory)
The software can build and insert a new LLIn’ and LLIn+1’ in the memory, after GPDMA
executed the transfer from the LLIn-1 and loaded a formerly elaborated LLIn from the
memory, by overwriting partly the linked-list register file (GPDMA_CxBR1.BNDT[15:0] to be
null and GPDMA_CxLLR to point to new LLIn’) as shown in Figure 105.

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Figure 105. Replace with a new LLIn’ and LLIn+1’ in memory in link step mode (option 1)

LSM = 1 with 1-stage linked-list programming:

Overwriting the (pre)loaded LLIn linked-list register file with a new LLIn' and LLIn+1' in memory and
overwrite partly linked-list register file
(DMA_CxBR1.BNDT = 0 and DMA_CxLLR to point to new LLIn')
DMA executes LLIn-1 and load LLIn then CPU builds (LLIn' and LLIn+1') and overwrite (BR1 and LLR)

DMA Channel CPU

Executing LLIn-1 data transfer

transfer
LLIn-1

Loading LLIn

Transfer complete interrupt

Build LLIn' and LLIn+1' in memory

Write DMA_CxBR1.BNDT = 0
Write DMA_CxLLR to point to new LLIn'

Enable DMA channel

transfer
LLIn'

Loading LLIn’

Transfer complete interrupt

Enable DMA channel

Executing LLIn+1' data transfer

transfer
LLIn+1'

Loading LLIn+1'

Transfer complete interrupt

MSv62636V1

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Run-time replacing a LLIn with a new LLIn’ in link step mode

Other software implementations exist. Meanwhile GPDMA executes the transfer from the
LLIn-1 and loads a formerly elaborated LLIn from the memory (or even earlier), the software
can do the following:
1. Disable the NVIC for not being interrupted by the interrupt handling.
2. Build a new LLIn’ and a new LLIn+1’.
3. Enable again the NVIC for the channel interrupt (transfer complete) notification.
The software in the interrupt handler for LLIn-1 is then restricted to overwrite
GPDMA_CxBR1.BNDT[15:0] to be null and GPDMA_CxLLR to point to new LLIn’, as shown
in Figure 106.

Figure 106. Replace with a new LLIn’ and LLIn+1’ in memory in link step mode (option 2)

LSM = 1 with 1-stage linked-list programming:

Overwriting the (pre)loaded LLIn linked-list register file by building new LLIn' and LLIn+1' in memory
while disabling (temporary) channel interrupt at NVIC level, and overwriting DMA_CxBR1.BNDT = 0
and DMA_CxLLR to point to new LLIn'
DMA executes LLIn-1 and loading LLIn while CPU builds (LLIn' and LIn+1'), then CPU overwrites
(BR1 and LLR)

DMA channel CPU

Disable NVIC DMA irq channel

Executing LLIn-1 data transfer
transfer
LLIn-1

Build LLIn' & LLIn+1' in memory

Loading LLIn
Enable NVIC DMA irq channel
Transfer complete interrupt
Write DMA_CxBR1.BNDT = 0
Write DMA_CxLLR to point to new LLIn'

Enable DMA channel

transfer
LLIn'

Loading LLIn’

Transfer complete interrupt

Enable DMA channel

Executing LLIn+1' data transfer

transfer
LLIn+1'

Loading LLIn+1'
Transfer complete interrupt MSv62637V1

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19.4.9 GPDMA channel state and linked-list programming

The software can reconfigure a channel when the channel is disabled
(GPDMA_CxCR.EN = 0) and update the execution mode (GPDMA_CxCR.LSM) to change
from/to run-to-completion mode to/from link step mode.
In any execution mode, the software can:
• reprogram LLIn+1 in the memory to finally complete the channel by this LLIn+1 (clear the
GPDMA_CxLLR of this LLIn+1), before that this LLIn+1 is loaded/used by the GPDMA
channel
• abort and reconfigure the channel with a LSM update (see Section 19.4.4.)
In link step mode, the software can clear LSM after each a single execution of any LLI,
during LLIn-1.
Figure 107 shows the overall and unified GPDMA linked-list programming, whatever is the
execution mode.
Note: Figure 107 is not intended to illustrate how often a TCEF can be raised, depending on the
programmed value of TCEM[1:0] in GPDMA_CxTR2. It can be raised at (each) block
completion, at (each) 2D block completion, at (each) LLI completion, or only at the last LLI
data transfer completion. In run-to-completion mode, whatever is the value of TCEM[1:0], at
the channel completion the hardware always set TCEF = 1 and disables the channel. In link
step mode, the channel is disabled after each single execution of a LLI, and depending on
the value of TCEM[1:0] a TCEF is raised or not.
In Figure 107, BNDT ≠ 0 is the typical condition for starting the first data transfer. This
condition becomes (BNDT ≠ 0 and PFREQ = 1) if the peripheral requests a data transfer
with early termination (see Section 19.3.5).

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Figure 107. GPDMA channel execution and linked-list programming

Channel state = Idle

Initialize DMA channel

Reconfigure DMA channel

Enable DMA channel

Channel state = Active

Valid user
setting ? N

Setting USEF = 1
BNDT  0 ? N Disabling DMA channel

Executing once the data

transfer from the register file

No transfer
N
error ?

Y
Setting DTEF = 1
N LLR 0 ? Disabling DMA channel

Loading next LLI

into the register file

No transfer
N
error ?

Y Setting ULEF = 1
Disabling DMA channel

Valid user
N
setting ?
Y Setting USEF = 1
Disabling DMA channel
N LSM = 1 ?
Y
Setting TCF = 1
Disabling DMA channel

End

MSv62638V1

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19.4.10 GPDMA FIFO-based transfers

There is a single transfer operation mode: the FIFO mode. There are FIFO-based transfers.
Any channel x is implemented with a dedicated FIFO whose size is defined by
dma_fifo_size[x] (see Section 19.3.1 for more details).

GPDMA burst
A programmed transfer at the lowest level is a GPDMA burst.
A GPDMA burst is a burst of data received from the source, or a burst of data sent to the
destination. A source (and destination) burst is programmed with a burst length by the field
SBL_1[5:0] (respectively DBL_1[5:0]), and with a data width defined by the field
SDW_LOG2[1:0] (respectively DDW_LOG2[1:0]) in the GPDMA_CxTR1 register.
The addressing mode after each data (named beat) of a GPDMA burst is defined by SINC
and DINC in GPDMA_CxTR1, for source and destination respectively: either a fixed
addressing or an incremented addressing with contiguous data.
The start and next addresses of a GPDMA source/destination burst (defined by
GPDMA_CxSAR and GPDMA_CxDAR) must be aligned with the respective data width.
The table below lists the main characteristics of a GPDMA burst.

Table 104. Programmed GPDMA source/destination burst

Data Burst Next data/ Burst
SDW_LOG2[1:0] SBL_1[5:0] Next burst
width SINC/DINC length beat address
DDW_LOG2[1:0] DBL_1[5:0] address
(bytes) (data/beats) address alignment

00 1 1
01 2 0 (fixed) +0 +0 2
10 4 4
n = 0 to 63(1) n+1
00 1 +1 + (n + 1) 1
1
01 2 (contiguously +2 + 2 * (n + 1) 2
incremented)
10 4 +4 + 4 * (n + 1) 4
11 forbidden user setting, causing USEF generation and none burst to be issued.
1. When S/DBL_1[5:0] = 0, burst is of length 1. Then burst can be also named as single.

The next burst address in the above table is the next source/destination default address
pointed by GPDMA_CxSAR or GPDMA_CxDAR, once the programmed source/destination
burst is completed. This default value refers to the fixed/contiguously incremented address.

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GPDMA burst with 2D addressing (channel x = 12 to 15)

When the channel has additional 2D addressing feature, this default value refers to the
value without taking into account the two programmed incremented or decremented offsets.
These two additional offsets (with a null default value) are applied:
• after each completed source/destination burst, as defined respectively by
GPDMA_CxTR2.SAO[12:0]/DAO[12:0] and GPDMA_CxBR1.SDEC/DDEC
• after each completed block, as defined respectively by
GPDMA_CxBR2.BRSAO[15:0]/BRDAO[15:0] and
GPDMA_CxBR1.BRSDEC/BRDDEC)
Then, a 2D/repeated block can be addressed with a first programmed address jump after
each completed burst, and with a second programmed address jump after each block, as
depicted by Figure 108 with a 2D destination buffer.

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Figure 108. Programmed 2D addressing

Memory

32b
Cx_DAR Data0
Data1
... Burst0
DataI-1
+ DAO
Data0
Data1
... Burst1
DataI-1
+ DAO Block0

+ DAO
Data0
Data1
... BurstJ-1
DataI-1
Memory-mapped + DAO
Peripheral

+ BRDAO
32b
Cx_SAR Data Register Burst0
...

(fixed addressing, + DAO

SINC=0)
... Burst1
Restore Cx_DAR 2D/repeated block
+ DAO Blockk
LLIL

+ DAO

... BurstJ-1

+ DAO

+ BRDAO

Data0
Data1
... Burst0
DataI-1
+ DAO
Data0
Data1
... Burst1
DataI-1
+ DAO BlockK-1

+ DAO
Data0
Data1
... BurstJ-1
Programmable address jumps 1) after burst and 2) after DataI-1
+ DAO
block.
Example:
burst: I * words (DBL_1=I-1; DDW_LOG2=’b10) + BRDAO
block: J * bursts (BNDT=J*I*4)
LLI: K * blocks (BRC=K-1)

MSv63674V1

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GPDMA FIFO-based burst

In FIFO-mode, a transfer generally consists of two pipelined and separated burst transfers:
• one burst from the source to the FIFO over the allocated source master port, as defined
by GPDMA_CxTR1.SAP
• one burst from the FIFO to the destination over the allocated destination master port,
as defined by GPDMA_CxTR1.DAP

GPDMA source burst

The requested source burst transfer to the FIFO can be scheduled as early as possible over
the allocated port, depending on the current FIFO level versus the programmed burst size
(when the FIFO is ready to get one new burst from the source):
when FIFO level ≤ 2dma_fifo_size[x] - (SBL_1[5:0]+1) * 2SDW_LOG2[1:0]
where:
• FIFO level is the current filling level of the FIFO, in bytes.
• 2dma_fifo_size[x] is the half of the FIFO size of the channel x, in bytes (see Section 19.3.1
for the implementation details and dma_fifo_size[x] value).
• (SBL_1[5:0]+1) * 2SDW_LOG2[1:0] is the size of the programmed source burst transfer,
in bytes.
Based on the channel priority (GPDMA_CxCR.PRIO[1:0]), this ready FIFO-based source
transfer is internally arbitrated versus the other requested and active channels.

GPDMA destination burst

The requested destination burst transfer from the FIFO can be scheduled as early as
possible over the allocated port, depending on the current FIFO level versus the
programmed burst size (when the FIFO is ready to push one new burst to the destination):
when FIFO level ≥ (DBL_1[5:0]+1) * 2DDW_LOG2[1:0]
where:
• FIFO level is the current filling level of the FIFO, in bytes.
• (DBL_1[5:0]+1) * 2DDW_LOG2[1:0] is the size of the programmed destination burst
transfer, in bytes.
Based on the channel priority, this ready FIFO-based destination transfer is internally
arbitrated versus the other requested and active channels.

GPDMA burst vs source block size, 1-Kbyte address boundary and FIFO size
The programmed source/destination GPDMA burst is implemented with an AHB burst as is,
unless one of the following conditions is met:
• When half of the FIFO size of the channel x is lower than the programmed
source/destination burst size, the programmed source/destination GPDMA burst is
implemented with a series of singles or bursts of a lower size, each transfer being of a
size that is lower or equal than half of the FIFO size, without any user constraint.
• if the source block size (GPDMA_CxBR1.BNDT[15:0]) is not a multiple of the source
burst size but is a multiple of the data width of the source burst
(GPDMA_CxTR1.SDW_LOG2[1:0]), the GPDMA modifies and shortens bursts into
singles or bursts of lower length, in order to transfer exactly the source block size,
without any user constraint.

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• if the source/destination burst transfer have crossed the 1-Kbyte address boundary on
a AHB transfer, the GPDMA modifies and shortens the programmed burst into singles
or bursts of lower length, to be compliant with the AHB protocol, without any user
constraint.
• If the source/destination burst length exceeds 16 on a AHB transfer, the GPDMA
modifies and shortens the programmed burst into singles or bursts of lower length, to
be compliant with the AHB protocol, without any user constraint.
In any case, the GPDMA keeps ensuring source/destination data (and address) integrity
without any user constraint. The current FIFO level (software readable in GPDMA_CxSR) is
compared to and updated with the effective transfer size, and the GPDMA re-arbitrates
between each AHB single or burst transfer, possibly modified.
Based on the channel priority, each single or burst of a lower burst size versus the
programmed burst, is internally arbitrated versus the other requested and active channels.
Note: In linked-list mode, the GPDMA read transfers related to the update of the linked-list
parameters from the memory to the internal GPDMA registers, are scheduled over the link
allocated port, as programmed by GPDMA_CxCR.LAP.

GPDMA data handling: byte-based reordering, packing/unpacking,

padding/truncation, sign extension and left/right alignment
The data handling is controlled by GPDMA_CxTR1. The source/destination data width of
the programmed burst is byte, half-word or word, as per the SDW_LOG2[1:0] and
DDW_LOG2[1:0] fields (see Table 105).
The user can configure the data handling between transferred data from the source and
transfer to the destination. More specifically, programmed data handling is orderly
performed with:
1. Byte-based source reordering
– If SBX = 1 and if source data width is a word, the two bytes of the unaligned
half-word at the middle of each source data word are exchanged.
2. Data width conversion by packing, unpacking, padding or truncation, if destination data
width is different than the source data width, depending on PAM[1:0]:
– If destination data width > source data width, the post SBX source data is either
right-aligned and padded with 0 s, or sign extended up to the destination data
width, or is FIFO queued and packed up to the destination data width.
– If destination data width < source data width, the post SBX data is either
right-aligned and left-truncated down to the destination data width, or is FIFO
queued and unpacked and streamed down to the destination data width.
3. Byte-based destination re-ordering:
– If DBX = 1 and if the destination data width is not a byte, the two bytes are
exchanged within the aligned post PAM[1:0] half-words.
– If DHX = 1 and if the destination data width is neither a byte nor a half-word, the
two aligned half-words are exchanged within the aligned post PAM[1:0] words.
Note: Left-alignment with 0s-padding can be achieved by programming both a right-alignment with
a 0s-padding and a destination byte-based re-ordering.

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The table below lists the possible data handling from the source to the destination.

Table 105. Programmed data handling

SDW_ Source DDW_
Source SB Destination DB DH Destination data
LOG2 data LOG2 PAM[1:0](2)
data X data X X stream(1)
[1:0] stream(1) [1:0]

00 Byte xx x B7,B6,B5,B4,B3,B2,B1,B0
0 0B3,0B2,0B1,0B0
00 (RA, 0P)
1 B30,B20,B10,B00
0 x SB3,SB2,SB1,SB0
01 Half-word 01 (RA, SE)
1 B3S,B2S,B1S,B0S
0 B7B6,B5B4,B3B2,B1B0
1x (PACK)
1 B6B7,B4B5,B2B3,B0B1
0 000B1,000B0
0
1 00B10,00B00
B7,B6,B5, 00 (RA, 0P)
00 Byte B4,B3,B2, 0 0B100,0B000
B1,B0 1
1 B1000,B0000
x
0 SSSB1,SSSB0
0
1 SSB1S,SSB0S
10 Word 01 (RA, SE)
0 SB1SS,SB0SS
1
1 B1SSS,B0SSS
0 B7B6B5B4,B3B2B1B0
0
1 B6B7B4B5,B2B3B0B1
1x (PACK)
0 B5B4B7B6,B1B0B3B2
1
1 B4B5B6B7,B0B1B2B3
00 (RA, LT) B6,B4,B2,B0
B7B6,B5B4
Half-
01 ,B3B2, 00 Byte 01 (LA, RT) x x B7,B5,B3,B1
word
B1B0
1x (UNPACK) B7,B6,B5,B4,B3,B2,B1,B0

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Table 105. Programmed data handling (continued)

SDW_ Source DDW_
Source SB Destination DB DH Destination data
LOG2 data LOG2 PAM[1:0](2)
data X data X X stream(1)
[1:0] stream(1) [1:0]

0 B7B6,B5B4,B3B2,B1B0
01 Half-word xx x
1 B6B7,B4B5,B2B3,B0B1
0 00B3B2,00B1B0
0
1 00B2B3,00B0B1
00 (RA, 0P)
0 B3B200,B1B000
1
1 B2B300,B0B100
B7B6,B5B4 0 SSB3B2,SSB1B0
Half-
01 ,B3B2, x 0
word 1 SSB2B3,SSB0B1
B1B0
10 Word 01 (RA, SE)
0 B3B2SS,B1B0SS
1
1 B2B3SS,B0B1SS
0 B7B6B5B4,B3B2B1B0
0
1 B6B7B4B5,B2B3B0B1
1x (PACK)
0 B5B4B7B6,B1B0B3B2
1
1 B4B5B6B7,B0B1B2B3
00 (RA, LT) B12,B8,B4,B0
00 Byte 01 (LA, RT) x B15,B11,B7,B3
10 (UNPACK) B7,B6,B5,B4,B3,B2,B1,B0
0 B5B4,B1B0
B7B6B5B4, 00 (RA, LT)
10 Word 0 1 x B4B5,B0B1
B3B2B1B0
0 B7B6,B3B2
01 Half-word 01 (LA, RT)
1 B6B7,B2B3
0 B7B6,B5B4,B3B2,B1B0
1x (UNPACK)
1 B6B7,B4B5,B2B3,B0B1

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Table 105. Programmed data handling (continued)

SDW_ Source DDW_
Source SB Destination DB DH Destination data
LOG2 data LOG2 PAM[1:0](2)
data X data X X stream(1)
[1:0] stream(1) [1:0]

0 B7B6B5B4,B3B2B1B0
0
1 B6B7B4B5,B2B3B0B1
0 10 Word xx
0 B5B4B7B6,B1B0B3B2
1
1 B4B5B6B7,B0B1B2B3
00 (RA, LT) B12,B8,B4,B0
00 Byte 01 (LA, RT) x B15,B11,B7,B3
1x (UNPACK) B7,B5,B6,B4,B3,B1,B2,B0
0 B6B4,B2B0
B7B6B5B4, 00 (RA, LT)
10 Word 1 x B4B6,B0B2
B3B2B1B0
0 B7B5,B3B1
01 Half-word 01 (LA, RT)
1 1 B5B7,B1B3
0 B7B5,B6B4,B3B1,B2B0
1x (UNPACK)
1 B5B7,B4B6,B1B3,B0B2
0 B7B5B6B4,B3B1B2B0
0
1 B5B7B4B6,B1B3B0B2
10 Word xx
0 B6B4B7B5,B2B0B3B1
1
1 B4B6B5B7,B0B2B1B3
1. Data stream is timely ordered starting from the byte with the lowest index (B0).
2. RA= right aligned, LA = left aligned, RT = right truncated, LT = left truncated, 0P = zero bit padding up to the destination
data width, SE = sign bit extended up to the destination data width.

19.4.11 GPDMA transfer request and arbitration

GPDMA transfer request
As defined by GPDMA_CxTR2, a programmed GPDMA data transfer is requested with one
of the following:
• a software request if the control bit SWREQ = 1: This is used typically by the CPU for a
data transfer from a memory-mapped address to another memory mapped address
(memory-to-memory, GPIO to/from memory)
• an input hardware request coming from a peripheral if SWREQ = 0: The selection of
the GPDMA hardware peripheral request is driven by the REQSEL[7:0] field
(see Section 19.3.3). The selected hardware request can be one of the following:
– an hardware request from a peripheral configured in GPDMA mode (for a transfer
from/to the peripheral data register respectively to/from the memory)
– an hardware request from a peripheral for its control registers update from the
memory
– an hardware request from a peripheral for a read of its status registers transferred
to the memory

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Caution: The user must not assign a same input hardware peripheral GPDMA request via
GPDMA_CxTR.REQSEL[7:0] to two different channels, if at a given time this request is
asserted by the peripheral and each channel is ready to execute this requested data
transfer. There is no user setting error reporting.

GPDMA transfer request for arbitration

A ready FIFO-based GPDMA source single/burst transfer (from the source address to the
FIFO) to be scheduled over the allocated master port (GPDMA_CxTR1.SAP) is arbitrated
based on the channel priority (GPDMA_CxCR.PRIO[1:0]) versus the other simultaneous
requested GPDMA transfers to the same master port.
A ready FIFO-based GPDMA destination single/burst transfer (from the FIFO to the
destination address) to be scheduled over the allocated master port (GPDMA_CxTR1.DAP)
is arbitrated based on the channel priority (GPDMA_CxCR.PRIO[1:0]) versus the other
simultaneous requested GPDMA transfers to the same master port.
An arbitrated GPDMA requested link transfer consists of one 32-bit read from the linked-list
data structure in memory to one of the linked-list registers (GPDMA_CxTR1,
GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR or GPDMA_CxLLR,
plus GPDMA_CxTR3, GPDMA_CxBR2). Each 32-bit read from memory is arbitrated with
the same channel priority as for data transfers, in order to be scheduled over the allocated
master port (GPDMA_CxCR.LAP).
Whatever the requested data transfer is programmed with a software request for a memory-
to- memory transfer (GPDMA_CxTR2.SWREQ = 1), or with a hardware request
(GPDMA_CxTR2.SWREQ = 0) for a memory-to-peripheral transfer or a peripheral-to-
memory transfer and whatever is the hardware request type, re-arbitration occurs after each
granted single/burst transfer.
When an hardware request is programmed from a destination peripheral
(GPDMA_CxTR2.SWREQ = 0 and GPDMA_CxTR2.DREQ = 1), the first memory read of a
(possibly 2D/repeated) block (the first ready FIFO-based source burst request), is gated by
the occurrence of the corresponding and selected hardware request. This first read request
to memory is not taken into account earlier by the arbiter (not as soon as the block transfer
is enabled and executable).

GPDMA arbitration
The GPDMA arbitration is directed from the 4-grade assigned channel priority
(GPDMA_CxCR.PRIO[1:0]). The arbitration policy, as illustrated in Figure 109, is defined
by:
• one high-priority traffic class (queue 3), dedicated to the assigned channels with
priority 3, for time-sensitive channels
This traffic class is granted via a fixed-priority arbitration against any other low-priority
traffic class. Within this class, requested single/burst transfers are round-robin
arbitrated.
• three low-priority traffic classes (queues 0, 1, or 2) for non time-sensitive channels with
priority 0, 1, or 2
Each requested single/burst transfer within this class is round-robin arbitrated, with a
weight that is monotonically driven from the programmed priority:
– Requests with priority 0 are allocated to the queue 0.
– Requests with priority 1 are allocated and replicated to the queue 0 and queue 1.

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– Requests with priority 2 are allocated and replicated to the queue 0, queue 1, and
queue 2.
– Any queue 0, 1, or 2 equally grants any of its active input requests in a round-robin
manner, provided there are simultaneous requests.
– Additionally, there is a second stage for the low-traffic with a round-robin arbiter
that fairly alternates between simultaneous selected requests from queue 0,
queue 1, and queue 2.

Figure 109. GPDMA arbitration policy

Request from any channel x

Queue 0
being assigned with GPDMA_CxCR.PRIO = 0 RRA

Request from any channel x Low FPA

Queue 1
RRA
Granted
being assigned with GPDMA_CxCR.PRIO = 1 RRA request
Request from any channel x Queue 2 High
being assigned with GPDMA_CxCR.PRIO = 2 RRA

Request from any channel x Queue 3

being assigned with GPDMA_CxCR.PRIO = 3 RRA

GPDMA arbitration
RRA = round-robin arbitration, FPA = fixed-priority arbitration MSv63647V1

GPDMA arbitration and bandwidth

With this arbitration policy, the following is guaranteed:
• Equal maximum bandwidth between requests with same priority
• Reserved bandwidth (noted as BQ3) to the time-sensitive requests (with priority 3)
• Residual weighted bandwidth between different low-priority requests (priority 0 versus
priority 1 versus priority 2).
The two following examples highlight that the weighted round-robin arbitration is driven by
the programmed priorities:
• Example 1: basic application with two non time-sensitive GPDMA requests: req0 and
req1. There are the following programming possibilities:
– If they are assigned with same priority, the allocated bandwidth by the arbiter to
req0 (Breq0) is equal to the allocated bandwidth to req1(Breq1).
Breq0 = Breq1 = 1/2 * (1 - BQ3)
– If req0 is assigned to priority 0 and req1 to priority 1, the allocated bandwidth to
req0 (BP0) is 3 times less than the allocated bandwidth to req1 (BP1).
Breq0 = BP0 = 1/2 * 1/2 * (1 - BQ3) = 1/4 * (1 - BQ3)
Breq1 = BP1 = (1/2 + 1) * 1/2 * (1 - BQ3) = 3/4 * (1 - BQ3)
– If req0 is assigned to priority 0 and req1 to priority 2, the allocated bandwidth to
req0 (BP0) is 5 times less than the allocated bandwidth to req1 (BP2).
Breq0 = BP0 = 1/2 * 1/3 * (1 - BQ3) = 1/6 * (1 - BQ3)
Breq1 = BP2 = (1/2 + 1 +1) * 1/3 * (1 - BQ3) = 5/6 * (1 - BQ3)
The above computed bandwidth calculation is based on a theoretical input request,
always active for any GPDMA clock cycle. This computed bandwidth from the arbiter
must be weighted by the frequency of the request given by the application, that cannot
be always active and may be quite much variable from one GPDMA client (example
I2C at 400 kHz) to another one (PWM at 1 kHz) than the above x3 and x5 ratios.

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• Example 2: application where the user distributes a same non-null N number of

GPDMA requests to every non time-sensitive priority 0, 1 and 2. The bandwidth
calculation is then the following:
– The allocated bandwidth to the set of requests of priority 0 (BP0) is
BP0 = 1/3 * 1/3 * (1 - BQ3) = 1/9 * (1 - BQ3)
– The allocated bandwidth to the set of requests of priority 1(BP1) is
BP1 = (1/3 + 1/2) * 1/3 * (1 - BQ3) = 5/18 * (1 - BQ3)
– The allocated bandwidth to the set of requests of priority 2(BP2) is
BP2 = (1/3 + 1/2 + 1) * 1/3 * (1 - BQ3) = 11/18 * (1 - BQ3)
– The allocated bandwidth to any request n (Bn) among the N requests of that
priority Pi (i = 0 to 2) is Bn = 1/N * BPi
– The allocated bandwidth to any request n of priority 0i (Bn, Pi) is
Bn, P0 = 1/N *1/9 * (1 - BQ3)
Bn, P1 = 1/N *5/18 * (1 - BQ3)
Bn, P2 = 1/N *11/18 * (1 - BQ3)
In this example, when the master port bus bandwidth is not totally consumed by the
time-sensitive queue 3, the residual bandwidth is such that 2.5 times less bandwidth is
allocated to any request of priority 0 versus priority 1, and 5.5 times less bandwidth is
allocated to any request of priority 0 versus priority 2.
More generally, assume that the following requests are present:
• I requests (I ≥ 0) assigned to priority 0
If I > 0, these requests are noted from i = 0 to I-1.
• J requests (J ≥ 0) assigned to priority 1
If J > 0, these requests are noted from j = 0 to J-1.
• K requests (K > 0) assigned to priority 2
These requests are noted from k = 0 to K-1
• L requests (L ≥ 0) assigned to priority 3
If L > 0, these requests are noted from l = 0 to L-1.
As BQ3 is the reserved bandwidth to time-sensitive requests, the bandwidth for each
request L with priority 3 is:
• Bl = BQ3 / L for L > 0 (else: Bl = 0)
The bandwidth for each non-time sensitive queue is:
• BQ0 = 1/3 * (1 - BQ3)
• BQ1 = 1/3 * (1 - BQ3)
• BQ2 = 1/3 * (1 - BQ3)
The bandwidth for the set of requests with priority 0 is:
• BP0 = I / (I + J + K) * BQ0
The bandwidth for each request i with priority 0 is:
• Bi = BP0 / I for L > 0 (else BP0 = 0)
The bandwidth for the set of requests with priority 1 and routed to queue 0 is:
• BP1,Q0 = J / (I + J + K) * BQ0

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The bandwidth for the set of requests with priority 1 and routed to queue 1 is:
• BP1,Q1 = J / (J + K) * BQ1
The total bandwidth for the set of requests with priority 1 is:
• BP1 = BP1,Q0 + BP1,Q1
The bandwidth for each request j with priority 1 is:
• Bj = BP1 / J for J > 0 (else Bj = 0)
The bandwidth for the set of requests with priority 2 and routed to queue 0 is:
• BP2,Q0 = K / (I + J + K) * BQ0
The bandwidth for the set of requests with priority 2 and routed to queue 1 is:
• BP2,Q1 = K / (J + K) * BQ1
The bandwidth for the set of requests with priority 2 and routed to queue 2 is:
• BP2,Q2 = BQ2
The total bandwidth for the set of requests with priority 2 is:
• BP2 = BP2,Q0 + BP2,Q1+ BP2,Q2
The bandwidth for each request k with priority 2 is:
• Bk = BP2 / K (K>0 in the general case)
Thus finally the maximum allocated residual bandwidths for any i, j, k non-time sensitive
request are:
• in the general case (when there is at least one request k with a priority 2 (K > 0)):
– Bi = 1/I * 1/3 * I/(I + J + K) * (1 - BQ3)
– Bj = 1/J * 1/3 *[J/(I + J + K) + J/(J + K)] * (1 - BQ3)
– Bk = 1/K * 1/3 *[K/(I + J + K) + K/(J + K) + 1] * (1 - BQ3)
• in the specific case (when there is no request k with a priority 2 (K = 0)):
– Bi = 1/I * 1/2 * I/(I + J) * (1 - BQ3)
– Bj = 1/J * 1/2 *[J/(I + J) + 1] * (1 - BQ3)
Consequently, the GPDMA arbiter can be used as a programmable weighted bandwidth
limiter, for each queue and more generally for each request/channel. The different weights
are monotonically resulting from the programmed channel priorities.

19.4.12 GPDMA triggered transfer

A programmed GPDMA transfer can be triggered by a rising/falling edge of a selected input
trigger event, as defined by GPDMA_CxTR2.TRIGPOL[1:0] and
GPDMA_CxTR2.TRIGSEL[6:0] (see Section 19.3.6 for the trigger selection).
The triggered transfer, as defined by the trigger mode in GPDMA_CxTR2.TRIGM[1:0], can
be at LLI data transfer level, to condition the first burst read of a block, the first burst read of
a 2D/repeated block for channel x (x = 12 to 15), or each programmed single read. The
trigger mode can also be programmed to condition the LLI link transfer (see TRIGM[1:0] in
GPDMA_CxTR2 for more details).

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Trigger hit memorization and trigger overrun flag generation

The GPDMA monitoring of a trigger for a channel x is started when the channel is
enabled/loaded with a new active trigger configuration: rising or falling edge on a selected
trigger (respectively TRIGPOL[1:0] = 01 or TRIGPOL[1:0] = 10).
The monitoring of this trigger is kept active during the triggered and uncompleted (data or
link) transfer. If a new trigger is detected, this hit is internally memorized to grant the next
transfer, as long as the defined rising/falling edge and TRIGSEL[6:0] are not modified, and
the channel is enabled.
Transferring a next LLIn+1, that updates the GPDMA_CxTR2 with a new value for any of
TRIGSEL[6:0] or TRIGPOL[1:0], resets the monitoring, trashing the possible memorized hit
of the formerly defined LLIn trigger.
Caution: After a first new trigger hitn+1 is memorized, if another trigger hitn+2 is detected and if the hitn
triggered transfer is still not completed, hitn+2 is lost and not memorized. A trigger overrun
flag is reported (GPDMA_CxSR.TOF = 1) and an interrupt is generated if enabled
(if GPDMA_CxCR.TOIE = 1). The channel is not automatically disabled by hardware due to
a trigger overrun.
Figure 110 illustrates the trigger hit, memorization and overrun in the configuration example
with a block-level trigger mode and a rising edge trigger polarity.

Figure 110. Trigger hit, memorization, and overrun waveform

Channel state IDLE ACTIVE

Trigger

Peripheral
request

DMA transfer block transfer block transfer block transfer

Trigger monitoring
Idle Active (monitoring) Active Active Active Active Active Active
state

Trigger monitoring Hit and Hit and Fire Hit and Hit and Fire
action fire memorize memorize trash

Trigger overrun

Hit and trash Hit and fire (or fire alone) Hit and memorize
MSv66923V1

Note: The user can assign the same input trigger event to different channels. This can be used to
trigger different channels on a broadcast trigger event.

19.4.13 GPDMA circular buffering with linked-list programming

GPDMA circular buffering for memory-to-peripheral and
peripheral-to-memory transfers, with a linear addressing channel
For a circular buffering, with a continuous memory-to-peripheral (or peripheral-to-memory)
transfer, the software must set up a channel with half transfer and complete transfer

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events/interrupts generation (GPDMA_CxCR.HTIE = 1 and GPDMA_CxCR.TCIE = 1), in

order to enable a concurrent buffer software processing.
LLI0 is configured for the first block transfer with the linear addressing channel. A
continuously-executed LLI1 is needed to restore the memory source (or destination) start
address, for the memory-to-peripheral transfer (respectively the peripheral-to-memory
transfer). GPDMA automatically reloads the initially programmed
GPDMA_CxBR1.BNDT[15:0] when a block transfer is completed, and there is no need to
restore GPDMA_CxBR1.
Figure 111 illustrates this programming with a linear addressing GPDMA channel and a
source circular buffer.

Figure 111. GPDMA circular buffer programming: update of the memory start address
with a linear addressing channel

Req=PERIPH_TX Req=PERIPH_TX

Reset
Restore
Init/LLI0
SAR/LLI1

Channel x
Ht+ tcf Ht+ tcf

Linked-list register file

LLI0
DMA_CxTR1 Memory
CxLBA (LA = 0)
DMA_CxTR2 USA = 1
LLI1
DMA_CxBR1 others Uxx = 0
DMA_CxSAR
DMA_CxSAR
DMA_CxDAR
DMA_CxLLR
MSv62640V1

Note: With a 2D addressing channel, the user may use a single LLI with
GPDMA_CxBR1.BRC[10:0] = 1, and program a negative memory block address offset with
GDMA_CxBR2 and GDMA_CxBR1, in order to jump back to the memory source or the
destination start address.
If circular buffering must be executed after some other transfers over the shared GPDMA
channel x, the before-last LLIN-1 in memory is needed to configure the first block transfer.
And the last LLIN restores the memory source (or destination) start address in
memory-to-peripheral transfer (respectively in peripheral-to-memory transfer).
Figure 112 illustrates this programming with a linear addressing shared GPDMA channel,
and a source circular buffer.

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Figure 112. Shared GPDMA channel with circular buffering: update of the memory
start address with a linear addressing channel
Req=PERIPH_TX Req=PERIPH_TX

Reset
Init/LLI0 LLI1 ... LLIN-1 LLIN

Channel X Ht+ tcf Ht+ tcf

Memory
LLIN-2 LLIN-1
All Uxx=1
DMA_Cx... DMA_CxTR1

DMA_Cx... DMA_CxTR2
DMA_Cx... DMA_CxBR1

DMA_CxLLR LLIN DMA_CxSAR

DMA_CxDAR
DMA_CxLLR

USA = 1, others Uxx = 0 LA+ = 0xC MSv62641V1

19.4.14 GPDMA transfer in peripheral flow-control mode

A peripheral with the peripheral flow-control mode feature can decide to early terminate a
GPDMA block transfer, provided that the allocated channel is implemented with this feature
(see Section 19.3.5).
If the related GPDMA channel x is also programmed in peripheral flow-control mode
(GPDMA_CxTR2.PFREQ = 1):
• The GPDMA block transfer starts as follows:
– If GPDMA_CxBR1.BNDT[15:0] ≠ 0, the programmed value is internally taken into
account by the GPDMA hardware.
– If GPDMA_CxBR1.BNDT[15:0] = 0, the GPDMA hardware internally considers a
64-Kbyte value for the maximum source block size to be transferred.
• The GPDMA block transfer is completed as soon as the first occurrence of one of the
following condition occurs:
– when GPDMA_CxBR1.BNDT[15:0] = 0
– when the peripheral early terminates the block. The complete transfer event is
generated if programmed, depending on GPDMA_CxTR2 (see GPDMA channel x
transfer register 2 (GPDMA_CxTR2)). Then the software can read the current
number of transferred bytes from the source (GPDMA_CxBR1.BNDT[15:0]),
and/or read the current source or destination address of the buffer in memory
(GPDMA_CxSAR[31:0] or GPDMA_CxDAR[31:0]).

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In peripheral flow-control mode:

• a destination peripheral with a hardware requested transfer is not supported:
memory-to-peripheral transfer is not supported.
• Data packing from a source peripheral is not supported.
• 2D/repeated block is not supported.
• GPDMA_CxBR1.BNDT[15:0] must be programmed as a multiple of the source
(peripheral) burst size.

19.4.15 GPDMA secure/nonsecure channel

The GPDMA controller is compliant with the TrustZone hardware architecture at channel
level, partitioning all its resources so that they exist in one of the secure and nonsecure
worlds at any given time.
Any channel x is a secure or a nonsecure hardware resource, as configured
by GPDMA_SECCFGR.SECx.
When a channel x is configured in secure state by a secure and privileged agent, the
following access control rules are applied:
• A nonsecure read access to a register field of this channel is forced to return 0, except
for GPDMA_SECCFGR, GPDMA_PRIVCFGR and GPDMA_RCFGLOCKR that are
readable by a nonsecure agent.
• A nonsecure write access to a register field of this channel has no impact.
When a channel x is configured in secure state, a secure agent can configure separately as
secure or nonsecure the GPDMA data transfer from the source (GPDMA_CxTR1.SSEC)
and the GPDMA data transfer to the destination (GPDMA_CxTR1.DSEC).
When a channel x is configured in secure state and in linked-list mode, the loading of the
next linked-list data structure from the GPDMA memory into its register file, is automatically
performed with secure transfers via the GPDMA_CxCR.LAP allocated master port.
The GPDMA generates a secure bus that reflects GPDMA_SECCFGR, to keep the other
peripherals informed of the secure/nonsecure state of each GPDMA channel x.
The GPDMA also generates a security illegal access pulse signal on an illegal nonsecure
access to a secure GPDMA register. This signal is routed to the TrustZone interrupt
controller.
When the secure software must switch a channel from a secure state to a nonsecure state,
the secure software must abort the channel or wait until the secure channel is completed
before switching. This is needed to dynamically re-allocate a channel to a next nonsecure
transfer as a nonsecure software is not allowed to do so and must have
GPDMA_CxCR.EN = 0 before the nonsecure software can reprogram the GPDMA_CxCR
for a next transfer. The secure software may reset not only the channel x
(GPDMA_CxCR.RESET = 1) but also the full channel x register file to its reset value.

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19.4.16 GPDMA privileged/unprivileged channel

Any channel x is a privileged or unprivileged hardware resource, as configured by a
privileged agent via GPDMA_PRIVCFGR.PRIVx.
When a channel x is configured in a privileged state by a privileged agent, the following
access control rules are applied:
• An unprivileged read access to a register field of this channel is forced to return 0,
except for GPDMA_PRIVCFGR, GPDMA_SECCFGR, and GPDMA_RCFGLOCKR
that are readable by an unprivileged agent.
• An unprivileged write access to a register field of this channel has no impact.
When a channel is configured in a privileged (or unprivileged) state, the source and
destination data transfers are privileged (respectively unprivileged) transfers over the AHB
master port.
When a channel is configured in a privileged (or unprivileged) state and in linked-list mode,
the loading of the next linked-list data structure from the GPDMA memory into its register
file, is automatically performed with privileged (respectively unprivileged) transfers, via the
GPDMA_CxCR.LAP allocated master port.
The GPDMA generates a privileged bus that reflects GPDMA_PRIVCFGR, to keep the
other peripherals informed of the privileged/unprivileged state of each GPDMA channel x.
When the privileged software must switch a channel from a privileged state to
an unprivileged state, the privileged software must abort the channel or wait until that the
privileged channel is completed before switching. This is needed to dynamically re-allocate
a channel to a next unprivileged transfer as an unprivileged software is not allowed to do so,
and must have GPDMA_CxCR.EN = 0 before the unprivileged software can reprogram the
GPDMA_CxCR for a next transfer. The privileged software may reset not only the channel x
(GPDMA_CxCR.RESET = 1) but also the full channel x register file to its reset value.

19.4.17 GPDMA error management

The GPDMA is able to manage and report to the user a transfer error, as follows, depending
on the root cause.

Data transfer error

On a bus access (as a AHB single or a burst) to the source or the destination:
• The source or destination target reports an AHB error.
• The programmed channel transfer is stopped (GPDMA_CxCR.EN cleared by the
GPDMA hardware). The channel status register reports an idle state
(GPDMA_CxSR.IDLEF = 1) and the data error (GPDMA_CxSR.DTEF = 1).
• After a GPDMA data transfer error, the user must perform a debug session, taking care
of the product-defined memory mapping of the source and destination, including the
protection attributes.
• After a GPDMA data transfer error, the user must issue a channel reset (set
GPDMA_CxCR.RESET) to reset the hardware GPDMA channel data path and the
content of the FIFO, before the user enables again the same channel for a next
transfer.

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Link transfer error

On a tentative update of a GPDMA channel register from the programmed LLI in the
memory:
• The linked-list memory reports an AHB error.
• The programmed channel transfer is stopped (GPDMA_CxCR.EN cleared by the
GPDMA hardware), the channel status register reports an idle state
(GPDMA_CxSR.IDLEF = 1) and the link error (GPDMA_CxSR.ULEF = 1).
• After a GPDMA link error, the user must perform a debug session, taking care of the
product-defined memory mapping of the linked-list data structure (GPDMA_CxLBAR
and GPDMA_CxLLR), including the protection attributes.
• After a GPDMA link error, the user must explicitly write the linked-list register file
(GPDMA_CxTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR,
GPDMA_CxDAR and GPDMA_CxLLR, plus GPDMA_CxTR3 and GPDMA_CxBR2),
before the user enables again the same channel for a next transfer.

User setting error

On a tentative execution of a GPDMA transfer with an unauthorized user setting:
• The programmed channel transfer is disabled (GPDMA_CxCR.EN forced and cleared
by the GPDMA hardware) preventing the next unauthorized programmed data transfer
from being executed. The channel status register reports an idle state
(GPDMA_CxSR.IDLEF = 1) and a user setting error (GPDMA_CxSR.USEF = 1).
• After a GPDMA user setting error, the user must perform a debug session, taking care
of the GPDMA channel programming. A user setting error can be caused by one of the
following:
– a programmed null source block size without a programmed update of this value
from the next LLI1 (GPDMA_CxBR1.BNDT[15:0] = 0 and
GPDMA_CxLLR.UB1 = 0)
– a programmed non-null source block size being not a multiple of the programmed
data width of a source burst transfer (GPDMA_CxBR1.BNDT[2:0] versus
GPDMA_CxTR1.SDW_LOG2[1:0])
– when in packing/unpacking mode (if PAM[1] = 1), a programmed non-null source
block size being not a multiple of the programmed data width of a destination burst
transfer (GPDMA_CxBR1.BNDT[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0])
– a programmed unaligned source start address, being not a multiple of the
programmed data width of a source burst transfer (GPDMA_CxSAR[2:0] versus
GPDMA_CxTR1.SDW_LOG2[1:0])
– for channel x (x = 12 to 15): a programmed unaligned source address offset being
not a multiple of the programmed data width of a source burst transfer
(GPDMA_CxTR3.SAO[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0])
– for channel x (x = 12 to 15): a programmed unaligned block repeated source
address offset being not a multiple of the programmed data width of a source burst
transfer (GPDMA_CxBR2.BRSAO[2:0] versus GPDMA_CxTR1.SDW_LOG2[1:0])
– a programmed unaligned destination start address, being not a multiple of the
programmed data width of a destination burst transfer (GPDMA_CxDAR[2:0]
versus GPDMA_CxTR1.DDW_LOG2[1:0])
– for channel x (x = 12 to 15): a programmed unaligned destination address offset
being not a multiple of the programmed data width of a destination burst transfer
(GPDMA_CxTR3.DAO[2:0] versus GPDMA_CxTR1.DDW_LOG2[1:0])

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– for channel x (x = 12 to 15): a programmed unaligned block repeated destination

address offset being not a multiple of the programmed data width of a destination
burst transfer (GPDMA_CxBR2.BRDAO[2:0] versus
GPDMA_CxTR1.DDW_LOG2[1:0])
– a programmed double-word source data width
(GPDMA_CxTR1.SDW_LOG2[1:0] = 11)
– a programmed double-word destination data width
(GPDMA_CxTR1.DDW_LOG2[1:0] = 11)
– a programmed linked-list item LLIn+1 with a null data transfer
(GPDMA_CxLLR.UB1 = 1 and GPDMA_CxBR1. BNDT = 0)

19.5 GPDMA in debug mode

When the microcontroller enters debug mode (core halted), any channel x can be
individually either continued (default) or suspended, depending on the programmable
control bit in the DBGMCU module.
Note: In debug mode, GPDMA_CxSR.SUSPF is not altered by a suspension from the
programmable control bit in the DBGMCU module. In this case, GPDMA_CxSR.IDLEF can
be checked to know the completion status of the channel suspension.

19.6 GPDMA in low-power modes

Table 106. Effect of low-power modes on GPDMA
Mode Description

Sleep No effect. GPDMA interrupts cause the device to exit Sleep mode.
Stop(1) The content of the GPDMA registers is kept when entering Stop mode.
Standby The GPDMA is powered down and must be reinitialized after exiting Standby mode.
1. Refer to Section 19.3.2 to know if any Stop mode is supported.

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19.7 GPDMA interrupts

There is one GPDMA interrupt line for each channel, and separately for each CPU
(if several ones in the devices).

Table 107. GPDMA interrupt requests

Interrupt Interrupt
Interrupt enable Event flag Event clear method
acronym event

Transfer
GPDMA_CxCR.TCIE GPDMA_CxSR.TCF Write 1 to GPDMA_CxFCR.TCF
complete
Half transfer GPDMA_CxCR.HTIE GPDMA_CxSR.HTF Write 1 to GPDMA_CxFCR.HTF
Data transfer
GPDMA_CxCR.DTEIE GPDMA_CxSR.DTEF Write 1 to GPDMA_CxFCR.DTEF
error
GPDMA_CHx

Update link
GPDMA_CxCR.ULEIE GPDMA_CxSR.ULEF Write 1 to GPDMA_CxFCR.ULEF
error
User setting
GPDMA_CxCR.USEIE GPDMA_CxSR.USEF Write 1 to GPDMA_CxFCR.USEF
error
Suspended GPDMA_CxCR.SUSPIE GPDMA_CxSR.SUSPF Write 1 to GPDMA_CxFCR.SUSPF
Trigger
GPDMA_CxCR.TOFIE GPDMA_CxSR.TOF Write 1 to GPDMA_CxFCR.TOF
overrun

A GPDMA channel x event may be:

• a transfer complete
• a half-transfer complete
• a transfer error, due to either:
– a data transfer error
– an update link error
– a user setting error completed suspension
• a trigger overrun
Note: When a channel x transfer complete event occurs, the output signal gpdma_chx_tc is
generated as a high pulse of one clock cycle.
An interrupt is generated following any xx event, provided that both:
• the corresponding interrupt event xx is enabled (GPDMA_CxCR.xxIE = 1)
• the corresponding event flag is cleared (GPDMA_CxSR.xxF = 0). This means that,
after a previous same xx event occurrence, a software agent must have written 1 into
the corresponding xx flag clear control bit (write 1 into GPDMA_CxFCR.xxF).
TCF (transfer complete) and HTF (half transfer) events generation is controlled by
GPDMA_CxTR2.TCEM[1:0] as follows:
• A transfer complete event is a block transfer complete, a 2D/repeated block transfer
complete, or a LLI transfer complete including the upload of the next LLI if any, or the
full linked-list completion, depending on the transfer complete event mode
GPDMA_CxTR2.TCEM[1:0].

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• A half transfer event is an half block transfer or a half 2D/repeated block transfer,
depending on the transfer complete event mode GPDMA_CxTR2.TCEM[1:0].
A half-block transfer occurs when half of the source block size bytes (rounded-up
integer of GPDMA_CxBR1.BNDT[15:0] / 2) is transferred to the destination.
A half 2D/repeated block transfer occurs when half of the repeated blocks (rounded-up
integer of (GPDMA_CxBR1.BRC[10:0] + 1) / 2) is transferred to the destination.
See GPDMA channel x transfer register 2 (GPDMA_CxTR2) for more details.
A transfer error rises in one of the following situations:
• during a single/burst data transfer from the source or to the destination (DTEF)
• during an update of a GPDMA channel register from the programmed LLI in memory
(ULEF)
• during a tentative execution of a GPDMA channel with an unauthorized setting (USEF)
The user must perform a debug session to correct the GPDMA channel programming
versus the USEF root causes list (see Section 19.4.17).
A trigger overrun is described in Trigger hit memorization and trigger overrun flag
generation.

19.8 GPDMA registers

The GPDMA registers must be accessed with an aligned 32-bit word data access.

19.8.1 GPDMA secure configuration register (GPDMA_SECCFGR)

Address offset: 0x00
Reset value: 0x0000 0000
A write access to this register must be secure and privileged. A read access is secure or
nonsecure, privileged or unprivileged.
A write access is ignored at bit level if the corresponding channel x is locked
(GPDMA_RCFGLOCKR.LOCKx = 1).
This register must be written when GPDMA_CxCR.EN = 0.
This register is read-only when GPDMA_CxCR.EN = 1.
This register must be programmed at a bit level, at the initialization/closure of a GPDMA
channel (when GPDMA_CxCR.EN = 0), to securely allocate individually any channel x to
the secure or nonsecure world.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15 SEC14 SEC13 SEC12 SEC11 SEC10 SEC9 SEC8 SEC7 SEC6 SEC5 SEC4 SEC3 SEC2 SEC1 SEC0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

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Bits 15:0 SECx: secure state of channel x (x = 15 to 0)

0: Nonsecure
1: Secure

19.8.2 GPDMA privileged configuration register (GPDMA_PRIVCFGR)

Address offset: 0x04
Reset value: 0x0000 0000
A write access to this register must be privileged. A read access can be privileged or
unprivileged, secure or nonsecure.
This register can mix secure and nonsecure information. If a channel x is configured as
secure (GPDMA_SECCFGR.SECx = 1), the PRIVx bit can be written only by a secure (and
privileged) agent.
A write access is ignored at bit level if the corresponding channel x is locked
(GPDMA_RCFGLOCKR.LOCKx = 1).
This register must be written when GPDMA_CxCR.EN = 0.
This register is read-only when GPDMA_CxCR.EN =1.
This register must be programmed at a bit level, at the initialization/closure of a GPDMA
channel (GPDMA_CxCR.EN = 0), to individually allocate any channel x to the privileged or
unprivileged world.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIV15 PRIV14 PRIV13 PRIV12 PRIV11 PRIV10 PRIV9 PRIV8 PRIV7 PRIV6 PRIV5 PRIV4 PRIV3 PRIV2 PRIV1 PRIV0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PRIVx: privileged state of channel x (x = 15 to 0)
0: unprivileged
1: privileged

19.8.3 GPDMA configuration lock register (GPDMA_RCFGLOCKR)

Address offset: 0x08
Reset value: 0x0000 0000
This register can be written by a software agent with secure privileged attributes in order to
individually lock, for example at boot time, the secure privileged attributes of any GPDMA

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channel/resource (to lock the setting of GPDMA_CxSECCFGR and GPDMA_CxPRIVCFGR

for any channel x, for example at boot time).
A read access may be privileged or unprivileged, secure or nonsecure.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK1 LOCK1 LOCK1 LOCK1 LOCK1 LOCK1
LOCK9 LOCK8 LOCK7 LOCK6 LOCK5 LOCK4 LOCK3 LOCK2 LOCK1 LOCK0
5 4 3 2 1 0
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 LOCKx: lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx,
until a global GPDMA reset (x = 15 to 0)
This bit is cleared after reset and, once set, it cannot be reset until a global GPDMA reset.
0: secure privilege configuration of the channel x is writable.
1: secure privilege configuration of the channel x is not writable.

19.8.4 GPDMA nonsecure masked interrupt status register

(GPDMA_MISR)
Address offset: 0x0C
Reset value: 0x0000 0000
This register is a read register.
This is a nonsecure register, containing the masked interrupt status bit MISx for each
nonsecure channel x (channel x configured with GPDMA_SECCFGR.SECx = 0). It is a
logical OR of all the flags of GPDMA_CxSR, each source flag being enabled by the
corresponding interrupt enable bit of GPDMA_CxCR.
Every bit is deasserted by hardware when writing 1 to the corresponding flag clear bit in
GPDMA_CxFCR.
If a channel x is in secure state (GPDMA_SECCFGR.SECx = 1), a read access to the
masked interrupt status bit MISx of this channel x returns zero.
This register may mix privileged and unprivileged information, depending on the privileged
state of each channel GPDMA_PRIVCFGR.PRIVx. A privileged software can read the full
nonsecure interrupt status. An unprivileged software is restricted to read the status of
unprivileged (and nonsecure) channels, other privileged bit fields returning zero.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIS15 MIS14 MIS13 MIS12 MIS11 MIS10 MIS9 MIS8 MIS7 MIS6 MIS5 MIS4 MIS3 MIS2 MIS1 MIS0
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

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Bits 15:0 MISx: masked interrupt status of channel x (x = 15 to 0)

0: no interrupt occurred on channel x
1: an interrupt occurred on channel x

19.8.5 GPDMA secure masked interrupt status register (GPDMA