Results in Engineering 25 (2025) 104050

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Single-switch ultra-high step-Up DC-DC converter for PV applications

T. Sakthiram a , L Yogesh a , Rahul Srikanth a , M. Prabhakar b, S. Angalaeswari a,*
a
School of Electrical Engineering (SELECT), Vellore Institute of Technology, Chennai, India
b
Centre for Smart Grid Technologies, School of Electrical Engineering (SELECT), Vellore Institute of Technology, Chennai, India

A R T I C L E I N F O A B S T R A C T

Keywords: In this research article, a high-gain DC-DC converter that is suitable for photovoltaic (PV) applications and
DC-DC converters possesses ultra-high step-up voltage gain capability is presented. Despite using a single switch, the proposed
Microgrids converter yields a voltage gain value that is more than double the cubic times the output voltage obtained from a
Power conversion
classical boost converter (CBC). In the proposed converter, two gain extension techniques viz., switched inductor
Power electronics
Voltage gain
(SI) networks and enhanced quadratic boost converter (EQBC) structure with classical voltage multiplier cells
(VMC) are synergized to obtain a nominal voltage gain of 20. The proposed synthesis methodology is practically
validated by conducting experiments on a 20 V to 400 V, 100 W prototype converter. The single switch prototype
converter operates at a full-load efficiency of 94.3 % when switched at 50 kHz frequency and 0.475 duty ratio.
Under dynamic conditions, when the input voltage is reduced to 16 V, the voltage gain of the proposed converter
is extended safely to 25 to meet the 400 V load requirement. The salient features of the proposed converter are
clearly proven by comparing it with several converters with quadratic, cubic, and quartic voltage gain functions.

1. Introduction voltage spikes across the switching elements.

In [9], the voltage lift technique is adopted along with a comple­
In recent years, renewable energy sources (RES) viz., solar, wind, and mentary switching strategy to achieve high voltage gain values. How­
fuel cells provide the much-needed impetus for achieving sustainable ever, in [9], to achieve a voltage gain >10, the duty ratio value needs to
development. These RES also support the charging infrastructure for be >0.62, and the switch is subjected to excessive voltage stress. In
electric vehicles [1]. Among the above-mentioned RES, converting solar single-switch-based boost-derived converters, adopting switched ca­
energy into electrical energy using photovoltaic (PV) panels has gained pacitors (SCs) and switched inductors (SIs) enhance the overall voltage
significant attention. However, the PV panels typically yield electrical gain [10–12]. When SIs and SCs are adopted, the input current stress and
power at lower DC voltage levels while the electrical loads operate at switch voltage stress magnitudes are reduced respectively [10–12].
higher voltage levels. The gap in the voltage level requirements is effi­ Nevertheless, the practical voltage gain of the CBC and its derivatives is
ciently met using appropriate power electronic converters. Often, limited to moderate values due to the restriction of duty ratio values and
high-gain DC-DC converters along with suitable other types of power higher input current ripple.
converter interfaces are employed to integrate and utilize the power Interleaving multiple phases of a CBC and operating the individual
generated from the PV sources for modern applications [2–4]. switches with appropriately phase-shifted duty ratios results in the
For high voltage gain (>10) applications, due to the inherent source current being smooth and ripple-free. Nevertheless, the voltage
drawbacks of the classical boost converter (CBC) [5], several voltage gain of such interleaved boost converters (IBC) is like that of a CBC and
gain extension techniques like voltage multiplier cells (VMCs) [6] and needs to be stepped up for practical application. In [13], CIs with the
coupled inductors (CIs) [7–8] are embedded within the CBC structure. In desired turns in the windings are implemented in the IBC structure to
VMC-based converters, as the voltage gain directly depends on the meet the load requirement. The converter presented in [14] employs
number of cells employed, enhancing the voltage conversion ratio is diode capacitor multiplier (DCM) cells to obtain higher voltage gain.
practically limited due to the additional losses across the components. Generally, the power handling capability of CI-based converters is more
Despite providing higher voltage gain values, CIs tend to make the than the counterparts with discrete inductors. When CI-based converters
magnetic design more complex. Moreover, leakage inductance causes are employed along with gain extension mechanisms, the high voltage

* Corresponding author.
E-mail address: angalaeswari.s@[Link] (S. Angalaeswari).

[Link]
Received 12 November 2024; Received in revised form 20 December 2024; Accepted 14 January 2025
Available online 15 January 2025
2590-1230/© 2025 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license ([Link]
nc-nd/4.0/).
T. Sakthiram et al. Results in Engineering 25 (2025) 104050

gain requirement is comfortably met. However, the factors such as size, elaborated in Section 5. The main advantages of the proposed converter
weight, and leakage inductance must be carefully tacked by the user. are highlighted by comparing it with some similar existing power con­
By adopting switched inductors (SIs) at the converter’s source side, verters in Section 6. The concluding remarks are presented in Section 7.
the voltage gain value is enhanced without employing additional com­
ponents [15–17]. Unfortunately, due to the charging and discharging 2. Description of the power circuit
paths, SI-based converters invariably draw pulsating input currents. The
converter elaborated in [18] employs an active-quad-SI structure to Fig. 1(a) portrays the schematic block diagram of a DC microgrid.
achieve continuous input current. However, its voltage gain is limited The power circuit of the proposed SSUHSDC is depicted in Fig. 1(b). The
and uses many components. An iterated version of the SI network yields proposed converter is synthesized from the classical boost converter by
the inductor-capacitor-inductor (LCL) structure-based converter judiciously incorporating LCL-based SI and EQBC as the gain extension
detailed in [19]. The converter employs the LCL structure along with SCs mechanisms. The LCL network comprises of two discrete inductors L1,
to increase the overall gain throughput along with reduced input current L2, two diodes DL1, DL2 and a capacitor CB.
stress. The converter in [20] employs a dual active SI network with SCs The VMC embedded within the QBC network comprises of D3, D6, C2
to enhance the voltage gain and power handling capability at reduced and C3. While serving as a diode in classical rectifier diode allowing L3
input current levels. transfer its energy to C3 It also performs the dual role of diode in VMC
To achieve higher voltage conversion ratios at low and safe duty allowing C3 to charge C2. The energy storage capacitor C1 acts as a stiff
ratios, converters that possess high-order voltage gain profiles like the DC source by storing the energy obtained from the LCL stage and
quadratic boost converter (QBC) are needed [21–22]. Although the transfers the same to the next stage. The discrete inductors L3 and L4 act
single-switch QBC variants possess better voltage scaling, their as the classical energy storage inductors in boost-derived topologies and
maximum voltage gain is still limited. By incorporating SC and SI cells aid in enhancing the voltage gain obtained from their respective previ­
within the QBC structure, their voltage gain is further increased while ous stages. Switch S1 acts like the power switch in the CBC while D5 acts
reducing the voltage stress on the switches [23–24]. When CIs are also as the boost rectifier diode and C3 is the output capacitor. The operation
employed in QBC-based converters, impressive voltage gain is easily of the proposed SSUHSDC is elaborated in the succeeding section.
achieved [25–29]. Nevertheless, the input current ripple in QBC and its
variants discussed so far is higher and mainly depends on the inductor 3. Operating principle
design.
By interleaving two or more QBC structures, the input current ripple The working principle is elucidated using two modes in one
is easily reduced. In [30], an interleaved QBC (IQBC) structure is syn­ switching cycle with the following assumptions.
thesized from two QBC structures. The voltage output of the two phase (i) All the semiconductor devices are ideal.
IQBC is coupled through a voltage-lift capacitor to achieve an impressive (ii) All the capacitors are pre-charged.
voltage gain of 16.66. However, due to the location of the switches, they (iii) The converter operates in continuous conduction mode (CCM).
experience higher voltage stress levels. Gain extension mechanisms such
as CIs and DCMs are incorporated to extend the voltage gain of the IQBC
and reduce the switch voltage stress [31–32]. Due to interleaving, the 3.1. Mode 1 (t0-t1)
source current is also continuous and ripple-free. The converter pre­
sented in [33] is an interesting variant of the basic QBC. The converter Mode 1 commences when the power switch S1 is turned ON. Current
structure is subtly varied by incorporating the SC structure. The modi­ through the inductors L2 and L2 raise linearly through DL1, DL2, D2, and
fied QBC operates with reduced current stress on inductors. Generally, S1. The capacitor CB also charges through the current path formed by L1,
QBC-derived structures with extended gain extension techniques are L2, D2, and S1. Thus, the energy storage elements in the LCL network (L1,
employed judiciously to achieve ultra-high voltage gain values [34–41]. L2 and CB) charge in a parallel manner. Further, the energy stored in C1 is
Nevertheless, the location of the switches, input current ripple, and transferred to L3 through the diode D4 and the switch S1 as in the case of
range of voltage gain achievable from the structures determine the a CBC. Consequently, Since the cathode of D1 is connected to a higher
application of QBC-based structures. voltage level it is reversed-biased. Meanwhile, in the VMC network, the
Converters that provide higher voltage conversion ratios than QBCs energy stored in C2 forward-biases D6 and transfers its stored energy to
are presented in [42–43]. By cascading the QBC and IBC structures, L4 and C2. Hence, the VMC diode D3 remains OFF. Since S1 conducts, D5
cubic boost converters (CUBC) are synthesized. These converters oper­ is reverse-biased and the load demand is met by C4. This mode ends
ate with reduced input current ripple and deliver the output at when the current through the energy storage inductors reaches their
high-efficiency values even at high voltage conversion ratios. However, respective maximum values and the switch S1 is turned OFF at time t =
their component count is high. In [44], the converter employs t1. Fig. 2(a) illustrates the state of the components employed in the
inductor-capacitor-2-diodes network (LC2 N) to achieve a voltage gain proposed SSUHSDC during mode 1. The governing equations are given
profile which is cubic times that of the CBC. However, the voltage stress by (1) to (6). All capacitors except CB and C2 discharge in mode 1 and
on the single switch is the same as that of the output voltage. The con­ transfer their stored energy to the inductors located in the next stage.
verter in [45] proposes a single-switch-based bi-quadratic (quartic) VL1 Vin
boost converter with switched inductor-capacitor network (SLCN) to iL1 = IL1 ,min + t = IL1 ,min + t (1)
L1 L1
achieve an even higher voltage gain; it is CBC’s voltage gain raised to the
power 4. However, the switch experiences a higher voltage stress due to VL2 Vin
iL2 = IL2 ,min + t = IL2 ,min + t (2)
its proximity to the output in addition to large input current ripples. L2 L2
In this paper, a single-switch ultra-high step-up DC-DC converter
(SSUHSDC) with cubic voltage gain characteristics is presented. The VL3 vC1
iL3 = IL3 ,min + t = IL3 ,min + t (3)
manuscript is presented as follows: Section 1 lays the foundation for the L3 L1
SSUHSDC’s development by elaborately discussing the technologies and
VL4 vC3
voltage gain capabilities of some existing converters. In Section 2, the iL4 = IL4 ,min + t = IL4 ,min + t (4)
L4 L1
proposed converter is described followed by its operating principle in
Section 3. In Section 4, the converter is analyzed under steady-state icx
conditions to obtain the expressions for voltage gain and key ele­ vCx = VCx ,min − t, x = B, 1, 3, 4 (5)
Cx
ments. The experimental findings obtained from the prototype are

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T. Sakthiram et al. Results in Engineering 25 (2025) 104050

Fig. 1. Diagrams depicting the (a) schematic block diagram of a DC microgrid to highlight the application of the proposed converter and (b) Power circuit of the
proposed SSUHSDC.

i cy Vc1 and the negative plate of boost capacitor CB respectively. Diodes D2

vCy = VCy ,max + , y = B, 2 (6) and D4 are reverse-biased as their anode is clamped at V0. The voltage
Cy
induced across L3 forward biases D3 and transfers its stored energy to C3.
Diode D5 is forward-biased due to the electrical inertia of L4 and charges
3.2. Mode 2 (t1-t2) C4. Further, the energy stored in C2 and L4 meets the load demand. Mode
2 ends with the individual inductor currents reaching their respective
Mode 2 commences at t1 when S1 is turned OFF. The induced volt­ minimum values. At t = t2, the switch S1 is turned ON again to mark the
ages across L1 and L2 forward biases D1. Hence, the energy stored in L1, end of one switching cycle. The governing equations during mode 2 are
L2, and CB is transferred to C1. Thus, the energy storage elements in the given by (7) to (12). Fig. 2(b) portrays the equivalent circuit during
LCL stage discharge are in series. Diode DL1 is reversed-biased as both its Mode 2. Fig. 3 shows the characteristic waveforms.
terminals are connected to the same potential level. Diode DL2 is
reversed-biased due to its cathode and anode terminals being clamped to

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T. Sakthiram et al. Results in Engineering 25 (2025) 104050

Fig. 2. Equivalent circuits during (a) Mode 1 and (b) Mode 2.

VL1 (Vin + vCB − vC1 ) 4.1. Voltage conversion ratio

iL1 = IL1 ,max − t = IL1 ,max + t (7)
L1 2L1
Generally, the voltage gain is obtained by employing the volt-second
VL2 (Vin + vCB − vC1 ) balance principle across the inductors. Alternatively, by viewing the
iL2 = IL2 ,max − t = IL2 ,max + t (8)
L2 2L2 proposed SSUHSDC being comprised of two stages, the voltage gain
( ) expression is derived intuitively. The net voltage gain obtained from the
VL3 vC1 − vC3 proposed converter is contributed by the LCL network-fed boost-derived
iL3 = IL3 ,max − t = IL3 ,max + t (9)
L3 L3 stage followed by the VMC network embedded within the QBC structure.
( ) Since C1 is the output capacitor of the LCL-boost-derived stage, its
VL4 2vC3 − Vo voltage gain is given by (13). The second stage consists of modified QBC
iL4 = IL4 ,max − t = IL4 ,max + t (10)
L4 L3 structure with a VMC network formed by the addition of link capacitor
C2 and diode D6. The capacitors C2 and C3 are in parallel and series
ica
vCa = VCa ,min + t, a = 1, 3, 4 (11) during the ON and OFF periods respectively. Hence, the input to the
Ca intermittent stage in QBC fluctuates. For additional clarity, the volt-
second balance across the inductor L4 is presented in (14) and (15).
ick
vCk = VCk ,max − , k = B, 2 (12)
Ck VC1 2
MStage1 = = (13)
Vin (1 − D)
4. Steady-State Analysis and design equations
DVC2 + D(VC1 − VC2 ) = 0 (14)
In this section, the expression for steady-stage voltage gain and the
switch voltage stress magnitudes are derived along with the design DVC2 + D(2VC2 − Vo ) = 0 (15)
equations for the passive elements. Simplifying, the effective voltage gain obtained from stage 2 is given
by (16).

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T. Sakthiram et al. Results in Engineering 25 (2025) 104050

voltage and current stress values are the same. During mode 2, the anode
of DL1 is connected to Vin, and the cathode is connected to the positive
plate of boost capacitor CB. Hence, its voltage stress is derived and
expressed by (18).

VC1 (1 − D)2 V0
VDL1 = VDL2 = = (18)
2 2(2 − D)
The diodes DL1 and DL2 are turned ON during mode 1. They conduct
the current through L1 and L2 respectively. Hence their current stress is
given by (19).
2Iin
IDL1 = IDL2 = (19)
3
The diodes D1 and D3 are reverse-biased in mode 1. From Fig. 2(a),
based on the voltage impressed them, their voltage stress magnitudes are
obtained and expressed by (20) and (21) respectively.

(1 − D)2 V0
VD1 = (20)
(2 − D)

(1 − D)V0
VD3 = (21)
(2 − D)
The current through D1 is same as the current through the inductor L1
while the current through D3 is given by IL3-IL4. Their current ratings are
derived and presented in (22) and (23) respectively.
2Iin
ID1 = (22)
3

Iin (1 − D)
ID3 = (23)
2(2 − D)
Diode D2 is reversed biased when S1 is turned OFF. Based on the
voltage impressed across its power terminals, its voltage stress is given
by (24).
( )
V0 1 + D − D2
VD2 = (24)
(2 − D)
Since D2 carries the current that flows through L2, its current stress is
given by IL2 and is expressed by (25).
Fig. 3. Characteristic waveforms of the proposed SSUHSDC. 4Iin
ID2 = (25)
3
Vo 2− D The voltage stress magnitude of D4 is given by (26). Its current is
MStage2 = = (16)
VC2 (1 − D)2 same as the current flowing through L3 as presented in (27).
Since stage 1 acts as the input to stage 2, the overall voltage gain (M) V0
VD4 = (26)
of the proposed SSUHSDC is obtained as the product of two individual (2 − D)
stage gain and given by (17).
Iin (1 − D)
V0 2(2 − D) ID4 = (27)
M= = MStage1 × MStage2 = (17) 2
Vin (1 − D)3
Since D5 is directly connected to the output its voltage stress is given
As observed from (17), the overall voltage gain is a cubic function of by V0 and its current stress is given by IL4 . The voltage and current stress
the CBC’s gain. Thus, by using a single switch and judiciously cascading impressed on D6 are the same as D3 and expressed by (21) and (23)
the LCL-modified QBC networks, the voltage conversion ratio of the respectively.
proposed SSUHSDC is significantly enhanced.
4.4. Design of inductors
4.2. Switch Ratings
The design values for the inductors are obtained from basic princi­
The proposed converter employs only one switch S1. The switch is ples and expressed using (28).
located near the output. Hence, its voltage stress is V0. The current stress D Vin
of the switch is sum of all currents through all the inductors. Lx = , x = 1, 2 (28)
fs ΔiLx

4.3. Diode Voltage and current where D is the duty ratio of the switch, ΔiLx is the inductor current ripple,
fs is the switching frequency and Vin is the input voltage. Due to the
The voltage stress of diodes is the reverse voltage impressed across location of L3 and L4, they are at a considerably higher voltage level
their power terminals. Since DL1 and DL2 operate simultaneously, their based on which the design expressions are given by (29) and (30)

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T. Sakthiram et al. Results in Engineering 25 (2025) 104050

respectively. ⎛ ⎞
DVC1 2DVin ⎜ ⎟
L3 = = (29) ⎜ − (1 − D) ⎟
fs ΔiL 3 fs ΔiL3 (1 − D) ⎜ 0 0 0 0 0 0
⎟
⎜
⎜ 2L1 ⎟
⎟
⎜ ⎟
DVC3 2DVin ⎜
⎜ 0 1 − (1 − D) ⎟
L4 = = (30) 0 0 0 0 ⎟
fs ΔiL 4 fs ΔiL4 (1 − D)2
⎜
⎜ L3 L3 ⎟
⎟
⎜ ⎟
⎜
⎜ 0 (2 − D) − (1 − D) ⎟
The capacitance values are based on the voltage ripple impressed 0 0 0 0 ⎟
⎜ L4 L4 ⎟
across them and are designed using (31) and (32). ⎜
⎜
⎟
⎟
⎜ (1 − D) − D ⎟
DICi A=⎜
⎜ C 0 0 0 0 0 ⎟
Ci = , i = 1, 3, 4 (31) ⎜ 1 C1 ⎟
⎟
fs ΔvCi ⎜ ⎟
⎜
⎜ 0 (1 − D) D ⎟
− 0 0 0 0 ⎟
(1 − D)ICk
⎜
⎜ C2 C2 ⎟
⎟
Ck = , k = 2, B (32) ⎜
(1 − D) − D
⎟
fs ΔvCk ⎜
⎜ 0 0 0 0 0
⎟
⎟
⎜
⎜ C3 C3 ⎟
⎟
⎜ ⎟
4.5. State Space analysis
⎜
⎜ 0 (1 − D) − 1 ⎟
0 0 0 0 ⎟
⎜
⎝ C0 R0 C0 ⎟ ⎠
In this section, the focus lies on representing the low-frequency
characteristics and response to small-signal variations using a state- [ ]ʹ
1
space model. The variables of interest are the voltages across capaci­ Bg = 0 0 0 0 0 0
L1
tors and currents through inductors, which serve as the state variables.
Due to the identical behavior of inductors L1 and L2, it becomes possible (37)
to reduce the system’s order from eight to seven. The state space model [ ( ) ]ʹ
VC1 VC3 − VC3 − V0 − IL1 IL3 IL3 IL4 IL3 IL4 IL4
of the system is given by (33–38). Bg = + − + − + −
2L1 L3 L3 L4 C1 C1 C2 C2 C3 C3 C0
ẋ = Ax + Bu (33) (38)

y = Cx + Du (34)

IL3 IL4 VC1 VC2 VC3 V0 ]

ʹ
x = [ IL1 (35)

where x represents a column vector with state variables and u column

vector with input voltage. The state-matrix A is found by using simpli­

V0 8.325e21s
GVg = = (39)
v in s7 + 13.3s6 + 4.02e07s5 + 4.566e08s4 + 3.87e14s3 + 3.034e15s2 + 3.95e20s
̂

V0 − 1.064e04s6 + 2.848e09s5 − 6.634e11s4 + 1.002e17s3 − 1.631e19s2 + 8.25e23s − 4.118e10

GVd = = (40)
d
̂ s7 + 13.3s6 + 4.02e07s5 + 4.566e08s4 + 3.87e14s3 + 3.034e15s2 + 3.95e20s

fied state equations and is expressed using (37). 4.6. Critical inductance
The two transfer functions Gvd and Gvg (output voltage to duty ratio
and output voltage to input voltage) are found by the following ex­ In this section, the boundary between continuous and discontinuous
pressions. Since all the poles of the transfer function lie of the left half of conduction mode (DCM) is discussed along with critical value of in­
the plane the proposed converter is stable. The transfer function of the ductances required to make the proposed converter operate in CCM.
systems with respect to the input voltage when duty ratio is held con­ Since L1 is closer to input and is at a low voltage level its value is lowest
stant (disturbances in duty ratio is zero) is given by at a nominal duty among the other power inductors used in the proposed converter. Since
ratio value of 0.475 using (39). Similarly, the output voltage to duty L2 is identical to L1 in its operation its critical value is same as L1.
ratio when disturbances in input voltage is considered is given by (40).
3DVin 3(1 − D)6 R
− 1 L1 ≥ = (41)
Y = Gvi = C(SI − A) Bi where i = g, d (36) 4fs Iin 4(2(2 − D))2 fs
Since inductor L3 is at a considerably higher voltage level charging at
output voltage of LCL stage, its critical inductance is higher and given by
(42).

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T. Sakthiram et al. Results in Engineering 25 (2025) 104050

D(1 − D)4 R Table II

L3 ≥ (42) Components used to construct and test the prototype SSUHSDC.
2(2 − D)2 fs
Circuit element Device Part number
L4 carries the least current and has the highest inductance value as it
Switch (S1) MOSFET NTHL041N60S5H (600 V, 57 A, 33
is located very close to the output. Although critical value of L4 is
mΩ)
significantly higher, its lower current stress makes its design less com­ Diodes (DL1, DL2, D1) Fast recovery STPS1545D (45 V, 15 A, 0.5 V)
plex. Its design expression is given by (43). diode
Diodes (D2, D4) Fast recovery MUR1540 (400 V,15 A, 1.05 V)
D(1 − D)2 R diode
L4 ≥ (43)
(2 − D)fs Diode (D3) Fast recovery MUR1520 (200 V, 15 A, 0.85 V)
diode
Diode (D5) Fast recovery BYV29X-600 (600 V, 9 A, 1.26 V)
5. Experimental Results and inferences diode
Diode (D6) Fast recovery DSA30C15 0 PB (150 V, 30 A, 0.75 V)
A prototype version of the proposed SSUHSDC with the specifica­ diode
Inductors (L1, L2) Ferrite core PCV2–104–10 L (100 μH, 10 A)
tions mentioned in Table I is fabricated and tested. Table II provides the Inductor (L3) Ferrite core PCV2–564–06 L (564 μH, 6 A)
list of components that are used in the prototype. The gating pulse under Inductor (L4) Ferrite core PCV2–105–02 L (1 mH, 2 A)
open-loop and closed-loop is generated using STM32F411RE nucleo-64 Capacitors (C1, C2, Electrolytic 107CKE20 0 M (100 μF, 200 V)
microcontroller. The gate pulse is amplified using IR25600 MOSFET C3)
Capacitor (C0) Electrolytic EEUED2 W 470 (47 μF, 450 V)
driver and applied across the gate and source terminals. The experi­
Capacitor (CB) Polypropylene JFX02E405J000000B (4 μF, 250 V)
mental waveforms are captured using a mixed domain oscilloscope
(MDO4014C). Figs. 4(a) and 4(b) depict the photograph of the prototype
SSUHSDC and the experimental setup respectively. Fig. 8 portrays the operation of diodes D2, D4, and D5 and their
Fig. 5 depicts the input and output characteristics of the proposed voltage stress levels as compared with V0. The diode pair D2-D4 operate
converter. The converter is fed from a 20 V input (CH1) and the gate simultaneously while D5 complements both their operation. The oper­
pulse (CH2) to S1 are applied with a duty ratio of D = 0.475 at 50 kHz ating principle is practically validated. Additionally, the voltage stress
frequency. The single switch in the converter operates as desired (CH3) levels are in accordance with the theoretical values predicted using (18),
and yields 400 V (CH4). (26), and (27). Since D5 is located very close to the output ports, its
Thus, the nominal voltage gain of 20 at a safe duty ratio of 0.475 and voltage stress is the same as that of V0. The proposed SSUHSDC is syn­
the proposed gain extension concept is practically verified. thesized in such a way that the cathode terminal of D2 is connected to the
The voltage gain obtained at each stage is validated through the drain terminal of S1. Consequently, D2 is subjected to a voltage stress of
waveforms presented in Fig. 6. In the proposed SSUHSDC, C1 acts as the 330V. As discussed earlier, the voltage stress on D4 is equal to 285 V
output capacitor of the first stage consisting of the LCL network. Its based on its connection and proximity to the load.
effective voltage gain is twice that of a CBC. The practical waveform The waveforms presented in Fig. 9 validate the proper operation of
depicted in CH2 of Fig. 6 confirms the theoretically predicted value. The the diodes employed in the VMC i.e., Stage 2 of the proposed SSUHSDC
voltage obtained across C1 serves as the source for the next stage. In when correlated with the operation of S1. The voltage across them is also
stage 2, voltage gain is doubled and stored across C2. The practical value observed and compared with the output voltage. From the waveforms
of 150 V across C2 (CH3) confirms the proper operation of the two gain depicted through CH1 and CH2 of Fig. 9, the complementary operation
extension stages. Capacitor C2 is located within the QBC network. of the VMC diode pair D3-D6 is verified. Further, their voltage stress
Consequently, due to the proper operation of the gain extension stages, levels are the same and equal to 140 V (35 % of V0) which is in accor­
an output voltage of 400 V is obtained across the output port (CH4). dance with the theoretical values obtained using (21). Notably, except
The switching operation of the diodes in the LCL network is verified DL1, the other diodes do not experience voltage ringing mainly due to
through the waveforms in Fig. 7. The waveforms aptly depict the voltage their topological arrangement.
stress across diodes DL1, D1, and D4. The simultaneous operation of DL1 The practical efficiency of the proposed SSUHSDC under full-load
and D4 (CH1, CH3 respectively) and their complementary working with condition is computed from the waveforms presented in Fig. 10. The
respect to D1 (CH2) is practically confirmed. To obtain a fair idea about SSUHSDC delivers 100 W power to the load at 400 V when fed from a 20
the voltage stress on the three diodes, they are compared with the output V input. From the input current waveform (CH2), its value is computed
voltage (CH4). Evidently, as DL1 is located within the LCL structure, its as 5.4A and the operating efficiency works out to 94.3 %. Since the
voltage stress is just 37.5 V which translates to 9.375 % of the output voltage stress on most diodes is lower, the proposed SSUHSDC operates
voltage. As D1 is placed before C1 and gain extension occurs, its voltage with a good efficiency value under full-load condition.
stress is doubled and equal to 75 V (18.75 % of V0). As validated earlier, Fig. 11 shows the practical waveforms to determine the SSUHSDC’s
gain extension occurs in both the stages as expected. Since D4 is directly efficiency at lightly-loaded conditions when it feeds 95 W to the load.
connected to the drain of S1 and near the load, its voltage stress is higher The output voltage is increased to 419 V as depicted in CH3 under open-
and equal to 285V. Further, the voltage ringing observed across the loop operation which is expected from all boost-derived converters. The
diode DL1 is due to the LC oscillations in the LCL gain extension mech­ converter draws 5.2A from the input and the efficiency value is calcu­
anism. However, as the diodes are located closer to the input side, the lated as 91.3 %. The loss across the magnetic elements and capacitors is
ringing effect is within the safe limit. DL2 operates like DL1 and its mainly responsible for the slight reduction in efficiency value.
voltage stress is also expected to be same as that of DL1. The waveforms presented in Fig. 12 are used to obtain the efficiency
value of the SSUHSDC when it supplies 120 W to the load. Under open-
Table I loop conditions, the converter delivers 120 W of power to the load at 380
Prototype of the proposed SSUHSDC and its specification. V only. Due to the incremental load on the converter, it draws 6.55A
Parameter Value from the input. Thus, the efficiency of the proposed converter at a
slightly increased power level of 120 W is calculated to be 91.6 %. Due to
Load power (P0) 100 W
Voltage input (Vin) 20 V
the increment in current under heavy-load conditions, the conduction
Load voltage (V0) 400 V losses increase and result in reduced efficiency.
Duty ratio (D) 0.475 Fig. 13 portrays the efficiency curve under simulated and practical
Switching frequency (fs) 50 kHz conditions. The practical values match closely with the simulated

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T. Sakthiram et al. Results in Engineering 25 (2025) 104050

Fig. 4. Photographs portraying the (a) top-view of the prototype SSUHSDC and (b) experimental setup used to obtain the test results.

Fig. 5. Experimental results to demonstrate the voltage gain capability of the proposed SSUHSDC. CH1-input voltage, CH2-gate pulse to S1, CH3-voltage stress across
S1 and CH4-output voltage.

values; the minor variation in simulation is due to the stray losses across actual output voltage is reduced to a safer level of 3.3 V and fed as an
the passive elements. The power loss dissipated across the various input to the analog-to-digital converter (ADC) peripheral of the micro­
components of the proposed converter are categorized as (i) loss across controller. The ADC output is filtered using an appropriate software-
the switch, (ii) loss across the diodes and (iii) loss across the inductors. based filter. Further, the filtered-ADC output is compared with the
Based on the equations presented in (44)-(46), the individual loss reference voltage and the error signal is then fed to a discrete-time
component under full-load condition is computed and projected in proportional controller. The controller is suitably tuned to provide a
Fig. 14. Most of the loss is due to the diodes as they constitute to 44 % of very quick response with minimal overshoot. Fig. 15(b) depicts the soft-
the total components used in the proposed SSUHSDC. start turn-ON process adopted in the controller.
As the SSUHSDC is intended to be deployed for renewable energy
Psw,loss = I2 sw,RMS × Rsw,ON + Psw,ON + Psw,OFF (44)
applications, soft-start is essential to protect the semiconductor devices
against excessive dv/dt. Initially, the microcontroller is programmed to
Pdiode loss = Vdiode ON × Idiode (45)
operate under open-loop conditions for 18 s and the duty ratio D is
limited to 0.3. During this time interval, the converter reaches its steady-
Pinductor loss = I2 inductor Rinductor + Piron (46)
state operation as observed from the waveforms. Further, despite the
Fig. 15(a) portrays the block-diagram of the closed-loop system that input voltage being set at 20V , the output voltage is capped at 150V due
is employed for achieving soft-start turn-ON process besides regulating to the reduced duty ratio value. The controller automatically switches to
the output voltage of the converter under dynamic conditions. The closed-loop mode at the end of 18 s. Resultantly, the duty ratio is

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T. Sakthiram et al. Results in Engineering 25 (2025) 104050

Fig. 6. Experimental waveform of voltage obtained across C1 (CH2) and C2 (CH3) along with the input (CH1) and output voltages (CH4).

Fig. 7. Practical waveforms of voltage stress across the diodes DL1 (CH1), D1 (CH2), D4 (CH3) compared with V0 (CH4).

adjusted to obtain the desired 400V at the output port as evident from SSUHSDC when the input voltage varies from 16.1 V to 28 .3V. The
the output voltage waveform (CH2) presented in Fig. 15(b). After the output voltage is quickly restored to the desired 400 V with minimal
closed-loop operation sets in, the dynamic performance of the proposed undershoots and overshoots. The proposed SSUHSDC regulates the
SSUHSDC is examined by varying the input voltage in a stepped manner. output voltage over a wide range of load current variations as depicted
The output voltage undergoes minor overshoot and undershoot when in Fig. 17. As observed from the practical waveforms, when the load
the input voltage is increased and decreased respectively. current is varied from 185 mA to 300 mA, the SSUHSDC delivers the
Fig. 16 depicts the output voltage regulation profile of the proposed required load demand at 400V. in power terms, the load varies from 74

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T. Sakthiram et al. Results in Engineering 25 (2025) 104050

Fig. 8. Practical waveforms to validate the operation stress of diodes D2 (CH1), D4 (CH2), D5 (CH3) along with output voltage (CH4).

Fig. 9. Experimental waveforms to demonstrate working of diodes in the VMC. Voltage across D3 (CH1), D6 (CH2), S1 (CH3) and V0 (CH4).

W to 120W. Thus, the converter’s ability to handle varying load con­ features. Table III presents the references and the converters which are
ditions and line voltage variations is practically proven. compared. For understanding and validating the favourable features of
the SSUHSDC, the converters that are chosen for comparison belong to
6. Benchmarking the proposed SSUHSDC either quadratic or cubic variants. The main comparison attributes are
elaborated in the following sub-sections.
In this section, the proposed SSUHSDC is compared with similar
state-of-the-art high gain DC-DC converters to appreciate its superior

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T. Sakthiram et al. Results in Engineering 25 (2025) 104050

Fig. 10. Practical voltage and current waveforms to compute the efficiency under full-load condition. Vin (CH1), Iin (CH2), V0 (CH3) and I0 (CH4).

Fig. 11. Experimental waveforms to compute the efficiency at 95 W Vin (CH1), Iin (CH2), V0 (CH3) and I0 (CH4).

6.1. Voltage Gain (M) and duty ratio (D) converter elaborated in [39]. The converter in [39] is a QBC variant and
it operates at a duty ratio of 0.565. The converters described in [42] and
All the converters that are compared in Table III yield very good [43] provide a voltage conversion ratio of 21.11. Both these converters
voltage conversion ratios. The converter presented in [44] yields the used interleaved arrangement at the input side. To reduce the input
minimum voltage gain value of 17.78 at a duty ratio of D = 0.632. The current ripple, the switches in the interleaved phases are operated at a
second lowest voltage gain value is 20 which is provided by the duty ratio of 0.5 while the other switch is used to meet the voltage gain

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T. Sakthiram et al. Results in Engineering 25 (2025) 104050

Fig. 12. Waveforms to determine the practical efficiency when the SSUHSDC supplies 120 W to the load Vin (CH1), Iin (CH2), V0 (CH3) and I0 (CH4).

Fig. 15(a). Schematic block diagram of the closed-loop control employed.

Fig. 13. Simulated and experimented efficiency curves. requirement. These two converters use 3 switches. By employing 4
switches and operating at the highest duty ratio value of 0.64, the
converter elaborated in [41] provides the highest voltage gain value of
30 among all the converters compared in Table III.
The converter in [41] uses the maximum number of components
also. Comparatively, the proposed converter uses only one switch which
operates at a safe and moderate duty ratio of D = 0.475. The proposed
gain extension technique results in achieving a high voltage gain.
Employing VMC network in conjunction embedded within the QBC
structure results in enhancing the voltage conversion ratio while the LCL
structure at the input side easily doubles the voltage gain at the initial
stage itself. Fig. 18 shows the voltage gain plots of all the converters
which are compared.

6.2. Component Utilization factor – ratio of gain (M) to total components

used (TCU)

Fig. 14. Power loss distribution in various components of the proposed con­ To understand the voltage gain capability from a deeper perspective,
verter at nominal load condition (100 W). the number of components used in all the converters must also be
considered. The ratio of voltage gain (M) to total components used

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T. Sakthiram et al. Results in Engineering 25 (2025) 104050

Fig. 15(b). Waveforms depicting the operating soft-start process and setting up of closed-loop operation.

Fig. 16. Waveforms depicting the line regulation profile of the proposed SSUHSDC.

(TCU) is considered as a comparison attribute for comprehending the M/TCU ratio is 1.2. The converter discussed in [44] uses the least
way components are utilized. Its value is obtained for all the converters number of components; it uses only 12 components. Expectedly, its
that are compared. Since all the converters provide excellent M values, M/TCU ratio is the highest at 1.481. Similarly, the converter in [39] uses
the M/TCU ratio is >1 for all the converters except the converter in [43]. 14 components to achieve a very high voltage gain of 20 and its M/TCU
Understandably, its TCU value is the second highest as it employs 20 value is the second highest at 1.42. The proposed converter is a
components. Despite 25 components which is the highest TCU value, the single-switch version. Moreover, its duty ratio value is also the least.
converter in [41] provides the highest voltage gain of 30. Hence, its Despite the above-mentioned aspects, the M/TCU value of the SSUHSDC

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T. Sakthiram et al. Results in Engineering 25 (2025) 104050

Fig. 17. Waveforms portraying the load regulation profile of the SSUHSDC.

Table III
Comparison of the proposed ssuhsdc and some similar converters.
Attributes Converter presented in Proposed SSUHSDC

[39] [41] [42] [43] [44]

Vin (20–30) V (20–36) V 18V 18V 45V (16–32) V

V0 400V 600V 380V 380V 800V 400V
M 20 30 21.1 21.1 17.78 20
D 0.565 0.64 δ0 = 0.50 δ0 = 0.50 0.632 0.475
δ3 = 0.57 δ3 = 0.62
No. of magnetic 2 6 4 5 3 4
components
No. of switches 2 4 3 3 1 1
No. of diodes 5 10 5 7 5 8
Total components 14 25 16 20 12 18
used (TCU)
M/TCU 1.42 1.2 1.31 0.935 1.481 1.389
Maximum switch 43.5 % 25 % 100 % 100 % 100 % 100 %
voltage stress (%
V 0)
Gain extension QBC with coupled Interleaved quadratic IBC with lift IQBC with a single Active inductor- Switched Inductors
technique inductor and multiplier extended-duty-ratio (IQ- capacitor cascaded boost converter capacitor-two diodes + Modified QBC
cell EDR) to QBC (LC2D) network
Voltage gain function Quadratic Quadratic Cubic Cubic Cubic Cubic

is high and is computed to be 1.389. 6.3. Voltage Stress on the switch

All the converters which are compared belong to the QBC and cubic
variants. Hence, they yield excellent voltage gain values which are The proposed SSUHSDC utilizes a single switch for while the other
sensitive to duty ratio variations. For understanding the impact of duty converters use multiple switches. Generally, in four out of the six con­
ratio, a graph depicting the variation of M/TCU versus D is plotted in verters which are compared, the switches experience a voltage stress
Fig. 19. In the proposed converter, the M/TCU variation remains the which is same as the output voltage. The location of the switch which
highest consistently when D is varied from 0.4 to 0.8. For the converter depends on the gain extension technique adopted is the main reason for
in [39], the M/TCU value is especially higher till D = 0.55 beyond which the voltage stress on the switch. Due to the gain extension mechanisms,
it decreases. Similarly, the converter in [44] possesses the highest the switches of the converters of [39] and [41] experience a very low
M/TCU value of 1.481 when its D value is 0.632. voltage stress.
For the proposed SSUHSDC, the M/TCU value is 3.05. Thus, the Nevertheless, considering the efficiency value and other attributes,
components in the SSUHSDC are utilized in a judicious and efficient the proposed SSUHSDC outperforms the other converters. Fig. 20 por­
manner as projected in Fig. 19. trays the pictorial representation of the key attributes of all the con­
verter compared.

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T. Sakthiram et al. Results in Engineering 25 (2025) 104050

proposed synthesis methodology was practically validated by con­

ducting experiments on a prototype converter under laboratory condi­
tions. When the proposed converter was supplied from a 20 V input, the
SSUHSDC delivered 100 W power to the load at 400V. The switch was
operated at a duty ratio of 0.475 at 50 kHz. The full-load efficiency of the
converter was 94.3 %. The voltage stress on the diodes of the converter
was less and only a fraction of the output voltage except for the output
diode D5. The converter’s output voltage was regulated using a simple
closed-loop control algorithm to make it suitable for DC microgrid
application. The closed-loop performance was also practically validated
by varying the input voltage from 16.1 V to 28 .3V. When the input
voltage was dynamically reduced to 16.1 V, the duty ratio of the switch
was slightly adjusted and the SSUHSDC was able to meet the 400 V load
requirement. Thus, the converter operated with a voltage gain of 25
under dynamic conditions. Further, when the load on the converter was
Fig. 18. Voltage gain plots of the SSUHSDC and the other converters compared
varied in a stepped manner from 75 W to 120 W, the output voltage of
in Table III.
the proposed converter was restored to 400 V quickly. To appreciate the
salient features of the SSUHSDC, it was benchmarked against a variety of
high gain converters. Based on the detailed comparison, the admirable
features of the proposed SSUHSDC are (i) its ability to provide an ultra-
high voltage gain value of 20 at a low duty ratio value of 0.475, (ii)
capability to extend the voltage gain even at safe duty ratio value, and
(iii) swift line and load voltage regulation capabilities. Thus, the pro­
posed SSUHSDC is suitable for integrating the low-voltage PV source
with the high-voltage DC bus when appropriate protection mechanisms
are also employed.

CRediT authorship contribution statement

T. Sakthiram: Methodology, Investigation, Conceptualization. L

Yogesh: Writing – original draft, Methodology, Conceptualization.
Rahul Srikanth: Software, Methodology, Formal analysis, Conceptu­
alization. M. Prabhakar: Visualization, Validation, Supervision, Project
administration. S. Angalaeswari: Writing – review & editing, Valida­
tion, Supervision, Project administration.
Fig. 19. Plot depicting D versus M/TCU ratio to appreciate the way compo­
nents are utilized in the converters compared in Table III
Declaration of competing interest

The authors declare the following financial interests/personal re­

lationships which may be considered as potential competing interests S
ANGALAESWARI reports a relationship with Vellore Institute of Tech­
nology - Chennai Campus that includes: employment. If there are other
authors, they declare that they have no known competing financial in­
terests or personal relationships that could have appeared to influence
the work reported in this paper.

Data availability

No data was used for the research described in the article.

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