TRIBHUVAN UNIVERSITY INSTITUTE OF ENGINEERING
PURWANCHAL CAMPUS DHARAN
Department of and Computer Engineering Electronics
COMPUTER ORGANIZATION AND ARCHITECTURE
A LAB REPORT ON NON-RESTORING DIVISION
Submitted By: Submitted To:
Name : Sonu Kumar Gupta Er. Sujan Karki Sir
Roll No : PURO78BCT084
Year/Part : III/I
ARITHMETIC AND LOGIC UNIT DESIGN
Introduction
An Arithmetic Logic Unit (ALU) is a crucial component of the CPU in a computer, performing essential
arithmetic and logical operations. The design of an ALU involves integrating multiple operations into a
single unit, which can then be selected and executed based on control signals. This lab will focus on
designing an ALU that performs various operations, including subtraction, multiplication, division, logical
shifts, rotations, and logical comparisons.
Objectives
Understand the functionality of an ALU and the operations it can perform.
Design and implement an ALU using basic logic gates and hardware description languages (HDLs) such as
VHDL or Verilog.
Verify and test the ALU using simulation tools to ensure correct operation.
Basic Concepts
1. Subtraction:
Perform subtraction by directly connecting inputs A and B and using the subtraction operator.
Example: ALU_Result = A - B;
2. Multiplication:
Multiply the inputs A and B using the multiplication operator.
Example: ALU_Result = A * B;
3. Division:
Divide the input A by B using the division operator.
Example: ALU_Result = A / B;
4. Logical Shift Left:
Shift the bits of input A one position to the left.
Example: ALU_Result = A << 1;
5. Logical Shift Right:
Shift the bits of input A one position to the right.
Example: ALU_Result = A >> 1;
6. Rotate Left:
Rotate the bits of input A one position to the left, with the most significant bit wrapping around to
the least significant bit.
Example: ALU_Result = {A[6:0], A[7]};
7. Rotate Right:
Rotate the bits of input A one position to the right, with the least significant bit wrapping around to
the most important bit.
Example: ALU_Result = {A[0], A[7:1]};
8. Logical AND:
Perform a bitwise AND operation between inputs A and B.
Example: ALU_Result = A & B;
9. Logical OR:
Perform a bitwise OR operation between inputs A and B.
Example: ALU_Result = A | B;
10. Logical XOR:
Perform a bitwise XOR operation between inputs A and B.
Example: ALU_Result = A ^ B;
11. Logical NOR:
Perform a bitwise NOR operation (NOT OR) between inputs A and B.
Example: ALU_Result = ~(A | B);
12. Logical NAND:
Perform a bitwise NAND operation (NOT AND) between inputs A and B.
Example: ALU_Result = ~(A & B);
13. Logical XNOR:
Perform a bitwise XNOR operation (NOT XOR) between inputs A and B.
Example: ALU_Result = ~(A ^ B);
14. Greater Comparison:
Compare if input A is greater than B. If true, output 1; else, output 0.
Example: ALU_Result = (A > B) ? 8'd1 : 8'd0;
15. Equal Comparison:
Compare if input A is equal to B. If true, output 1; else, output 0.
Example: ALU_Result = (A == B) ? 8'd1 : 8'd0;
16. Control Logic:
Use a 4-to-1 multiplexer (MUX) to select the appropriate operation based on the 4-bit control signal
(ALU_Sel).
Code:
// [Link]
module ALU_Design(
input [7:0] A, B, // ALU 8-bit Inputs
input [3:0] ALU_Sel, // ALU Selection
output reg [7:0] ALU_Result, // ALU 8-bit Result
output reg CarryOut // Carry Out Flag
);
reg [8:0] tmp;
always @(*) begin
CarryOut = 1'b0;
case(ALU_Sel)
4'b0000: // Addition
begin
tmp = {1'b0, A} + {1'b0, B};
ALU_Result = tmp[7:0];
CarryOut = tmp[8]; // Carryout flag
end
4'b0001: // Subtraction
ALU_Result = A - B;
4'b0010: // Multiplication
ALU_Result = A * B;
4'b0011: // Division
ALU_Result = A / B;
4'b0100: // Logical shift left
ALU_Result = A << 1;
4'b0101: // Logical shift right
ALU_Result = A >> 1;
4'b0110: // Rotate left
ALU_Result = {A[6:0], A[7]};
4'b0111: // Rotate right
ALU_Result = {A[0], A[7:1]};
4'b1000: // Logical and
ALU_Result = A & B;
4'b1001: // Logical or
ALU_Result = A | B;
4'b1010: // Logical xor
ALU_Result = A ^ B;
4'b1011: // Logical nor
ALU_Result = ~(A | B);
4'b1100: // Logical nand
ALU_Result = ~(A & B);
4'b1101: // Logical xnor
ALU_Result = ~(A ^ B);
4'b1110: // Greater comparison
ALU_Result = (A > B) ? 8'd1 : 8'd0;
4'b1111: // Equal comparison
ALU_Result = (A == B) ? 8'd1 : 8'd0;
default:
ALU_Result = A + B;
endcase
end
endmodule
// [Link]
module TF;
integer i;
// Inputs
reg [7:0] a;
reg [7:0] b;
reg [3:0] s;
// Outputs
wire [7:0] yout;
wire cf;
// Instantiate the Unit Under Test (UUT)
ALU_Design uut (a, b, s, yout, cf);
initial begin
// Initialize inputs
a = 8'h0C;
b = 8'h08;
for (i = 0; i <= 15; i = i + 1) begin
s = i;
#10;
$display("Case: %d, Ans: %d, CarryOut: %b", s, yout, cf);
end
end
initial begin
$dumpfile("[Link]");
$dumpvars(1);
end
endmodule
Output :
[2024-07-10 [Link] UTC] iverilog '-Wall' '-g2012' [Link] [Link] &&
unbuffer vvp [Link]
VCD info: dumpfile [Link] opened for output.
VCD warning: $dumpvars: Package ($unit) is not dumpable with VCD.
Case: 0, Ans: 20, CarryOut: 0
Case: 1, Ans: 4, CarryOut: 0
Case: 2, Ans: 96, CarryOut: 0
Case: 3, Ans: 1, CarryOut: 0
Case: 4, Ans: 24, CarryOut: 0
Case: 5, Ans: 6, CarryOut: 0
Case: 6, Ans: 24, CarryOut: 0
Case: 7, Ans: 6, CarryOut: 0
Case: 8, Ans: 8, CarryOut: 0
Case: 9, Ans: 12, CarryOut: 0
Case: 10, Ans: 4, CarryOut: 0
Case: 11, Ans: 243, CarryOut: 0
Case: 12, Ans: 247, CarryOut: 0
Case: 13, Ans: 251, CarryOut: 0
Case: 14, Ans: 1, CarryOut: 0
Case: 15, Ans: 0, CarryOut: 0
Finding VCD file...
./[Link]
Conclusion :
Hence different types of logical operations were performed using the eda playground and Verilog
compiler. This type of design is very crucial for understanding complex computer systems and computer
architecture.
