DESIGNING COMBINATIONAL
LOGIC GATES IN CMOS
Chapter 4
Introduction
(a) Combinational (b) Sequential
Figure: High level classification of logic circuits.
Static CMOS Design
• At every point in time (except during the
switching transients) each gate output is
connected to either VDD or VSS via a low-
resistive path
• The outputs of the gates assume at all times the
value of the Boolean function, implemented by
the circuit
• In contrast, a dynamic circuit relies on temporary
storage of signal values on the capacitance of high
impedance circuit nodes
Complementary CMOS
Figure: Complementary logic gate as a combination of a PUN (pull-up
network) and a PDN (pull-down network).
Cont.….
• What type of MOS is preferable for PDN and
PUN?
Figure : Simple examples illustrate why an NMOS should be used as a pull-down,
and a PMOS should be used as a pull-up device.
NMOS transistors in parallel/series
combination
• Transistors can be thought as a switch
controlled by its gate signal
– NMOS switch closes when switch control input is
high
– NMOS passes a strong 0 but a weak 1
Cont.….
• NMOS Transistors in Series/Parallel Connection
PMOS transistors in parallel/series
combination
Cont.….
• Combine series PDN and parallel PUN or parallel PDN and series
PUN to complete the logic design to output good 1 and 0
Cont.….
• Using De Morgan’s theorems
• The pull-up and pull-down networks of a
complementary CMOS structure are dual networks.
• This means that a parallel connection of transistors in
the pull-up network corresponds to a series connection
of the corresponding devices in the pull-down
• The number of transistors required to implement an N-
input logic gate is 2N.
Examples
Example: Two-input NAND Gate
Table: Truth Table for 2 input NAND
Figure: Two-input NAND gate in complementary static CMOS style.
Cont.….
• Example: Two-input NOR Gate
Cont.….
• Example: Synthesis of complex CMOS Gate
Cont.….
Exercise:
1. Synthesis a full adder circuit using CMOS
gates
2. Synthesis the following using CMOS gates
a. Two input OR
b. Four input AND
c. Two input XOR
d. F =AC D +AB D
Static CMOS Properties
• Full rail-to-rail swing: high noise margins
• Logic levels not dependent upon the relative device
sizes: ratio-less
• Always a path to VDD or GND in steady state; Low
output impedance
• Extremely high input resistance, nearly zero steady
state input current(input to CMOS gate)
• No steady state direct path between power and
ground: no static power dissipation
• Propagation delay function of output load capacitance
and resistance of transistors
Switch Delay model
Input pattern effects on delay
• Delay is dependent on the pattern of inputs
(Assume 𝑅𝑃 = 2𝑅𝑁 for same size of
transistors )
– Low-to-high transition
• Both inputs go low
– Delay is 0.69 (𝑅𝑃 /2) 𝐶𝐿
• One input goes low
– Delay is 0.69 (𝑅𝑃 ) 𝐶𝐿
– High-to-low transition:
• Both inputs go high (required for
NAND)
– Delay is 0.69 (2𝑅𝑛 ) 𝐶𝐿
Transistor Sizing
Delay dependency on input pattern
Figure: Example showing the delay dependence on input patterns
for two input NAND gate.
Transistor Sizing in complex CMOS
Gates
Fan in consideration
Figure : Four input NAND gate and its RC model.
• The propagation delay can be computed using the
Elmore delay model and is approximated as:
Propagation 𝐻 → 𝐿 delay deteriorates rapidly as a
function of fan-in no.: quadratically in the worst case
𝒕𝒑 as a function of Fan-In
Figure: Propagation delay of CMOS NAND gate as a function of
fan-in. A fan-out of one inverter is assumed, and all pull-down
transistors are minimal size.
Design Techniques for Large Fan-in
• Transistor sizing
• Progressive Transistor Sizing
• Input Re-Ordering
• Logic Restructuring
Transistor sizing
• To reduce the delay and resistance of the device,
the designer must have to increase the sizes
• However, increase in size increases the parasitic
capacitors which adds its effects in the preceding
gate
• If the load capacitor is dominated over the
intrinsic capacitor then widening the device only
creates a self loading effect
• Sizing is only effective when the load is
dominated by the fan-out
Cont….
tp as a function of Fan-In and Fan-Out
• Fan-in: quadratic duet to increasing resistance
and capacitance
• Fan-out: each additional fan-out gate adds two
gate capacitances to CL to the preceding stage
Progressive sizing
• This technique reduces the
dominant resistance while
keeping the capacitance in
bounds
• Progressive scaling of
transistors is beneficial M1 >
M2 > M3 > MN
• The progressive scaling is
easy in schematic diagram
but it is not as simple layout
Input reordering
• All the signals in the complex logic blocks might
not appear at the same time due to propagation
delay or preceding logic gates
• The signal, last to all the inputs which have a
stable value can be called as a critical signal and
the path over which the ultimate speed of the
structure can be calculated is called critical path
• Putting the critical path transistor closer to the
output gives a higher speed of operation
Cont. ….
• Put late arrival signal near
the output node
Logic Restructuring
Figure: Logic restructuring can reduce the gate fan-in.
Cont.…..
Power Consumption in CMOS Logic
Gates
• The dynamic power dissipation is given by
𝑃 = 𝛼0→1 𝐶𝐿 V 𝐷𝐷 2 𝑓
Where 𝛼0→1 is called switching activity
• switching activity has two components
– Static component, which is a function of network
topology
– Dynamic component, which is a function of timing
behavior of the circuit (glitches)
• Let 𝑃0 be the probability that the output will be in
zero state in one cycle, and 𝑃1 be the probability
that output will be one state in next cycle then
𝛼0→1 = 𝑃0 . 𝑃1 = 𝑃0 (1-𝑃0 )
Cont.
• Logic Function-The transition activity is a strong
function of the logic function being implemented.
• Assuming that the inputs are independent and
uniformly distributed, any N-input static gate has
a transition probability that corresponds to
where N0 is the number of zero entries and N1 is the
number of one entries in the output column of the
truth table of the function.
• Example: Derived the output transition
probability of a 2-input static CMOS NOR
gate
Truth table of a 2 input NOR gate
• Signal Statistics- The switching activity of a logic gate is a
strong function of the input signal statistics. Using a uniform
input distribution to compute activity is not a good one since
the propagation through logic gates can significantly modify the
signal statistics. For example, consider once again a 2-input
static NOR gate, and let 𝑃𝑎 and 𝑃𝑏 be the probabilities that the
inputs A and B are one.
• Assuming that the inputs are not correlated. The probability that
the output node equals one is given by
• Example: Derived the output transition
probability of a 2-input static CMOS AND
gate
A B AB
𝑃1 = 𝑃𝑎 . 𝑃𝑏
0 0 0
0 1 0 𝛼0→1 = 𝑃0 . 𝑃1
1 0 0
𝛼0→1 = (1 − 𝑃𝑎 . 𝑃𝑏 )(𝑃𝑎 . 𝑃𝑏 )
1 1 1
Exercise:
1. Derive the 𝛼0→1 output transition probabilities for
the basic logic gates (NAND, OR, XOR)
2. Please explain the design techniques to Reduce
Switching Activity
Ratioed Logic
• Ratioed logic is used to reduce the transistor
count but at the cost of extra power dissipation
• In ratioed logic the entire PUN is replaced by a
single unconditional load
• The nominal high voltage (VOH) is VDD but the
nominal low voltage (VOL) is not zero, which
results in static power dissipation
• This also reduced the noise-margin
• Since, the output voltage depends on the sizes of
the transistor so it is called ratioed logic
Figure: Ratioed logic gate.
Pseudo-nMOS Pseudo-nMOS
NOR NAND
Impact of size on Pseudo-nMOS
• At optimal threshold operation point, it is reasonable
to assume that the NMOS device resides in linear
mode while the PMOS load is saturated.
• Assuming that VOL is small relative to the gate drive
(VDD-VT) and that VTn is equal to VTp in magnitude,
VOL can be approximated as:
Example: Pseudo-nMOS Inverter
VDD
Output
Input
Figure: Voltage-transfer curves of
the pseudo-NMOS inverter as a function of the
PMOS size.
Cont.
Exercise
• Why Pseudo n-MOS is rationed logic
• Please explain the advantages and limitation of
Pseudo n-MOS compared to complimentary CMOS
logic gate implementation
• Given the choice between NOR or NAND logic,
which one would you prefer for implementation in
pseudo-NMOS?
44
Differential Cascode Voltage Switch
Logic (or DCVSL)
Figure: DCVSL logic gate.
Cont.…..
Example: Design XOR-NXOR gate using DCVSL
XOR-NXOR gate
Exemple: Design AND/NAND gate using DCVSL.
Figure : Transient response of a simple AND/NAND DCVSL gate. M1 and
M2 1mm/0.25mm, M3 and M4 are 0.5mm/0.25mm and the cross-coupled
PMOS devices are 1.5mm/0.25mm.
Exercise
• Please explain the advantages and limitation of
DCVSL compared to Pseudo n-MOS and
complementary CMOS
• Design OR/NOR using DCVSL
• Design full adder using DCVSL
Pass-Transistor Logic
• Gate is static – a path exists to both
supply rails under all circumstances
• N transistors instead of 2N
• No static power consumption
• Ratioless
• Bidirectional (versus undirectional)
Figure : Pass-transistor implementation of an AND gate.
• Note: Pass-transistor gates cannot be cascaded
by connecting the output of a pass gate to the
gate input of another pass transistor.
Figure: Pass transistor output (Drain/Source) terminal should not drive other
gate terminals to avoid multiple threshold drops.
• Example: Design OR gate
a) Using pass transistor
b) Compare the with CMOS gate designs
Figure OR gate using pass transistor
Figure: OR gate using CMOS
Pass transistor Need 4 transistors instead of 6 for CMOS OR gate.
Exercise:
1. Design AND gate
a) using pass transistor
b) Using Complementary CMOS gate
c) Compare the two designs
2. Design F=
2. Design full adder circuit using
a) using pass transistor
b) Using Complementary CMOS gate
c) Compare the two designs
Differential Pass Transistor Logic:
• For high performance design, a differential
pass-transistor logic family, called CPL or DPL,
is commonly used.
• The basic idea is to accept true and
complementary inputs and produce true and
complementary outputs. A number of CPL
gates (AND/NAND, OR/NOR, and
XOR/NXOR) are shown in Figure.
Complementary Pass-Transistor Logic
(differential pass-transistor logic)
• Every signal and its complement is generated.
• Gates are static, because the output is
connected to either VDD or GND.
• Design is modular; same cell can produce
various gates by simply permuting the input
signals
54
Energy: Pass Transistor Logic vs.
CMOS
• PTL consumes less dynamic power than static
CMOS Logic.
• PTL leakage may be higher when output is
low, because the reduced voltage level may be
insufficient to turn the PMOS transistor in the
inverter off.
Ways to Reduce Leakage
Exercise: Reading assignment
• Please explain the cause of leakage and ways
to Reduce Leakage power
Transmission Gate
• NMOS pass transistor passes a
strong 0 and a weak 1
• PMOS pass transistor passes a
strong 1 and a weak 0
• Combine the two to make a
CMOS pass gate which will pass a
strong 0 and a strong 1
• The transmission gate acts as a
bidirectional switch controlled by
the gate signal C
• Provides both power and ground
levels.
• Good design, except needs more
transistors.
Figure: Transmission gates enable rail-
to-rail switching
Cont.…
• Example: Design MUX using Transmission
gate
Cont.…
• Example: Design XOR using Transmission
gate
• Exercise
1. Please explain the advantage of transmission
gate compared to pass transistor logic and
CMOS gate design
2. Design the following using transmission gate
logic
a) Inverting multiplexer
b) AND gate
c) OR gate
d) S=
Dynamic CMOS Design
Figure: Basic concepts of a dynamic gate.
Cont….
VDD
Precharge
transistor
Inputs Output
PDN CL
Evaluate
CK transistor
Two-Phase Operation in a Vector Period
Phase CK Inputs Output
Precharge low don’t care high
Evaluation high Valid inputs Valid outputs
• 4-Input NAND Dynamic CMOS Gate
VDD
CK
Output
A = CK’ + (ABCD)’∙ CK
CL
B
C tL→H ≈ 0
CK
Characteristics of Dynamic CMOS
• Nonratioed logic – sizing of pMOS transistor is not important
for output levels.
• Smaller number of transistors, N+2 vs. 2N for CMOS.
• Faster switching due to smaller capacitance.
• Larger precharge transistor reduces output precharge time, but
increases precharge power.
• It only consumes dynamic power
• Static power – negligible, similar to CMOS.
• Short-circuit power – none.
• Dynamic power
– no glitches – following precharge, signals can either make transition
only in one direction, 1→0, or no transition, 1→1.
– only logic transitions – all nodes at logic 0 are charged to VDD during
precharge phase.
Issues in Dynamic Design
• Charge Leakage
• Charge Sharing
• Capacitive Coupling
• Clock Feed through.
Charge leakage
Ideal
Actual
Figure : Leakage issues in dynamic circuits
• Question: How to compensate for the charge lost due to the pull-down
leakage paths?
• Solution: Bleeder Transistor
Charge Sharing
Reading assignment:
• Capacitive Coupling
• Clock Feed through.
Cascading Dynamic Gates
• Limitation of dynamic CMOS design is its
limitation during cascading
• Why ∆𝑉?
• How can we solve this problem? Answer using Domino logic desing
Domino Logic
Example on Domino CMOS
VDD VDD
CK prech. evaluate
CK CK C
B A
A = 0 →1
CK CK B
R. H. Krambeck, C. M. Lee and H.-F. S. Law, “High-Speed Compact Circuits with
CMOS,” IEEE J. Solid-State Circuits, vol. SC-17, no. 3, pp. 614-619, June 1982.
Differential (Dual Rail) Domino
Exercise
• Implement using Domino logic
Final Remark
• Static CMOS:
• most reliable and predictable
• reasonable in power and speed
• voltage scaling and device sizing are well understood.
• Pass-transistor logic:
• beneficial for multiplexer and XOR dominated circuits like adders,
etc.
• For large fan in gates, static CMOS is inefficient; a
choice can be made between pseudo-nMOS, dynamic
CMOS and domino CMOS.
